Programmable Peripheral Interface 8255

PPI 8255 is a general-purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can assign
different ports as input or output functions.
The common applications of 8255 are:
 Traffic light control
 Generating square wave
 Interfacing with DC motors and stepper motors
Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-
PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and upper
PORT C. Group B includes PORT B and lower PORT C. These two groups can be programmed
in three different modes, i.e. the first mode is named as mode 0, the second mode is named as
Mode 1 and the third mode is named as Mode 2.
8255 Architecture
The following figure shows the architecture of 8255A −
Data Bus Buffer
It is a tristate 8-bit buffer, which is used to interface the microprocessor to the system data bus.
Data is transmitted or received by the buffer as per the instructions by the CPU. Control words
and status information is transferred using this bus.
Read/Write Control Logic
This block is responsible for controlling the internal/external transfer of data/control/status word.
It accepts the input from the CPU address and control buses, and in turn issues command to both
the control groups.
CS
It stands for Chip Select. A LOW on this input selects the chip and enables the communication
between the 8255A and the CPU. It is connected to the decoded address, and A0 & A1 are
connected to the microprocessor address lines.
Their result depends on the following conditions –

CS A1 A0 SELECTION ADDRESS

0 0 0 PORT A 80 H

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H

0 1 1 Control Register 83 H

1 X X No Selection X

WR
It stands for write. This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or control register.
RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.
RD
It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.
A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the table
showing their various signals with their result.

A1 A0 RD WR CS Result

0 0 0 1 0 Input Operation
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

0 0 1 0 0 Output Operation
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT B

1 0 1 0 0 Data Bus → PORT C Lower

1 1 1 0 0 Data Bus → PORT C Upper

To communicate with peripherals through 8255 three steps are necessary:

1. Determine the addresses of Port A, B, C and Control register according to Chip Select Logic
and the Address lines A0 and A1.
2. Write a control word in control register.
3. Write I/O instructions to communicate with peripherals through port A, B, C.

Operational modes of 8255

There are two basic operational modes of 8255:
1. Bit Set/Reset mode (BSR mode).
2. Input/output mode (I/O mode).
The two modes are selected based on the value present at the D7 bit of the control word register.
When D7 =1, 8255 operates in I/O mode, and when D7 = 0, it operates in the BSR mode.
Bit Set/Reset (BSR) mode
The Bit Set/Reset (BSR) mode is available on port C only. Each line of port C (PC7 - PC0) can be
set or reset by writing a suitable value to the control word register. BSR mode and I/O mode are
independent and selection of BSR mode does not affect the operation of other ports in I/O mode.

8255 BSR mode

 D7 bit is always 0 for BSR mode.
 Bits D6, D5 and D4 are don't care bits.
 Bits D3, D2 and D1 are used to select the pin of Port C.
 Bit D0 is used to set/reset the selected pin of Port C.

Selection of port C pin is determined as follows:

D3 D2 D1 Bit/pin of port C selected

0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
As an example, if it is needed that PC5 be set, then in the control word,
1. Since it is BSR mode, D7 = '0'.
2. Since D4, D5, D6 are not used, assume them ‘0’.
3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
4. PC5 has to be set, hence, D0 = '1'.
Thus, as per the above values, 0B (Hex) will be loaded into the Control Word Register (CWR).

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 1 1

Input/output (IO) mode

This mode is selected when D7 bit of the Control Word Register is 1. There are three I/O modes:
1. Mode 0 - Simple I/O
2. Mode 1 - Strobed I/O
3. Mode 2 - Strobed Bi-directional I/O

Control Word format

 D0, D1, D3, D4 are assigned for port C lower, port B, port C upper and port A respectively.
When these bits are 1, the corresponding port acts as an input port. For e.g., if D0 = D4 = 1,
 then lower port C and port A act as input ports. If these bits are 0, then the corresponding port
acts as an output port. For e.g., if D1 = D3 = 0, then port B and upper port C act as output ports.
 D2 is used for mode selection of Group B (port B and lower port C). When D 2 = 0, mode 0 is
selected and when D2 = 1, mode 1 is selected.
 D5 & D6 are used for mode selection of Group A (port A and upper port C). The selection is
done as follows:
D6 D5 Mode
0 0 0
0 1 1
1 X 2
 As it is I/O mode, D7 = 1.
For example, if port B and upper port C have to be initialized as input ports and lower port C and
port A as output ports (all in mode 0):
1. Since it is an I/O mode, D7 = 1.
2. Mode selection bits, D2, D5, D6 are all 0 for mode 0 operation.
3. Port B and upper port C should operate as Input ports, hence, D1 = D3 = 1.
4. Port A and lower port C should operate as Output ports, hence, D4 = D0 = 0.
Hence, for the desired operation, the control word register will have to be loaded with "10001010"
= 8A (hex).
Mode 0 - simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking signals. Port A,
port B provide simple I/O operation. Either the two halves of port C can be used together as an
additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C
are independent, they may be used such that one-half is initialized as an input port while the other
half is initialized as an output port.
The input/output features in mode 0 are as follows:
1. Output ports are latched.
2. Input ports are buffered, not latched.
3. Ports do not have handshake or interrupt capability.
4. With 4 ports, 16 different combinations of I/O are possible.
'Latched' means the bits are put into a storage register (array of flip-flops) which holds its output
constant even if the inputs change after being latched.
The 8255's outputs are latched to hold the last data written to them. This is required because the
data only stays on the bus for one cycle. So, without latching, the outputs would become invalid
as soon as the write cycle finishes.
The inputs are not latched because the CPU only has to read their current values, and then store
the data in a CPU register or memory if it needs to be referenced later. If an input changes while
the port is being read then the result may be indeterminate.
Mode 0 – input mode

 In the input mode, the 8255 gets data from the external peripheral ports and the CPU reads the
received data via its data bus.
 The CPU first selects the 8255 chip by making CS low. Then it selects the desired port using
A0 and A1 lines.
 The CPU then issues an RD signal to read the data from the external peripheral device via the
system data bus.

Mode 0 - output mode

 In the output mode, the CPU sends data to 8255 via system data bus and then the external
peripheral ports receive this data via 8255 port.
 CPU first selects the 8255 chip by making CS low. It then selects the desired port using A0 and
A1 lines.
 CPU then issues a WR signal to write data to the selected port via the system data bus. This
data is then received by the external peripheral device connected to the selected port.

Mode 1 - Strobed Input/output mode

When we wish to use port A or port B for handshake (strobed) input or output operation, we
initialize that port in mode 1 (port A and port B can be initialized to operate in different modes,
i.e., for e.g., port A can operate in mode 0 and port B in mode 1). Some of the pins of port C
function as handshake lines.
For port B in this mode (irrespective of whether is acting as an input port or output port), PC0,
PC1 and PC2 pins function as handshake lines.
If port A is initialized as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals.
Pins PC6 and PC7 are available for use as input/output lines.
The mode 1 that supports handshaking has following features:
1. Two ports i.e. port A and B can be used as 8-bit I/O ports.
2. Each port uses three lines of port c as handshake signal and remaining two signals can be
used as I/O ports.
3. Interrupt logic is supported.
4. Input and Output data are latched.
Mode 2 - Strobed Bidirectional Input/output mode

Only port A can be initialized in this mode. Port A can be used for bidirectional handshake data
transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins
PC3 - PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 - PC2) can
be used as input/output lines if group B is initialized in mode 0 or as handshaking for port B if
group B is initialized in mode 1. In this mode, the 8255 may be used to extend the system bus to a
slave microprocessor or to transfer data bytes to and from a floppy disk controller.
Acknowledgement and handshaking signals are provided to maintain proper data flow and
synchronization between the data transmitter and receiver.