International Journal of communication and computer Technologies, ISSN: 2278-9723

Available at http://www.ijccts.org

6-bit, 180nm Digital to Analog Converter (DAC) Using Tanner EDA Tool for
Low Power Applications
S.Surender1, K.Venkatachalam2 and V.Gowrishankar3

Received: 13-08-2017, Revised: 21-09-2017, Accepted: 24-11-2017, Published online: 19-12-2017

Abstract

This paper describes a CMOS current-steering digital-to-analog converter with a full-swing output signal. In a Wireless system
the quality of the communication link is main criteria, for great distance transmission it is necessary to convert analog signal into
digital signal at input side, same as convert digital signal to analog signal at output side. In the Existing DAC, 6 Binary inputs to
63 thermometer-coded (unary) outputs will use 6-input NOR and NAND logic gate, and the timing delay of these gates are very
different. As the clock rate rising, it will cause error decoding problems.so we propose the 6 to 63 thermometer decoder by 2
section decoding. There is two 3 to 7 thermometer decoder for column and row decoder. This scheme reduces the error decoding
problems. A new scheme of the quaternary driver and an output current cell composed of both nMOS and pMOS.The nMOS
operates from the power supply to the half of the supply. The pMOS operates independently from the half of the supply to the
ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects
the optimized current cell. The circuit is simulated using 180nm Complementary Metal-oxide Semiconductor technology at a
power supply voltage of 3.0 V on Tanner tool and the power consumption is about 17.8 mW. The proposed Current Steering
Digital to Analog converter are schematic using Tanner S-EDIT and simulation of the proposed work is done using Tanner T-
EDIT. The waveform analysis is done using Tanner W-EDIT software

Index Terms: Binary to thermometer decoder, Current steering digital-to-analog converter (DAC), full-swing output, quaternary
driver, TANNER EDA tool.

I. INTRODUCTION of the output voltage depends on the slew rate of the

operational amplifier, voltage-steering type based on
Digital-To-Analog (D/A) converters are crucial the op-amp for the DAC output is not suitable for
components of modern applications such as video high-speed applications. In the case of the current-
signal processing, digital signal synthesis, and both steering type, the current generally flows directly
wired and wireless transmitters. Formerly, time- through off-chip resistors or termination resistors
domain applications such as high-resolution inside the chip to obtain a fast operating speed.
performance and video signal processing were the However, the output voltage at the termination resistor
main operator of high-speed D/A development. cannot have a full swing since the inevitable voltage
Accordingly, the emphasis was on specification drop is generated between the drain and the source of
parameters which were of importance for visual value: the output current cell.
settling time, glitch performance, and linearity,
especially integral nonlinearity (INL). The widespread In this brief, a current-steering DAC with a full-
use of digital modulation techniques has cause to swing output voltage from the ground voltage to the
more frequency-domain applications. For these power supply is proposed. The DAC has an
applications, where the D/A converter (DAC) is used architecture that follows the thermometer code
in the transmit path.The current system-on-a-chip method, which has excellent monotonicity and low
(SOC) trends are toward integrating digital and analog glitch energy. The latch circuits have been simplified
circuits in a chip. As a result, a data converter, which in order to reduce the power consumption and to
is part of a vital interface within those systems, is correct mismatches.[2] In order to implement the full-
becoming an increasingly more important block.[1]- swing output voltage, a quaternary driver and an
[7] A digital-to-analog converter (DAC) is a output current cell composed of both nMOS and
representative circuit that a digital code is converted pMOS are discussed. First, the nMOS current cell
into an analog signal. Normally, the kinds of DAC are operates from the power supply to the half of the
mainly divided into two categories: voltage-steering power supply. Second, the pMOS current cell operates
type and current-steering type. Since the settling time separately from the half of the power supply to the
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International Journal of communication and computer Technologies, ISSN: 2278-9723

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ground voltage. Then, the final output voltage is steering DAC is designed with a full matrix structure
acquired through a multiplexer that is driven by a for high-speed operation and accuracy. Furthermore,
digital driver that selects the optimized current cell. there are many advantages such as a simple design,
The contents of the brief are as follows. In Section II, low integral nonlinearity and differential nonlinearity
the circuit design technique of the full-swing DAC is error, accurate monotonicity, low noise analog output,
described. Measurement results and conclusions are low glitches energy.
summarized in Sections IV and V respectively.
However, since the signals to drive the output
current cell are entirely thermometer code, the
complexity of the binary-to-thermometer decoder
II. DESIGN OF FULL-SWING CURRENT- increases exponentially with DAC resolution.
STEERING DAC

The Current Steering consists of weighted currents

produced by current mirrors, switches to steer the
current and an added. The reference elements are
current sources and sum elements are only wire
connections. The switches are normally MOS
transistors. The switches are controlled by the input
bits. The every element is weighted with 21, 22, 23 ...
2N where N is the number of bits. The output current
is given by

Iout=b0 Iunit+b1 2-1 Iunit +…bn2-N Iunit

Fig-1: Block diagram of the full-swing DAC.

The switches are controlled by the input word.

Depending on the input word, the current source is
switched to the load or to the ground which improves B. Digital Block
the speed of the DAC.
The output voltage cannot have a full swing. In
The advantage of current steering architecture is order to solve this problem, it is necessary to add a
the ease of implementing the elements on the chip. level restoration circuit. The design example of
thermometer decoder for the 4-bit binary digital input
code. From 0000 to 0111, the output of the
thermometer decoder is increased like a normal one.
A. Architecture However, from 1000 to 1111, the output of the
thermometer decoder is decreased like a reverse one.
Fig. 1 shows the block diagram of the full-swing Thus, we can obtain 15 output codes at the
DAC. The 6-bit digital input codes are arranged at the thermometer decoder, and it operates like a
input data sync block to obtain the same delay time. symmetrical one. 6 to 63 binary to thermometer
The block 6-to-63 binary-to-thermometer decoder, the (unary) decoder consists of 6 input NOR and NAND
binary digital codes are converted into thermometer gates and the timing delay of these gates are very
codes to improve the linearity and decrease the glitch different. As the clock rate rising, it will cause error
noise. Then, the thermometer codes are transferred to decoding problems. After the end of the binary-to-
the Giga latch, level shifter, and driver. Finally, the thermometer decoder, the digital codes are holding at
output currents are converted into analog voltages by the Giga latch. Then, the digital signals of 1.8 V are
the termination resistors. Generally, the 6-bit current- shifted into 3.3 V at the level shifter. In order to have
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International Journal of communication and computer Technologies, ISSN: 2278-9723

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the full-swing output analog signal at the current cell,

a quaternary driver is proposed at the final digital
block.

In the 6-bit DAC, there are 32 output current cells

composed of both nMOS and pMOS. Since the
current cells are driven by the proposed symmetrical
thermometer decoder, we can obtain 63 codes at the
output. With the thermometer decoder, the full-swing
analog output voltage is obtained. It will be also
discussed in the next section.

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respectively. This is because the switching

MOS should be operated in the saturation
C. Analog Block mode, not in the linear mode. If the
switching MOS is operated in the linear
The output current cell is the most important mode, there exists a voltage drop at the
circuit that dominantly determines the switching MOS. In order to minimize the
performance of the current-steering DAC. voltage drop at the switching MOS, to
Thus, it needs a careful design to consider reduce the error decoding problem and
many factors. First of all, it must drive the reduce glitch energy, therefore, the proposed
correct current as one LSB and operate at a digital driver is designed.
high speed. Furthermore, it must have a high
output impedance to obtain good
performances.
III. BINARY TO THERMOMETER
If the output impedance of the current DECODER
cell is increased, it is possible to obtain the
suitable current because it can minimize the The Thermometer codes are the
swing of the current cell node. Those results representation of numbers based on how
improve not only INL and DNL, which are many '1s' are present. The Binary to
the static performance but also signal-to thermometer decoder is used to convert the
noise and distortion ratio (SNDR) and N-bit binary input into 2N – 1 Thermometer
spurious-free dynamic range (SFDR), which coded output lines.
are the dynamic performance. The Cell
composed of four MOS: two MOSs are for The decoder utilized for effective
switching MOSs and two MOSs are for the transformation of code from binary to
output current cell with CCM. In the case of thermometer for the realization of
the conventional current-steering DAC, the thermometric type digital to analog
output voltage is determined by the converter. The general idea of the decoder is
operating range of the MOS. For example, if based upon the detail that the decoder is the
the nMOSs are only used, the output range component which chooses one of the 2n
is operated from the power supply voltage to outputs by decoding the binary value on the
weak GND. If the pMOSs are only used, the ‘n’ inputs. The binary to thermometer
output range is operated from the weak decoder is designed with the utilization of
VDD to the ground voltage. If we want to gates like AND, OR, NOT gate with CMOS
obtain the full swing output voltage, both 180nm technology.
pMOS and nMOS must be used. In order to
improve the drawbacks of the conventional
full swing current cell, a novel current cell
with a digital driver is proposed. The digital
driver is composed of four types that drive
the output current cell, respectively. Thus, it
is called the quaternary driver. Dependent
on the digital code, the digital driver drives
the appropriate digital value to the output
current cell. The digital driver generates
weak high positive, weak high negative,
weak low positive, and weak low negative,

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Fig-2: 3 to 7 block diagram Binary to

Thermometer Decoder
Fig-3: Schematic of Binary to
Thermometer decoder

In this execution, 6 bits are transformed

into thermometer code. Thus we need 6 bit
binary to thermometer decoder. To reduce
the complexity, the 6-bit decoder is divided
into two 3 bit decoders which are used for
row and column of the unary current cell
array. The 3 bit binary to 7-bit thermometer
bit decoder is shown in fig. 2. Before
sending the signals after first section
decoding, we use the true single phase clock
(TSPC) latch to convey the signals to the
second decoding section (local decoder) in
the case for high-speed data processing. It
will reduce glitches energy.

IV. SIMULATION RESULTS OF

PROPOSED DAC

The DAC is prepared in standard Fig.4: Schematic of PMOS current cell

180-nm CMOS technology. The power
consumption is about 17.8mW with 1.2 V
for the digital and 3.3 V for the analog. The
fig. 3 shows the schematic diagram of
Binary to Thermometer decoder. The 468
MOSFETs devices, 3 MOSFET geometries,
122 Subcircuit instances, 8 Boundary nodes,
235 Independent nodes, 243 Total nodes are
present in the binary to thermometer
decoder.

Fig.5: Schematic of NMOS current cell

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the measured performance summary and the

comparison with the conventional ones.

TABLE-1: PERFORMANCE SUMMARY AND

COMPARISON

Parameters [1] [2] [3] This

Work
Fig.6: Waveform of Working of Binary to
thermometer decoder Full Swing YES NO NO YES

[Buffe
r]

Resolution 10-b 6-b 6-b 6-b

Technology 45nm 90 0.13 180nm

nm µm

Power 476m 8.3 29m 17.8m

W 2m W W
Consumpti W
on

Fig.7: Waveform of Working of DAC

VI. Future Work

However, the inconsistency between the

V. CONCLUSIONS pMOS current cell and the nMOS current
cell is getting worse as the operating
In this brief, a current-steering DAC frequency is increased. Thus, it must be
with the full-swing output voltage was considered and solved in a near future. For
designed. The decoder was designed with example, an internal calibration circuit to
two 3 to 7 binary to thermometer decoder guarantee the matching and consistency of
for row and column. The current cell was the complementary current sources is
composed of both pMOS and nMOS. absolutely needed in the real applications.
Furthermore, the output voltage was driven
by a quaternary driver that selects the REFERENCES
optimized current cell. The power
consumption was 17.8 mW. Table I shows

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