Data Acquisition Using INS8048

National Semiconductor
Data Acquisition Using Application Note 281
INS8048 Daniel Hagerty
November 1981

Abstract: This application note describes techniques for in- The ADC0804 is a CMOS 8-bit successive-approximation
terfacing National Semiconductor’s ADC0833 serial I/O, A/D converter with parallel I/O. This A/D can be mapped
and ADC0804 parallel I/O A/D converters to the INS8048 into memory space or can be controlled as an I/O device.
family of microprocessors. A hardware and software inter- No external logic is needed to interface with the INS8048. A
face example is provided for each A/D, along with a brief new differential analog voltage input allows increasing the
theory of operation. common-mode rejection and offsetting the analog zero in-
put voltage value. In addition, the voltage reference input
INTRODUCTION
can be adjusted to allow encoding smaller voltage spans to
Since the INS8048 series microprocessors are single-chip, the full 8 bits of resolution.
multiple I/O line, high speed devices designed as efficient
controllers, the capacity to interface with analog peripherals ADC0833 IMPLEMENTATION
is obvious. That the conversion be fast, inexpensive and Before explaining the system configuration, it is worthwhile
easily expanded to accommodate a number of I/O devices for one to understand the operation of the INS8048 proces-
is desirable. sor’s I/O ports. Ports 1 and 2 are quasi-bidirectional; that is,
The INS8048 is a self-contained, 8-bit processor in a 40-pin they can be used as inputs or outputs while being statically
dual-in-line package. It contains its own system timing, con- latched. If a ‘‘1’’ is written into any port bit, that bit can
trol logic and memory. All parts contain RAM (64, 128, 256 function as an input or as a high level output. If a ‘‘0’’ is
bytes) and offer the option of on-board ROM (1k, 2k, 4k written into any port bit, that bit can function only as a low
depending on part). It provides extensive bit-handling capa- level output. Outputs are latched until changed and inputs
bilities, 97 instructions, and offers easy expansion for I/O are unlatched and must be read immediately. When used
and memory. with the ANL Pp,A (AND accumulator to port) or the ORL
Pp,A (OR accumulator to port) instructions, these ports pro-
The ADC0833 A/D converter is an 8-bit successive-approxi-
vide an efficient means of handling single line inputs and
mation device with serial I/O and conversion time of 25 ms.
outputs. Port expansion, if anticipated, is handled via the
This family of converters offers various configurations of
lower four bits of Port 2. These four bits fulfill three distinct
multiplexed analog inputs which can be software pro-
functions:
grammed as single-ended, or as differential inputs, or both.
Single-ended inputs are referenced to a common pin which (1) A quasi-bidirectional static port
is either referred to analog ground or to a fixed reference (2) The four high order address bits for external memory
voltage. Like the INS8048 family, a single 5V power supply (3) An expander port interface
is all that is needed. The inputs will accept a 0V-5V range.
Only four pins of the processor’s Port 1 or Port 2 are need-
No zero adjust is necessary. It is compatible with TTL and
ed for physical interfacing (see Figure 1 ). The ANL or ORL
MOS at both input and output. The output can be selected
instructions set up the port pins to produce the proper out-
as either MSB or LSB first.
puts (CS, CLK, and the multiplex address) or to allow for
data input from the A/D converter.

TL/H/5632 – 1
FIGURE 1. A/D Conversion Circuit for Single-Ended MSB First Mode
AN-281

C1995 National Semiconductor Corporation TL/H/5632 RRD-B30M115/Printed in U. S. A.

The following description of the program can be used with carry, each bit is tested and the appropriate ‘‘1’’ or ‘‘0’’ is
the listing or flow chart to understand the procedure. To output to the port. After five such operations, the start bit is
begin conversion, the processor must drive CS low, reset- shifted on the rising edge of the clock pulse through the
ting the multiplex address shift register, the successive-ap- A/D’s 5-bit shift register (see Figures 2 and 3 , Tables 1 and
proximation register and the 9-bit shift register. After the 2). At this point, the digital data input is disabled, and the
A/D converter has been selected, the multiplexer address is digital data output enabled. One more clock pulse is needed
shifted out serially to the converter. The 4-bit multiplexer to synchronize the output on the falling edge of the clock
address is always preceded by a start bit, a ‘‘1’’. The pro- pulse. On each successive clock pulse, data is shifted seri-
gram loads the multiplexer address, start bit and mode bit ally to the processor. The data bits are then shifted, upon
into the accumulator as a single byte which is processed reception, into the accumulator to form the digitized analog
and shifted out to the converter. By shifting this byte into the input.

FIGURE 2. Example I/O Transaction (A/D Output e 7A; Channel 2, Single-Ended Selected)

TL/H/5632 – 2
FIGURE 3. A/D Conversion Flow Chart

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 TABLE I. Single-Ended Mux Mode
Single-Ended HEX
LSB MSB S/D Start
0 1 2 3 Code
1 0 0 1 1 a 13
1 1 0 1 1 a 1B
1 0 1 1 1 a 17
1 1 1 1 1 a 1F

TABLE II. Differential Mux Mode

Differential HEX
LSB MSB S/D Start
0 1 2 3 Code
1 0 0 0 1 a b 11
1 1 0 0 1 a b 19
1 0 1 0 1 b a 15
1 1 1 0 1 b a 1D

START: ANL P1, Ý0F3H ;SELECT A/D, SET CS0 to 0

MOV R2 Ý5 ;BIT COUNTER w 5
MOV A, ÝDATA ;A w MUX ADDR
MOV R3, Ý0 ;CLEAR R3
LOOP 1: RRC A ;CY w ADDR BIT
JC ONE ;IF CY e 1 GO TO ONE
ZERO: ANL P1, Ý0FEH ;SET DI e 0
JMP CONT ;CONTINUE IF 0
ONE: ORL P1, Ý1 ;SET DI e 1
CONT: CALL PULSE ;PULSE CLK 0 x 1 x 0, CLK IN DATA
DJNZ R2, LOOP 1 ;LOOP, TO SHIFT AND OUTPUT MUX
;ADDR AND SENTINEL
MOV R2, Ý8 ;BIT COUNTER w 8, FOR SERIAL IN
LOOP2: CALL PULSE ;PULSE CLK 0 x 1 x 0
IN A, P1 ;A w (D0), BIT SHIFTED TO CARRY
RRC A
RRC A
MOV A, R3 ;A w RESULT
RLC A ;A(0) w CY, SHIFT LEFT
MOV R3, A ;R1 w RESULT
DJNZ R2, LOOP 2 ;LOOP THRU FOR ALL 8 BITS
RETR
PULSE: ORL P1, Ý04 ;CLK w 1
NOP ;DELAY
ANL P1, Ý0FBH ;CLK w 0
RET
END START

FIGURE 4. Single-Ended A/D Conversion Routine

3
Easy expansion, mentioned earlier, has not been forgotten. A sample program is shown in Figure 6 . The processor
With the addition of the one chip (see Figure 5 ), the number starts the A/D, reads and stores the result of an analog-to-
of peripherals can be expanded TEN-FOLD! The INS8243 digital conversion through an interrupt service routine. This
I/O expander consists of five 4-bit bidirectional ports. One subroutine starts at address 30H, and the external interrupt
port provides the interface with the processor, the other four vector is located at address 03H. The converted data word
provide the I/O expansion. The INS8243 I/O expander is stored at on-chip RAM location, 10H. The following is a
serves as a direct extension for the resident I/O port of the line by line description of the parallel A/D conversion sub-
INS8048 family of processors. The INS8048 instruction set routine.
provides four instructions solely for use with this chip. They BEGIN: This is where the program starts execution after
are: having been reset. R0 and R1 are set up with addresses to
MOVD Pp,AÐShift accumulator data to addressed port point to the A/D converter and the address where data is to
MOVD A,PpÐShift addressed port data to accumulator be stored.
ANLD Pp,AÐANDing accumulator data to addressed port AGAIN: Interrupts are enabled to allow the A/D to signal
that it has completed its conversion; arbitrary data is written
ORLD Pp,AÐORing accumulator data to addressed port
to the device to start its conversion process.
The last two instructions can be used in the same way as
LOOP: The processor waits here for an interrupt to occur.
the ANL and ORL instructions in the first example. It should
The interrupt service routine returns with a zero in the accu-
be noted that only one pin can be used in Port 7, since the
mulator to allow the program to continue at CONT.
INS8243, unlike the INS8048 series, has true bidirectional
ports and thus requires that each port be either input or CONT: This is where the analog input received earlier is
output. Figure 5 shows how 10 A/D converters could be processed.
connected to allow up to 80 analog inputs to be monitored INDATA: Upon the occurrence of an interrupt, this routine is
at the expense of only four I/O pins on the INS8048 itself. entered. It reads data from the A/D converter (with a MOVX
A, @ R0) and puts it into the RAM location pointed to by R1
ADC0804 IMPLEMENTATION
(MOV @ R1, A). The accumulator is cleared in order to pass
The ADC0801/2/3/4/5 A/D converters have been de- location LOOP:, (see Figure 6 ) and control is returned to
signed to directly interface with processors similar to the the user’s program.
INS8048 family. The A/D is memory mapped into the exter-
Upon inspection, it can be seen that each system has its
nal data memory space of the INS8048 system. The RD,
strengths and limitations. Because of the need to handle
WR and INTR signals of the A/D, and the processor are tied
serial data with loops for input and output, the ADC0833 is
directly. In the example circuit, an arbitrarily chosen ad-
approximately five times slower than the ADC0804. There-
dress, E0, is assigned to the A/D, and CS is decoded by a
fore, for raw speed, the ADC0804, at 100 ms conversion
bus comparator, the DM8131. Since the address and the
time plus minimal processor service time, is preferable.
data of the INS8048 processor are multiplexed on the same
Faster processors can be used to decrease the response
bus, an inverted ALE signal from the INS8048 is tied to the
time from any given analog input. All INS8048 series devic-
strobed input of the bus comparator in order to latch the
es are available with clock rates up to 11 MHz. Though
address output from the processor. If no other devices are
slower, the ADC0833 provides up to eight multiplexed in-
attached to the INS8048’s bus, this decoding can be left off
puts configurable in single-ended or differential modes, and
and the CS input to the ADC0804 is simply grounded.
uses only four processor I/O pins. In either case, the imple-
mentation is not formidable and, with only 2 or 3 chips per
system, not expensive.

Expander Outputs
Port 4 DI
SK
CS1
CS2
Port 5 CS3
CS4
CS5
CS6
Port 6 CS7
CS8
CS9
CS10
Port 7 D0
TL/H/5632 – 3
FIGURE 5. I/O Expansion

4
 ;TEST ROUTINE FOR INTERFACING INS8048 WITH ADC0804
;PROGRAM STARTS AT MEMORY LOCATION 10H
;INTERRUPT SUBROUTINE STARTS AT LOCATION 30H
;DATA WILL BE STORED IN MEMORY LOCATION AT 20H
;
ADDRESS OBJECT CODE
ORG 0H
0000 04 10 JMP 10H ;PROGRAM STARTS AT 10H
ORG 3H ;INTERRUPT VECTOR
0003 04 30 JMP 30H
ORG 10H ;MAIN PROGRAM
0010 B8 E0 BEGIN: MOV R0, Ý0E0H ;RO POINTS TO A/D
0012 B9 20 MOV R1, Ý20H ;R1 POINTS TO DATA ADDRESS
0014 05 AGAIN: EN I
0015 23 FF MOV A, Ý0FFH ;SET THE ACC FOR INTR LOOP
0017 90 MOVX @ R0, A ;START A/D
0018 96 18 LOOP: JNZ LOOP ;LOOP UNTIL INTR FROM A/D
001A 00 NOP ;GO TO USER’S PROGRAM
;
001B 00 CONT: NOP ;USER’S PROGRAM TO PROCESS
;CONVERTED DATA
;
;INTERRUPT ROUTINE STARTS
ORG 30H ;AT 30H
0030 80 INDATA: MOVX A, @ R0 ;INPUT CONVERTED DATA
0031 A1 MOV @ R1, A ;STORE IN DATA ADDRESS
0032 27 CLR A ;CLEAR ACC TO GET OUT OF
0033 93 RETR ;THE INTERRUPT LOOP
END

FIGURE 6. A/D Conversion Routine

ADDRESS DECODING
(OPTIONAL) A/D CONVERTER

MICROPROCESSOR

FIGURE 7. A/D Conversion Circuit TL/H/5632 – 4

5
Data Acquisition Using INS8048

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AN-281

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