PCM1742

www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma,

Audio Digital-to-Analog Converter
FEATURES APPLICATIONS
• 24-Bit Resolution • AV Receivers
• Analog Performance (VCC = 5 V): • DVD Movie Players
– Dynamic Range: • DVD Add-On Cards for High-End PCs
• 106 dB, Typical (PCM1742KE) • DVD Audio Players
• HDTV Receivers
• 100 dB, Typical (PCM1742E)
• Car Audio Systems
– SNR:
• Other Applications Requiring 24-Bit Audio
• 106 dB, Typical (PCM1742KE)
• 100 dB, Typical (PCM1742E) DESCRIPTION
– THD+N:
The PCM1742 is a CMOS, monolithic, integrated
• 0.002%, Typical (PCM1742KE) circuit which includes stereo digital-to-analog con-
• 0.003%, Typical (PCM1742E) verters (DACs) and support circuitry in a small
SSOP-16 package. The data converters use Texas
– Full-Scale Output: 3.1 Vp-p, Typical
Instruments' enhanced multilevel delta-sigma archi-
• 4x/8x Oversampling Digital Filter: tecture that employs fourth-order noise shaping and
Stop-Band Attenuation: –55 dB 8-level amplitude quantization to achieve excellent
Pass-Band Ripple: ±0.03 dB dynamic performance and improved tolerance to
• Sampling Frequency: 5 kHz to 200 kHz clock jitter. The PCM1742 accepts industry-standard
audio data formats with 16- to 24-bit data, providing
• System Clock: 128 fS, 192 fS, 256 fS, 384 fS, easy interfacing to audio DSP and decoder chips.
512 fS, 768 fS With Autodetect Sampling rates up to 200 kHz are supported. A full
• Accepts 16-, 18-, 20-, and 24-Bit Audio Data set of user-programmable functions is accessible
• Data Formats: Standard, I2S, and through a 3-wire serial control port that supports
Left-Justified register write functions.
• User-Programmable Mode Controls:
Digital Attenuation: 0 dB to –63 dB, 0.5
dB/Step
Digital De-Emphasis
Digital Filter Rolloff: Sharp or Slow
Soft Mute
Zero Flags for Each Output
• Dual-Supply Operation: 5-V Analog, 3.3-V
Digital
• 5-V Tolerant Digital Inputs
• Small SSOP-16 Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCM1742
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SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
Power supply voltage, VDD –0.3 V to 4 V
Power supply voltage, VCC –0.3 V to 6.5 V
Supply voltage difference, VCC, VDD VCC – VDD < 3 V
Ground voltage differences ±0.1 V
Digital input voltage –0.3 V to 6.5 V
Input current (except power supply pins) ±10 mA
Ambient temperature under bias –40°C to 125°C
Storage temperature, Tstg –55°C to 150°C
Junction temperature, TJ 150°C
Lead temperature (soldering) 260°C, 5 s
Package temperature (IR reflow, peak) 235°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range
MIN NOM MAX UNIT
Digital supply voltage, VDD 3 3.3 3.6 V
Analog supply voltage, VCC 4.5 5 5.5 V
Digital input logic family TTL
System clock 8.192 36.864 MHz
Digital input clock frequency
Sampling clock 32 192 kHz
Analog output load resistance 5 kΩ
Analog output load capacitance 50 pF
Digital output load capacitance 20 pF
Operating free-air temperature, TA –25 85 °C

ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
DATA FORMAT
Audio data interface formats Standard, I2S, left-justified
Audio data bit length 16-, 18-, 20-, 24-bit selectable
Audio data format MSB-first, binary 2s complement
fS Sampling frequency 5 200 kHz
System clock frequency 128, 192, 256, 384, 512, 768 fS
DIGITAL INPUT/OUTPUT
Logic family TTL compatible
Input Logic Level
VIH High-level input votlage 2 Vdc
VIL Low-level input voltage 0.8 Vdc

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ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Logic Current
IIH High-level input current (1) VIN = VDD 10 µA
IIL Low-level input current (1) VIN = 0 V –10 µA
IIH High-level input current (2) VIN = VDD 65 100 µA
IIL Low-level input current (2) VIN = 0 V –10 µA
Output Logic Level
VOH High-level output voltage (3) IOH = –2 mA 2.4 Vdc
VOL Low-level output voltage (3) IOL = 2 mA 1 Vdc
DYNAMIC PERFORMANCE (4) (5)
PCM1742E
VOUT = 0 dB, fS = 44.1 kHz 0.003% 0.008%
VOUT = 0 dB, fS = 96 kHz 0.004%
VOUT = 0 dB, fS = 192 kHz 0.005%
THD+N Total harmonic distortion + noise
VOUT = –60 dB, fS = 44.1 kHz 1.2%
VOUT = –60 dB, fS = 96 kHz 1.6%
VOUT = –60 dB, fS = 192 kHz 1.8%
EIAJ, A-weighted, fS = 44.1 kHz 94 100
Dynamic range A-weighted, fS = 96 kHz 98 dB
A-weighted, fS = 192 kHz 96
EIAJ, A-weighted, fS = 44.1 kHz 94 100
SNR Signal-to-noise ratio A-weighted, fS = 96 kHz 98 dB
A-weighted, fS = 192 kHz 96
fS = 44.1 kHz 91 98
Channel separation fS = 96 kHz 96 dB
fS = 192 kHz 94
Level linearity error VOUT = –90 dB ±0.5 dB

(1) Pins 1, 2, 3, 16 (SCK, BCK, LRCK, DATA).

(2) Pins 13–15 (MD, MC, ML).
(3) Pins 11, 12 (ZEROR, ZEROL).
(4) Analog performance specifications are tested with a Shibasoku #725 THD meter with 400-Hz HPF on, 30-kHz LPF on, and an average
mode with 20-kHz bandwidth limiting. The load connected to the analog output is 5 kΩ or larger, via capacitive coupling.
(5) Conditions in 192-kHz operation are: system clock = 128 fS and oversampling rate = 64 fS (under register control).

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ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PCM1742KE
VOUT = 0 dB, fS = 44.1 kHz 0.002% 0.006%
VOUT = 0 dB, fS = 96 kHz 0.003%
VOUT = 0 dB, fS = 192 kHz 0.004%
THD+N Total harmonic distortion + noise
VOUT = –60 dB, fS = 44.1 kHz 0.65%
VOUT = –60 dB, fS = 96 kHz 0.8%
VOUT = –60 dB, fS = 192 kHz 0.95%
EIAJ, A-weighted, fS = 44.1 kHz 100 106
Dynamic range A-weighted, fS = 96 kHz 104 dB
A-weighted, fS = 192 kHz 102
EIAJ, A-weighted, fS = 44.1 kHz 100 106
SNR Signal-to-noise ratio A-weighted, fS = 96 kHz 104 dB
A-weighted, fS = 192 kHz 102
fS = 44.1 kHz 97 103
Channel separation fS = 96 kHz 101 dB
fS = 192 kHz 100
Level linearity error VOUT = –90 dB ±0.5 dB
DC ACCURACY
Gain error ±1 ±6 % of FSR
Gain mismatch, channel-to-channel ±1 ±3 % of FSR
Bipolar zero error VOUT = 0.5 VCC at bipolar zero ±30 ±60 mV
ANALOG OUTPUT
Output voltage Full scale (0 dB) 0.62 VCC Vp-p
Center voltage 0.5 VCC Vdc
Load Impedance AC load 5 kΩ
DIGITAL FILTER PERFORMANCE
Filter Characteristics, Sharp Rolloff
Pass band ±0.03 dB 0.454 fS
Pass band –3 dB 0.487 fS
Stop band 0.546 fS
Pass-band ripple ±0.03 dB
Stop band = 0.546 fS –50
Stop-band attenuation dB
Stop band = 0.567 fS –55
Filter Characteristics, Slow Rolloff
Pass band ±0.5 dB 0.198 fS
Pass band –3 dB 0.39 fS
Stop band 0.884 fS
Pass-band ripple ±0.5 dB
Stop-band attenuation Stop band = 0.884 fS –40 dB
Delay time 20/fS s
De-emphasis error ±0.1 dB
ANALOG FILTER PERFORMANCE
f = 20 kHz –0.03
Frequency response dB
f = 44 kHz –0.20

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ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY REQUIREMENTS (6)

VDD 3 3.3 3.6

Voltage range Vdc
VCC 4.5 5 5.5
fS = 44.1 kHz 6 10
IDD Supply current fS = 96 kHz 13 mA
fS = 192 kHz 16
fS = 44.1 kHz 8.5 13
ICC Supply current fS = 96 kHz 9 mA
fS = 192 kHz 9
fS = 44.1 kHz 62 98
Power dissipation fS = 96 kHz 88 mW
fS = 192 kHz 98
TEMPERATURE RANGE
TA Operation temperature –25 85 °C
θJA Thermal resistance 115 °C/W

(6) Conditions in 192-kHz operation are: system clock = 128 fS and oversampling rate = 64 fS (under register control).

Functional Block Diagram

BCK

Audio
LRCK Serial Output Amp and VOUTL
DAC
Port Low−Pass F ilter

DATA 4x/8x
Oversampling Enhanced
Digital Filter Multilevel
with Delta−Sigma
VCOM
Function Modulator
ML
Controller

Serial Output Amp and

DAC
MC Control Low−Pass F ilter VOUTR
Port

MD

System Clock

System Clock
SCK Zero Detect Power Supply
M anager
ZEROL

ZEROR

VDD
DGND

VCC
AGND

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PIN ASSIGNMENTS
PCM1742DBQ PACKAGE
(TOP VIEW)

BCK 1 16 SCK

DATA 2 15 ML

LRCK 3 14 MC

DGND 4 13 MD
PCM1742
VDD 5 12 ZEROL/NA

VCC 6 11 ZEROR/ZEROA

VOUTL 7 10 VCOM

VOUTR 8 9 AGND

TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
AGND 9 – Analog ground
BCK 1 I Audio data bit clock input (1)

DATA 2 I Audio data digital input (1)

DGND 4 – Digital ground

LRCK 3 I L-channel and R-channel audio-data latch-enable input (1)

MC 14 I Mode control clock input (2)

MD 13 I Mode control data input (2)

ML 15 I Mode control latch input (2)

SCK 16 I System clock input (1)

VCC 6 – Analog power supply, 5 V

VCOM 10 – Common voltage decoupling
VDD 5 – Digital power supply, 3.3 V
VOUTL 7 O Analog output for L-channel
VOUTR 8 O Analog output for R-channel
ZEROL/NA 12 O Zero-flag output for L-channel/No assign
ZEROR/ZEROA 11 O Zero-flag output for R-channel/Zero-flag output for L-/R-channel

(1) Schmitt-trigger input, 5-V tolerant.

(2) Schmitt-trigger input with internal pulldown, 5-V tolerant.

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TYPICAL PERFORMANCE CURVES

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless
otherwise noted

Digital Filter (De-Emphasis Off)

FREQUENCY RESPONSE (SHARP ROLLOFF) PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF)

0 0.05
0.04
−20
0.03
−40 0.02

Amplitude (dB)
Amplitude (dB)

0.01
−60
0
−80 −0.01

−100 −0.02
−0.03
−120
−0.04
−140 −0.05
0 1 2 3 4 0 0.1 0.2 0.3 0.4 0.5
Frequency (x fS ) Frequency (x fS)

Figure 1. Figure 2.

FREQUENCY RESPONSE (SLOW ROLLOFF) TRANSITION CHARACTERISTICS (SLOW ROLLOFF)

0 5
4
−20
3
−40 2
Amplitude (dB)

Amplitude (dB)

1
−60
0
−80 −1

−100 −2
−3
−120
−4

−140 −5
0 1 2 3 4 0 0.1 0.2 0.3 0.4 0.5
Frequency (x fS ) Frequency (x fS )

Figure 3. Figure 4.

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SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless
otherwise noted

Digital Filter (De-Emphasis)

DE-EMPHASIS (fS = 32 kHz) DE-EMPHASIS ERROR (fS = 32 kHz)

0.0 0.5
−1.0 0.4
−2.0 0.3
−3.0 0.2
−4.0 0.1
Level (dB)

Error (dB)
−5.0 0.0
−6.0 −0.1
−7.0 −0.2
−8.0 −0.3
−9.0 −0.4
−10.0 −0.5
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
Frequency (kHz) Frequency (kHz)

Figure 5. Figure 6.

DE-EMPHASIS (fS = 44.1 kHz) DE-EMPHASIS ERROR (fS = 44.1 kHz)

0.0 0.5
−1.0 0.4
−2.0 0.3
−3.0 0.2
−4.0 0.1
Level (dB)

Error (dB)

−5.0 0.0
−6.0 −0.1
−7.0 −0.2
−8.0 −0.3
−9.0 −0.4
−10.0 −0.5
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
Frequency (kHz) Frequency (kHz)

Figure 7. Figure 8.

DE-EMPHASIS (fS = 48 kHz) DE-EMPHASIS ERROR (fS = 48 kHz)

0.0 0.5
−1.0 0.4
−2.0 0.3
−3.0 0.2
−4.0 0.1
Level (dB)

Error (dB)

−5.0 0.0
−6.0 −0.1
−7.0 −0.2
−8.0 −0.3
−9.0 −0.4
−10.0 −0.5
0 2 4 6 8 10 12 14 16 18 22 0 2 4 6 8 10 12 14 16 18 22
Frequency (kHz) Frequency (kHz)

Figure 9. Figure 10.

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TYPICAL PERFORMANCE CURVES (continued)

ANALOG DYNAMIC PERFORMANCE

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise specified. Conditions in
192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS (under register control).

Supply Voltage Characteristics

TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE

vs vs
VCC (VDD = 3.3 V) VCC (VDD = 3.3 V)
10 110
− 60dB/192kHz, 384f S
− 60dB/96kHz, 384fS
108
1 44.1kHz, 384fS

Dynamic Range (dB)

106
96kHz, 384fS
− 60dB/44.1kHz, 384f S
0.1
THD+N (%)

104
192kHz, 384fS
0dB/192kHz, 384fS 102
0.01 0dB/96kHz, 384fS

100
0.001
0dB/44.1kHz, 384fS 98

0.0001 96
4 4.5 5 5.5 6 4 4.5 5 5.5 6
VCC (V) VCC (V)

Figure 11. Figure 12.

SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION

vs vs
VCC (VDD = 3.3 V) VCC (VDD = 3.3 V)
110 110

108 44.1kHz, 384fS 108

Channel Separation (dB)

106 96kHz, 384fS 106

44.1kHz, 384fS
SNR (dB)

104 104

102 192kHz, 384fS 102

96kHz, 384fS
100 100
192kHz, 384fS
98 98

96 96
4 4.5 5 5.5 6 4 4.5 5 5.5 6
VCC (V) VCC (V)

Figure 13. Figure 14.

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TYPICAL PERFORMANCE CURVES (continued)

ANALOG DYNAMIC PERFORMANCE (continued)

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise specified. Conditions in
192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS (under register control).

Temperature Characteristics

TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE

vs vs
TEMPERATURE (TA) TEMPERATURE (TA)
10 110
−60dB/192kHz, 384f S
−60dB/96kHz, 384f S 108
1 44.1kHz, 384fS
106

Dynamic Range (dB)

96kHz, 384fS
0.1 −60dB/44.1kHz, 384fS
THD+N (%)

104
192kHz, 384fS
0dB/192kHz, 384fS
0dB/96kHz, 384fS 102
0.01
100
0.001
0dB/44.1kHz, 384f S 98

0.0001 96
−50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100
Temperature (°C) Temperature (°C)

Figure 15. Figure 16.

SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION

vs vs
TEMPERATURE (TA) TEMPERATURE (TA)
110 110

108 108
44.1kHz, 384fS
Channel Separation (dB)

106 106
96kHz, 384fS
44.1kHz, 384fS
SNR (dB)

104 104

102 192kHz, 384fS 102 96kHz, 384fS

100 100
192kHz, 384fS
98 98

96 96
−50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100
Temperature (°C) Temperature (°C)

Figure 17. Figure 18.

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SYSTEM CLOCK AND RESET FUNCTIONS

SYSTEM CLOCK INPUT

The PCM1742 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. The PLL1700 multiclock generator from Texas Instruments is
an excellent choice for providing the PCM1742 system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
128 fS 192 fS 256 fS 384 fS 512 fS 768 fS
8 kHz (1) (1) 2.048 3.072 4.096 6.144
16 kHz (1) (1) 4.096 6.144 8.192 12.288
32 kHz (1) (1) 8.192 12.288 16.384 24.576
44.1 kHz (1) (1) 11.2896 16.9344 22.5792 33.8688
48 kHz (1) (1) 12.288 18.432 24.576 36.864
88.2 kHz (1) (1) 22.5792 33.8688 45.1584 (1)

96 kHz (1) (1) 24.576 36.864 49.152 (1)

192 kHz 24.576 36.864 (1) (1) (1) (1)

(1) This system clock is not supported for the given sampling frequency.

t SCKH

H 2V

System Clock
L 0.8 V

t SCKL t SCKY

SYMBOL DESCRIPTION MIN MAX UNIT

tSCKY System clock cycle time (1) 20 ns
tSCKH System clock pulse duration, HIGH 7 ns
tSCKL System clock pulse duration, LOW 7 ns

(1) 1/128 fS, 1/192 fS, 1/256 fS, 1/384 fS, 1/512 fS, or 1/768 fS
Figure 19. System Clock Input Timing

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POWER-ON RESET FUNCTIONS

The PCM1742 includes a power-on-reset function, as shown in Figure 20. With the system clock active and VDD
> 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires 1024
system clocks from the time VDD > 2 V. After the initialization period, the PCM1742 is set to its reset default
state, as described in the Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level, or VCC/2.
After the reset period, all the mode control registers are initialized in the next 1/fS period and, if SCK, BCK, and
LRCK are provided continuously, the PCM1742 provides proper analog output with group delay corresponding to
the input data.

2.4V
VDD 2.0V
1.6V
0V

Reset Reset Removal

Internal Reset

Don’t Care 1024 System Clocks

System Clock

Figure 20. Power-On-Reset Timing

AUDIO SERIAL INTERFACE

The audio serial interface for the PCM1742 comprises a 3-wire synchronous serial port. It includes LRCK (pin 3),
BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit clock, which is used to clock the serial data present on
DATA into the audio interface serial shift register. Serial data is clocked into the PCM1742 on the rising edge of
BCK. LRCK is the serial audio left/right word clock used to latch serial data into the serial audio interface internal
registers.
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK
be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can be
operated at 32 (16-bit, right-justified only), 48, or 64 times the sampling frequency. Internal operation of the
PCM1742 is synchronized with LRCK. Accordingly, internal operation of the device is suspended when the
sampling rate clock of LRCK is changed or SCK and/or BCK is interrupted at least for three bit-clock cycles. If
SCK, BCK, and LRCK are provided continuously after this suspended state, the internal operation is
resynchronized automatically within a period of less than 3/fS. During this resynchronization period and for a 3/fS
time thereafter, the analog output is forced to the bipolar zero level, or VCC/2. External resetting is not required.

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AUDIO DATA FORMATS AND TIMING

The PCM1742 supports industry-standard audio data formats, including standard, I2S, and left-justified, as shown
in Figure 21. Data formats are selected using the format bits, FMT[2:0], in control register 20. The default data
format is 24-bit, left-justified. All formats require binary 2s complement, MSB-first audio data. See Figure 22 for a
detailed timing diagram of the serial audio interface.
(1) Sta nd ard D ata Fo rm at: L −C h an n el = H IG H , R−C ha nn el = L O W
1/fS

LRCK R−Channel
L−Channel

BCK
(= 32, 48 or 64fS )

16−Bit Right−Justified, BCK = 48fS or 64f S

DATA 14 15 16 1 2 3 14 15 16 1 2 3 14 15 16

MSB LSB MSB LSB

16−Bit Right−Justified, BCK = 32fS

DATA 14 15 16 1 2 3 14 15 16 1 2 3 14 15 16

MSB LSB MSB LSB

18−Bit Right−Justified

DATA 16 17 18 1 2 3 16 17 18 1 2 17 18

MSB LSB MSB LSB

20−Bit Right−Justified

DATA 18 19 20 1 2 3 18 19 20 1 2 3 18 19 20

MSB LSB MSB LSB

24−Bit Right−Justified
DATA 22 23 24 1 2 3 22 23 24 1 2 3 22 23 24

MSB LSB MSB LSB

2
(2) I S D ata Fo rm at: L −C h an n el = L O W , R −Ch an nel = H IG H
1/fS

LRCK
L−Channel
R−Channel

BCK
(= 48 or 64fS )

DATA 1 2 3 N−2 N−1 N 1 2 3 N−2 N−1 N 1 2

MSB LSB MSB LSB

(3) L eft−Ju stified D ata Fo rm at: L−C han nel = H IG H , R −C h ann el = L O W

1/fS

L−Channel
LRCK

R−Channel
BCK
(= 48 or 64fS )

DATA 1 2 3 N−2 N−1 N 1 2 3 N−2 N−1 N 1 2

MSB LSB MSB LSB

Figure 21. Audio Data Input Formats

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LRCK 50% of VDD

tBCH tBCL t LB
BCK 50% of VDD

tBCY tBL

DATA 50% of VDD

tDS t DH

SYMBOL DESCRIPTION MIN MAX UNIT

tBCY BCK pulse cycle time 1/(64 fS)(1)
tBCH BCK high-level time 35 ns
tBCL BCK low-level time 35 ns
tBL BCK rising edge to LRCK edge 10 ns
tLB LRCK falling edge to BCK rising edge 10 ns
tDS DATA setup time 10 ns
tDH DATA hold time 10 ns

(1) fS is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.).

Figure 22. Audio Interface Timing

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SERIAL CONTROL INTERFACE

The serial control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. The
serial control interface is used to program the on-chip mode registers. The serial control interface includes
MD (pin 13), MC (pin 14), and ML (pin 15). MD is the serial data input, used to program the mode registers; MC
is the serial bit clock, used to shift data into the control port; and ML is the control-port latch clock.

REGISTER WRITE OPERATION

All write operations for the serial control port use 16-bit data words. Figure 23 shows the control data word
format. The most significant bit must be a 0. Seven bits, labeled IDX[6:0], set the register index (or address) for
the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified
by IDX[6:0].
MSB LSB
0 IDX 6 IDX 5 IDX 4 IDX3 IDX 2 IDX 1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0

Register Index (or Address) Register Data

Figure 23. Control Data Word Format for MD

Figure 24 shows the functional timing diagram for writing to the serial control port. ML is held at a logic-1 state
until a register needs to be written. To start the register write cycle, ML is set to logic-0. Sixteen clocks are then
provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has
completed, ML is set to logic-1 to latch the data into the indexed mode control register.

ML

MC

MD X 0 IDX6 IDX 5 IDX 4 IDX3 IDX 2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 IDX 6

Figure 24. Register Write Operation

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CONTROL INTERFACE TIMING REQUIREMENTS

See Figure 25 for a detailed timing diagram of the serial control interface. These timing parameters are critical for
proper control port operation.
tMHH

ML 50% of V D D

tMCH tMCL
tM L S tMLH

MC 50% of V D D

tMCY
LSB

MD 50% of V D D

tMDS t MDH

SYMBOL PARAMETER MIN TYP MAX UNIT

tMCY MC pulse cycle time 100 ns
tMCL MC low-level time 50 ns
tMCH MC high-level time 50 ns
tMHH ML high-level time 3/(256 × fS) (2) ns
tMLS ML falling edge to MC rising edge 20 ns
tMLH ML hold time(1) 20 ns
tMDH MD hold time 15 ns
tMDS MD setup time 20 ns

(1) MC rising edge for LSB to ML rising edge

(2) fS = sampling rate

Figure 25. Control Interface Timing

MODE CONTROL REGISTERS

User-Programmable Mode Controls

The PCM1742 includes a number of user-programmable functions that are accessed via control registers. The
registers are programmed using the serial control interface that is discussed in a preceding section of this data
sheet. Table 2 lists the available mode control functions, along with their reset default conditions and associated
register index.

Table 2. User-Programmable Mode Controls

FUNCTION RESET DEFAULT CONTROL INDEX IDX[6:0]
REGISTER
Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps 0 dB, no attenuation 16 and 17 AT1[7:0], AT2[7:0]
Soft mute control Mute disabled 18 MUT[2:0]
Oversampling rate control (64 fS or 128 fS) 64-fS oversampling 18 OVER
DAC operation control DAC1 and DAC2 enabled 19 DAC[2:1]
De-emphasis function control De-emphasis disabled 19 DM12
De-emphasis sample rate selection 44.1 kHz 19 DMF[1:0]
Audio data format control 24-bit, left-justified 20 FMT[2:0]
Digital filter rolloff control Sharp rolloff 20 FLT
Zero-flag function select L-/R-channels independent 22 AZRO
Output phase select Normal phase 22 DREV
Zero-flag polarity select High 22 ZREV

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Register Map
The mode control register map is shown in Table 3. Each register includes an index (or address) indicated by the
IDX[6:0] bits.

Table 3. Mode Control Register Map

IDX REGIS- B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(B14–B8) TER
10h 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
11h 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
12h 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) OVER RSV (1) RSV (1) RSV (1) RSV (1) MUT2 MUT1
13h 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) DMF1 DMF0 DM12 RSV (1) RSV (1) DAC2 DAC1
14h 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) RSV (1) FLT RSV (1) RSV (1) FMT2 FMT1 FMT0
15h 21 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1)
16h 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) AZRO ZREV DREV

(1) RSV: Reserved for test operation. It should be set to 0 during normal operation.

REGISTER DEFINITIONS
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10

REGISTER 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20

ATx[7:0] – Digital Attenuation Level Setting

where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default value: 1111 1111b
Each DAC channel (VOUTL and VOUTR) includes a digital attenuator function. The attenuation level can be set
from 0 dB to –63 dB, in 0.5-dB steps. Changes in attenuation levels are made by incrementing or decrementing,
by one step (0.5 dB), for every 8/fS time interval until the programmed attenuator setting is reached. Alternatively,
the attenuation level can be set to infinite attenuation, or mute. The attenuation data for each channel can be set
individually.
The attenuation level is calculated using the following formula:

Attenuation level (dB) = 0.5 (ATx[7:0]DEC – 255)

where: ATx[7:0]DEC = 0 through 255
for: ATx[7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings.
ATx[7:0] DECIMAL VALUE ATTENUATOR LEVEL SETTING
1111 1111b 255 0 dB, no attenuation (default)
1111 1110b 254 –0.5 dB
1111 1101b 253 –1 dB
: : :
1000 0011b 131 –62 dB
1000 0010b 130 –62.5 dB
1000 0001b 129 –63 dB
1000 0000b 128 Mute
: : :
0000 0000b 0 Mute

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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

REGISTER 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV OVER RSV RSV RSV RSV MUT2 MUT1

MUTx – Soft Mute Control

where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default value: 0
MUTx = 0 Mute disabled (default)
MUTx = 1 Mute enabled

The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC
outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is
disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the
digital attenuator for the corresponding output is decreased from the current setting to the infinite attenuation
setting by one attenuator step (0.5 dB) at a time for every 8/fS period. This provides a pop-free muting of the
DAC output.
By setting MUTx = 0, the attenuator is increased by one step for every 8/fS period to the previously programmed
attenuation level.

OVER – Oversampling Rate Control

Default value: 0
System clock rate = 256 fS, 384 fS, 512 fS, or 768 fS
OVER = 0 64× oversampling (default)
OVER = 1 128× oversampling

System clock rate = 128 fS or 192 fS

OVER = 0 32× oversampling (default)
OVER = 1 64× oversampling

The OVER bit is used to control the oversampling rate of the delta-sigma DACs. The OVER = 1 setting is
recommended when the oversampling rate is 192 kHz (system clock is 128 fS or 192 fS).

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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

REGISTER 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1

DACx – DAC Operation Control

where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2).
Default value: 0
DACx = 0 DAC operation enabled (default)
DACx = 1 DAC operation disabled

The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR. When DACx =
0, the corresponding output generates the audio waveform dictated by the data present on the DATA pin. When
DACx = 1, the corresponding output is set to the bipolar zero level, or VCC/2.

DM12 – Digital De-Emphasis Function Control

Default value: 0
DM12 = 0 De-emphasis disabled (default)
DM12 = 1 De-emphasis enabled

The DM12 bit is used to enable or disable the digital de-emphasis function. Refer to the Typical Performance
Curves section of this data sheet for more information.

DMF[1:0] – Sampling Frequency Selection for the De-Emphasis Function

Default value: 00
DMF[1:0] De-Emphasis Sample Rate Selection
00 44.1 kHz (default)
01 48 kHz
10 32 kHz
11 Reserved

The DMF[1:0] bits select the sampling frequency used for the digital de-emphasis function when it is enabled.

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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

REGISTER 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0

FMT[2:0] – Audio Interface Data Format

Default value: 101
The FMT[2:0] bits are used to select the data format for the serial audio interface. The following table shows the
available format options.
FMT[2:0] Audio Data Format Selection
000 24-bit standard format, right-justified data
001 20-bit standard format, right-justified data
010 18-bit standard format, right-justified data
011 16-bit standard format, right-justified data
100 I2S format, 16- to 24-bit
101 Left-justified format, 16- to 24-bit (default)
110 Reserved
111 Reserved

FLT – Digital Filter Rolloff Control

Default value: 0
FLT = 0 Sharp rolloff (default)
FLT = 1 Slow rolloff

The FLT bit allows the user to select the digital filter rolloff that is best suited to their application. Two filter rolloff
selections are available: sharp or slow. The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.

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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

REGISTER 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV AZRO ZREV DREV

DREV – Output Phase Select

Default value: 0
DREV = 0 Normal output (default)
DREV = 1 Inverted output

The DREV bit is used to set the output phase of VOUTL and VOUTR.

ZREV – Zero-Flag Polarity Select

Default value: 0
ZREV = 0 Zero-flag pins HIGH at a zero detect (default)
ZREV = 1 Zero-flag pins LOW at a zero detect

The ZREV bit allows the user to select the active polarity of zero-flag pins.

AZRO – Zero-Flag Function Select

Default value: 0
AZRO = 0 L-/R-channel independent zero flags (default) Pin 11: ZEROR; zero-flag output for R-channel
Pin 12: ZEROL; zero flag output for L-channel
AZRO = 1 L-/R-channel common zero flag Pin 11: ZEROA; zero flag output for L-/R-channel
Pin 12: NA; not assigned

The AZRO bit allows the user to select the function of the zero-flag pins

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ANALOG OUTPUTS
The PCM1742 includes two independent output channels: VOUTL and VOUTR. These are unbalanced outputs,
each capable of driving 3.1 Vp-p typical into a 5-kΩ ac-coupled load. The internal output amplifiers for VOUTL and
VOUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to VCC/2.
The output amplifiers include an RC continuous-time filter that helps to reduce the out-of-band noise energy
present at the DAC outputs, due to the noise shaping characteristics of the PCM1742 delta-sigma DACs. The
frequency response of this filter is shown in Figure 26. By itself, this filter is not enough to attenuate the
out-of-band noise to an acceptable level for many applications; therefore, an external low-pass filter is required to
provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the
Applications Information section of this data sheet.

−10
Response (dB)

−20

−30

−40

−50

−60
0.1 1 10 100 1K 10K
Frequency (kHz)

Figure 26. Output Filter Frequency Response

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VCOM OUTPUT
One unbuffered common-mode voltage output pin, VCOM (pin 10), is brought out for decoupling purposes. This
pin is nominally biased to a dc voltage level equal to VCC/2. This pin can be used to bias external circuits. An
example of using the VCOM pin for external biasing applications is shown in Figure 27.

R2
AV = −1, where AV = −
R2 C1 R1
P C M 17 4 2 VCC
10µF R1 R3
2
VOUTx
+ 1/2 1 Filtered
C2 OP A2353
3 Output

VCOM
+
10µF
x = L or R

(a) Using VCOM to Bias a Single−Supply Filter Stage

VCC
P C M 1 74 2

Buffered
OPA337
VCOM
VCOM
+
10µ F

(b) Using a Voltage Follower to Buffer VCOM When Biasing Multiple Nodes

V+
VCC

49.9kΩ 25kΩ SENSE

P C M 17 4 2 1%
25kΩ
−IN
VOUTx
OUT To Low−Pass
25kΩ Filter Stage
+IN
VCOM
+
10µF 25kΩ
REF
INA134
x = L or R

V−

(c) Using an INA134 for DC−Coupled Output

Figure 27. Biasing External Circuits Using the VCOM Pin

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ZERO FLAGS

Zero-Detect Condition
Zero detection for each output channel is independent from the other. If the data for a given channel remains at a
0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.

Zero Output Flags

Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are set
to a logic-1 state. The zero-flag pins for each channel are ZEROL (pin 12) and ZEROR (pin 11). These pins can
be used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal
processor, or other digitally controlled function.
The active polarity of the zero-flag output can be inverted by setting the ZREV bit of control register 22 to 1. The
reset default is active-high output, or ZREV = 0.
The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22
to 1. The reset default is L-channel and R-channel independent zero flag, or AZRO = 0.

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APPLICATION INFORMATION

Connection Diagram
A basic connection diagram is shown in Figure 28, with the necessary power-supply bypassing and decoupling
components. Texas Instruments recommends using the component values shown in Figure 28 for all designs.

1 BCK SCK 16 System Clock

PCM
Audio Data 2 DATA ML 15
Input
Mode
3 LRCK MC 14
Control
4 DGND MD 13
10µF
+ 5 VDD
+3.3V ZEROL/NA 12
Zero Mute
Regulator
6 VCC ZEROR/ZEROA 11 Control

7 VOUTL VCOM 10

+
+
10µF 10µF
8 VOUTR AGND 9
+5V VCC

Post LPF Post LPF

L−Chan OUT R−Chan OUT

Figure 28. Basic Connection Diagram

The use of series resistors (22 Ω to 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs. The
series resistor combines with stray PCB and device input capacitance to form a low-pass filter that reduces
high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines.

Power Supplies and Grounding

The PCM1742 requires a 5-V analog supply (VCC) and a 3.3-V digital supply (VDD). The 5-V supply is used to
power the DAC analog and output-filter circuitry, while the 3.3-V supply is used to power the digital filter and
serial interface circuitry. For best performance, the 3.3-V supply should be derived from the 5-V supply using a
linear regulator, as shown in Figure 28. The REG1117-3.3 from Texas Instruments is an ideal choice for this
application.
Proper power-supply bypassing is shown in Figure 28. The 10-µF capacitors should be tantalum or aluminum
electrolytic.

DAC Output Filter Circuits

Delta-sigma DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at
the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band
noise must be low-pass filtered in order to provide the optimal converter performance. This is accomplished by a
combination of on-chip and external low-pass filtering.
Figure 27(a) and Figure 29 show the recommended external low-pass active filter circuits for single- and
dual-supply applications. These circuits are second-order Butterworth filters using a multiple feedback (MFB)
circuit arrangement that reduces sensitivity to passive component variations over frequency and temperature. For
more information regarding MFB active filter design, see FilterPro™ MFB and Sallen-Key Low-Pass Filter Design
Program (SBFA001), available from the TI Web site at http://www.ti.com.

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APPLICATION INFORMATION (continued)

R2
AV ≈ −
R1
R2 C1
R1 R3
2
VIN R4
1
OP A2 134 VOUT
3
C2

Figure 29. Dual-Supply Filter Circuit

Because the overall system performance is defined by the quality of the DACs and their associated analog
output circuitry, high-quality audio operational amplifiers are recommended for the active filters. The OPA2353
and OPA2134 dual operational amplifiers from Texas Instruments are recommended for use with the PCM1742;
see Figure 27(a) and Figure 29.

PCB LAYOUT GUIDELINES

A typical PCB floor plan for the PCM1742 is shown in Figure 30. A ground plane is recommended, with the
analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1742
should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections
to the digital audio interface and control signals originating from the digital section of the board.
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the PCM1742. In cases where a common 5-V supply must be used for the analog and
digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V
supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 31 shows the
recommended approach for single-supply applications.

Digital Power Analog Power

+VD DGND AGND +5VA +VS −VS

REG

VCC

VDD
Digital Logic
and DGND Output
Audio Circuits
Processor PCM1742 Digital
Ground
AGND

Analog
DIGITAL SECTION ANALOG SECTION
Ground

Return Path for Digital Signals

Figure 30. Recommended PCB Layout

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APPLICATION INFORMATION (continued)

Power Supplies

RF Choke or Ferrite Bead +5V AGND +VS −VS

REG

VDD VCC

Digital Logic VDD

and DGND Output
Audio Circuits
Processor PCM1742

AGND
Common
Ground
DIGITAL SECTION ANALOG SECTION

Figure 31. Single-Supply PCB Layout

THEORY OF OPERATION

The delta-sigma section of the PCM1742 is based on an 8-level amplitude quantizer and a fourth-order noise
shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the
8-level delta-sigma modulator is shown in Figure 32. This 8-level delta-sigma modulator has the advantage of
stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined
oversampling rate of the delta-sigma modulator and the interpolation filter is 64 fS.
The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 33. The
enhanced multilevel delta-sigma architecture also has advantages for input clock-jitter sensitivity due to the
multilevel quantizer, with the simulated jitter sensitivity, as shown in Figure 34.

−
+

8fS + Z−1 + Z−1 + Z−1 + Z−1

8−Level Quantizer

64fS

Figure 32. 8-Level Delta-Sigma Modulator

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THEORY OF OPERATION (continued)

QUANTIZATION NOISE SPECTRUM QUANTIZATION NOISE SPECTRUM

(64x Oversampling) (128x Oversampling)
0 0

− 20 − 20
− 40 − 40
Amplitude (dB)

Amplitude (dB)
− 60 − 60
− 80 − 80
− 100 − 100
− 120 − 120

− 140 − 140
− 160 − 160
− 180 − 180
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Frequency (fS) Frequency (f S)

Figure 33. Quantization Noise Spectrum

JITTER DEPENDENCE (64x Oversampling)

125

120
Dynamic Range (dB)

115

110

105

100

95

90
0 100 200 300 400 500 600
Jitter (ps)

Figure 34. Jitter Sensitivity

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KEY PERFORMANCE PARAMETERS AND MEASUREMENT

This section provides information on how to measure key dynamic performance parameters for the PCM1742. In
all cases, a System Two™ Cascade audio measurement system by Audio Precision™ or equivalent audio
measurement system is used to perform the testing.

Total Harmonic Distortion + Noise

Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio DACs, because it takes into
account both harmonic distortion and all noise sources within a specified measurement bandwidth. The true rms
value of the distortion and noise is referred to as THD+N. Figure 35 shows the test setup for THD+N
measurements.
For the PCM1742, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at the input
of the DAC. The digital generator is set to a 24-bit audio word length and a sampling frequency of 44.1 kHz or 96
kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurement system.
The S/PDIF data is transmitted via a coaxial cable to the digital audio receiver on the DEM-DAI1742
demonstration board. The receiver is then configured to output 24-bit data in either I2S or left-justified data
format. The DAC audio interface format is programmed to match the receiver output format. The analog output is
then taken from the DAC post filter and connected to the analog analyzer input of the measurement system. The
analog input is band-limited using filters resident in the analyzer. The resulting THD+N is measured by the
analyzer and displayed by the measurement system.
Evaluation Board

DEM−DAI1742

2nd−Order
S/PDIF
PCM1742 Low−Pass
Receiver
Filter

f− 3dB = 54kHz or 108kHz

Digital Analyzer 20kHz

Generator and Apogee
S/PDIF Display Filter Band Limit Notch Filter
Output
0dBFS, rms Mode HPF = 22Hz f C = 1kHz
1kHz Sine Wave LPF = 30kHz

Figure 35. Test Setup for THD+N Measurements

Dynamic Range
Dynamic range is specified as A-weighted, THD+N measured with a –60-dBFS, 1-kHz digital sine wave stimulus
at the input of the DAC. This measurement is designed to give a good indicator of the DAC performance given a
low-level input signal.
The measurement setup for the dynamic range measurement is shown in Figure 36 and is similar to the THD+N
test setup discussed previously. The differences include the band limit filter selection, the additional A-weighting
filter, and the –60-dBFS input level.

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KEY PERFORMANCE PARAMETERS AND MEASUREMENT (continued)

Evaluation Board

DEM−DAI1742

2nd−Order
S/PDIF PCM1742(1)
Low−Pass
Receiver
Filter

f− 3dB = 54kHz or 108kHz

Analyzer
Digital A−Weight
and
Generator Filter(2)
S/PDIF Display Band Limit Notch Filter
Output
0% Full−Scale, rms Mode HPF = 22Hz fC = 1kHz
Dither Off (SNR) LPF = 22kHz
− 60dBFS,
1kHz Sine Wave
(Dynamic Range)

(1) Infinite-zero-detect mute disabled

(2) Results without A-weighting are approximately 3 dB worse.

Figure 36. Test Setup Dynamic Range and SNR Measurements

Idle-Channel Signal-to-Noise Ratio

The SNR test provides a measure of the noise floor of the DAC. The input to the DAC is all-0s data, and the
DAC infinite-zero-detect mute function must be disabled (default condition at power up for the PCM1742). This
ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if
present) can be observed and affect the SNR measurement. The dither function of the digital generator must
also be disabled to ensure an all-0s data stream at the input of the DAC. The measurement setup for SNR is
identical to that used for dynamic range, with the exception of the input signal level (see the notes provided in
Figure 36).

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REVISION HISTORY
DATE REV PAGE SECTION DESCRIPTION
Apr 2005 A – Global Changed to new format
2 Absolute Maximum Ratings Changed values for power supply voltage, digital input voltage, lead
temperature, and package temperature. Added supply voltage
difference, VCC – VDD < 3 V.
2 Electrical Characteristics Corrected maximum sampling frequency from 100 kHz to 200 kHz.
Added new values of 128 fS and 192 fS for system clock frequency.
2 Package/Ordering Information Table removed from page 2, reformatted, and appended at end of
data sheet.
2 Recommended Operating Con- New table added to data sheet.
ditions
6 Pin Assignments and Terminal Moved from page 4
Functions
9, 10 Typical Performance Curves In Figure 11, corrected Y-axis scale and X-axis scale.
In Figure 15, corrected frequency from 96 kHz to 192 kHz on graph
label.
11 System Clock Input In Figure 19, added 1/128 fS and 1/192 fS to note for clock cycle
time.
13, 14 Audio Data Formats and Timing In Figure 21, Audio Data Input Formats, removed 32-fS availability
from left-justified format. In Figure 22, Audio Interface Timing,
corrected specification for BCK pulse cycle time.
17 Register Map For Table 3, Mode Control Register Map, added note to explain the
RSV table entry.
18 Register Definitions For MUTx – Soft Mute Control, added description about in-
crementing/decrementing attenuation level by one step for every
8/fS period.
25 Connection Diagram In Figure 28, corrected capacitor polarity for VDD decoupling
capacitor.
26, 27 PCB Layout Guidelines In Figure 30 and Figure 31, deleted extraneous signal lines. In
Figure 31, changed leftmost block to Digital Logic and Audio
Processor.
30 Dynamic Range Corrected parameters in test setup diagram, Figure 36.

31
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

PCM1742E ACTIVE SSOP DBQ 16 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 PCM
& no Sb/Br) 1742E
PCM1742E/2K ACTIVE SSOP DBQ 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 PCM
& no Sb/Br) 1742E
PCM1742KE ACTIVE SSOP DBQ 16 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 PCM
& no Sb/Br) 1742KE
PCM1742KE/2K ACTIVE SSOP DBQ 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 PCM
& no Sb/Br) 1742KE
PCM1742KE/2KG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 85 PCM
& no Sb/Br) 1742KE

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1742E/2K SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PCM1742KE/2K SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1742E/2K SSOP DBQ 16 2000 367.0 367.0 35.0
PCM1742KE/2K SSOP DBQ 16 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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