Unit 02 – Advanced Microprocessor

1. Features of 80386
 The 80386 microprocessor is an enhanced version of the 80286 microprocessor
 Memory-management unit is enhanced to provide memory paging.
 The 80386 also includes 32-bit extended registers and a 32-bit address and data bus. These
extended registers include EAX, EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and EFLAGS.
 The 80386 has a physical memory size of 4GBytes that can be addressed as a virtual
memory with up to 64TBytes.
 The 80386 is operated in the pipelined mode, it sends the address of the next instruction
or memory data to the memory system prior to completing the execution of the current
instruction
 This allows the memory system to begin fetching the next instruction or data before the
current is completed. This increases access time.
 The instruction set of the 80386 is enhanced to include instructions that address the 32-
bit extended register set.
 The 80386 memory manager is similar to the 80286, except the physical addresses
generated by the MMU are 32 bits wide instead of 24-bits.
 The concept of paging is introduced in 80386
 80386 support three operating modes:
1) Real Mode (default)
2) Protected Virtual Address Mode (PVAM)
3) Virtual Mode
 The memory management section of 80386 supports virtual memory, paging and four
levels of protection.
 The 80386 includes special hardware for task switching.
2. 80386 Architecture
 The internal architecture of the 80386 includes six functional units that operate in
parallel. The parallel operation is called as pipeline processing.
 Fetching, decoding execution, memory management, and bus access for several
instructions are performed simultaneously.
 The six functional units of the 80386 are
1) Bus Interface Unit
2) Code Pre-fetch Unit
3) Instruction Decoder Unit
4) Execution Unit
5) Segmentation Unit
6) Paging Unit
 Figure: 80386 Architecture
 The Bus Interface Unit connects the 80386 with memory and I/O. Based on internal
requests for fetching instructions and transferring data from the code pre-fetch unit, the
80386 generates the address, data and control signals for the current bus cycles.
 The code pre-fetch unit pre-fetches instructions when the bus interface unit is not
executing the bus cycles. It then stores them in a 16-byte instruction queue for decoding
by the instruction decode unit.
 The instruction decode unit translates instructions from the pre-fetch queue into micro-
codes. The decoded instructions are then stored in an instruction queue (FIFO) for
processing by the execution unit.
 The execution unit processes the instructions from the instruction queue. It contains a
control unit, a data unit and a protection test unit.
 The control unit contains microcode and parallel hardware for fast multiply, divide and
effective address calculation. The unit includes a 32-bit ALU, 8 general purpose
registers and a 64-bit barrel shifter for performing multiple bit shifts in one clock. The
data unit carries out data operations requested by the control unit.
 The protection test unit checks for segmentation violations under the control of
microcode.
 The segmentation unit calculates and translates the logical address into linear addresses
at the request of the execution unit.
 The translated linear address is sent to the paging unit. Upon enabling the paging
mechanism, the 80386 translates these linear addresses into physical addresses.
  If paging is not enabled, the physical address is identical to the linear address and no
translation is necessary.
3. Register organization of 80386
The Register organization of 80386 is as follows:

Figure:80386 General Purpose, Index and Pointer Register

3.1. General Purpose Register

 Registers EAX, EBX, ECX, EDX, EBP, EDI and ESI are regarded as general purpose or
multipurpose registers.
 EAX (ACCUMULATOR):The accumulator is used for instructions such as multiplication,
division and some of the adjustment instructions. In 80386 and above, the EAX register
may also hold the offset address of a location in memory system.
 EBX (BASE INDEX): This can hold the offset address of a location in the memory
system in all version of the microprocessor. It the 80386 and above EBX also can address
memory data.
 ECX (count): This acts as a counter for various instructions.
 EDX (data): EDX is a general-purpose registers that holds a part of the result for
multiplication or part of the division. In the 80386 and above this register can also
address memory data.
3.2. Pointer and Index Register
 EBP (Base Pointer): EBP points to a memory location in all version of the
microprocessor for memory data transfers.
 ESP (Stack Pointer): ESP addresses an area of memory called the stack. The stack
memory is a data LIFO data structure. The register is referred to as SP if used in 16 bit mode
and ESP if referred to as a 32 bit register.
 EDI (Destination index): EDI often addresses string destination data for the string
instruction. It also functions as either a 32-bit (EDI) or 16-bit (DI) general-purpose register.
 ESI (Source index): ESI can either be used as ESI or SI. It is often used to the address
source string data for the string instructions. Like EDI ESI also functions as a general-
purpose registers.

Figure:80386 Segment Register

 CS (Code): The code segment is a section of memory that holds the code used by the
microprocessor. The code segment registers defines the starting address of the section of
memory holding code.
 SS (Stack): The stack segment defines the area of memory used for the stack. The stack
entry point is determined by the stack segment and stack pointer registers. The BP
registers also addresses data within the stack segment.
 DS (Data): The data section contains most data used by a program. Data are accessed in
the data segment by an offset address of the contests of other registers that hold the offset
address.
 ES (extra): The extra segment is used to hold information about string transfer and
manipulation
 FS and GS: These are supplementing segment registers available in the 80386 and above
microprocessors to allow two additional memory segments for access by programs.
 EIP (Instruction Pointer): EIP addresses the next instruction in a section of memory
defined as a code segment. This register is IP (16bit) when microprocessor operates in the
real mode and EIP (32 bits) when 80386 and above operate in protected mode
 Figure: 80386 Instruction Pointer
3.3. Flag Register:
 Indicates the condition of the microprocessor and controls its operations. Flag registers
are also upward compatible since the 8086-80268 have 16bit registers and the 80386
and above have EGLAF register (32 bits)

Figure: 80386 Flag Register

 IOPL (I/O Privilege level): IOPL is used in protected mode operation to select the
privilege level for I./O devices. IF the current privilege level is higher or more trusted than
the IOPL, I/O executed without hindrance. If the IOPL is lover than the current privilege
level, an interrupt occurs, causing execution to suspend. Note that an IPOL is 00 is the
highest or more trusted; if IOPL is 11, it’s the lowest or least trusted.
 NT (Nested Task): The nested task flag is used to indicate that the current task is
nested within another task in protected mode operation. This flag is when the task I
nested by software.
 RF (Resume): The resume flag is used with debugging to control the resumption of
execution after the next instruction.
 VM (Virtual Mode): The VM flag bit selects virtual mode operation in a protected
mode system.
Note: All the other flag bit is having similar description as in 8086 flag register.

3.4. System Address Register:

 Four memory management registers are used to specify the locations of data structures
which control segmented memory management.
  GDTR (Global Descriptor Table Register) and IDTR (Interrupt Descriptor Table
Register) be loaded with instructions which get a 6 byte data item from memory

 LDTR (Local Descriptor Table Register) and TR (Task Register) can be loaded with
instructions which take a 16-bit segment selector as an operand.

3.5. Special 80386 Register

 Control Register: Four Control Register (CR0-CR3)
 Debug Register: Eight Debug Register (DR0-DR7)
 Test Register: Two Test Register (TR6-TR7)
3.5.1. Control Register in detail.
 The 80386 has three 32 bit control registers CR0, CR2 and CR3 to hold global machine
status independent of the executed task.
 Load and store instructions are available to access these registers
 Common tasks performed by control registers include interrupt control, switching the
addressing mode, paging control, and coprocessor control.

Figure: Control Register

CR0:
 CR0 contains system control flags, which control or indicate conditions that apply to the
system as a whole, not to an individual task.
 PE (Protection Enable, bit 0): Setting PE causes the processor to begin executing in
protected mode. Resetting PE returns to real-address mode.
  MP (Math Present, bit 1): MP controls the function of the WAIT instruction, which is used
to coordinate a coprocessor.
 EM (Emulation, bit 2):EM indicates whether coprocessor functions are to be emulated.
 TS (Task Switched, bit 3):The processor sets TS with every task switch and tests TS
when interpreting coprocessor instructions.
 ET (Extension Type, bit 4):ET indicates the type of coprocessor present in the system
(80287 or 80387).
 PG (Paging, bit 31): PG indicates whether the processor uses page tables to translate
linear addresses into physical addresses.
CR2:
 CR2 is used for handling page faults when PG is set. The processor stores in CR2 the linear
address that triggers the fault.
 Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs,
the address the program attempted to access is stored in the CR2 register.
CR3:
 Used when virtual addressing is enabled, hence when the PG bit is set in CR0, CR3
enables the processor to translate linear addresses into physical addresses by locating
the page directory and page tables for the current task.
 Typically, the upper 20 bits of CR3 become the page directory base register (PDBR),
which stores the physical address of the first page directory entry.
Note: Reserved field shown in figure are kept reserved by manufacturer

3.5.2. Debug Register

 Debugging of 80386 allows data access breakpoints as well as code execution
breakpoints.
 80386 contains 6 debug registers to specify
1) 4 breakpoints
2) Breakpoint Control options
3) Breakpoint Status
 Figure: 80386 Debug Register
Linear Breakpoint Address Registers:
The breakpoint addresses specified are 32-bit linear addresses
While debugging, Intel 386 h/w continuously compares the linear breakpoint addresses
in DR0-DR3 with the linear addresses generated by executing software.
Debug Control Register:

Figure: Debug Control Register

 LENi(i=0 - 3): Breakpoint Length Specification Bits:
1) 2 bit field for each breakpoint
2) Specifies length of breakpoint fields
3) The choices of data breakpoints are 1byte, 2bytes & 4bytes
4) For instruction execution breakpoint, the length is 1(beginning byte address)
 Table: LENi Encoding

 RWi(i=0 - 3): Memory Access Qualifier Bit

1) 2 bit field for each breakpoint
2) Specifies the type of usage which must occur inorder to activate the associated
breakpoint

Table: Table: RWii Encoding

GD: Global Debug Register Access Detect
 Debug registers can only be accessed in real mode or at privilege level 0 in protected
mode
  GD bit, when set, provides extra protection against any Debug Register access even in Real
Mode or at privilege level 0 in Protected Mode.
 The GD bit, when set, causes an exception 1 fault if an instruction attempts to read or
write any Debug Register.
 The GD bit is then automatically cleared when the exception 1 handler is invoked, allowing
the exception 1 handler free access to the debug registers.
GE and LE bit: Exact data breakpoint match, global and local
Gi and Li(i=0 - 3): Breakpoint Enable, global and local
 If either Gi or Li is set then the associated breakpoint is enabled.
Debug Status Register:
 A Debug Status Register allows the exception 1 handler to easily determine why it was
invoked.
 It can be invoked as a result of one of several events:
1) DR0 Breakpoint fault/trap.
2) DR1 Breakpoint fault/trap.
3) DR2 Breakpoint fault/trap.
4) DR3 Breakpoint fault/trap.
5) Single-step (TF) trap.
6) Task switch trap.
7) Fault due to attempted debug register access when GD = 1.

Figure: Debug Status Register

Bi : Debug fault/trap due to breakpoint 0 -3
 Four breakpoint indicator flags, B0-B3, correspond one-to-one with the breakpoint
registers in DR0-DR3.
 A flag Bi is set when the condition described by DRi, LENi, and RWi occurs.
BD: Debug fault due to attempted register access when GD bit is set
 This bit is set if the exception 1 handler was invoked due to an instruction attempting to
read or write to the debug registers when GD bit was set.
BS: Debug trap due to single step
 This bit is set if the exception 1 handler was invoked due to the TF bit in the flag
register being set
BT: Debug trap due to task switch
  This bit is set if the exception 1 handler was invoked due to a task switch occurring to a
task having an Intel386.
3.5.3. Test Register
 Two more test register are provided by 80386 for page caching
 They are used to control the testing of Translation Look-aside Buffer(TLB) of Intel386.
 TR6 is the command test register
 TR7 is the data register which contains the data of Translation Look-aside buffer test.

Figure: Test Register

3.6. Program-Invisible registers

 The global and local descriptor tables are found in the memory system.
 In order to access and specify the address of these tables, the program invisible registers
used.
 The program invisible registers are not directly addressed by software so they are given
name.
 The GDTR (global descriptor table register) and IDTR (interrupt descriptor table
register) contain the base addresses of the descriptor table and its limit.
 The limit of each descriptor table is 16 bits because the maximum table length is 64
Kbytes.
 When the protected mode operation is desired, the address of the global descriptor table
and its limit are loaded into the GDTR.
4. Real Modes of 80386
 Default Mode
 After reset, the 80386 starts from the memory location FFFFFFF0 H under real address
mode.
 In real address mode, 80386 works as a fast 8086 with 32 bit registers and data types.
 Real-address mode is in effect after a signal on the RESET pin. Even if the system is
going to be used in protected mode, the start-up program will execute in real-address
mode temporarily while initializing for protected mode.
 The addressing techniques, memory size, interrupt handling in this mode of 80386 are
similar to the real addressing mode of 80286.
 In real address mode, the default operand size is 16 bit but 32 bit operands and
addressing modes may be used with the help of override prefixed.
 Maximum physical memory = 1Mega byte (1MB)
 The only way to leave real-address mode is to switch to protected mode.
5. PVAM of 80386
  Introduced in the 80386 processor.
 32-bit address bus => access up to 232 bytes = 22. 230 B = 4 GB
 Base address => 32-bit value
 Offset =>16-bit or 32-bit value
 Linear address = base address + offset
 Linear address → physical address with paging
 In protected mode, the segment registers contain an index into a table of segment
descriptors.
 Each segment descriptor contains the start address of the segment, to which the offset is
added to generate the address.
 In addition, the segment descriptor contains memory protection information.
 This includes an offset limit and bits for write and read permission.
 This allows the processor to prevent memory accesses to certain data.
 Protected mode is accessed by placing a logic 1 into the PE bit of CR0
 This system contains one data segment descriptor and one code segment descriptor with
each segment set to 4G bytes in length.
 PVAM mode support memory management, virtual memory, multitasking, protection,
debugging, segmentation and paging.
6. Virtual Mode of 80386
 In its protected mode of operation, 80386DX provides a virtual 8086 operating
environment to execute the 8086 programs.
 The real mode can also use to execute the 8086 programs along with the capabilities of
80386, like protection and a few additional instructions.
 Once the 80386 enters the protected mode from the real mode, it cannot return back to
the real mode without a reset operation.
 Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086
programs while in protected mode.
 The address forming mechanism in virtual 8086 mode is exactly identical with that of
8086 real mode.
 In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in
the 4Gbytes address space of the protected mode of 80386.
 Like 80386 real mode, the addresses in virtual 8086 mode lie within 1Mbytes of memory.
 In virtual mode, the paging mechanism and protection capabilities are available at the
service of the programmers.
 The 80386 supports multiprogramming, hence more than one programmer may be using
the CPU at a time.
  Paging unit may not be necessarily enable in virtual mode, but may be needed to run the
8086 programs which require more than 1Mbyts of memory for memory management
function.
 In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size.
 Each of the pages may be located anywhere in the maximum 4Gbytes physical memory.
 The virtual mode allows the multiprogramming of 8086 applications.
 The virtual 8086 mode executes all the programs at privilege level 3.
 Any of the other programmers may deny access to the virtual mode programs or data.
 Even in the virtual mode, all the interrupts and exceptions are handled by the protected
mode interrupt handler.
 To return to the protected mode from the virtual mode, any interrupt or execution may
be used.
 As a part of interrupt service routine, the VM bit may be reset to zero to pull back the
80386 into protected mode.
7. Segment in
80386
 In protected mode the contents of segment register is called selectors shown below:-

Figure: Segment Selector

Descriptor Index: Selects any one of the 8192(213) descriptor from a descriptor table
TI – Table Indicator
 TI=1 Local Descriptor Table
 TI=0 Global Descriptor Table
RPL (Requested Privilege Level)(2-bit): Refers the privilege of that segment. They are used
while protection checks to indicate whether access to segment is allowed or not allowed.

7.1. 80386 Descriptor

Need of Descriptor
 Segments are the memory area defined by programmer and can be code, stack and data
segment.
 80386 segments are also assigned to have attributes viz. privilege level, segment type, segment
limit.
 So, it’s not possible to use a 16 bit segment register to represent all the info regarding a
segment. therefore the Solution is Descriptor
 Segment sizes vary from 1byte to 4GB in 80386.

Figure: Segment Descriptor in Protected Mode

Offset Bit Description

40 A(Accessed) 80386 sets this bit to 1 whenever a memory reference to a segment

defined by this descriptor is made.

41-43 TYPE 3-bit field describes the type of segment

000 Data segment , read only

001 Data segment , read/write

010 Stack segment, read only

011 Stack segment, read/write

100 Code segment, execute-only, non-conforming

101 Code segment, execute/read, non-conforming

110 Code segment, execute-only, conforming

111 Code segment, execute/read, conforming

44 S(System) 0 – Specifies system segment descriptor

E.g. LDS, TSS, Gates

1 – Specifies non system segment descriptor

E.g. code, stack or data

45-46 DPL (Descriptor Indicates privilege level associated with memory space. 0 - most
privileged 3 – least privileged
Privilege level)

47 Present If set 0 , indicates that the address range that is specified by the
descriptor is temporarily not present.

52 U(User) Undefined bit.

53 X Reserved by Intel

54 D(Default Size) 0 – Operands within this segments are assumed to be 16 bits.

1 – Operands assumed to be 32 bits

55 G(Granularity 1 – Unit of limit field is 1 byte.

bit)
2 – Unit of limit field is of 4096 bytes (or 1 page).

 The Above figure is the format of the code/data descriptor; one descriptor is 64-bit long.
 As we can see, a descriptor actually includes a 32-bit base address and a 20-bit limit and
some attributes, the 32-bit base address indicate where the segment starts, and the 20-bit
limit indicates the length of the segment.
 However, a problem comes up, 20-bit limit can only represent 2^20 = 1MB memory, to access
a 4GB memory space, descriptor uses G bit to indicate whether the limit use 4K or 1 byte for
one unit, that means if G bit is set then we get 2^20*4K = 4GB memory, if it is unset then we
only use a memory space under 1MB.

7.2. Descriptor tables in 80386

 The segment descriptors that we defined are grouped together and placed in a continuous
memory location. The group arrangement called Descriptor Table.
 Each descriptor requires 8byte in order to store the info of a particular segment.
 Descriptor table can contain 8192(8K) descriptors at the max.
 The maximum length of a descriptor table is a 64Kbytes.
 The descriptor tables define all the segments used in the 80386 when it operates in the
protected mode.
 There are three types of descriptor tables: the global descriptor table (GDT), the local
descriptor table (LDT), and the interrupt descriptor table (IDT).
 The registers used by the 80386to address these three tables are called the global descriptor
table register (GDTR), the local descriptor table register (LDTR), and the interrupt
descriptor table register (IDTR).
 These registers are loaded with the LGDT, LLDT, and LIDT instructions, respectively.
 The local and global descriptor tables hold up to 8192 entries each, and the interrupt
descriptor table holds up to 256 entries.
 A descriptor is indexed from either the local or global descriptor table by the selector that
appears in a segment register.
 Whenever a new selector is placed into one of the segment registers, the 80386 accesses
one of the descriptor tables and automatically loads the descriptor into a program-invisible
cache portion of the segment register.

1) Global Descriptor Table (GDT):

 This is the main table of descriptors.
 The same GDT can be used by all programs to refer to segment of memory.
 80386 can have many LDT’s but only one GDT.

Figure: Global Descriptor Table

2) Local Descriptor Table (LDT) :
 A multi-tasking system is defined on a per task basis.
 The main purpose of an LDT would be combined with GDT in order to expand the total
number of available descriptors.
 Generally, each task can have its own LDT and can also be shared with other task.
8. Paging
  Paging is one of the memory management techniques
 The paging mechanism allows any linear (logical) address, as it is generated by a program,
to be placed into any physical memory page, as generated by the paging mechanism.
 A linear memory page is a page that is addressed with a selector and an offset in either
the real or protected mode.
 A physical memory page is a page that exists at some actual physical memory location.
 For example, linear memory location 20000H could be mapped into physical memory
location 30000H, or any other location, with the paging unit. This means that an
instruction that accesses location 20000H actually accesses location 30000H. Each
80386 memory page is 4K bytes long.
 Paging allows the system software to be placed at any physical address with the paging
mechanism.
 Three components are used in page address translation: the page directory, the page
table, and the actual physical memory page.
 The segmentation scheme may divide the physical memory into a variable size
segments but the paging divides the memory into a fixed size pages.
 The segments are supposed to be the logical segments of the program.
 The pages are just fixed size portions of the program module or data.
Advantage:
 The advantage of paging scheme is that the complete segment of a task need not be in
the physical memory at any time.
 Only a few pages of the segments, which are required currently for the execution need to be
available in the physical memory.
 Thus the memory requirement of the task is substantially reduced, relinquishing the
available memory for other tasks.
8.1. Page Directory
 The page directory contains the location of up to 1024 page translation tables, which are
each four bytes long.
 Each page translation table translates a logical address into a physical address.
 The page directory is stored in the memory and accessed by the page descriptor address
register (CR3).
 Control register CR3 holds the base address of the page directory, which starts at any
4K- byte boundary in the memory system.
 Each entry in the page directory translates the leftmost 10 bits of the memory address.
This 10-bit portion of the linear address is used to locate different page tables for
different page table entries.
8.2. Page Table
  The page table contains 1024 physical page addresses, accessed to translate a linear
address into a physical address.
8.3. Page Directory Entry
 Total Page Directory Entries are1024
 Each directory entry is of 4byte

8.4. Page Table Entry Figure: Page Directory Entry

 The page table entries contain the starting address of the page and the statistical
information about the page.
 Total Entries are1024
 Each page table entry is of 4byte

Figure: Page Table Entry

 D-bit: Dirty bit is undefined for page table directory entries by the 80386
microprocessor and is provided for use by the operating system.
 A-bit: Accessed bit is set to logic 1 whenever the microprocessor accesses the page
Directory entry.
 R/W (Read/write) & U/S (user/supervisor) are both used in the protection scheme.
Both bits combine to develop paging priority level protection for level 3, the lowest user
level.

 P-bit: Present bit, if logic1 indicates that the entry can be used in address translation. If
P = 0, the entry cannot be used for translation. When P = 0, the remaining bits of the
entry can be used to indicate the location of the page on the disk memory system.
Difference between page directory and page table entry:
  The main difference is that the page directory entry contains the physical address of a page
table, while the page table entry contains the physical address of a 4K-bytephysical page of
memory.
 The other difference is the D (dirty bit), which has no function in thepage directory entry,
but indicates that a page has been written to in a page table entry.
8.5. Page Translation Mechanism in 80386
 A page frame is a 4K-byte unit of contiguous addresses of physical memory. Pages begin on
byte boundaries and are fixed in size.
 A linear address refers indirectly to a physical address by specifying a page table, a page
within that table, and an offset within that page

Figure: Format of Linear Address

 The below figure of page translation shows, how processor converts the DIR, PAGE, and
OFFSET fields of a linear address into the physical address by consulting two levels of page
tables.
 The addressing mechanism uses the DIR field as an index into a page directory, uses the
PAGE field as an index into the page table determined by the page directory, and uses
the OFFSET field to address a byte within the page determined by the page table.
 In the second phase of address transformation, the 80386 transforms a linear address
into a physical address.
 This phase of address transformation implements the basic features needed for page-
oriented virtual-memory systems and page-level protection.
 Page translation is in effect only when the PG bit of CR0 is set.

Figure: Page Translation

9. Features of 80486
 The 32-bit 80486 is the next evolutionary step up from the 80386.
 One of the most obvious feature included in a 80486 is a built in math coprocessor. This
coprocessor is essentially the same as the 80387 processor used with a 80386, but being
integrated on the chip allows it to execute math instructions about three times as fast as
a 80386/387 combination.
 80486 is an 8Kbyte code and data cache.
 To make room for the additional signals, the 80486 is packaged in a 168 pin, pin grid
array package instead of the 132 pin PGA used for the 80386.
 Operates on 25MHz, 33 MHz, 50 MHz, 60 MHz, 66 MHz or 100MHz.
 It consists of parity generator/checker unit in order to implement parity detection and
generation for memory reads and writes.
 Supports burst memory reads and writes to implement fast cache fills.
 Three mode of operation: real, protected and virtual 8086 mode.
 The 80486 microprocessor is a highly integrated device, containing well over 1.2
million transistors.
10. Pentium Processor
Features
 It consists of all the features of 80486. The additional enhancements that Pentium
provides are:
1) Wider data bus width :
 It has 64 bit data bus and 32 bit address bus.
 It allows 8 byte of data info to be transferred to and from memory.
 Bus cycle pipelining has been added to allow two bus cycles to be in progress
simultaneously.
2) Improved Cache Structure:
 8KB dedicated instruction cache which gives instruction to its execution units and
floating point unit via dual instruction pipeline.
 Cache is organized in a 2 way set associate cache with 32 byte line(256 lines).
 8KB data cache which gives data to its execution unit.
 This allows 32 byte transfer from cache to pre-fetch buffer which is of 64 bytes.
3) Two parallel integer execution unit :
 It allows the execution of two instructions to be executed simultaneously in a single
processor clock.
4) Faster floating point unit :
 The floating point unit has been completely redesigned over 80486.
  Faster algorithms provide up to ten times speed – up for common operations including
add, multiply etc.
5) Branch prediction logic:
 The Pentium uses tech called branch prediction.
 To implement this Pentium has two pre-fetch buffers, one to pre-fetch code in linear
fashion, and one that pre-fetches code according to the Branch Target Buffer (BTB).
 Therefore, needed code is almost pre-fetched before it is required for execution.
6) Data Integrity and Error Detection:
 The Pentium have added significant data integrity and error detection capability.
 Data parity checking is still byte-by-byte basis.
 Address parity checking has also been added.
7) Functional Redundancy Checking: (provides maximum error detection)
 Two or more Pentium Processor can participate in functional redundancy checking.
 One processor (the master) fetching the instruction and executes the instruction in
normal fashion.
 Other processor (the checker) (connected directly to the master processor’s buses) verify
correctness of master processor.
 Checker executes the instruction same as the master but doesn’t drive the buses.
 Checker samples master’s output and compares the values with the internal computed
values. An error signal is asserted in case if mismatch occurs.
8) Super Scalar Architecture:
 Processor is capable of parallel instruction execution of multiple instructions are known
as superscalar processors.
 Pentium is capable in some cases of executing two integer of two floating point
instruction simultaneously and thus support superscalar architecture.
10.1 Architecture
 Figure: Pentium Architecture
Features of
80486
 The 32-bit 80486 is the next evolutionary step up from the 80386.
 One of the most obvious feature included in a 80486 is a built in math coprocessor. This
coprocessor is essentially the same as the 80387 processor used with a 80386, but being
integrated on the chip allows it to execute math instructions about three times as fast as
a 80386/387 combination.
 80486 is an 8Kbyte code and data cache.
 To make room for the additional signals, the 80486 is packaged in a 168 pin, pin grid
array package instead of the 132 pin PGA used for the 80386.
 Operates on 25MHz, 33 MHz, 50 MHz, 60 MHz, 66 MHz or 100MHz.
 It consists of parity generator/checker unit in order to implement parity detection and
generation for memory reads and writes.
 Supports burst memory reads and writes to implement fast cache fills.
 Three mode of operation: real, protected and virtual 8086 mode.
 The 80486 microprocessor is a highly integrated device, containing well over 1.2
million transistors.
Explain Architecture of 80486 Processor.
 The architecture of the 80486DX is almost identical to the 80386. Added to the 80386
architecture inside the 80486DX is a math coprocessor and an 8K-byte level 1 cache
memory.

Figure: 80486 Architecture

BIU:

 BIU generates address, data and control signals for a bus cycle it is supported with an
additional parity detection/generation for memory reads and writes.
 During memory write operation, the 486 generates even parity bit for each byte outputs
these bits.
 These bits will be stored in a separate parity memory bank.
 During read operation, stored parity bits will be read from the parity memory.
 80486 checks the parities of data bytes read and compare them with the DP0 – DP3
signals and generates parity check error, if it occurs.

Instruction Pre-fetch Unit :

 It pre-fetches the instruction bytes in advance and holds them in a 32–byte code queue.

Instruction Decoder :

 Decodes the instructions in the queue and passes the control and protection test unit.

Execution Unit:

 Executes the instruction with the help of Barrel Shifter, ALU and Register bank.
Segmentation Unit and Paging Unit :

 They are part of MMU(which manages virtual memory of system). Helpful in generation of
Physical Address.
 Work same as they work in 80386.

Floating Point Unit:

 Responsible for performing the floating point operations.

 The 80486 has a built in math co-processor . It performs the floating point operations.
 It executes math instructions 3 times faster than the 386/387 combination.

Cache Unit:

 8KB cache
 Additional high speed cache memory provides a way of improving overall system
performance.
 It contains the recently used instructions, data or both.
 The main aim is that the microprocessor unit access code and data in the cache most of
time, instead from the main memory.

EFLAG Register
 The extended flag register EFLAG is illustrated in the figure below:-

 The only new flag bit is the AC alignment check, used to indicate that the
microprocessor has accessed a word at an odd address or a double word boundary.

Figure: EFLAG Register of The 80486

 02 – Advanced Microprocessor

1. Features of 8086 microprocessor

General Features:
1) 8086 is a 16-bit processor, which implies that
 16-bit data bus
 16-bit ALU, that perform 16-bit operation at the same time
 16-bit registers
2) Speed of processor: There are three versions based on the frequency of operation
 8086 -> 5MHz (5 million cycles per second)
 8086 -> 8MHz (8 million cycles per second)
 8086 -> 10MHz (10 million cycles per second)
3) 8086 has a 20 bit address bus can access up to 220 memory locations.( 220=1048576
bytes = 1 MB)
4) It can support up to 64K I/O ports. (216 I/O ports-> 216=65536 bytes=64 Kb)
5) In 8086 two Unit works in parallel:
 Bus Interface Unit (BIU)
 Execution Unit (EU)
6) 8086 has 256 vectored interrupt.
7) 8086 contains powerful instruction set , that supports Multiply and Divide operation
(this operation were not possible in previous versions of 8086)
8) 8086 can perform operation on bit, byte (8-bit), word (16-bit) or string types of data.

Special Features:
1) 8086 is a pipelined processor
2) 8086 is two staged pipelined architecture:
 Fetch Stage: It pre-fetch up to 6 bytes of instruction and store them in the queue.
 Execute stage: Executes the instruction
3) 8086 can operate in 2 modes
 Minimum mode: A system with only one processor i.e.8086
 Maximum mode: A system with multiple processors.
e.g. 8086 + math co-
processor(8087), 8086+ I/O
processor (8089), Multiple 8086
processors
4) 8086 uses memory bank
 In 8086 entire data is not stored in single sequential memory of 1MB.
 The memory is divided into two banks of 512KB each.
I. Lower Bank/ Even Bank: Stores the data types at even locations (0,2,4…)
 II. Higher Bank/ Odd Bank: Stores the data types at odd locations (1,3,5…)
5) 8086 uses memory segmentation
 Segmentation means dividing memory into logical components.
 In 8086 memory is divided into 16 segments of capacity 216 bytes each and used
as code, stack, data and extra segment

2. 8086 ARCHITECTURE

 The Block diagram for the internal architecture of 8086 is as follows:-

Figure 1 architecture of 8086

 In 8086 CPU is divided into two independent functional parts BIU and EU.
 Dividing the work between these two units’ speeds up the processing.

1) BIU (Bus Interface Unit)

 Components of BIU

 Instruction queue
- It holds the instruction bytes of the next instruction to be executed by EU
 Segment Registers
- Four 16-bit register that provides powerful memory management mechanism
- ES (extra segment), CS (code segment), SS (stack segment) , DS (data segment).
- The size of each register is 64kb.
 Instruction pointer (IP)
- Register that holds 16-bit address or offset of next code byte within code segment
 Address Generation and bus control
- Generation of 20-bit physical

address Task carried out by BIU

 Fetch instructions from memory

 Read/ Write instruction from / to the memory
 Input/ Output (I/O) of data from / to peripheral ports
 Write the data to memory.
 Address generation for memory reference
 Queuing of instruction (The instruction bytes are transferred to the instruction queue)
 Thus, BUI handles all transfer of data and address on the buses for Execution unit.
 BIU works in synchronous with machine cycles

2) EU (Execution Unit)

Components of EU

 ALU (Arithmetic logic Unit)

- Contains 16-bit ALU, that performs add, subtract, increment, decrement, compliment,
shift binary numbers, AND, OR, XOR etc.
 CU (Control Unit)
- Directs internal operation
 Flag Register
- 16-bit flag register
- EU contains 9 active flags
 General Purpose Registers (GPR)
- EU has 4 general purpose 16-bit register
- i.e. AX, BX, CX, DX
- each register is the combination of two 8-bit register
 - AH, AL, BH, BL, CH, CL, DH, DL where ‘L’ means Lower byte and ‘H’ means higher byte.
 Index Register
- 16-bit Register is SI (source index) and DI (destination index).
- Both the register used for string related operation and for moving block of memory
from one location to the other.
 Pointers
- 16-bit Register.
- i.e. SP (stack pointer), BP (base pointer)
- BP : is used when we need to pass parameter through stack
- SP: It always points to the top of the stack. Used for sequential access of stack
segment.
 Decoder (instruction decoder)
- Translates the instruction fetched from into series of action which EU carries out
 Task carried out by EU
- Decodes the instruction
- It executes instructions (executes decoded instructions)
- Tells BIU from where to fetch the instruction
- Decodes instruction (decode the fetched instruction)
- EU takes care of performing operation on the data
- EU is also known as execution heart of the processor

3. 8086 REGISTERS
The 8086 microprocessor has a total of fourteen registers that are accessible to the
programmer as follows:-

1. General Purpose Register

AX: - Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

 AX works as an intermediate register in memory and I/O operation.

 Accumulator is used for the instruction such as MUL and DIV.

BX: -Base register consists of two 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX.

 BX register usually contains a data pointer used for based, based indexed or
register indirect addressing.

CX:-Count Register consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX.
  Count register can be used in Loop, shift/rotate instructions and as a counter in
string manipulation.

DX: - Data register can be used together with AX register to execute MUL and DIV
instruction.

 Data register can be used as a port number in I/O operations.

2. Segment Register

Types of Segment registers are as follows:-

Code Segment (CS): The CS register is used for addressing a memory location in the
Code Segment of the memory, where the executable program is stored.

Data Segment (DS): The DS contains most data used by program. Data are accessed in
the Data Segment by an offset address or the content of other register that holds the offset
address.

Stack Segment (SS): SS defined the area of memory used for the stack.

Extra Segment (ES): ES is additional data segment that is used by some of the string to
hold the destination data

3. Pointer Registers

The pointers IP, BP, SP usually contain offsets within the code, data and stack segments
respectively.

Stack Pointer (SP): SP is a 16-bit register pointing to program stack in stack segment.

Base Pointer (BP): BP is a 16-bit register pointing to data in stack segment. BP register
is usually used for based, based indexed or register indirect addressing.

Instruction Pointer (IP): IP is a 16-bit register pointing to next instruction to be

executed.

4. Index registers

The Index Registers are as follows:-

Source Index (SI): SI is a 16-bit register used for indexed, based indexed and register
indirect addressing, as well as a source data addresses in string manipulation instructions.

Destination Index (DI): DI is a 16-bit register. DI is used for indexed, based indexed
and register indirect addressing, as well as a destination data addresses in string
manipulation instructions.
5. Flag Registers
 The 16-bit flag register of 8086 contains 9 active flags (six conditional & 3 control flags),
other 7 flags are undefined.

Status Flags: It indicates certain condition that arises during the execution. They are
controlled by the processor.

Control Flags: It controls certain operations of the processor. They are deliberately
set/reset by the user.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U U U U OF DF IF TF SF ZF U AF U PF U CF

U- Undefined CF- Carry Flag

TF- Trap Flag PF- Parity Flag
IF- Interrupt Flag AF- Auxiliary Flag
DF- Direction Flag ZF- Zero Flag
OF- Overflow Flag SF- Sign Flag

The Flag Registers are classified as follows:-

 CONTROL FLAGS
 Control flags are set or reset deliberately to control the operations of the execution unit.

Trap Flag (TF):

 It is used for single step control.

 It allows user to execute one instruction of a program at a time for debugging.
 When trap flag is set, program can be run in single step mode.

Interrupt Flag (IF):

 It is an interrupt enable/disable flag.

 If it is set, the mask able interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled.
 It can be set by executing instruction sit and can be cleared by executing CLI

instruction. Direction Flag (DF):

 It is used in string operation.

  If it is set, string bytes are accessed from higher memory address to lower memory
address.
 When it is reset, the string bytes are accessed from lower memory address to higher
memory address.

STATUS FLAG

Carry Flag (CF):

 This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in
multiple-precision arithmetic.

Auxiliary Flag (AF):

 If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 –

D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF
flag.
 This is not a general-purpose flag, it is used internally by the processor to perform
Binary to BCD conversion.

Parity Flag (PF):

 This flag is used to indicate the parity of result. If lower order 8-bits of the result contains
even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity Flag is reset.

Zero Flag (ZF):

 It is set; if the result of arithmetic or logical operation is zero else it is

reset. Sign Flag (SF):

 In sign magnitude format the sign of number is indicated by MSB bit. If the result of
operation is negative, sign flag is set.

Overflow Flag (OF):

 It occurs when signed numbers are added or subtracted. OF=1 indicates that the result
has exceeded the capacity of machine.

4. Addressing Mode
There are 12 addressing modes in 8086 as follows:-

1) Immediate Mode
  If a source operand is part of the instruction instead of the contents of a register or
memory location, it represents what is called the immediate operand.
 In other word it is constant data contained in an instruction
 If source operand is the part of instruction rather than register or memory, then referred
as immediate addressing mode.
 Operand = address field
 E.g. MOV AL, 05H; instruction copies immediate number 05H to AL register
 Immediate data may be 8-bits or 16-bits in length

Instruction

Opcode Immediate Operand

Advantage:

 Operand can be accessed quickly as they are directly available in instruction

queue.
 No need of External bus or bus-cycles to obtain data.
 No memory reference to fetch data
 Comparatively Faster execution

Limitation:

 The operand can only be used as a source operand.

 Value of the operand will remain Constant
2) Register Addressing Mode
 The operand is stored in one of the CPU register.
 Register may be used as source operand or destination operand or both
 E.g. ADD r1, r2; adding r1 and r2 and store the result in r2
 E.g. MOV AX,BX ; move value from BX to AX register

Advantage:

 This mode is normally preferred, as the execution of instruction is faster and

compact, because all the registers reside on the same chip.
 Therefore, data transfer is within the chip and no External bus is required.

Limitation:

 Number of CPU registers are limited

3) Direct Addressing Mode
 Address field of Instruction contains address of operand

Advantage:

 Single memory reference is required to access data

 No additional calculations to work out effective address
 Equation: Physical Address PA ={starting address of Segment Register } + {Direct
memory address}
 Example:
MOV [30540], TEMP; moving value of TEMP to memory location [30540]
DS=3060 and direct memory address=0030

3 0 6 0 0 (‘0’ is added to LSB by BIU)

+ 0 0 3 0 ( direct address)

---------------------

3 0 6 3 0 (physical address)
4) Register Indirect Addressing
 In this addressing mode effective address of memory is calculated from base register
(BX) or index register (SI, DI), specified in the instruction. Then it is added to the
segment register to generate physical address.
 Equation: Physical Address PA ={starting address of Segment Register } + { [BX] or index
register }

 E.g. MOV [DI], BX; value of BX is moved to the memory location specified in DI
 MOV [BX], AX ; value of AX is moved to the memory location specified in BX

Advantage:

 Large address space

Limitation:

 Slower access, as multiple memory accesses is needed to find operand.

5) Based Addressing Mode

When memory is accessed PA is computed from BX and DS, when the stack is accessed PA is
computed from BP and SS.

 Equation:
PA ={starting address of Segment Register } + { [BX] or [BP] }+ (8 or 16 bit)
displacement
 Example: MOV AL, TEMP [BX]; segment register address+ BX+ offset
MOV AL, TEMP [BP]; segment register address+ BP+ offset
Assume DS=3060, BX=0050 and displacement=08

3 0 6 0 0 H (starting address of segment register)

+ 0 0 5 0 H(base register)

+ 0 8 H(offset)

----------------------------------------

3 0 6 5 8 H(physical address)

6) Indexed Addressing Mode

 In this addressing mode offset address is added to index register and finally the sum is
added to segment register.
 Example. MOV BH, TEMP [SI] ; TEMP is the offset address
  Equation:
 PA ={starting address of Segment Register } + { [SI] or [DI] }+ (8 or 16 bit) displacement
 Assume DS=3060, SI=0050 and displacement=08

3 0 6 0 0 H (starting address of segment register)

+ 0 0 5 0 H (Source Index)

+ 0 8 H (offset)

----------------------------------------

3 0 6 5 8 H (physical address)

7) Based Indexed Addressing Mode

 This mode generates the effective address, which is sum of Base address +Index
Address + (8 or 16 bit) displacement address.
 This sum is added to segment register to generate effective address.
 Example : MOV CX, TEMP[BX] [SI]
 Equation: PA ={starting address of Segment Register } + {[BX] or [BP]}+({ [SI] or [DI] }+
(8 or 16 bit) displacement
Assume DS=5000, BX=3000, SI=0400 and

displacement=08 5 0 0 0 0 H (starting address of

segment register)

+ 3 0 0 0 H (base register)

+ 0 4 0 0 H (Source Index)
+ 0 8 H (offset)
 ----------------------------------------

5 3 4 0 8 H (physical address)

8) String Addressing Mode

 The string instructions automatically assume SI to point to the first byte or word of the
source operand and DI to point to the first byte or word of the destination operand.
 The contents of SI and DI are automatically incremented (by clearing DF to 0 by CLD
instruction) to point to the next byte or word.
 Source address : 20500, assume it contains 38
 PA : [DS] + [SI] = 20000+0500=20500
 Destination address : [ES] + [DI] = 40000+0300
 After executing MOV SI, DI

[40300] = 38

[SI] = 0501 incremented

[DI] = 03

9) Relative addressing mode:

 Relative address means ‘relative to IP (Instruction Pointer)’.
 Example : JNC START ; jump to label if no carry is generated

- If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START,
otherwise the next instruction is executed.
 - Displacement is calculated on the basis of next location to be executed.

10) Implied addressing mode:

 Instructions using this mode have no operands.
 Example: CLC; which clears carry flag to zero.
STC; set the carry flag
11) I/O mode (direct) :
 Port number is an 8 bit immediate operand.
 Example : OUT 05 H, AL
Outputs value of AL to 8 bit port 05 H
IN and OUT instructions are allowed to use only AL or AX registers.
12) I/O mode (indirect):
 I/O port address is provided in DX register. Port address ranges from 0000 to FFFFH.
 The port number is taken from DX.
 Example 1 : IN AL, DX
 IN and OUT instructions are allowed to use only AL or AX registers.

5. SEGMENTATION IN 8086
 In Segmentation, the total memory size is divided into segments of various sizes.
 Segment is just an area in memory.
 The process of dividing memory into segments of various sizes is called Segmentation.
 Memory is huge collection of bytes. In order to organize these bytes in an efficient
manner Segmentation is used.

The complete 1Mbyte memory is divided into 16 logical segments.

 In memory, data is stored as bytes.

 Each byte has a specific address.
 Intel 8086 has 20 lines address bus.
 With 20 address lines, the memory that can be addressed is 220 bytes.
 20 lines= 220 = 1,048,576 bytes =1 MB= 1111 1111 1111 1111 1111= FFFFF H
 At a time 8086 can only access 4 segments.

i.e 64KB * 4 = 256KB of segments can be accessed at a time.

8086 memory with address ranging from 000000 H to FFFFFF H.

 Size of each Segment Register is 16-bit

216 = 65535 bytes = 64K [size of each segment]

 Total number of segments:

= Total memory available/size of each segment

= 1MB/64KB

= 1024KB/64KB

= 16 segments.

 Segment Registers are used to hold the upper 16-bit of the starting address for each of
the segment.
 The 16-bit of the starting address is the starting address of the segment from where the
BIU is currently fetching instruction code bytes.
 The BIU always inserts zeros for the LSB of the 20-bit address for a segment. Because the
segment registers cannot store 20 bits, they only store the upper 16 bits.
 The 20-bit address of a byte is called its Physical Address (PA).

PA= Base Address : Offset

 Offset is the displacement of the memory location from the starting location of the
segment.
 The value of Data Segment Register (DS) is 2222 H.
 To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSBs of the base
address.
 After appending, the starting address of the Data Segment becomes 22220H.
 If the data at any location has an address specified as: 2222H: 0016 H where the number
0016 H is an offset.
 To calculate the effective address of the memory, BIU uses the following formula:
 Physical Address = Starting Address of Segment + Offset

 To find the starting address of the segment, BIU appends the contents of Segment Register
with 0H and then, it adds offset to it.

EA = 2 2 2 2 0 H
+0016H
----------------
22236H
 Unit 02 – Advanced Microprocessor

1. 80286
 The 80286 was designed for multi-user systems with multitasking applications, including
communications and real-time process control.
 It had 134,000 transistors and consisted of four independent units: address unit, bus unit,
instruction unit and execution unit.
 These were organized into a pipeline, significantly increasing performance.
 It was produced in a 68-pin package including PLCC (Plastic Leaded Chip Carrier), LCC
(Leadless chip carrier) and PGA (Pin Grid Array) packages.
 The Intel 80286 had a 24-bit address bus and was able to address up to 16 MB of RAM,
compared to 1 MB for its predecessor. However cost and initial rarity of software using the
memory above 1 MB meant that 80286 computers were rarely shipped with more than one
megabyte of RAM.
 80286 Architecture contains 4 separate processing units.
(1) Bus Unit (BU)
(2) Instruction Unit (IU)
(3) Address Unit (AU)
(4) Execution Unit (EU)

Fig. 1: Architecture of Intel 80286

Bus Unit
(BU):
 It has address latches, data transceivers, bus interface and circuitry, instruction pre-
fetcher, processor extension interface and 6 byte instruction queue.
Functions :
 Unit 02 – Advanced Microprocessor
 To perform all memory and I/O read and write.
  To pre-fetch the instruction bytes.
 To control the transfer of data to and from processor extension devices like 80287 math
co- processor.
 Whenever BU is not using the buses for the operation, it pre-fetches the instruction
bytes and put them is a 6 byte pre-fetch queue.
Instruction Unit (IU):
 It has 3 decoded instruction queue and instruction
decoder. Functions:
 It fully decodes up to three pre-fetched instructions and holds them in a queue.
 So that EU can access them.
 It helps the processor to speed up, as pipelining of instruction is done.
Execution Unit (EU):
 It includes ALU, registers and the Control unit. Registers are general purpose, index,
pointer, flag register and 16 –bit Machine Status Word (MSW).
Functions:
 To sequentially execute the instructions received from the instruction unit.
 ALU result is either stored in register bank or sent over the data bus.
Address Unit (AU):
 It consists of segment registers, offset address and a physical address adder.
Functions:
 Compute the physical address that will be sent out to the memory or I/O by BU.
 80286 operate in two different modes
 Real address mode
 Protected virtual address mode.
 When used in Real address mode, AU computes the address with segment base and offset
like 8086. Segment register are CS, DS, ES and SS hold base address. IP, BP, SI, DI, SP
hold offset.
 Maximum physical space allowed in this mode is 1MB.
 When 80286 operate in protected mode, the address unit acts as MMU.
 All 24 address lines used and can access up to 16MB of physical memory.
 If descriptor table scheme is used it can address up to 1GB of virtual memory.

2. REGISTER ORGANIZATION OF 80286

The 80286 CPU contains almost the same set of registers, as in 8086, namely
(1) Eight 16-bit general purpose registers (AX, BX, CX, DX)
(2) Four 16-bit segment registers (CS, SS, DS, ES)
(3) Status and control registers (SP, BP, SI, DI)
(4) Instruction Pointer (IP)
(5) Two 16-bit register - FLAGS, MSW
(6) Two 16-bit register - LDTR and TR
(7) Two 48-bit register -GDTR and IDTR

Fig.2: 80286 Register Set

 Fig. 3: 80286 Flag Register

 Flag register is of 32 bit. 15th bit undefined/reserved.

 IOPL – I/O Privilege Level flag: 2 –bits are used in protected mode. It holds the privilege
level from 0 to 3. ‘0’ assigns to highest privilege whereas ‘3’ assigns to lower privilege
level.
 NT: Nested Task flag: It is used in protected mode. Bit is set when one task invokes
another task.
MSW machine status word
There are four Processor Status bit in 80286:-

Fig. 4 : Machine Status Word

1) PE - Protection Enable
 The PE bit is set to enable the Protected Mode. If PE is reset, the processor operates
again in Real Mode.
2) MP - Monitor Processor Extension
 The MP bit is used in conjunction with the TS bit to determine if the WAIT opcode will
generate a Coprocessor Not Available fault when TS=1. When both MP = 1 and TS = 1,
the WAIT opcode generates a trap. Otherwise, the WAIT opcode does not generate a
trap. Note that TS is automatically set whenever a task switch operation is performed.
3) EM - Processor Extension Emulator
 The EMulate coprocessor bit is set to cause all coprocessor opcodes to generate a
Coprocessor Not Available fault. It is reset to allow coprocessor opcodes to be executed
on an actual Intel387 DX coprocessor. Note that the WAIT opcode is not affected by the
EM bit setting.
4) TS – Task Switch
  TS is automatically set whenever a task switch operation is performed.

3. Salient Features of 80286

 The 80286 is the first member of the family of advanced microprocessors with memory
management and protection abilities.
 The 80286 CPU, with its 24-bit address bus is able to address 16 Mbytes of physical
memory. Various versions of 80286 are available that runs on 12.5 MHz, 10 MHz and 8
MHz clock frequencies.
 80286 is upwardly compatible with 8086 in terms of instruction set.
 80286 have two operating modes namely real address mode and virtual address mode.
 In real address mode, the 80286 can address up to 1Mb of physical memory address like
8086.
 In virtual address mode, it can address up to 16 Mb of physical memory address space and
1 GB of virtual memory address space.
 The instruction set of 80286 includes the instructions of 8086 and 80186.
 80286 have some extra instructions to support operating system and memory
management.
 In protected virtual address mode, it is source code compatible with 8086.
 The performance of 80286 is five times faster than the standard 8086.

4. Memory Management Unit

 In advanced microprocessor, memory management becomes extremely important.
Memory management is required due to the following two reasons.

1. Limitation of physical memory

 A microprocessor has limited number of address lines. Hence the physical memory
addressability is limited. Increasing the number of address lines is not attractive as it
makes the architecture and design complex without significant gain. Packaging becomes
difficult and expensive. Memory Management Unit (MMU) solves this problem by
translating the virtual memory address into the physical memory address. Virtual
memory can be many times larger than the physical memory. Only the programs
currently required are brought from the secondary storage such as a hard disk to, the
physical memory (RAM) for execution.

2. Need for Protection

 In a multi-user operating system, there is a possibility that a user program can corrupt
the operating system area or the area of some other user unless a protection
mechanism is
 built. Hence each user should be protected from other users and the operating system
should be protected from other user (task). The user (task) should be allowed to have a
controlled access to the operating system resources. Hence various privilege levels are
defined. For example, in a situation having 4 privilege levels, 0 is the highest privilege
and 3 has the lowest privilege as shown in the figure. The figure shows a typical UNIX
operating system layout.
 It has to be noted that the user is at the lowest privilege level, i.e., privilege level 3 and the
operating system Kernel is at the highest privilege level, i.e., privilege level 0.

Role of Memory Management Unit (MMU):

 The virtual address space of a microprocessor may be many times larger than the actual
physical address space.
 This is desirable as a microprocessor is supposed to store large programs and data which
cannot be accommodated in the physical memory space.
 Usually programs and data are stored in a secondary storage such as a hard disk.
 The hard disk is in the virtual or logical address space but not in the physical address
space.
 Faster memory such as RAM is used as the physical memory (Primary Storage).
 When a microprocessor is to execute a program, it checks whether the program is
available in the physical memory (RAM).
 If the program is not available in the physical memory, it is brought from the secondary
memory to the physical memory for execution.
 If available space is inadequate in the physical memory, some less important or unused
program can be swapped back to the secondary memory to create space.

5. OPERATING MODES OF 80286

80286 works in two operating mode:

1. Real Address Mode (Just act as a fast 8086).

 Instruction set is upwardly compatible

 Because of extra pipelining and other circuit level improvements, in real address mode
also, the 80286 operates at a much faster rate than 8086, although functionally they
work in an identical fashion.
 As in 8086, the physical memory is organized in terms of segments of 64Kbyte maximum
size.
  In the real mode the first 1Kbyte of memory starting from address 0000H to 003FFH is
reserved for interrupt vector table.
 The addresses from FFFF0H to FFFFFH are reserved for system initialization.
 When the 80286 is reset, it always starts the execution in real address mode.
 In real address mode, it initializes the IP and other registers of 80286.

Fig.5 : Real Address Mode Address Calculation

2. Protected Virtual Address Mode (PVAM)

 80286 is the first processor to support the concepts of virtual memory and memory
management.
 The concept of Virtual Memory is implemented using Physical memory that the CPU
can directly access and secondary memory that is used as storage for data and program,
which are stored in secondary memory initially.
 The complete virtual memory is mapped on to the 16Mbyte physical memory.
 If a program larger than 16Mbyte is stored on the hard disk and is to be executed, if it is
fetched in terms of data or program segments of less than 16Mbyte in size into the program
memory by swapping sequentially as per sequence of execution.
 The 80286 is able to address 1 GB (230 bytes) of virtual memory.
 80286 uses the 16-bit content of a segment register as a selector to address a descriptor
stored in the physical memory.
  The descriptor is a block of contiguous memory locations containing information of a
segment, like segment base address, segment limit, segment type, privilege level, segment
availability in physical memory descriptor type and segment.
 Hardware reset is the only way to come out of protected mode

Fig. 6 : Physical Address Calculation in PVAM

6. Privilege level

 There are four types of privilege levels

1. 00 - kernel level (highest privilege level)
2. 01 - OS services
3. 10 - OS extensions
4. 11 - Applications (lowest privilege level)
 Fig. 7 : Privilege Level

 Each task assigned a privilege level, which indicates the priority or privilege of that task.
 It can only change by transferring the control, using gate descriptors, to a new segment.
 A task executing at level 0, the most privileged level, can access the entire data segment
defined in GDT and LDT of the task.
 A task executing at level 3, the least privileged level, will have the most limited access to
data and other descriptors.
 The use of rings allows for system software to restrict tasks from accessing data.
 In most environments, the operating system and some device drivers run in ring 0 and
applications run in ring 3.

7. DESCRIPTOR TABLE

 GDT, LDT, IDT and TSS are all data structures specified by Intel architecture in memory
management module.
 Descriptor is an identifier of a program segment or page.
GDT
 GDT, Global Descriptor Table, is used to define the characteristics of the various
memory areas used during program execution, including the base address, the size and
access privileges like execute ability and write ability.
  These memory areas are called segments in Intel terminology. Segment is a term for
memory management in Intel architecture, which is also used collaboratively with paging
mechanism.
LDT
 LDT, Local Descriptor Table, acts similar to GDT, which also saves segments descriptor.
 The LDT is the sibling of the Global Descriptor Table (GDT) and defines up to 8192
memory segments accessible to programs.

Difference between LDT and GDT

 The main differences between GDT and LDT is:

1. GDT have only one copy in system while LDT can have many
2. GDT may not change during execution which LDT often changes when task switches
3. Entry of LDT is save in GDT. Entries in GDT and LDT have the same structure.
USE
 A segment cannot be accessed, if its descriptor does not exist in either LDT or GDT.
 Set of descriptor (descriptor table) arranged in a proper sequence describes the complete
program.
 The descriptor is a block of contiguous memory location containing information of a
segment, like
1) Segment base address
2) Segment limit
3) Segment type
4) Privilege level – prevents unauthorized access
5) Segment availability in physical memory
6) Descriptor type
7) Segment use by another task

Requirement of Descriptor Table

 The descriptor describes the location, length, and access rights of the segment of memory.
 The selector, located in the segment register, selects one of descriptors from one of two
tables of descriptors.
 Fig. 8 : Protected Mode Addressing with Descriptor Table

1. Features of 80386
 The 80386 microprocessor is an enhanced version of the 80286 microprocessor
 Memory-management unit is enhanced to provide memory paging.
 The 80386 also includes 32-bit extended registers and a 32-bit address and data bus. These
extended registers include EAX, EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and EFLAGS.
 The 80386 has a physical memory size of 4GBytes that can be addressed as a virtual
memory with up to 64TBytes.
 The 80386 is operated in the pipelined mode, it sends the address of the next instruction
or memory data to the memory system prior to completing the execution of the current
instruction
 This allows the memory system to begin fetching the next instruction or data before the
current is completed. This increases access time.
 The instruction set of the 80386 is enhanced to include instructions that address the 32-
bit extended register set.
 The 80386 memory manager is similar to the 80286, except the physical addresses
generated by the MMU are 32 bits wide instead of 24-bits.
 The concept of paging is introduced in 80386
 80386 support three operating modes:
1) Real Mode (default)
2) Protected Virtual Address Mode (PVAM)
3) Virtual Mode
  The memory management section of 80386 supports virtual memory, paging and four
levels of protection.
 The 80386 includes special hardware for task switching.
2. 80386 Architecture
 The internal architecture of the 80386 includes six functional units that operate in
parallel. The parallel operation is called as pipeline processing.
 Fetching, decoding execution, memory management, and bus access for several
instructions are performed simultaneously.
 The six functional units of the 80386 are
1) Bus Interface Unit
2) Code Pre-fetch Unit
3) Instruction Decoder Unit
4) Execution Unit
5) Segmentation Unit
6) Paging Unit

Figure: 80386 Architecture

 The Bus Interface Unit connects the 80386 with memory and I/O. Based on internal
requests for fetching instructions and transferring data from the code pre-fetch unit, the
80386 generates the address, data and control signals for the current bus cycles.
  The code pre-fetch unit pre-fetches instructions when the bus interface unit is not
executing the bus cycles. It then stores them in a 16-byte instruction queue for decoding
by the instruction decode unit.
 The instruction decode unit translates instructions from the pre-fetch queue into micro-
codes. The decoded instructions are then stored in an instruction queue (FIFO) for
processing by the execution unit.
 The execution unit processes the instructions from the instruction queue. It contains a
control unit, a data unit and a protection test unit.
 The control unit contains microcode and parallel hardware for fast multiply, divide and
effective address calculation. The unit includes a 32-bit ALU, 8 general purpose
registers and a 64-bit barrel shifter for performing multiple bit shifts in one clock. The
data unit carries out data operations requested by the control unit.
 The protection test unit checks for segmentation violations under the control of
microcode.
 The segmentation unit calculates and translates the logical address into linear addresses
at the request of the execution unit.
 The translated linear address is sent to the paging unit. Upon enabling the paging
mechanism, the 80386 translates these linear addresses into physical addresses.
 If paging is not enabled, the physical address is identical to the linear address and no
translation is necessary.
3. Register organization of 80386
The Register organization of 80386 is as follows:
Figure:80386 General Purpose, Index and Pointer Register
3.1. General Purpose Register
 Registers EAX, EBX, ECX, EDX, EBP, EDI and ESI are regarded as general purpose or
multipurpose registers.
 EAX (ACCUMULATOR):The accumulator is used for instructions such as multiplication,
division and some of the adjustment instructions. In 80386 and above, the EAX register
may also hold the offset address of a location in memory system.
 EBX (BASE INDEX): This can hold the offset address of a location in the memory
system in all version of the microprocessor. It the 80386 and above EBX also can address
memory data.
 ECX (count): This acts as a counter for various instructions.
 EDX (data): EDX is a general-purpose registers that holds a part of the result for
multiplication or part of the division. In the 80386 and above this register can also
address memory data.
3.2. Pointer and Index Register
 EBP (Base Pointer): EBP points to a memory location in all version of the
microprocessor for memory data transfers.
 ESP (Stack Pointer): ESP addresses an area of memory called the stack. The stack
memory is a data LIFO data structure. The register is referred to as SP if used in 16 bit mode
and ESP if referred to as a 32 bit register.
 EDI (Destination index): EDI often addresses string destination data for the string
instruction. It also functions as either a 32-bit (EDI) or 16-bit (DI) general-purpose register.
 ESI (Source index): ESI can either be used as ESI or SI. It is often used to the address
source string data for the string instructions. Like EDI ESI also functions as a general-
purpose registers.

Figure:80386 Segment Register

 CS (Code): The code segment is a section of memory that holds the code used by the
microprocessor. The code segment registers defines the starting address of the section of
memory holding code.
  SS (Stack): The stack segment defines the area of memory used for the stack. The stack
entry point is determined by the stack segment and stack pointer registers. The BP
registers also addresses data within the stack segment.
 DS (Data): The data section contains most data used by a program. Data are accessed in
the data segment by an offset address of the contests of other registers that hold the offset
address.
 ES (extra): The extra segment is used to hold information about string transfer and
manipulation
 FS and GS: These are supplementing segment registers available in the 80386 and above
microprocessors to allow two additional memory segments for access by programs.
 EIP (Instruction Pointer): EIP addresses the next instruction in a section of memory
defined as a code segment. This register is IP (16bit) when microprocessor operates in the
real mode and EIP (32 bits) when 80386 and above operate in protected mode

Figure: 80386 Instruction Pointer

3.3. Flag Register:

 Indicates the condition of the microprocessor and controls its operations. Flag registers
are also upward compatible since the 8086-80268 have 16bit registers and the 80386
and above have EGLAF register (32 bits)

Figure: 80386 Flag Register

 IOPL (I/O Privilege level): IOPL is used in protected mode operation to select the
privilege level for I./O devices. IF the current privilege level is higher or more trusted than
the IOPL, I/O executed without hindrance. If the IOPL is lover than the current privilege
level, an interrupt occurs, causing execution to suspend. Note that an IPOL is 00 is the
highest or more trusted; if IOPL is 11, it’s the lowest or least trusted.
  NT (Nested Task): The nested task flag is used to indicate that the current task is
nested within another task in protected mode operation. This flag is when the task I
nested by software.
 RF (Resume): The resume flag is used with debugging to control the resumption of
execution after the next instruction.
 VM (Virtual Mode): The VM flag bit selects virtual mode operation in a protected
mode system.
Note: All the other flag bit is having similar description as in 8086 flag register.

3.4. System Address Register:

 Four memory management registers are used to specify the locations of data structures
which control segmented memory management.

 GDTR (Global Descriptor Table Register) and IDTR (Interrupt Descriptor Table
Register) be loaded with instructions which get a 6 byte data item from memory

 LDTR (Local Descriptor Table Register) and TR (Task Register) can be loaded with
instructions which take a 16-bit segment selector as an operand.

3.5. Special 80386 Register

 Control Register: Four Control Register (CR0-CR3)
 Debug Register: Eight Debug Register (DR0-DR7)
 Test Register: Two Test Register (TR6-TR7)
3.5.1. Control Register in detail.
 The 80386 has three 32 bit control registers CR0, CR2 and CR3 to hold global machine
status independent of the executed task.
 Load and store instructions are available to access these registers
  Common tasks performed by control registers include interrupt control, switching the
addressing mode, paging control, and coprocessor control.

Figure: Control Register

CR0:
 CR0 contains system control flags, which control or indicate conditions that apply to the
system as a whole, not to an individual task.
 PE (Protection Enable, bit 0): Setting PE causes the processor to begin executing in
protected mode. Resetting PE returns to real-address mode.
 MP (Math Present, bit 1): MP controls the function of the WAIT instruction, which is used
to coordinate a coprocessor.
 EM (Emulation, bit 2):EM indicates whether coprocessor functions are to be emulated.
 TS (Task Switched, bit 3):The processor sets TS with every task switch and tests TS
when interpreting coprocessor instructions.
 ET (Extension Type, bit 4):ET indicates the type of coprocessor present in the system
(80287 or 80387).
 PG (Paging, bit 31): PG indicates whether the processor uses page tables to translate
linear addresses into physical addresses.
CR2:
 CR2 is used for handling page faults when PG is set. The processor stores in CR2 the linear
address that triggers the fault.
 Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs,
the address the program attempted to access is stored in the CR2 register.
CR3:
 Used when virtual addressing is enabled, hence when the PG bit is set in CR0, CR3
enables the processor to translate linear addresses into physical addresses by locating
the page directory and page tables for the current task.
 Typically, the upper 20 bits of CR3 become the page directory base register (PDBR),
which stores the physical address of the first page directory entry.
Note: Reserved field shown in figure are kept reserved by manufacturer
 3.5.2. Debug Register
 Debugging of 80386 allows data access breakpoints as well as code execution
breakpoints.
 80386 contains 6 debug registers to specify
1) 4 breakpoints
2) Breakpoint Control options
3) Breakpoint Status

Figure: 80386 Debug Register

Linear Breakpoint Address Registers:
The breakpoint addresses specified are 32-bit linear addresses
While debugging, Intel 386 h/w continuously compares the linear breakpoint addresses
in DR0-DR3 with the linear addresses generated by executing software.
Debug Control Register:

Figure: Debug Control Register

 LENi(i=0 - 3): Breakpoint Length Specification Bits:
1) 2 bit field for each breakpoint
2) Specifies length of breakpoint fields
3) The choices of data breakpoints are 1byte, 2bytes & 4bytes
4) For instruction execution breakpoint, the length is 1(beginning byte address)
 Table: LENi Encoding

 RWi(i=0 - 3): Memory Access Qualifier Bit

1) 2 bit field for each breakpoint
2) Specifies the type of usage which must occur inorder to activate the associated
breakpoint

Table: Table: RWii Encoding

GD: Global Debug Register Access Detect
 Debug registers can only be accessed in real mode or at privilege level 0 in protected
mode
  GD bit, when set, provides extra protection against any Debug Register access even in Real
Mode or at privilege level 0 in Protected Mode.
 The GD bit, when set, causes an exception 1 fault if an instruction attempts to read or
write any Debug Register.
 The GD bit is then automatically cleared when the exception 1 handler is invoked, allowing
the exception 1 handler free access to the debug registers.
GE and LE bit: Exact data breakpoint match, global and local
Gi and Li(i=0 - 3): Breakpoint Enable, global and local
 If either Gi or Li is set then the associated breakpoint is enabled.
Debug Status Register:
 A Debug Status Register allows the exception 1 handler to easily determine why it was
invoked.
 It can be invoked as a result of one of several events:
1) DR0 Breakpoint fault/trap.
2) DR1 Breakpoint fault/trap.
3) DR2 Breakpoint fault/trap.
4) DR3 Breakpoint fault/trap.
5) Single-step (TF) trap.
6) Task switch trap.
7) Fault due to attempted debug register access when GD = 1.

Figure: Debug Status Register

Bi : Debug fault/trap due to breakpoint 0 -3
 Four breakpoint indicator flags, B0-B3, correspond one-to-one with the breakpoint
registers in DR0-DR3.
 A flag Bi is set when the condition described by DRi, LENi, and RWi occurs.
BD: Debug fault due to attempted register access when GD bit is set
 This bit is set if the exception 1 handler was invoked due to an instruction attempting to
read or write to the debug registers when GD bit was set.
BS: Debug trap due to single step
 This bit is set if the exception 1 handler was invoked due to the TF bit in the flag
register being set
BT: Debug trap due to task switch
  This bit is set if the exception 1 handler was invoked due to a task switch occurring to a
task having an Intel386.
3.5.3. Test Register
 Two more test register are provided by 80386 for page caching
 They are used to control the testing of Translation Look-aside Buffer(TLB) of Intel386.
 TR6 is the command test register
 TR7 is the data register which contains the data of Translation Look-aside buffer test.

Figure: Test Register

3.6. Program-Invisible registers

 The global and local descriptor tables are found in the memory system.
 In order to access and specify the address of these tables, the program invisible registers
used.
 The program invisible registers are not directly addressed by software so they are given
name.
 The GDTR (global descriptor table register) and IDTR (interrupt descriptor table
register) contain the base addresses of the descriptor table and its limit.
 The limit of each descriptor table is 16 bits because the maximum table length is 64
Kbytes.
 When the protected mode operation is desired, the address of the global descriptor table
and its limit are loaded into the GDTR.
4. Real Modes of 80386
 Default Mode
 After reset, the 80386 starts from the memory location FFFFFFF0 H under real address
mode.
 In real address mode, 80386 works as a fast 8086 with 32 bit registers and data types.
 Real-address mode is in effect after a signal on the RESET pin. Even if the system is
going to be used in protected mode, the start-up program will execute in real-address
mode temporarily while initializing for protected mode.
 The addressing techniques, memory size, interrupt handling in this mode of 80386 are
similar to the real addressing mode of 80286.
 In real address mode, the default operand size is 16 bit but 32 bit operands and
addressing modes may be used with the help of override prefixed.
 Maximum physical memory = 1Mega byte (1MB)
 The only way to leave real-address mode is to switch to protected mode.
5. PVAM of 80386
  Introduced in the 80386 processor.
 32-bit address bus => access up to 232 bytes = 22. 230 B = 4 GB
 Base address => 32-bit value
 Offset =>16-bit or 32-bit value
 Linear address = base address + offset
 Linear address → physical address with paging
 In protected mode, the segment registers contain an index into a table of segment
descriptors.
 Each segment descriptor contains the start address of the segment, to which the offset is
added to generate the address.
 In addition, the segment descriptor contains memory protection information.
 This includes an offset limit and bits for write and read permission.
 This allows the processor to prevent memory accesses to certain data.
 Protected mode is accessed by placing a logic 1 into the PE bit of CR0
 This system contains one data segment descriptor and one code segment descriptor with
each segment set to 4G bytes in length.
 PVAM mode support memory management, virtual memory, multitasking, protection,
debugging, segmentation and paging.
6. Virtual Mode of 80386
 In its protected mode of operation, 80386DX provides a virtual 8086 operating
environment to execute the 8086 programs.
 The real mode can also use to execute the 8086 programs along with the capabilities of
80386, like protection and a few additional instructions.
 Once the 80386 enters the protected mode from the real mode, it cannot return back to
the real mode without a reset operation.
 Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086
programs while in protected mode.
 The address forming mechanism in virtual 8086 mode is exactly identical with that of
8086 real mode.
 In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in
the 4Gbytes address space of the protected mode of 80386.
 Like 80386 real mode, the addresses in virtual 8086 mode lie within 1Mbytes of memory.
 In virtual mode, the paging mechanism and protection capabilities are available at the
service of the programmers.
 The 80386 supports multiprogramming, hence more than one programmer may be using
the CPU at a time.
  Paging unit may not be necessarily enable in virtual mode, but may be needed to run the
8086 programs which require more than 1Mbyts of memory for memory management
function.
 In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size.
 Each of the pages may be located anywhere in the maximum 4Gbytes physical memory.
 The virtual mode allows the multiprogramming of 8086 applications.
 The virtual 8086 mode executes all the programs at privilege level 3.
 Any of the other programmers may deny access to the virtual mode programs or data.
 Even in the virtual mode, all the interrupts and exceptions are handled by the protected
mode interrupt handler.
 To return to the protected mode from the virtual mode, any interrupt or execution may
be used.
 As a part of interrupt service routine, the VM bit may be reset to zero to pull back the
80386 into protected mode.
7. Segment in
80386
 In protected mode the contents of segment register is called selectors shown below:-

Figure: Segment Selector

Descriptor Index: Selects any one of the 8192(213) descriptor from a descriptor table
TI – Table Indicator
 TI=1 Local Descriptor Table
 TI=0 Global Descriptor Table
RPL (Requested Privilege Level)(2-bit): Refers the privilege of that segment. They are used
while protection checks to indicate whether access to segment is allowed or not allowed.

7.1. 80386 Descriptor

Need of Descriptor
 Segments are the memory area defined by programmer and can be code, stack and data
segment.
 80386 segments are also assigned to have attributes viz. privilege level, segment type, segment
limit.
 So, it’s not possible to use a 16 bit segment register to represent all the info regarding a
segment. therefore the Solution is Descriptor
 Segment sizes vary from 1byte to 4GB in 80386.

Figure: Segment Descriptor in Protected Mode

Offset Bit Description

40 A(Accessed) 80386 sets this bit to 1 whenever a memory reference to a segment

defined by this descriptor is made.

41-43 TYPE 3-bit field describes the type of segment

000 Data segment , read only

001 Data segment , read/write

010 Stack segment, read only

011 Stack segment, read/write

100 Code segment, execute-only, non-conforming

101 Code segment, execute/read, non-conforming

110 Code segment, execute-only, conforming

111 Code segment, execute/read, conforming

44 S(System) 0 – Specifies system segment descriptor

E.g. LDS, TSS, Gates

1 – Specifies non system segment descriptor

E.g. code, stack or data

45-46 DPL (Descriptor Indicates privilege level associated with memory space. 0 - most
privileged 3 – least privileged
Privilege level)

47 Present If set 0 , indicates that the address range that is specified by the
descriptor is temporarily not present.

52 U(User) Undefined bit.

53 X Reserved by Intel

54 D(Default Size) 0 – Operands within this segments are assumed to be 16 bits.

1 – Operands assumed to be 32 bits

55 G(Granularity 1 – Unit of limit field is 1 byte.

bit)
2 – Unit of limit field is of 4096 bytes (or 1 page).

 The Above figure is the format of the code/data descriptor; one descriptor is 64-bit long.
 As we can see, a descriptor actually includes a 32-bit base address and a 20-bit limit and
some attributes, the 32-bit base address indicate where the segment starts, and the 20-bit
limit indicates the length of the segment.
 However, a problem comes up, 20-bit limit can only represent 2^20 = 1MB memory, to access
a 4GB memory space, descriptor uses G bit to indicate whether the limit use 4K or 1 byte for
one unit, that means if G bit is set then we get 2^20*4K = 4GB memory, if it is unset then we
only use a memory space under 1MB.

7.2. Descriptor tables in 80386

 The segment descriptors that we defined are grouped together and placed in a continuous
memory location. The group arrangement called Descriptor Table.
 Each descriptor requires 8byte in order to store the info of a particular segment.
 Descriptor table can contain 8192(8K) descriptors at the max.
 The maximum length of a descriptor table is a 64Kbytes.
 The descriptor tables define all the segments used in the 80386 when it operates in the
protected mode.
 There are three types of descriptor tables: the global descriptor table (GDT), the local
descriptor table (LDT), and the interrupt descriptor table (IDT).
 The registers used by the 80386to address these three tables are called the global descriptor
table register (GDTR), the local descriptor table register (LDTR), and the interrupt
descriptor table register (IDTR).
 These registers are loaded with the LGDT, LLDT, and LIDT instructions, respectively.
 The local and global descriptor tables hold up to 8192 entries each, and the interrupt
descriptor table holds up to 256 entries.
 A descriptor is indexed from either the local or global descriptor table by the selector that
appears in a segment register.
 Whenever a new selector is placed into one of the segment registers, the 80386 accesses
one of the descriptor tables and automatically loads the descriptor into a program-invisible
cache portion of the segment register.

1) Global Descriptor Table (GDT):

 This is the main table of descriptors.
 The same GDT can be used by all programs to refer to segment of memory.
 80386 can have many LDT’s but only one GDT.

Figure: Global Descriptor Table

2) Local Descriptor Table (LDT) :
 A multi-tasking system is defined on a per task basis.
 The main purpose of an LDT would be combined with GDT in order to expand the total
number of available descriptors.
 Generally, each task can have its own LDT and can also be shared with other task.
8. Paging
  Paging is one of the memory management techniques
 The paging mechanism allows any linear (logical) address, as it is generated by a program,
to be placed into any physical memory page, as generated by the paging mechanism.
 A linear memory page is a page that is addressed with a selector and an offset in either
the real or protected mode.
 A physical memory page is a page that exists at some actual physical memory location.
 For example, linear memory location 20000H could be mapped into physical memory
location 30000H, or any other location, with the paging unit. This means that an
instruction that accesses location 20000H actually accesses location 30000H. Each
80386 memory page is 4K bytes long.
 Paging allows the system software to be placed at any physical address with the paging
mechanism.
 Three components are used in page address translation: the page directory, the page
table, and the actual physical memory page.
 The segmentation scheme may divide the physical memory into a variable size
segments but the paging divides the memory into a fixed size pages.
 The segments are supposed to be the logical segments of the program.
 The pages are just fixed size portions of the program module or data.
Advantage:
 The advantage of paging scheme is that the complete segment of a task need not be in
the physical memory at any time.
 Only a few pages of the segments, which are required currently for the execution need to be
available in the physical memory.
 Thus the memory requirement of the task is substantially reduced, relinquishing the
available memory for other tasks.
8.1. Page Directory
 The page directory contains the location of up to 1024 page translation tables, which are
each four bytes long.
 Each page translation table translates a logical address into a physical address.
 The page directory is stored in the memory and accessed by the page descriptor address
register (CR3).
 Control register CR3 holds the base address of the page directory, which starts at any
4K- byte boundary in the memory system.
 Each entry in the page directory translates the leftmost 10 bits of the memory address.
This 10-bit portion of the linear address is used to locate different page tables for
different page table entries.
8.2. Page Table
  The page table contains 1024 physical page addresses, accessed to translate a linear
address into a physical address.
8.3. Page Directory Entry
 Total Page Directory Entries are1024
 Each directory entry is of 4byte

8.4. Page Table Entry Figure: Page Directory Entry

 The page table entries contain the starting address of the page and the statistical
information about the page.
 Total Entries are1024
 Each page table entry is of 4byte

Figure: Page Table Entry

 D-bit: Dirty bit is undefined for page table directory entries by the 80386
microprocessor and is provided for use by the operating system.
 A-bit: Accessed bit is set to logic 1 whenever the microprocessor accesses the page
Directory entry.
 R/W (Read/write) & U/S (user/supervisor) are both used in the protection scheme.
Both bits combine to develop paging priority level protection for level 3, the lowest user
level.

 P-bit: Present bit, if logic1 indicates that the entry can be used in address translation. If
P = 0, the entry cannot be used for translation. When P = 0, the remaining bits of the
entry can be used to indicate the location of the page on the disk memory system.
Difference between page directory and page table entry:
  The main difference is that the page directory entry contains the physical address of a page
table, while the page table entry contains the physical address of a 4K-bytephysical page of
memory.
 The other difference is the D (dirty bit), which has no function in thepage directory entry,
but indicates that a page has been written to in a page table entry.
8.5. Page Translation Mechanism in 80386
 A page frame is a 4K-byte unit of contiguous addresses of physical memory. Pages begin on
byte boundaries and are fixed in size.
 A linear address refers indirectly to a physical address by specifying a page table, a page
within that table, and an offset within that page

Figure: Format of Linear Address

 The below figure of page translation shows, how processor converts the DIR, PAGE, and
OFFSET fields of a linear address into the physical address by consulting two levels of page
tables.
 The addressing mechanism uses the DIR field as an index into a page directory, uses the
PAGE field as an index into the page table determined by the page directory, and uses
the OFFSET field to address a byte within the page determined by the page table.
 In the second phase of address transformation, the 80386 transforms a linear address
into a physical address.
 This phase of address transformation implements the basic features needed for page-
oriented virtual-memory systems and page-level protection.
 Page translation is in effect only when the PG bit of CR0 is set.

Figure: Page Translation

9. Features of 80486
 The 32-bit 80486 is the next evolutionary step up from the 80386.
 One of the most obvious feature included in a 80486 is a built in math coprocessor. This
coprocessor is essentially the same as the 80387 processor used with a 80386, but being
integrated on the chip allows it to execute math instructions about three times as fast as
a 80386/387 combination.
 80486 is an 8Kbyte code and data cache.
 To make room for the additional signals, the 80486 is packaged in a 168 pin, pin grid
array package instead of the 132 pin PGA used for the 80386.
 Operates on 25MHz, 33 MHz, 50 MHz, 60 MHz, 66 MHz or 100MHz.
 It consists of parity generator/checker unit in order to implement parity detection and
generation for memory reads and writes.
 Supports burst memory reads and writes to implement fast cache fills.
 Three mode of operation: real, protected and virtual 8086 mode.
 The 80486 microprocessor is a highly integrated device, containing well over 1.2
million transistors.
10. Pentium Processor
Features
 It consists of all the features of 80486. The additional enhancements that Pentium
provides are:
1) Wider data bus width :
 It has 64 bit data bus and 32 bit address bus.
 It allows 8 byte of data info to be transferred to and from memory.
 Bus cycle pipelining has been added to allow two bus cycles to be in progress
simultaneously.
2) Improved Cache Structure:
 8KB dedicated instruction cache which gives instruction to its execution units and
floating point unit via dual instruction pipeline.
 Cache is organized in a 2 way set associate cache with 32 byte line(256 lines).
 8KB data cache which gives data to its execution unit.
 This allows 32 byte transfer from cache to pre-fetch buffer which is of 64 bytes.
3) Two parallel integer execution unit :
 It allows the execution of two instructions to be executed simultaneously in a single
processor clock.
4) Faster floating point unit :
 The floating point unit has been completely redesigned over 80486.
  Faster algorithms provide up to ten times speed – up for common operations including
add, multiply etc.
5) Branch prediction logic:
 The Pentium uses tech called branch prediction.
 To implement this Pentium has two pre-fetch buffers, one to pre-fetch code in linear
fashion, and one that pre-fetches code according to the Branch Target Buffer (BTB).
 Therefore, needed code is almost pre-fetched before it is required for execution.
6) Data Integrity and Error Detection:
 The Pentium have added significant data integrity and error detection capability.
 Data parity checking is still byte-by-byte basis.
 Address parity checking has also been added.
7) Functional Redundancy Checking: (provides maximum error detection)
 Two or more Pentium Processor can participate in functional redundancy checking.
 One processor (the master) fetching the instruction and executes the instruction in
normal fashion.
 Other processor (the checker) (connected directly to the master processor’s buses)
verify correctness of master processor.
 Checker executes the instruction same as the master but doesn’t drive the buses.
 Checker samples master’s output and compares the values with the internal computed
values. An error signal is asserted in case if mismatch occurs.
8) Super Scalar Architecture:
 Processor is capable of parallel instruction execution of multiple instructions are known
as superscalar processors.
 Pentium is capable in some cases of executing two integer of two floating point
instruction simultaneously and thus support superscalar architecture.
10.1 Architecture
 Figure: Pentium Architecture
Features of
80486
 The 32-bit 80486 is the next evolutionary step up from the 80386.
 One of the most obvious feature included in a 80486 is a built in math coprocessor. This
coprocessor is essentially the same as the 80387 processor used with a 80386, but being
integrated on the chip allows it to execute math instructions about three times as fast as
a 80386/387 combination.
 80486 is an 8Kbyte code and data cache.
 To make room for the additional signals, the 80486 is packaged in a 168 pin, pin grid
array package instead of the 132 pin PGA used for the 80386.
 Operates on 25MHz, 33 MHz, 50 MHz, 60 MHz, 66 MHz or 100MHz.
 It consists of parity generator/checker unit in order to implement parity detection and
generation for memory reads and writes.
 Supports burst memory reads and writes to implement fast cache fills.
 Three mode of operation: real, protected and virtual 8086 mode.
 The 80486 microprocessor is a highly integrated device, containing well over 1.2
million transistors.
Explain Architecture of 80486 Processor.
 The architecture of the 80486DX is almost identical to the 80386. Added to the 80386
architecture inside the 80486DX is a math coprocessor and an 8K-byte level 1 cache
memory.

Figure: 80486 Architecture

BIU:

 BIU generates address, data and control signals for a bus cycle it is supported with an
additional parity detection/generation for memory reads and writes.
 During memory write operation, the 486 generates even parity bit for each byte outputs
these bits.
 These bits will be stored in a separate parity memory bank.
 During read operation, stored parity bits will be read from the parity memory.
 80486 checks the parities of data bytes read and compare them with the DP0 – DP3
signals and generates parity check error, if it occurs.

Instruction Pre-fetch Unit :

 It pre-fetches the instruction bytes in advance and holds them in a 32–byte code queue.

Instruction Decoder :

 Decodes the instructions in the queue and passes the control and protection test unit.

Execution Unit:

 Executes the instruction with the help of Barrel Shifter, ALU and Register bank.
Segmentation Unit and Paging Unit :

 They are part of MMU(which manages virtual memory of system). Helpful in generation of
Physical Address.
 Work same as they work in 80386.

Floating Point Unit:

 Responsible for performing the floating point operations.

 The 80486 has a built in math co-processor . It performs the floating point operations.
 It executes math instructions 3 times faster than the 386/387 combination.

Cache Unit:

 8KB cache
 Additional high speed cache memory provides a way of improving overall system
performance.
 It contains the recently used instructions, data or both.
 The main aim is that the microprocessor unit access code and data in the cache most of
time, instead from the main memory.

EFLAG Register
 The extended flag register EFLAG is illustrated in the figure below:-

 The only new flag bit is the AC alignment check, used to indicate that the
microprocessor has accessed a word at an odd address or a double word boundary.

Figure: EFLAG Register of The 8048