Introduction to 80386

Syllabus

Part A:
1. Brief History of Intel Microprocessor
2. 80386DX Features and Architecture
3. Programmers Model
4. Operating Modes
5. Addressing Mode
6. Data Types
 Syllabus
Part B: Applications Instruction Set

1. Data Movement Instruction

2. Binary Arithmetic Instruction
3. Decimal Arithmetic Instruction
4. Logical Instruction
5. Control Transfer Instruction
6. String and Character Transfer Instruction
7. Flag Control Instruction
8. Coprocessor Interface Instruction
9. Segment Register Instruction
10.Mis. Instruction
Features of 80386
1. The 80386DX is a 32-bit microprocessor, which means it
can process 32-bit data and addresses at a time.
2. It has 8 general purpose 32 bit registers
3. The original 80386DX typically runs 12 MHz to 33 MHz.
4. The processor can address up to 4 gigabytes of physical
memory and 64 terabytes of virtual memory.
5. Pipeline architecture which allows simultaneous instruction
fetching, decoding, and executing, the average execution
time has been significantly reduced.
6. It allows user to switch between different OS such as DOS
and UNIX
7. Operates in Real, Protected and Virtual 8086 mode.
8. It compatible with 8086,8088, 80186, 80286
architecture.
9. It can operate on 17 data types like bits, byte,
word, double word, Quadword etc.
10. It has separate pins for its address and data
line for higher performance and easier hardware
design.
11. It support 4 level protection
12. It support high speed numeric 80387 coprocessor
Architecture of
80386
 Memory management unit
Central processing unit

Bus interface unit

Prefetch Unit
●The Internal Architecture of 80386 is divided into
3 sections.

1. Bus interface unit(BIU)

2. Central processing unit(CPU)
a. Execution Unit
b. Instruction Unit
3. Memory management unit(MMU)
a. Segmentation Unit
b. Paging Unit
Bus Control Unit:
1. Is the 80836 communication with the outside world. It
provides a full 32 bit bi-directional data and 32- bit
address bus.
2. Accepts internal requests for code fetch and for data
transfers from the code fetch unit and from the
execution unit. It then prioritize the request and
generates signals to perform bus cycles.
3. It send address, data and control signals to
communicate with memory and I/O devices
4. It controls the interface to external bus masters and
coprocessors.
5. It also provides the address relocation
facility.
.
Instruction Prefetch Unit
1. Fetches sequentially the instruction byte stream from
the memory. It uses bus control unit to fetch
instruction bytes.
2. These prefetched instruction bytes are stored in 16
bytes code queue.
3. When jump or call instructions are executed, the
contents of the prefetched and decode queues are
cleared out

Instruction Predecode Unit :

4. Takes instruction byte from the instruction prefetch
queue and translate them into microcode.
5. The decoded instruction then stored in instruction
queue
Central processing unit(CPU)
Execution Unit : Reads the instruction
instruction queue and execute the instruction.
1. Control Unit: It contains microcode and special
hardware allows processor to reduce time required for
execution of multiply and divide instruction. It also
speeds the effective address calculation.
2. Data Unit: Responsible for data operations requested by
the control unit. It contains ALU, eight 32 bit general
purpose registers and 64 bit barrel shifter. The barrel
shifter is used for multiple bit shifts in one clock. Thus it
increases the speed of all shift and rotate operations.
3. Protection Test Unit: checks for segmentation violations
under the control of the microcode.
Memory Management Unit
Segmentation Unit:
1. Translate logical address to linear addresses at the request
of execution unit.
2. Compares the effective address for the length limit
specified in the segment descriptor. Adds the segment base
and the effective address to generate linear address.
3. Before calculation of linear address it also checks access
rights.
4. It provides a 4 level protection mechanism for protecting
and isolating the system code and data from those of the
application program
2) Memory Management Unit
Paging Unit:
1. Translate linear addresses generated by the segmentation
unit into physical addresses.
2. If paging unit is not enabled, the physical address is the
same as the linear address.
3. It give physical address to the Bus Interface Unit to
perform memory and I/O accesses.
4. It organizes the physical memory in terms of pages of
4kbyts size each.
Programmer’s
Model of
80386
Programmer’s Model of 80386
The 80386 programmer’s model is a picture of the registers available to
the programmer .
These registers are used to hold the numbers and addresses , as well as
indicate status and acts as controls.

1. Data Registers :EAX, EBX , ECX, EDX

2. Address Registers:Segment register : CS, DS, ES , SS, FS, GS and IP,
SP,BP,SI,DI
3. Flag Registers
 Register
Organization
●General Purpose Register
●Pointer register
●Index register
●Segment Register
●Eflags
●System Address/Memory management
Registers
●Control Register
●Debug Register
●Test Register
●General Purpose Register
◦ The 32-bit general-purpose registers (EAX,
EBX, ECX, EDX).
◦ The 16-bit general-purpose registers (AX, BX, CX,
DX).
◦ The 8-bit general-purpose registers (AH,
BH, CH, DH, AL, BL, CL, or DL).
●Pointer Register
◦ The 32 bit pointer register (EBP, ESP)
◦ The 16-bit Pointer registers (BP, SP)
●Index Register
◦ The 32 bit Index register (ESI, EDI)
◦ The 16-bit Pointer registers (SI, DI)
●Instruction Pointer
◦ The 32 bit Instruction pointer (EIP)
●Segment Registers
◦ The 16- bit segment registers (CS, DS, SS, ES, FS,
and GS).
 Index
Register

General
Pointer
Purpose Register

Register

Segment

Register
 ●Six Conditional ●Three Control
or status Flags Flags
◦Carry Flag (CF) ◦Interrupt Flag (IF)
◦Parity Flag (PF) ◦Trap Flag (TF)
◦Auxiliary Flag( AF) ◦Direction Flag (DF)
◦Zero Flag (ZF)
◦Sign Flag (SF)
◦Overflow Flag (OF)
●Four System Flags
◦Input/output privilege level
(IOPL)
◦Nested Task (NT)
◦Resume Flag (RF)
◦Virtual Mode Flag (VM)
Control Flags

DF ( Direction flag) : The direction flag controls the direction of string operations.
When the D flag is cleared these operations process strings from low memory up
towards high memory. This means that offset pointers (usually SI and DI) are
incremented by 1 after each operation in the string instructions when D flag is
cleared. If the D flag is set, then SI and DI are decremented by 1 after each
operation to process strings from high to low memory.

IF (Interrupt Flag) : When interrupt flag is set, the 80386 recognizes and handles
external hardware interrupts on its INTR pin. If the interrupt flag is cleared, 80386
ignores any inputs on this pin. The IF flag is set and cleared with the STI and CLI
instructions, respectively.

TF (Trap Flag) : Trap flag allows user to single-step through programs. When an
80386 detects that this flag is set, it executes one instruction and then
automatically generates an internal exception 1. After servicing the exception, the
processor executes the next instruction and repeats the process. This single
stepping continues until program code resets this flag for debugging programs
single step facility is used.
System Flags

VM (Virtual Memory) flag indicates operating mode of 80386. When VM

flag is set, 80386 switches from protected mode to virtual 8086 mode.

R (Resume) flag/Restart flag : This flag, when set allows selective

masking of some exceptions at the time of debugging.

NT (Nested flag) : This flag is set when one system task invokes another
task. (i.e. nested task).

IOPL (1/0 Privilege level) : The two bits in the IOPL are used by the
processor and the operating system to determine your application's access
to I/0 facilities. It holds privilege level, from O to 3, at which the current
code is running in order to execute any I/0 related instruction.
●NT (Nested flag) :
◦ This flag is set when one system task invokes another
task.(i.e. nested task).
●IOPL (l/O Privilege level) :
◦ The two bits in the IOPL are used by the processor
and the operating system to determine your
application's access to I/O facilities.
Operating Modes of
80386
Operating Modes of 80386
1. Real Mode:
● In real mode, the processor emulates the behavior of these 8086
processors.
● It has access to only 1 MB of memory.
2. Protected Mode:
● Protected mode is a 32-bit operating mode all instruction and
features are available
● It provides access to a 4 GB address space and supports
multitasking and virtual memory.
● It includes features like privilege levels (Rings 0-3) to control
access to system resources.
3. Virtual 8086 Mode:
● This mode allows running multiple instances of real mode 8086
programs concurrently under protected mode.
● It enables multitasking in a way that is compatible with older 16-
bit software.
Operating Modes of 80386
Real Mode

When the 80386 is turned on for the first time, the Real mode is its
default operating mode.

Software created for the 8086 and 8088 processors will work on the
80386 without needing to be modified because it is fully backward-
compatible with these older CPUs.

The 80386 has a 20-bit address space in Real mode, giving it access to
1MB of memory. The memory is separated into 64K segments, and a
16-bit segment register can be used to access each section.

The processor uses segment-based memory addressing while operating

in this mode and is not given access to sophisticated memory
management and security functions. Real mode likewise has a
constrained set of instructions and does not support protected or
virtual memory.
Operating Modes of 80386
Protected Mode:
A 32-bit address space is available in protected mode, a
sophisticated operating mode that gives users access to up to 4GB
of memory.

Additionally, it offers sophisticated memory management and

security features including segmentation and paging. Pages are
fixed-size units of memory that can be moved in and out of physical
memory as needed. Paging enables this.

Memory can be separated into logical units called segments

through segmentation, which can be used to restrict access to
particular memory locations.

The 80386 also has access to a number of privileged instructions

and registers in a protected mode that are not present in regular
mode. The protected mode also supports virtual memory which
allows the system to use more memory than the physical memory
available by swapping memory pages to and from the disk.
Operating Modes of 80386
Virtual 8086 Modes

The 80386 may operate numerous virtual environments that are

compatible with the 8086 simultaneously in virtual 8086 modes.

Although they share the same physical memory, each virtual

environment has its own set of registers and memory space.
This mode enables the 80386 to mimic the actions of an 8086
processor, which is frequently used to run older applications on
more modern computers. T

he 80386 may move between many virtual environments as

needed thanks to the system for handling interrupts and
exceptions that are provided by virtual 8086 modes.

The virtual 8086 mode allows for the simultaneous operation of

numerous virtual machines without interfering with one another
while simulating the behavior of a real 8086 CPU in a protected
virtual memory environment.
Addressing Modes
of 80386
Addressing Modes of 80386
As a part of programming flexibility, processor provides
different ways to access these operands from different
locations.
The different ways by which processor can access data are
referred to as addressing modes.
The 80386DX provides a total of 11 addressing modes for
instructions to specify operands.
These addressing modes can be categorized in three
groups :
• Register operand addressing (Register Addressing mode)
• Immediate operand addressing (Immediate Addressing )
• Memory operand addressing.(Memory Addressing mode)
 Addressing Modes of 80386
Immediate Operands : (Immediate Addressing mode)
Certain instructions use data from the instruction itself as
operands.
Such an operand is called an immediate operand.
The operand may be 32-, 16-, or 8-bits long.

MOY EAX, 10B89C20H

 Addressing Modes of 80386
Register operand addressing : (Register Addressing mode)
Operands may be located in one of the 32-bit general
registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP), in one of
the 16-bit general registers (AX, BX, CX, DX, SI, DI, SP, or BP),
or in one of the 8-bit general registers (AH, BH, CH, DH, AL,
BL, CL, or DL).

MOV EAX, EDX

 Addressing Modes of 80386
Memory operand addressing:(Memory Addressing mode)
The remaining 9 addressing modes provide a mechanism for
specifying the physical address of an operand.
In 80386DX, physical address is calculated before any read or
write operation.
The physical address consists of two components : The
segment base address and an effective address. The effective
address can be specified in a variety of ways. One way is to
encode the effective address of the operand directly in the
instruction. This represents direct addressing mode. The
effective address can be generated with the combinations of
four addressing elements : Base, Index, Scale factor and
Displacement.
 Addressing Modes of 80386
Memory operand addressing:(Memory Addressing mode)
1. Direct Addressing Mode :

MOV EAX, [12345678H]

2. Register Indirect addressing Mode:

MOV EAX, [EBX]

3. Based addressing mode:

MOV EAX, [EBX+12345678H]

 Addressing Modes of 80386
Memory operand addressing:(Memory Addressing mode)
4. Index Addressing mode:
MOV EAX, [ESI+12345678H]

5. Scaled Index addressing mode:

MOV EAX, [4*ESI+12345678H]

6. Based Index addressing mode:

MOV EAX, [EBX, ESI]
 Addressing Modes of 80386
Memory operand addressing:(Memory Addressing mode)
7. Based scaled index addressing mode:
MOV EAX, [EBX+8*ESI]

8. Based index mode with displacement

MOV EAX, [EBX+ESI+12345678H]

9. Based scaled index mode with displacement

MOV EAX, [EBX+2*ESI+12345678H]

Data Types
●Fundamental Data
Types
Instruction Set of
80386
 Syllabus
Part B: Applications Instruction Set
1. Data Movement Instruction
2. Binary Arithmetic Instruction
3. Decimal Arithmetic Instruction
4. Logical Instruction
5. Control Transfer Instruction
6. String and Character Transfer Instruction
7. Flag Control Instruction
8. Coprocessor Interface Instruction
9. Segment Register Instruction
10.Mis. Instruction
 Data Movement Instructions
These instructions provide convenient methods for moving bytes, words, or doublewords
of data between memory and the registers of the base architecture.
They fall into the following classes:

1. General-purpose data movement instructions : MOV and XCHG

2. Stack manipulation instructions : PUSH, POP, PUSHA and POPA

3. Type-conversion instructions : CWD, CDQ CBW, CWDE, MOVSX and MOVZX

 Binary Arithmetic Instructions
The arithmetic instructions of the 80386 processor simplify the manipulation of numeric
data that is encoded in binary.
Operations include the standard add, subtract, multiply, and divide as well as increment,
decrement, compare, and change sign.
Both signed and unsigned binary integers are supported. T
he binary arithmetic instructions may also be used as one step in the process of
performing arithmetic on decimal integers.

1. Addition instructions : ADD, ADC, INC, AAA, and DAA.

2. Subtraction instructions SUB, SBB, DEC, AAS, DAS, CMP, and NEG

3. Comparison and Sign Change Instruction: CMP and NEG

4. Multiplication Instructions : MUL and IMUL

5. Division Instructions : DIV and IDIV

 Decimal Arithmetic Instructions
TThe decimal arithmetic instructions are classified as :
1. Packed BCD Adjustment Instructions : DAA and DAS
2. Unpacked BCD Adjustment Instructions : AAA, AAS, AAM and AAD
 Logical Instructions
The group of logical instructions includes:

1. The Boolean operation instructions : AND, OR, XOR and NOT

2. Bit test and modify instructions : BIT, BTS, BTR and BTC

3. Bit scan instructions : BSF and BSR

4. Shift instructions : SAL, SHL, SAR, SHR, SHLD and SHRD

5. Rotate instructions : ROL, ROR, RCL and RCR

6. Byte set on condition : SETcc

7. Test Instruction : TEST

 Control Transfer Instructions
The 80386 provides both conditional and unconditional control transfer instructions to
direct the flow of execution. Conditional control transfers depend on the results of
operations that affect the flag register. Unconditional control transfers are always
executed.
1. Jump Instruction : JMP
2. Call Instruction : CALL
3. Return and Return-From-Interrupt Instruction : RET and IRET
4. Unsigned Conditional Transfers : JA/JNBE, JAE/JNB, JB/JNAE, JBE/JNA, JC, JE/JZ,
JNE/JNZ,JNP/JPO and JP/JPE
5. Signed Conditional Transfers : JG/JNLE, JGE/JNL, JL/JNGE, JLE/JNG, JNO, JO
and JS
6. Loop Instructions : LOOP, LOOPE and LOOPNE
7. Executing a Loop or Repeat Zero Times : JCXZ
8. Software-Generated Interrupts : INT n, INTO, and BOUND
 String and Character Translation Instructions
A set of primitive string operations : MOVS, CMPS, SCAS, LOOS and STOS
Control flag instructions: CLD and STD
Repeat prefixes : REP, REPE/REPZ, REPNE/REPNZ

Flag Control Instructions

The flag control instructions provide a method for directly changing the state of bits
the flag register.
1. Carry and Direction Flag Control Instructions : STC, CLC, CMC, CLD and STD
2. Flag Transfer Instructions : LAHF, SAHF, PUSHF and POPF
 Segment Register Instructions
The instructions that deal with segment registers are

1. Segment-register transfer instructions : MOV SegReg, ... , MOV ... , SegReg, PUSH
SegReg and POP SegReg

2. Control transfers to another executable segment : JMP far, CALL far and RET far 3. Data
pointer instructions : LOS, LES, LFS, LGS and LSS

3. Interrupt-related instructions capable of transferring control to another segment

INT n, INTO, BOUND and IRET