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Design of high frequency D flip flop circuit for phase detector application

Conference Paper · November 2017

DOI: 10.1109/TENCON.2017.8227867

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 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

Design of High Frequency D Flip Flop Circuit for

Phase Detector Application
Suraj Kumar Saw1, Preetisudha Meher2 Swarnendu Kumar Chakraborty3
1.2
Department of Electronics and Communication Engineering
3
Department of Computer Science Engineering
National Institute of Technology
Arunachal Pradesh India
srjsaw98@gmail.com1

Abstract— A low power, high frequency positive edge D flip Nand based D flip flop circuit has been implemented and
flop circuit is implemented. Its operating frequency is 5GHz with found suitable for Phase detector applications [9]. The sources
a supply voltage of 1.8 V produces a output at a positive edge of power dissipation in the Flip flop circuits are implemented
triggered signal. It consists of 16 transistor which compel low by a following expression [10].
power of 10.42 µW with a phase noise of -147dBc/Hz and output
noise -154.77dB at offset frequency 1 MHz, Circuits is also tested
at different corner frequency and has minimal area of Pavg = Pshortcircuit + Pswitching + Pleakage (1)
88.571µmm2 simulation of results is done by cadence tools in
90nm CMOS process The proposed D flip flop has outplayed the Pavg = I sc .Vdd + αC V f clk + I leakage .Vdd
2
L dd (2)
prior research in terms of performance metrics.

Keywords—Delay Flip flop; Phase Noise; Output Noise; Phase

Where short circuit power due to flow of direct path from vdd
locked loop; to ground path get short circuited and thus power dissipates,
second the switching current is occurred whenever the
transition state occurs it depends upon certain factors such as
I. INTRODUCTION α is the activity factor, C L is the load capacitance and f clk is
High speed with low power consumption is the key role of any the clock and third the leakage power is dissipated by sub
handheld devices to perform in a significant way. Various threshold leakage current effect.
researches are carrying in this field by using scaling of
transistor sizing, reducing of supply voltages to reduce its area This paper is organized as follows. In section I introduction of
and noise. Several designs has been implemented for basic D flip flop, in section II, conventional phase detector
designing Phase detector circuits which is used for phase block are discussed. In section III proposed D flip flop circuit
locked loop applications in which D flip flop plays the major is discussed in detail, in section IV consists of results and
role for providing the phase error signal as a output. Flip flop discussion part along with comparison table is discussed, and
is a unit storage element to store the input data when clock in section V conclusion is discussed.
pulse goes high. A large amount on chip power is consumed
by clock element [1]. It is of two type’s single edge triggered II. CONVENTIONAL PHASE DETECTOR
and double edge triggered when data is sampled in either
positive or negative edge termed as single edge triggered and
in both edge is termed as double edge triggered flip flop [2]. A
master slave architecture used in single edge triggered
consumes less power and suitable for PFD architecture with
high frequency [3]. A multiplexer based D flip flop circuits is
implemented and found that output driving capacity and
latching ability is weak [4]. To mitigate the problem encounter
during multiplexer based designed A cross-coupled pMOS
transistors with a sense-amplifiers to execute the latching
operation [5][6]. A new circuit with transistor merging
technique has been used at high frequency up to 2.95 GHz
with high output driving capability [7]. In sub threshold region
it is suitable for optimal reduction of power but it is utilized
only for low frequency [8]. Fig. 1. Conventional phase detector Circuits

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 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

A conventional block diagram of phase detector circuits is

shown in fig.1 consists of couple of D flip flop and an AND
gate in which Fvco and Fref is provided as input with the
clock signal and reset. It gives the output signal up and dn
which is phase error signal whenever the reset pulse is high.
Here we have mainly focused on the high frequency D flip
flop architecture which is competent to design the Phase
Detector circuits. For designing the D flip flop circuits first
we designed a D latch by using two tristate inverter and these
latch is then replaced by a transmission gate logic in order to
minimize the numbers of transistors, A positive edge triggered
D flip flop has been designed with very less power and phase
noise, output noise at different corner is tested and found to be
suitable for high frequency applications such as clock
recovery architecture, clock synthesizer circuits etc.

III. PROPOSED D FLIP FLOP CIRCUITS

The pervasive use of sequential logic in every CMOS circuits
intended to achieve a consequence thickening in the field of
VLSI. As technology decreases the power consumption also
decreases with a very less no of transistor count. In this paper
we have designed a CMOS D latch circuit with ten transistors
which operation can be explained with help of the fig.2 it
consists of two tristate inverter circuits operated by clk and clk
bar input, here the first tristate inverter is used to drive the Fig. 3. Proposed D latch transient analysis
input and to lock the input state whenever there is a rising
clock edge and its holds the state up to the next rising edge. At In fig.4 we proposed a positive edge triggered D flip flop in
this time second tristate inverter is at high impedance phase, which it configuration is discussed in two stage i.e master and
and the output Q is transparent to input D. In second case slave stage by using two D latch circuits. In master stage it
when the clk input goes low the first tristate stage is inactive comprises of 8 transistors in which two tristate inverters are
region and the second tristate inverter completes the loop replaced by two transmission gate along with two inverter
which holds the state until the next clock pulse. Fig.3 connection. Its operation is similar to that of D latch. When
represents the transient response of a D latch which clearly clk is high master stage follows D input while slave stage hold
depicts the transparency with input whenever the clock pulse its last value stored, and when clk transits from high to low
gets high. slave stage takes the value of inputs and master stage holds the
last value stored. The circuits are positive edge triggered
because it takes the value at positive edge of the clock signals.
Fig.5 represents the transient response of a proposed positive
edge triggered D Flip flop circuits which shows the transition
similar to input whenever there is positive clock signals.

Fig. 2. Proposed D Latch Circuits Fig. 4. Proposed Positive edge D flip flop Circuits

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 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

Fig. 5. Proposed D flip flop transient analysis

Fig. 8. Phase noise at 1 MHz offset at different corners

IV. RESULTS & DISCUSSION

Fig. 6. Proposed Dflip flop power analysis

Fig.6 shows the transient power analysis of average of 10.42

µW which is very less as compared to conventional and other
architecture and can operate in low power devices such as Fig. 9. Output Noise noise at 1 MHz offset at different corners
clock circuitry architecture, portable device for long battery
life. As power is low energy consumption is also low which
makes a ciruits fits for high speed applications. In fig.7 represent Phase noise and output noise is stipulated as
-147dBc/Hz, -154.777dB at offset of 1 MHz respectively.
Fig.8 and Fig.9 represents the phase noise and output noise at
different corners which is found to be least varies with the
nominal corner. Table I shows the details analysis of output
and phase noise at different corner which is found to be varied
a output noise of -156.533 to -152.159 dB and phase noise
varied from -149.130 to -144.686 dBc/Hz is obtained without
variation of parameters. Noise analysis is also calculated at
5% process skew the results obtained which is found to be
varied a output noise of -156.598 to -152.178 dB and phase
noise varied from -149.311 to -144.701 dBc/Hz. Table II
represent the power and energy analysis at different corners
without variation and with 5% process variation.

Fig. 7. Phase noise and output noise at 1 MHz offset

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 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

TABLE I. OUTPUT AND PHASE NOISE AT DIFFERENT CORNER Table III shows the comparative analysis with different
parameter here only 16 transistors is being used to design a
Without Variation 5% Process Variation proposed D flip flop circuits with a 1.8V as a power supply in
Process gpdk90nm CMOS process. The result is validated in cadence
Output noise Phase noise Output noise Phase
Corners design environment with a phase noise and output noise at
(dB) (dBc/Hz) (dB) noise
(dBc/Hz) offset 1MHz frequency. Circuit is functioned up to 5 MHz
TT -154.777 -147.841 -154.811 -147.822 operating frequency may be used in high frequency
FF -156.533 -149.130 -156.598 -149.311 application the optimized layout of proposed D latch and
proposed positive edge D flip flop has been shown in fig.10
FS -155.203 -147.353 -155.333 -147.412 and fig 11 with an area of 38.520 and 88.571 µ m2 respectively.
SF -153.108 -145.627 -153.132 -145.697
SS -152.159 -144.686 -152.178 -144.701

TABLE II. POWER AND ENERGY ANALYSIS

Without 5% Process Variation
Process Variation
Corners Power Energy Power (µW) Energy (fJ)
(µW) (fJ)
M σ M σ
TT 10.42 104.21 10.38 8.028 104.17 011.54
FF 11.11 122.33 11.06 0.125 122.27 028.17
FS 10.09 102.41 10.01 0.134 102.33 009.47
SF 10.16 99.82 10.12 6.124 99.76 014.23
SS 9.916 82.88 9.877 7.099 82.81 010.17
*
M = Mean and σ = Standard Deviation
TABLE III. COMPARISION STUDY WITH DIFFERENTS PARAMETERS

Parameter [11] [12] [13] This Work

D latch Proposed Fig. 10. Layout of proposed D Latch circuits

D Flip
Flop
Technolog 90 90 90 90 90
y (nm)
Power (W) 1.43m 51.6 µ 1.39m 2.57 µ 10.42 µ

Supply 1.8 1.2 1.8 1.8 1.8

voltage
(V)
Output -- -- -- -161.76 -154.77
noise at
offset
1MHz
(dB)
Phase -90.7 --- -104 -149.06 -147.84
noise at
offset
1MHz
(dBc/Hz)
Transistor 22 16 28 10 16
Count
Operating 1 1.6 1 5 5
Frequency
(GHz)
Area -- 75.62 -- 38.520 88.571
Consumpt
Fig. 11. Layout of proposed positive edge D Flip flop circuits
ion( µ m2)

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 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

V. CONCLUSION [4] Li Ding; Mazumder, and P.; Srinivas, N., "A dual-rail static edge-
triggered latch," The 2001 IEEE International Symposium on Circuits
A D latch circuit with tristate inverter is implemented and and Systems,Volume: 2, 6-9 May 2001 Page(s):645 - 648 vol.2.
used in the proposed D flip flop circuit to accumulate low [5] Jimenez R., Parra P., Sanmartin P., Acosta A.,"High-performance edge-
power with less phase noise of -147dBc/Hz and output noise triggered flip-flops using weak-branch differential latch," Electronics
letters vol. 38 issue 21,10 oct 2002 pp 1243-1244.
of -154.777 dB. Circuit is simulated at higher frequency up to
[6] Jian Zhou, Jin Liu, and Dian Zhou, "Reduced setup time static D flip-
5 GHz and analyzed at five different process variation at flop," Electronics Letters, Volume 37, Issue 5, 1 Mar 2001, Page(s):279
different corners the results shows least variation in all – 280
parameters such as energy, power, output noise and phase [7] Sang-Hyun yang et.al “A new dynamic D flip flop Aiming at glitch and
noise. This circuit may be suitable for phase detector circuits, Charge Sharing free” IEICE Trans. Electron, VOL E86-C No3 march
Clock and data recovery application, frequency synthesizer 2003.
etc. [8] A. Wang, B. H. Calhoun and A. Chandrakasan, “Sub-threshold design
for ultra low-power systems”. Springer publishers, 2005
[9] Saw, Suraj Kumar, et al. "An ultra low power fast locking CMOS phase
locked loop for wireless communication." International journal of
Acknowledgment computer application (IJCA), Dec12-14. Vol. 5. 2014.
We give our sincere thanks to the SMDP-C2SD project MCIT [10] Z. Peiyi, M. Jason, K. Weidong, W. Nan, and W. Zhongfeng “Design of
Sequential Elements for Low Power Clocking System” IEEE
Meity, Government of India for providing CAD tools like Transaction of Very large Scale Integration “July 2010.
CADENCE to carry out this work. [11] S.L.J. Gierkink ,Low-spur ,low-phase-noise clock multiplier based on a
combination of PLL and recirculating DLL with dual-pulse ring
oscillator and self- correcting charge pump, IEEE J.Solid-State Circuits
43(2008)2967–2976
References
[12] Tambat, Rishikesh V., and Sonal A. Lakhotiya. "Design of Flip-Flops
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