Low Power Tunnel FET

Low power Tunnel FET circuits:
challenges and opportunities
Dehan Morin, imec
1
Outline
• Technology scaling context
• Circuit design perspective
• System level opportunity
• Specialty component opportunity
• Summary
2
Future Application requirements
• HIGH-PERFORMANCE COMPUTING
– Increased performance at constant
power density
– Constraints = Thermal and energy
budget
– Device: low-Vt, mobility boosters
• HIGH-PERFORMANCE MOBILE
– Increased performance at constant
leakage
– Constraints = Battery, Leakage in multi-
cores
– Device: Strong SCE control
System scaling drivers = PPAC
Pitch scaling to ensure 50%
area downscaling
• Node-to-node scaling targets
– >50% area downscaling node-to-node
– >30% more fmax node-to-node at constant power
pitch targets – [nm]
– >20% more fmax at constant leakage
120
– >35% more fmax at constant energy
100 CPP: Poly pitch
– <15% process cost
80 MP: Metal pitch
60
FP: Feature pitch
40
• 20
0
28 20 14 10
CPP 110 82 58 40
MP 90 64 44 30
Gate pitch FP 0 0 42 30
Technology node – [nm]
CPP=Contacted Poly Pitch (Gate); MP=Metal1 Pitch; FP=FinFET pitch
4
Scaling challenges ?
No room for S/D contacts → high access resistance.

But... this picture is not sufficient, better insight is required.
2013 / CONFIDENTIAL DMITRY YAKIMETS 5

Technology roadmap
Vdd 1.0-1.1V 0.9-1.0V 0.8-0.9V 0.7-0.8V 0.6-0.7V 0.5-0.6V < 0.5V
Strain & Fully-depleted Band-Engineered Novel Materials/

Advanced Gate Stack Channel for Improved Channel for New Transport/
Engineering Electrostatics Enhanced Transport Extreme
SD/stressors Metal Gate Electrostatics
+High-k
High-Mobility Nanowires/ Quantum/
Ultra-Thin Multi-gate FETs
Channels Tunnel FETs 2D Materials Spin Devices
SOI
MG
High-k
Si substrate
(Bi-layer
(SiGe, Ge IIIV)
Graphene)
Tech Node 32/28nm 14nm 7nm
...
45nm 22/20nm 10nm 5nm
• Feature Dimension & Voltage Scaling are concurrent drivers
• Material & Device Architecture Innovations Enablers of continual scaling
Technology roadmap
Full W/L variation
Width
Quantization
Width / Length
Quantization
Asymmetry
freedom
32/28nm 14nm 7nm

Design
...
45nm 22/20nm 10nm 5nm
Vdd 1.0-1.1V 0.9-1.0V 0.8-0.9V 0.7-0.8V 0.6-0.7V 0.5-0.6V < 0.5V
Need “dramatic” electrostatic Scaling
Electrostatic improvement not sustainable without

new device architecture
Emerging device architecture
• TFET alternative
architectures for
so called n5/n3
technology nodes
http://www.extremetech.com/computing/
162376-7nm-5nm-3nm-the-new-materials-and-transistors-that-will-take-us-to-the-limits-of-moores-law
9
Circuit design perspective
• TFET for designer
• Logic cell design
• SRAM
10
Circuit design perspective -
TFET
• Key Features
– Band to Ban mechanism –
Sub 60mv/Dec
– Low VDD operation
– Structure compatible with
CMOS
• Challenges
– Low Ion
– Source engineering
– Interface states
A.M. Ionescu, et al, IEDM, 378 (2011)
11
Device Expectation
• Logic properties
– Steep SS
– High drive
– Low capacitance
– Low Vt
– Symmetrical device
• Model
12
Device Expectation
• Logic properties
– Steep SS
– High drive
– Low capacitance
– Low Vt
– Symmetrical device
• Model
13
TFET asymmetry
• Unidirectional • Ambipolar
– Forward FET device
– Reverse - Diodes
G - High N-Type
P I N S P I N D - High
= G - Low P-Type
P I N S P I N D - High
14
NAND gate design
• Shared source & Drains
• Source to drain
connections
15
PLANAR CMOS NAND layout
A B
Z
Z
B
A B
16
PLANAR TFET NAND layout
A B
Z
Z
B
A B
Shared Node – How to deal with it?

17
TFET NAND layout
A B
Z Z
B B
A
Extra area penalty (1 PP)

Increase metal congestion
A
18
What about vertical devices?
• Need to go from
bottom to top
• Area penalty
19
SRAM
• Ambipolar behavior WL
(b)
problematic for M2 M4
pass gates M5 M6
• Special read/write BL
QB
BLB
Q
scheme needed or
other architectures M1 M3
Cfr: Strangio et al. ESSDERC2014
20
Summary
• Uni-directionality forces update on layout
template
• Might stress further the Lithography needs
for logic
• In planar technology sharing nodes might
be an option
21
System level opportunity
• High level analysis
• Activity factor 10%
(10 % of chip active)
System level opportunities for TFET

in low speed context
Wei et al., VOL. 58, NO. 8, AUGUST 2011
22
Specialty component opportunity
Is their applications which would take benefit of extra TFET
device in technology portfolio
High temperatures
Internet of things
Analog applications
Sensors RF
23
Summary
• TFET promised performances appealing for
low power systems.
• Challenges in integration
• IP libraries must be updated
• Circuit topology and operation should take
advantages of the TFET properties
24
Thank you &
Buon appetito

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Low power Tunnel FET circuits:

challenges and opportunities

Dehan Morin, imec

No room for S/D contacts → high access resistance.

2013 / CONFIDENTIAL DMITRY YAKIMETS 5

Strain & Fully-depleted Band-Engineered Novel Materials/

32/28nm 14nm 7nm

Electrostatic improvement not sustainable without

A.M. Ionescu, et al, IEDM, 378 (2011)

• Shared source & Drains

Shared Node – How to deal with it?

Extra area penalty (1 PP)

Cfr: Strangio et al. ESSDERC2014

System level opportunities for TFET

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