A B C D E

Vinafix.com
1 1

2 2

V330/V530/EX3
DIS M/B Schematics Document
Intel Kabylake RU Processor with DDR4
AMD R17M

2017-06-15
3 3

LA-F481P
R E V ：0 . 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 1 of 66
A B C D E
 A B C D E

Channel A
On board DDR4 X 4
DDR4 2133/2400MHz (1.2V , 2.5V)
P18
AMD Radeon 530M PCIe X4
VRAM GDDR5 x2
Vinafix.com Channel B DDR4 SO DIMM X1
1 1
P21 P19
eDP X1 DDR4 2133/2400MHz (1.2V , 2.5V)
eDP Conn. (2 Lanes)
FHD DDR4 support 2133/2400MHz on KBL-RU
P28
DDR4 support 2133MHz on SKL and KBL-U

HDMI Conn. DDI X1 USB3.0 x1

(HDMI 1.4) P29 USB2.0 x1 Right USB3.0 x1
P34
LAN
RJ45 Conn. RTL8111H-CG PCIe X1 Intel KBL-RU 15W/28W USB3.0 x1
100/1000 USB2.0 x1 Left USB3.0 x1
P36
SOC With AOU
P34
1356pin BGA TypeC TypeC
USB3.0 x1 USB3.0 x1
2

M.2 SSD PCIe X4 / SATA X1 RTS5448 (CC) 2

CC+MUX USB2.0 x1
P42 P43
(TYPE M)
P32

PCIe X1 for WLAN

USB3.0 x1 TypeC USB3.0 x1 TypeC
WLAN / BT
USB2.0 x1 for BT RTL5455 USB2.0 x1 (CC+PD+DP)
P31 PD+DP+MUX P40 P41

2nd Battery / USB2.0 conn. USB2.0 x1 DDI X1 DP MUX CRT converter

PS8338B RTD2166 CRT Conn.
(Reserve)P46 P38
P39 P39

Card Reader USB2.0 x1

Realtek USB2.0 x1 Int. Camera Opt i on
P28
LED RTS5146 P37
3 3

USB2.0 x1 SATA X1
Finger Print HDD Conn.
P30
P33
DC to DC
HDA Audio Codec
Touch Pad P33 I2C CONEXANT
CX11802 P35
APS P46 SMBUS
LPC SPI
Int. MIC Conn. Int. Speaker Conn. Audio Combo Jack
P28 P35 HP & MIC
EC SPI ROM
TPM/TCM ENE 16MB P35
P27 KB9022 P45 P08

4 4

Opt i on
Int. KBD
P33

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 2 of 66
A B C D E
 1 2 3 4 5

Item BOM Structure

BOM Structure Table SKL only SKL@
For 2+2 U22@
Voltage Rails USB 2.0 Port Table For 2+3 U23@
3 External For 4+2 U42@
Port USB Port For DIS DIS@
+5VS 1 USB 3.0 Port (AOU) For UMA UMA@
Vinafix.com +3VS 2 USB 3.0 Port Camera CMOS@
power +3VGS 3 TYPE-C USB 3.0 Port EMI pop EMI@
A plane A
+1.8VGS 4 TYPE-C USB 3.0 Port(FULL) EMI Un-pop @EMI@
+B
+5VALW +1.0V_VCCST +1.0VS_VCCIO 5 Camera ESD pop ESD@
+RTCBATT +5VL +PCIE_VGS 6 M.2 BT ESD Un-pop @ESD@
+3VALW +2.5V
+VGA_CORE 7 Card Reader RF pop RF@
+3VL
+1.8VALW +1.2V +1.35VS_VRAM 8 Finger Print RF unpop @RF@
+0.6VS 9 2nd Battery For SPI 8M 8M@
+1VALW
+VCCCORE 10 For SPI 16M 16M@
State +VCCGT Finger Print FP@
+VCCSA Keyboard backlight KBL@
AOU AOU@
USB 3.0 Port Table NONAOU NONAOU@
O O O O O Port
S0
TYPEC FULL TYPEC@
1 USB 3.0 Port (AOU) PCIE Port Table NONTYPEC NONTYPEC@
O O O O X 2 USB 3.0 Port APS APS@
S3 3 TYPE-C USB 3.0 Port NOAPS NOAPS@
Port Lane
4 TYPE-C USB 3.0 Port(FULL) 2nd Battery USB BATT2@
S5 and S4/AC O O O X X 5 1 1 GPU NO 2nd Battery USB NOBATT2@
6 2 2 Onboard RAM HYNIX X76DDRH@
S5 and S4/Battery only O O X X X 3 3 Onboard RAM MICRON X76DDRM@
B
SATA Port Table 4 4 Onboard RAM SAMSUNG X76DDRS@
B

S5 and S4/AC&Battery
5 LAN VRAM HYNIX X76H2G@
O X X X X Port
don't exist(Only RTC ) 6 M.2 WLAN+BT VRAM MICRON X76M4G@
0 HDD 7 VRAM SAMSUNG X76S2G@
1 8 CardReader RTS5146 X76RT@
9 CardReader GL835 X76GL@
EC SM Bus1 address 10 TPM TPM@
M.2 PCIE*4 SSD
11 TCM TCM@
Device Address 2 M.2 SATA SSD 12 NO TPM/TCM NOTPM@
Smart Battery 0001 011x Connector ME@

CPU
SKL-U KBL-U KBL-RU 4+2
PCH SM Bus address UC1
CPU1@
UC1
CPU2@
UC1
CPU3@
UC1
CPU7@
UC1
CPU8@
UC1
CPU9@
UC1
CPU15@
UC1
CPU16@
2+2 i7-6500U
SA000092P60
i5-6300U
SA000092T40
i5-6200U
SA000092O70
i3-7100U
SA0000A38H0
i5-7200U
SA0000A37B0
i7-7500U
SA0000A34F0
KBL-R QN5D
SA0000AR010
KBL-R QN5C
SA0000AQZ10
Device Address
DDR_JDIMM1 1010 000x A0h UC1 UC1 UC1 UC1 UC1 UC1
GPU 1000 001x A0h CPU4@ CPU10@ CPU11@ CPU12@ CPU17@ CPU18@
RTS5455 1010 1100 A0h i3-6006U i5-7300U 3865U 4415U KBL-R QNEF KBL-R QNBF
RTD2166 1100 100 A0h SA0000ACN10 SA0000ADO20 SA0000ADL30 SA0000ADV40 SA0000AWB00 SA0000AWC00
APS 1111 0100 A0h
UC1 UC1 UC1 UC1
C C
CPU5@ CPU6@ CPU13@ CPU14@
2+3 i7-6567U
SA00009E620
i5-6267U
SA00009E530
i7-7567U
SA0000AW620
i5-7267U
SA0000AKR20

SMBUS Control Table

ZZZ ZZZ ZZZ UV1 ZZZ

SOURCE GPU BATT NECP388 SODIMM SOC

SMB_EC_CK1
SMB_EC_DA1
EC KB9022
+3VALW
X V
+3VALW
X X X X76DDR4H@ X76DDR4M@ X76DDR4S@ GPU1@ PCB
2G HYNIX 2G MICRON 2G SAMSUNG VGA DA8001CE000
SMB_EC_CK2 X7675138L01 X7675138L02 X7675138L03 SA000098VB0

SMB_EC_DA2
EC KB9022
+3VGS
V X X X V
+3VALW
+3VS
PCH_SMBCLK On Board RAM GPU
PCH_SMBDATA
PCH
+3VALW
X X X V
+3VS
X
PCH_SML0CLK
PCH_SML0DATA
PCH
+3VALW
X X X X X ZZZ ZZZ

SML1CLK
SML1DATA
PCH
+3VALW +3VGS
V X V
+3VS
X X
X76RT@ X76GL@
RTS5146 GL835
SIGNAL X7675138L61 X7675138L62
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V(RAM) +VS Clock
D D

Full ON HIGH HIGH HIGH HIGH ON ON ON ON CardReader

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
ZZZ
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF X4E@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
X4E AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
X4EA8X38L01 C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-D562P
Thursday, June 15, 2017 Sheet 3 of 66
1 2 3 4 5
 5 4 3 2 1

[BIWB6/B7/E7/E8-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

G3->S0 S0->S3/DS3 S3/ DS3 ->S0 S0->S5

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST#

B+
Vinafix.com SOC_RTCRST#

+19VB
D D
+3VLP +3VLP/+5VLP

EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW / +3VALW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8VALW +1.8V_PRIM
tPCH34_Max : 20 ms
+1.0VALW tPCH06_Min : 200 us +1.0V_PRIM

SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
AC_PRESENT(VCIN1_AC_IN) AC_PRESENT

ON/OFF# ON/OFF

PBTN_OUT# PBTN_OUT#
C
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST# C

PM_SLP_S5# PM_SLP_S5#

PM_SLP_S4# PM_SLP_S4#

SYSON SYSON

+1.0V_VCCST +1.0V_VCCST/+1.0V_VCCSFR

+1.2V +1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3# PM_SLP_S3#

SUSP# SUSP#
tCPU10 Min : 1 ms
+1.0VS_VCCIO +1.0VS_VCCIO
tCPU04 Min : 100 ns

+5VS / +3VS / +1.05VS +5VS/+3VS/+1.5VS/+1.05VS

T4 = Min : 20ms Max : 30ms(EC Control)
EC_VCCST_PG(VCCST_PWRGD) EC_VCCST_PG

VR_ON VR_ON
tCPU19 Max : 100 ns
DDR_VTT_PG_CTRL SM_PG_CTRL
B B
tCPU18 Max : 35 us
+0.675VS +0.675VS_VTT
tCPU09 Min : 1 ms
+VCCSA +VCC_SA

+VCCCORE +VCC_CORE

+VCCGT +VCC_GT

VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK

H_CPUPWRGD H_CPUPWRGD

SYS_PWROK SYS_PWROK

SOC_PLTRST#(PCIRST#) SOC_PLTRST#

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/29 Deciphered Date 2016/01/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R
Reev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D561P
Date: Thursday, June 15, 2017 Sheet 4 of 66
5 4 3 2 1
 5 4 3 2 1

M1-30 VRAM STRAP Power-Up/Down Sequence

X76@ X76@ "M1" has the following requirements with regards to power-supply
Vendor R_pu R_pd sequencing to avoid damaging the ASIC:
ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ] ‧All the ASIC supplies must reach their respective nominal voltages within 20ms
UV3, UV4, UV5, UV6
HYNIX 4096Mbits 2GBytes
Vinafix.com RV22 RV27
of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.
The maximum slew rate on all rails is 50 mV/μ s.
X76H2G@ SA000076P80 TEMP
D 256MX16 K4W4G1646E-BC1A TEMP 0 0 0 0 NC 4.75K ‧It is recommended that the 3.3-V rail ramp up frist. D
X7667538L03 ‧It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later
Micron 4096Mbits 2GBytes than 2ms from the start of VDDC ramping up.
X76M2G@ SA00009HF00 TEMP
‧The power rails that are shared with other components on the system should be gated for
X7667538L04 256Mx16 MT41J256M16LY-091G:N TEMP1 0 0 1 8.45K 2K
the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state),
SAMSUNG 4096Mbits 2GBytes all the power rails are removed from the dGPU.
X76S2G@ SA00008DN00 TEMP The gate circuits must meet the slew rate requirement (such as ≦ 50mV/us)
256MX16 H5TC4G63CFR-N0C TEMP 2 0 1 0 4.53K 2K
X7667538L05 ‧VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
4 1 0 0 4.53K 4.99K ‧For power down, reversing the ramp-up sequence is recommended.

5 1 0 1 3.24K 5.62K

6 1 1 0 3.4K 10K

ZZZ ZZZ ZZZ VDDR3(+3VGS)

C
PCIE_VDDC(+0.95VGS) C

X76H2G@ X76M2G@ X76S2G@

2G HYNIX 2G MICRON 2G SAMSUNG
X7675138L04 X7675138L05 X7675138L06
VDD_CT(+1.8VGS)

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

DGPU_PWROK

PERSTb

REFCLK

Straps Reset
B B

Straps Valid

Global ASIC Reset

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 5 of 66
5 4 3 2 1
 A B C D E

Vinafix.com
1 1

UC1A SKL-U
Rev_1.0
E55 C47
[29] HDMI_TX2-_CK DDI1_TXN[0] EDP_TXN[0] EDP_TXN0 [28]
F55 C46
[29] HDMI_TX2+_CK DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 [28]
E58 D46
[29] HDMI_TX1-_CK DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 [28]
F58 C45
[29] HDMI_TX1+_CK DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 [28]
HDMI F53 A45
[29] HDMI_TX0-_CK DDI1_TXN[2] EDP_TXN[2]
G53 B45 <eDP>
[29] HDMI_TX0+_CK DDI1_TXP[2] EDP_TXP[2]
F56 A47
[29] HDMI_CLK-_CK DDI1_TXN[3] EDP_TXN[3]
G56 B47
[29] HDMI_CLK+_CK DDI1_TXP[3] EDP_TXP[3]
C50 E45 EDP_AUXN [28]
[38] DDI2_TX0-_CK DDI2_TXN[0] DDI EDP EDP_AUXN
D50 F45 EDP_AUXP [28]
[38] DDI2_TX0+_CK DDI2_TXP[0] EDP_AUXP
C52
[38] DDI2_TX1-_CK DDI2_TXN[1]
D52 B52
[38] DDI2_TX1+_CK DDI2_TXP[1] EDP_DISP_UTIL
DP MUX A50
[38] DDI2_TX2-_CK DDI2_TXN[2]
B50 G50
(Type-C/VGA) [38] DDI2_TX2+_CK
D51 DDI2_TXP[2] DDI1_AUXN F50
[38] DDI2_TX3-_CK DDI2_TXN[3] DDI1_AUXP
C51 E48
[38] DDI2_TX3+_CK DDI2_TXP[3] DDI2_AUXN DDIP2_AUXN [38]
F48
DDI2_AUXP DDIP2_AUXP [38]
G46
DISPLAY SIDEBANDS RSVD F46
L13 RSVD
[29] HDMICLK_NB GPP_E18/DDPB_CTRLCLK
HDMI DDC L12 L9 TMDS_B_HPD [29] From HDMI
[29] HDMIDAT_NB GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 DDIP2_HPD [38] From DP
N7 GPP_E14/DDPC_HPD1 L6
[38] DDIP2_CTRLCLK GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2
N8 N9
DP MUX DDC [38] DDIP2_CTRLDATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10
EC_SCI# [10,45]
GPP_E17/EDP_HPD EDP_HPD [28] From eDP
N11
N12 GPP_E22 R12
2 GPP_E23 EDP_BKLTEN ENBKL [45] 2
R11
EDP_COMP EDP_BKLTCTL INVPWM [28]
E52 1 OF 20 U13
EDP_RCOMP EDP_VDDEN PCH_ENVDD [28]

< Compensat i on P U For e DP > SKL-U_BGA1356

+1.0VS_VCCIO
@

1 2 EDP_COMP
RC1 24.9_0402_1%

Trace width=20 mils, Spacing=25mil, Max length=100mils

+1.0VS_VCCIO
1

UC1D SKL-U
RC2 Rev_1.0
SOC_CATERR# D63
1K_0402_5%
H_PECI
T1 TP@
A54 CATERR# < PU/PD for CMC Debug > +1.0VS_VCCIO
[45] H_PECI PECI
H_PROCHOT#_R C65 JTAG
2

1 2 H_PROCHOT#_R H_THERMTRIP# C63 PROCHOT#

[45] H_PROCHOT# THERMTRIP#
RC3 499_0402_1% SOC_OCC# A65 SOC_XDP_TMS RC4 1 @ 2 51_0402_5%
T2 TP@ SKTOCC#
CPU MISC B61 CPU_XDP_TCK0
XDP_BPM#0 C55 PROC_TCK D60 SOC_XDP_TDI SOC_XDP_TDI RC5 1 @ 2 51_0402_5%
T3 TP@ BPM#[0] PROC_TDI
XDP_BPM#1 D55 A61 SOC_XDP_TDO
+1.0V_VCCST T4 TP@ BPM#[1] PROC_TDO
XDP_BPM#2 B54 C60 SOC_XDP_TMS SOC_XDP_TDO RC6 1 @ 2 51_0402_5%
T5 TP@ BPM#[2] PROC_TMS
XDP_BPM#3 C56 B59 SOC_XDP_TRST#
T6 TP@ BPM#[3] PROC_TRST#
1 2 H_THERMTRIP# T7 TP@
SOC_GPIOE3 A6 B56 PCH_JTAG_TCK1
RC7 1K_0402_5% A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI CPU_XDP_TCK0 RC8 1 @ 2 51_0402_5%
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 SOC_XDP_TDO
SOC_GPIOB4 AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 SOC_XDP_TMS PCH_JTAG_TCK1 RC9 1 @ 2 51_0402_5%
T8 TP@ GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 PCH_XDP_TRST# T9 TP@
3 RC10 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 PCH_TRST# A59 CPU_XDP_TCK0 3
RC11 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
RC12 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP SOC_XDP_TRST# RC13 1 2 51_0402_5%
RC14 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
4 OF 20
SKL-U_BGA1356
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(1/12)DDI,EDP,MISC,CMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 6 of 66
A B C D E
 5 4 3 2 1

Interleaved Memory

D
Vinafix.com D

SKL-U
UC1B SKL-U UC1C
Rev_1.0 Rev_1.0
[18] DDR_A_D[0..15] DDR_A_D0 DDR_A_CLK#0
AL71 AU53 DDR_A_CLK#0 [18]
DDR_A_D1 DDR0_DQ[0] DDR0_CKN[0] DDR_A_CLK0 [19] DDR_B_D[0..15] DDR_B_D0
Interleave / Non-Interleaved
DDR_B_CLK#0
AL68 AT53 DDR_A_CLK0 [18] AF65 AN45 DDR_B_CLK#0 [19]
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_B_D1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1
DDR0_DQ[2] DDR0_CKN[1] @ T10 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK#1 [19]
DDR_A_D3 AN69 AT55 DDR_A_CLK1 DDR_B_D2 AK65 AP45 DDR_B_CLK0
DDR0_DQ[3] DDR0_CKP[1] @ T13 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDR_B_CLK0 [19]
DDR_A_D4 AL70 DDR_B_D3 AK64 AP46 DDR_B_CLK1
DDR0_DQ[4] DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 [19]
DDR_A_D5 AL69 BA56 DDR_A_CKE0 DDR_B_D4 AF66
DDR0_DQ[5] DDR0_CKE[0] DDR_A_CKE0 [18,20] DDR1_DQ[4]/DDR0_DQ[20]
DDR_A_D6 AN70 BB56 DDR_A_CKE1 DDR_B_D5 AF67 AN56 DDR_B_CKE0
DDR0_DQ[6] DDR0_CKE[1] @ T11 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE0 [19]
DDR_A_D7 AN71 AW56 DDR_B_D6 AK67 AP55 DDR_B_CKE1
DDR0_DQ[7] DDR0_CKE[2] DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDR_B_CKE1 [19]
DDR_A_D8 AR70 AY56 DDR_B_D7 AK66 AN55
DDR_A_D9 AR68 DDR0_DQ[8] DDR0_CKE[3] DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#0 [18,20] DDR1_DQ[9]/DDR0_DQ[25]
DDR_A_D11 AU68 AU43 DDR_A_CS#1 DDR_B_D10 AH71 BB42 DDR_B_CS#0
DDR0_DQ[11] DDR0_CS#[1] @ T14 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS#0 [19]
DDR_A_D12 AR71 AT45 DDR_A_ODT0 DDR_B_D11 AH68 AY42 DDR_B_CS#1
DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT0 [18,20] DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_CS#1 [19]
DDR_A_D13 AR69 AT43 DDR_A_ODT1 DDR_B_D12 AF71 BA42 DDR_B_ODT0
DDR0_DQ[13] DDR0_ODT[1] @ T12 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT0 [19]
DDR_A_D14 AU70 DDR_B_D13 AF69 AW42 DDR_B_ODT1
DDR0_DQ[14] DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 [19]
DDR_A_D15 AU69 DDR_B_D14 AH70
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4
BA51 DDR_A_MA5 DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA5 [18,20] [19] DDR_B_D[16..31] DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4
BB54 DDR_A_MA9 DDR_B_D16 AT66 AY48 DDR_B_MA5
[18] DDR_A_D[16..31] Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA9 [18,20] DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA5 [19]
DDR_A_D16 BB65 BA52 DDR_A_MA6 DDR_B_D17 AU66 AP50 DDR_B_MA9
DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA6 [18,20] DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR_B_MA9 [19]
DDR_A_D17 AW65 AY52 DDR_A_MA8 DDR_B_D18 AP65 BA48 DDR_B_MA6
DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA8 [18,20] DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA6 [19]
DDR_A_D18 AW63 AW52 DDR_A_MA7 DDR_B_D19 AN65 BB48 DDR_B_MA8
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_A_MA7 [18,20] DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR_B_MA8 [19]
DDR_A_D19 AY63 AY55 DDR_A_BG0 DDR_B_D20 AN66 AP48 DDR_B_MA7
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 [18,20] DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_MA7 [19]
DDR_A_D20 BA65 AW54 DDR_A_MA12 DDR_B_D21 AP66 AP52 DDR_B_BG0
DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_A_MA12 [18,20] DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BG0 [19]
DDR_A_D21 AY65 BA54 DDR_A_MA11 DDR_B_D22 AT65 AN50 DDR_B_MA12
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_MA11 [18,20] DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR_B_MA12 [19]
DDR_A_D22 BA63 BA55 M_A_ACT# DDR_B_D23 AU65 AN48 DDR_B_MA11
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# M_A_ACT# [18,20] DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR_B_MA11 [19]
DDR_A_D23 BB63 AY54 DDR_A_BG1 DDR_B_D24 AT61 AN53 M_B_ACT#
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 [18] DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# M_B_ACT# [19]
DDR_A_D24 BA61 AU46 DDR_A_MA13 DDR_B_D25 AU61 AN52 DDR_B_BG1
C DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA13 [18,20] DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 [19] C
DDR_A_D25 AW61 AU48 DDR_A_MA15 DDR_B_D26 AP60 BA43 DDR_B_MA13
DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA15 [18,20] DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA13 [19]
DDR_A_D26 BB59 AT46 DDR_A_MA14 DDR_B_D27 AN60 AY43 DDR_B_MA15
DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA14 [18,20] DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_MA15 [19]
DDR_A_D27 AW59 AU50 DDR_A_MA16 DDR_B_D28 AN61 AY44 DDR_B_MA14
DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_MA16 [18,20] DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA14 [19]
DDR_A_D28 BB61 AU52 DDR_A_BA0 DDR_B_D29 AP61 AW44 DDR_B_MA16
DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BA0 [18,20] DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_MA16 [19]
DDR_A_D29 AY61 AY51 DDR_A_MA2 DDR_B_D30 AT60 BB44 DDR_B_BA0
DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_MA2 [18,20] DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_BA0 [19]
DDR_A_D30 BA59 AT48 DDR_A_BA1 DDR_B_D31 AU60 AY47 DDR_B_MA2
DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_BA1 [18,20] [19] DDR_B_D[32..47] DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_MA2 [19]
DDR_A_D31 AY59 AT50 DDR_A_MA10 DDR_B_D32 AU40 BA44 DDR_B_BA1
[18] DDR_A_D[32..47] DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA10 [18,20] DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_BA1 [19]
DDR_A_D32 AY39 BB50 DDR_A_MA1 DDR_B_D33 AT40 AW46 DDR_B_MA10
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA1 [18,20] DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA10 [19]
DDR_A_D33 AW39 AY50 DDR_A_MA0 DDR_B_D34 AT37 AY46 DDR_B_MA1
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA0 [18,20] DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR_B_MA1 [19]
DDR_A_D34 AY37 DDR_B_D35 AU37 BA46 DDR_B_MA0
DDR0_DQ[34]/DDR1_DQ[2] DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA0 [19]
DDR_A_D35 AW37 BA50 DDR_A_MA3 DDR_B_D36 AR40
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA3 [18,20] DDR1_DQ[36]/DDR1_DQ[20]
DDR_A_D36 BB39 BB52 DDR_A_MA4 DDR_B_D37 AP40 BB46 DDR_B_MA3
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 [18,20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] DDR_B_MA3 [19]
DDR_A_D37 BA39 AM70 DDR_A_DQS#0 DDR_B_D38 AP37 BA47 DDR_B_MA4
DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS#0 [18] DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4] DDR_B_MA4 [19]
DDR_A_D38 BA37 AM69 DDR_A_DQS0 DDR_B_D39 AR37
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] DDR_A_DQS0 [18] DDR1_DQ[39]/DDR1_DQ[23]
DDR_A_D39 BB37 AT69 DDR_A_DQS#1 DDR_B_D40 AT33
DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] DDR_A_DQS#1 [18] DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved
DDR_A_D40 AY35 AT70 DDR_A_DQS1 DDR_B_D41 AU33 AH66 DDR_B_DQS#0
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_A_DQS1 [18] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_B_DQS#0 [19]
DDR_A_D41 AW35 DDR_B_D42 AU30 AH65 DDR_B_DQS0
DDR0_DQ[41]/DDR1_DQ[9] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS0 [19]
DDR_A_D42 AY33 DDR_B_D43 AT30 AG69 DDR_B_DQS#1
DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS#1 [19]
DDR_A_D43 AW33 BA64 DDR_A_DQS#2 DDR_B_D44 AR33 AG70 DDR_B_DQS1
DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] DDR_A_DQS#2 [18] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3] DDR_B_DQS1 [19]
DDR_A_D44 BB35 AY64 DDR_A_DQS2 DDR_B_D45 AP33 AR66 DDR_B_DQS#2
DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS2 [18] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_B_DQS#2 [19]
DDR_A_D45 BA35 AY60 DDR_A_DQS#3 DDR_B_D46 AR30 AR65 DDR_B_DQS2
DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] DDR_A_DQS#3 [18] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6] DDR_B_DQS2 [19]
DDR_A_D46 BA33 BA60 DDR_A_DQS3 DDR_B_D47 AP30 AR61 DDR_B_DQS#3
DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS3 [18] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS#3 [19]
DDR_A_D47 BB33 BA38 DDR_A_DQS#4 AR60 DDR_B_DQS3
[18] DDR_A_D[48..63] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] DDR_A_DQS#4 [18] [19] DDR_B_D[48..63] DDR1_DQSP[3]/DDR0_DQSP[7] DDR_B_DQS3 [19]
DDR_A_D48 AY31 AY38 DDR_A_DQS4 DDR_B_D48 AU27 AT38 DDR_B_DQS#4
DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_A_DQS4 [18] DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS#4 [19]
DDR_A_D49 AW31 AY34 DDR_A_DQS#5 DDR_B_D49 AT27 AR38 DDR_B_DQS4
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS#5 [18] DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS4 [19]
DDR_A_D50 AY29 BA34 DDR_A_DQS5 DDR_B_D50 AT25 AT32 DDR_B_DQS#5
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_A_DQS5 [18] DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS#5 [19]
DDR_A_D51 AW29 BA30 DDR_A_DQS#6 DDR_B_D51 AU25 AR32 DDR_B_DQS5
DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS#6 [18] DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS5 [19]
DDR_A_D52 BB31 AY30 DDR_A_DQS6 DDR_B_D52 AP27
DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS6 [18] DDR1_DQ[52]
DDR_A_D53 BA31 AY26 DDR_A_DQS#7 DDR_B_D53 AN27 AR25 DDR_B_DQS#6
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS#7 [18] DDR1_DQ[53] DDR1_DQSN[6] DDR_B_DQS#6 [19]
DDR_A_D54 BA29 BA26 DDR_A_DQS7 DDR_B_D54 AN25 AR27 DDR_B_DQS6
DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 [18] DDR1_DQ[54] DDR1_DQSP[6] DDR_B_DQS6 [19]
DDR_A_D55 BB29 DDR_B_D55 AP25 AR22 DDR_B_DQS#7
DDR0_DQ[55]/DDR1_DQ[39] DDR1_DQ[55] DDR1_DQSN[7] DDR_B_DQS#7 [19]
DDR_A_D56 AY27 AW50 DDR_B_D56 AT22 AR21 DDR_B_DQS7
DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# DDR_A_ALERT# [18] DDR1_DQ[56] DDR1_DQSP[7] DDR_B_DQS7 [19]
DDR_A_D57 AW27 AT52 DDR_B_D57 AU22 AN43 DDR_B_ALERT#
DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR DDR_A_PARITY [18,20] DDR1_DQ[57] DDR1_ALERT# DDR_B_ALERT# [19]
DDR_A_D58 AY25 DDR_B_D58 AU21 AP43 DDR_B_PARITY
DDR0_DQ[58]/DDR1_DQ[42] DDR1_DQ[58] DDR1_PAR DDR_B_PARITY [19]
DDR_A_D59 AW25 DDR CH - A AY67 +0.6V_VREFCA Trace width/Spacing >= 20mils DDR_B_D59 AT21 AT13 DDR_DRAMRST#
DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA +0.6V_VREFCA [18] Place componment near SODIMM DDR1_DQ[59] DRAM_RESET# DDR_DRAMRST# [18,19]
B DDR_A_D60 BB27 AY68 DDR_B_D60 AN22 DDR CH - B AR18 B
DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ @ T16 DDR1_DQ[60] DDR_RCOMP[0]
DDR_A_D61 BA27 BA67 +0.6V_B_VREFDQ DDR_B_D61 AP22 AT18
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ +0.6V_B_VREFDQ [19]
DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[1] AU18 SM_RCOMP0 RC15 2
X76@
1 200_0402_1%
0606 : RC15 add X76@
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 DDR_PG_CTRL DDR_B_D63 AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2] SM_RCOMP1 RC16 1 2 80.6_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL #543016 PDG0.9 P.163 RC place near SODIMM DDR1_DQ[63] SM_RCOMP2 RC17 1 2 100_0402_1%
SKL-U_BGA1356 SKL-U_BGA1356
@ @ #543016 PDG0.9 P.117
W=12-15 Space= 20/25 L=500mil

+1.2V
SDP DDP

1
+1.2V +3VS +3VALW
< For ODT & VTT Power Control > RC18
DDR_VTT_CNTL to DDR 470_0402_5%
RC15 200 1% 121 1%
VTT supplied ramped
1

<35uS 1
CRB ORB

2
(tCPU18) CC1
0.1U_0201_10V6K RC19 @ RC20 DDR_DRAMRST#
220K_0402_5% 100K_0402_5%
UC8 2
2

1 5
NC VCC
DDR_PG_CTRL 2
A 4
Y DDR_VTT_PG_CTRL [54]
3
GND
74AUP1G07GW_TSSOP5
SA00007WE00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/29 Deciphered Date 2016/01/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(2/12)DDR4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 7 of 66
5 4 3 2 1
 5 4 3 2 1

SMBALERT# (Internal Pull Down): SML0ALERT# (Internal Pull Down):

0 = Disable Intel ME TLS function ==> Default eSPI or LPC

1 = Enable Intel ME TLS function 0 = LPC is selected for EC ==> Default

Vinafix.com 1 = eSPI is selected for EC
D UC1E SKL-U D
+3VALW Rev_1.0
SPI - FLASH
SMBUS, SMLINK
RC21 1 2 10K_0402_5% KB_RST# SOC_SPI_CLK AV2 R7 SOC_SMBCLK SMB
SPI0_CLK GPP_C0/SMBCLK SOC_SMBCLK [19]
SOC_SPI_SO AW3 R8 SOC_SMBDATA
SPI0_MISO GPP_C1/SMBDATA SOC_SMBDATA [19]
SOC_SPI_SI AV3 R10 SOC_SMBALERT# TP@ T17 (Link to DDR)
RC22 1 @ 2 1K_0402_5% SOC_SPI_IO2 SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C2/SMBALERT#
SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK
SOC_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SOC_SML0DATA
RC23 1 @ 2 1K_0402_5% SOC_SPI_IO3 AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SOC_SML0ALERT#TP@ T18
AU1 SPI0_CS1# GPP_C5/SML0ALERT#
SPI0_CS2# W3 SOC_SML1CLK
GPP_C6/SML1CLK V3 SOC_SML1DATA
SOC_SML1CLK [22,39,45,46] SML1
SPI - TOUCH GPP_C7/SML1DATA SOC_SML1DATA [22,39,45,46]
AM7 SOC_SML1ALERT# (Link to EC,DGPU,CRT,APS,RTS5455)
M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2 AY13 LPC_AD0
GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_AD0 [27,45]
M1 LPC BA13 LPC_AD1
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 LPC_AD1 [27,45]
BB13 LPC_AD2
GPP_A3/LAD2/ESPI_IO2 LPC_AD2 [27,45]
AY12 LPC_AD3
C LINK GPP_A4/LAD3/ESPI_IO3 LPC_AD3 [27,45]
BA12 LPC_FRAME#
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# [27,45]
G3 BA11
G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
G1 CL_DATA
CL_RST# AW9 LPC_CLK0 RC24 1 EMI@ 2 22_0402_1%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CK_LPC_KBC [45]
AY9 LPC_CLK1 RC102 1 EMI@ 2 22_0402_1%
GPP_A10/CLKOUT_LPC1 CK_LPC_TPM [27]
[45] KB_RST# KB_RST# AW13 AW11 CLKRUN#
GPP_A0/RCIN# GPP_A8/CLKRUN# CLKRUN# [45]
C C

[27,45] SERIRQ SERIRQ AY11

GPP_A6/SERIRQ 5 OF 20 1
+1.8VS_3VS_PGPPA @RF@
SKL-U_BGA1356 CC95
@ 33P_0402_50V8J
RC25 1 2 8.2K_0402_5% SERIRQ 2 +3VS

RPC1, RPC3 and RC30 are close to UC3 +3VALW SOC_SML1ALERT# RC26 2 @ 1 150K_0402_5%

RPC1 EMI@ < SPI ROM - 8M > SOC_SML0CLK RC27 1 2 499_0402_1%

SOC_SPI_IO2 1 8 SOC_SPI_IO2_0_R @
SOC_SPI_SO 2 7 SOC_SPI_SO_0_R UC9 8M@ CC2 1 2 0.1U_0201_10V6K SOC_SML0DATA RC28 1 2 499_0402_1%
SOC_SPI_SI 3 6 SOC_SPI_SI_0_R SOC_SPI_CS#0 1 8
SOC_SPI_IO3 4 5 SOC_SPI_IO3_0_R SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R RPC2
From CPU 33_0804_8P4R_5% 4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R SOC_SMBCLK 1 8
GND DI(IO0)

CC3 10P_0603_50V8-J
1 SOC_SMBDATA 2 7

@EMI@
SOC_SPI_CLK 1 2 SOC_SPI_CLK_0_R W25Q64FVSSIQ_SO8 SOC_SML1DATA 3 6
B RC29 EMI@ 33_0402_5% SOC_SML1CLK 4 5 B

UC9 2 1K_0804_8P4R_5%

RPC3 EMI@
EC_SPI_CS0# 1 8 SOC_SPI_CS#0 +1.8VS_3VS_PGPPA
[45] EC_SPI_CS0#
EC_SPI_MOSI 2 7 SOC_SPI_SI_0_R
[45] EC_SPI_MOSI
EC_SPI_CLK 3 6 SOC_SPI_CLK_0_R
From EC [45] EC_SPI_CLK
EC_SPI_MISO 4 5 SOC_SPI_SO_0_R 16M@ CLKRUN# 1 @ 2
[45] EC_SPI_MISO
16M ROM RC30 8.2K_0402_5%
33_0804_8P4R_5% SA00005VV20
Follow 543016_SKL_U_Y_PDG_0_9

+3VALW

RC110 1 2 SOC_SPI_CS#0
10K_0402_5%

For ENE auto load search code V12

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(3/12)SPI,SMB,LPC,ESPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 8 of 66
5 4 3 2 1
 5 4 3 2 1

< HD AUDIO >

RPC4 EMI@
1 8 HDA_BIT_CLK
[35]
[35]
[35]
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO
Vinafix.com2
3
7 HDA_SYNC
6 ME_EN
[35] HDA_RST_AUDIO# 4 5 HDA_RST#
D D
33_0804_8P4R_5%

UC1G SKL-U
Rev_1.0
AUDIO

[44] HDA_SYNC HDA_SYNC BA22

HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
[44] HDA_BIT_CLK HDA_BLK/I2S0_SCLK
ME_EN BB22
< To Enable ME Override > [44,45] ME_EN
BA21 HDA_SDO/I2S0_TXD
SDIO / SDXC
[35] HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
[44] HDA_RST# HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
J5 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 RC31 2 @ 1 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0

[38] DDI_PRIORITY DDI_PRIORITY D8 AF13

C C8 GPP_D17/DMIC_CLK1 GPP_F23 C
GPP_D18/DMIC_DATA1

[35] HDA_SPKR HDA_SPKR AW5

GPP_B14/SPKR
7 OF 20

SKL-U_BGA1356
@

+3VS
UC1I SKL-U
Rev_1.0
CSI-2
1 @ 2 HDA_SPKR
RC32 2.2K_0402_5% A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
SPKR (Internal Pull Down): D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
CSI2_DN3 CSI2_CLKN3
TOP Swap Override B38
CSI2_DP3 CSI2_CLKP3
A26
B C31 E13 RC33 2 @ 1 100_0402_1% B
0 = Disable TOP Swap mode. ==> Default D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
1 = Enable TOP Swap Mode. A31 CSI2_DP5 EMMC

B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 RC34 2 @ 1 200_0402_1%
EMMC_RCOMP
SKL-U_BGA1356
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 9 of 66
5 4 3 2 1
 5 4 3 2 1

SOC_XTAL24_IN RC1011 2 33_0201_1% SOC_XTAL24_IN_R

0606 change EMI@

U22@ RC35
SOC_XTAL24_OUT RC1001 2 33_0201_1% SOC_XTAL24_OUT_R 1 2 1M_0402_5%
+3VS EMI@ RC35 1M_0402_5% U23@
SD028100480
UC1J SKL-U YC1 U22@ SJ10000UJ00
Rev_1.0 YC1 24MHZ_18PF_XRCGB24M000F2P51R0
CLOCK SIGNALS 24MHZ_18PF_XRCGB24M000F2P51R0
U23@ 3 1
D42 SJ10000UJ00 3 1
RPC5 [21] CLK_PCIE_GPU# CLKOUT_PCIE_N0 NC NC

Vinafix.comDGPU

27P_0402_50V8J
CC4 U22@

27P_0402_50V8J
CC5 U22@
C42 CC4 1 1 CC5
EC_SCI# [21] CLK_PCIE_GPU GPUCLK_REQ# CLKOUT_PCIE_P0
8 1 EC_SCI# [6,45] [22] GPUCLK_REQ# AR10 27P_0402_50V8J 27P_0402_50V8J
7 2 WLANCLK_REQ# GPP_B5/SRCCLKREQ0# U23@ 4 2 U23@
6 3 M2CLK_REQ# B42 SE071270J80 SE071270J80
LANCLK_REQ# [36] CLK_PCIE_LAN# CLKOUT_PCIE_N1 2 2
5 4 LAN A42 F43
D [36] CLK_PCIE_LAN LANCLK_REQ# CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N D
[36] LANCLK_REQ# AT7 E43
10K_0804_8P4R_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17 SUSCLK
[31] CLK_PCIE_WLAN# CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK [31]
NGFF WL+BT(KEY E) C41
[31] CLK_PCIE_WLAN WLANCLK_REQ# CLKOUT_PCIE_P2 SOC_XTAL24_IN
RC36 1 UMA@ 2 10K_0402_5% [31] WLANCLK_REQ# AT8 E37 YC1 need to be replaced by
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 SOC_XTAL24_OUT
XTAL24_OUT 38.4MHz (30ohm ESR) XTAL for Cannonlake-U
1 DIS@ 2 GPUCLK_REQ# D40
[32] CLK_PCIE_M2# CLKOUT_PCIE_N3 XCLK_BIASREF
RC37 10K_0402_5% M.2 PCIE SSD C40 E42
[32] CLK_PCIE_M2 M2CLK_REQ# CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5_F24NS
[32] M2CLK_REQ# AT10
GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1
B40 RTCX1 AM20 SOC_RTCX2 XCLK_BIASREF 1 2
A40 CLKOUT_PCIE_N4 RTCX2 RC38 2.7K_0402_1%
AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST# 1 @ 2
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST# RC39 60.4_0402_1%
E40 RTCRST#
E38 CLKOUT_PCIE_N5
AU7 CLKOUT_PCIE_P5
+3VL_RTC GPP_B10/SRCCLKREQ5#
Follow 546765_2014WW48_Skylake_MOW_Rev_1_0
10 OF 20
RC40 1 2 20K_0201_5% SOC_SRTCRST# Stuff 2.7k ohm(RC35) PU for Skylake-U
SKL-U_BGA1356
CC6 1 2 1U_0402_6.3V6K @ Stuff 60.4 ohm(RC110) PD for Cannonlake-U

RC42
RC41 1 2 20K_0402_5% SOC_RTCRST# 1 2 EC_CLEAR_CMOS# [45]
0_0402_5%
CC7 1 2 1U_0402_6.3V6K SOC_RTCX2
< PCH PLTRST Buf f er >
CLRP1 1 2 SHORT PADS CLR CMOS RC43
1 2
0_0402_5% SOC_RTCX1
RC441 2 1M_0402_5% SM_INTRUDER#
C +3VS 1 2 C
RC45 10M_0402_5%

5
UC11
SOC_PLTRST# 1 YC2

P
B 4 1 2
Y PCIRST# [21,27,31,32,36,45]
2
A

G
32.768KHZ 9PF 20PPM 9H03280012

1
TC7SH08FUF_SSOP5

1
RC46
100K_0402_5%
@ 1 1
+3VALW CC8
100P_0402_50V8J CC9 CC10

2
4.7P_0402_50V8B 4.7P_0402_50V8B
RPC6 ESD@

2
2 2
8 1 PCH_PWROK
7 2 EC_RSMRST#
6 3 LAN_WAKE#
5 4 SYS_RESET#

10K_0804_8P4R_5%

ESD
UC1K SKL-U
EC_RSMRST# RC47 1 2 0_0402_5% PCH_DPWROK Rev_1.0
ESD@ 1 2 SYS_RESET# SYSTEM POWER MANAGEMENT
CC11 100P_0402_50V8J AT11 PM_SLP_S0#
GPP_B12/SLP_S0# TP@T19
ESD@ 1 2 EC_RSMRST# AP15 PM_SLP_S3#
SOC_PLTRST# GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# [45]
CC12 100P_0402_50V8J AN10 BA16
SYS_PWROK SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# [45,54]
ESD@ 1 2 B5 AY16 TP@T20
CC13 100P_0402_50V8J EC_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5#
[45] EC_RSMRST# RSMRST# AN15
H_CPUPWRGD A68 SLP_SUS# AW15
Only For Power Sequence Debug T21 TP@ PROCPWRGD SLP_LAN#
B EC_VCCST_PG B65 BB17 SLP_WLAN# B
VCCST_PWRGD GPD9/SLP_WLAN# TP@T22
AN16 PM_SLP_A#
GPD6/SLP_A# TP@T23
SYS_PWROK B6
[45] SYS_PWROK SYS_PWROK
PCH_PWROK BA20 BA15 PBTN_OUT#
[45] PCH_PWROK PCH_PWROK GPD3/PWRBTN# PBTN_OUT# [45]
RC107 1 2 10K_0402_5% SYS_PWROK PCH_DPWROK BB20 AY15 AC_PRESENT RC48 1 2 0_0402_5%
DSW_PWROK GPD1/ACPRESENT PM_BATLOW# AC_PRESENT_R [45]
AU13
SUSWARN# AR13 GPD0/BATLOW#
T24 TP@ GPP_A13/SUSWARN#/SUSPWRDNACK +3VALW
AP11
GPP_A15/SUSACK# AU11
WAKE# BB15 GPP_A11/PME# AP16 SM_INTRUDER#
LAN_WAKE# AM15 WAKE# INTRUDER# PM_BATLOW# 1 2
AW17 GPD2/LAN_WAKE# AM10 RC50 8.2K_0402_5%
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT#
GPD7/RSVD 11 OF 20 GPP_B2/VRALERT#
+3VALW SOC_VRALERT# 1 @ 2
SKL-U_BGA1356 RC51 10K_0402_5%
1 2 WAKE# @
RC49 1K_0402_5%

+1.0V_VCCST
From EC (Open-Drain)
1

RC52
1K_0402_5%
2

A RC53 1 2 60.4_0402_1% EC_VCCST_PG A

[45] VCCST_PWRGD

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(5/12)CLK,PM,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 10 of 66
5 4 3 2 1
 5 4 3 2 1

RAM vender OBRAM_ID2 OBRAM_ID1 OBRAM_ID0

Hynix 1 1 1
Micron 1 1 0
Samsung 1 0 1

Vinafix.com
1
+3VS +3VS
0 0
+3VS
D D
Reserve

1
RC105 RC55 RC54
10K_0402_5% 10K_0402_5% 10K_0402_5%
X76@ X76@ X76@
GSPI0_MOSI (Internal Pull Down):

2
OBRAM_ID2 OBRAM_ID1 OBRAM_ID0
No Reboot

1
RC104 RC57 RC56
0 = Disable No Reboot mode. ==> Default 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76@ X76@ X76@
1 = Enable No Reboot Mode. (PCH will disable the TCO

2
Timer system reboot feature). This function is useful
when running ITP/XDP.

GSPI1_MOSI (Internal Pull Down):

UC1F SKL-U
Boot BIOS Strap Bit Rev_1.0
LPSS ISH
0 = SPI Mode ==> Default
OBRAM_ID2 AN8 P2
+3VS 1 = LPC Mode OBRAM_ID0 AP7 GPP_B15/GSPI0_CS# GPP_D9 P3
OBRAM_ID1 AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1
1 @ 2 GSPI0_MOSI GPP_B18/GSPI0_MOSI GPP_D12
RC58 2.2K_0402_5% AM5 M4
1 @ 2 GSPI1_MOSI AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
RC59 2.2K_0402_5% AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
AB1 GPP_D8/ISH_I2C1_SCL +3VS
C WLBT_OFF# [33] TP_INT# GPP_C8/UART0_RXD C
RC1031 2 10K_0402_5% AB2 AD11
[28] DMIC_DET# GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
W4 AD12
RC1061 2 10K_0402_5% DMIC_DET# WLBT_OFF# AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
[31] WLBT_OFF# GPP_C11/UART0_CTS#
1 2 UART_2_CRXD_DTXD UART_2_CRXD_DTXD AD1 U1
[31] UART_2_CRXD_DTXD UART_2_CTXD_DRXD AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
RC60 49.9K_0402_1% U2
UART_2_CTXD_DRXD [31] UART_2_CTXD_DRXD GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
1 2 AD3 U3
RC61 49.9K_0402_1% AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 RPC7 DIS@
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# DGPU_HOLD_RST# 1 8
AC1 DGPU_PWR_EN DGPU_PWR_EN 2 7
+3VS GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_HOLD_RST# DGPU_PWR_EN [23,45,57,58] DGPU_PWROK
U7 AC2 3 6
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD DGPU_PWROK DGPU_HOLD_RST# [21] DGPU_PRSNT#
U6 AC3 DGPU_PWROK [57,58] 4 5
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 DGPU_PRSNT#
R469 1 2 2.2K_0201_5%I2C1_SDA_TP I2C1_SDA_TP U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS# 10K_0804_8P4R_5%
[33] I2C1_SDA_TP I2C1_SCL_TP GPP_C18/I2C1_SDA AOU_STRAP
U9 AY8
[33] I2C1_SCL_TP GPP_C19/I2C1_SCL GPP_A18/ISH_GP0
R470 1 2 2.2K_0201_5%I2C1_SCL_TP BA8 TPM_STRAP
AH9 GPP_A19/ISH_GP1 BB7 TPM_STRAP2
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2
DGPU_PRSNT# PD for DIS SKU
AH10 BA7 APS_STRAP
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 PD_STRAP
AH11 GPP_A22/ISH_GP4 AW7 ULTBY_STRAP
Funct i on GPP_C15
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6 UMA 1
AF11 DIS 0
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL 6 OF 20
+3VS
SKL-U_BGA1356
@ RC62 1 UMA@ 2 10K_0402_5% DGPU_PRSNT#

B B
Funct i on GPP_A18 Funct i on GPP_A20 R3163 PCH_[GPPA20,GPPA19]
AOU 1 +3VS APS 1 +3VS
TCM@ Funct i on
10K_0402_5% TPM_STARP2 TPM_STARP
NONAOU 0 NO APS 0 SD028100280 NOTPM 0 1
+3VS

AOU_STRAP 2 1 APS_STRAP 2 1 TPM_STRAP 10K_0402_5% 2 1 R3163

TCM 1 1
10K_0402_5% AOU@ RC112 10K_0402_5% APS@ RC108 NOTPM@ TPM 1 0
2 1 2 1 10K_0402_5% 2 1 R3164
10K_0402_5% NONAOU@ RC111 10K_0402_5% NOAPS@ RC109 TPM@

+3VS R3165
TPM@
TPM_STRAP2 10K_0402_5% 2 1 R3165 10K_0402_5%
Funct i on GPP_A23 Funct i on GPP_A22 TCM@ SD028100280
ULTRA BAY 1 PD 1 10K_0402_5% 2 1 R3166
+3VS +3VS NOTPM@
NO ULTRA BAY 0 NO PD 0
ULTBY_STRAP 2 1 PD_STRAP 2 1
10K_0402_5% BATT2@ RC114 10K_0402_5% TYPEC@ RC116
2 1 2 1
10K_0402_5% NOBATT2@ RC113 10K_0402_5% NONTYPEC@ RC115

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(6/12)GPIO,I2C,GSPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 11 of 66
5 4 3 2 1
 5 4 3 2 1

UC1H SKL-U

Vinafix.com SSIC / USB3

Rev_1.0

PCIE / USB3 / SATA

D H8 USB3_RX_N1 [34] D
USB3_1_RXN G8
USB3_1_RXP USB3_RX_P1 [34]
[21] PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N1 H13 C13 USB3(AOU)
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3_TX_N1 [34]
[21] PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 G13 D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_TX_P1 [34]
CC18 1 2 DIS@ 0.22U_0402_6.3V6KPCIE_CTX_GRX_N1 B17
[21] PCIE_CTX_C_GRX_N1 PCIE1_TXN/USB3_5_TXN
[21] PCIE_CTX_C_GRX_P1 CC19 1 2 DIS@ 0.22U_0402_6.3V6KPCIE_CTX_GRX_P1 A17 J6 USB3_RX_N2 [34]
PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6
USB3_2_RXP / SSIC_RXP USB3_RX_P2 [34]
PCIE_CRX_GTX_N2 G11 B13 USB3(Type-A)
[21] PCIE_CRX_GTX_N2 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN USB3_TX_N2 [34]
PCIE_CRX_GTX_P2 F11 A13
[21] PCIE_CRX_GTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_TX_P2 [34]
CC14 1 2 DIS@ 0.22U_0402_6.3V6KPCIE_CTX_GRX_N2 D16
[21] PCIE_CTX_C_GRX_N2 CC15 1 2 DIS@ 0.22U_0402_6.3V6KPCIE_CTX_GRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
[21] PCIE_CTX_C_GRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN USB3_RX_N3 [42]
H10 USB3_RX_P3 [42]
PCIE_CRX_GTX_N3 H16 USB3_3_RXP B15
dGPU [21] PCIE_CRX_GTX_N3 PCIE3_RXN USB3_3_TXN USB3_TX_N3 [42] USB3(Type-C)
PCIE_CRX_GTX_P3 G16 A15
[21] PCIE_CRX_GTX_P3 PCIE3_RXP USB3_3_TXP USB3_TX_P3 [42]
CC16 1 2 DIS@ 0.22U_0402_6.3V6KPCIE_CTX_GRX_N3 D17
[21] PCIE_CTX_C_GRX_N3 PCIE3_TXN
CC17 1 2 DIS@ 0.22U_0402_6.3V6KPCIE_CTX_GRX_P3 C17 E10 USB3_RX_N4 [40]
[21] PCIE_CTX_C_GRX_P3 PCIE3_TXP USB3_4_RXN F10
USB3_4_RXP USB3_RX_P4 [40]
PCIE_CRX_GTX_N4 G15 C15 USB3(Type-C Full)
[21] PCIE_CRX_GTX_N4 PCIE4_RXN USB3_4_TXN USB3_TX_N4 [40]
PCIE_CRX_GTX_P4 F15 D15
[21] PCIE_CRX_GTX_P4 PCIE4_RXP USB3_4_TXP USB3_TX_P4 [40]
CC20 1 2 DIS@ 0.22U_0402_6.3V6KPCIE_CTX_GRX_N4 B19
[21] PCIE_CTX_C_GRX_N4 PCIE4_TXN
CC21 1 2 DIS@ 0.22U_0402_6.3V6KPCIE_CTX_GRX_P4 A19 AB9 USB20_N1
[21] PCIE_CTX_C_GRX_P4 PCIE4_TXP USB2N_1 USB20_N1 [34]
AB10 USB20_P1 USB2(AOU)
USB2P_1 USB20_P1 [34]
PCIE_CRX_DTX_N5 F16
[36] PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 E16 PCIE5_RXN AD6 USB20_N2
[36] PCIE_CRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 [34]
LAN CC22 1 2 0.1U_0201_10V6K PCIE_CTX_DRX_N5 C19 AD7 USB20_P2 USB2(Type-A)
[36] PCIE_CTX_C_DRX_N5 PCIE5_TXN USB2P_2 USB20_P2 [34]
CC23 1 2 0.1U_0201_10V6K PCIE_CTX_DRX_P5 D19
[36] PCIE_CTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3
USB2N_3 USB20_N3 [43]
[31] PCIE_CRX_DTX_N6 PCIE_CRX_DTX_N6 G18 AJ3 USB20_P3 USB2(Type-C)
PCIE6_RXN USB2P_3 USB20_P3 [43]
[31] PCIE_CRX_DTX_P6 PCIE_CRX_DTX_P6 F18
PCIE_CTX_DRX_N6 D20 PCIE6_RXP AD9 USB20_N4
C M.2 WLAN [31] PCIE_CTX_DRX_N6 PCIE6_TXN USB2N_4 USB20_N4 [41]
C
PCIE_CTX_DRX_P6 C20 AD10 USB20_P4 USB2(Type-C Full)
[31] PCIE_CTX_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 [41]
F20 AJ1 USB20_N5
[30] SATA_CRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 [28]
E20 AJ2 USB20_P5 Camera
[30] SATA_CRX_DTX_P0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 [28]
HDD B21 USB2
[30] SATA_CTX_DRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
[30] SATA_CTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 [31]
AF7 USB20_P6 M.2 BT
USB2P_6 USB20_P6 [31]
G21
F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 [37]
D21 AH2 USB20_P7 Card Reader
PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 [37]
C21
PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
USB2N_8 USB20_N8 [33]
E22 AF9 USB20_P8 Finger Print
[32] PCIE_CRX_DTX_N9 PCIE9_RXN USB2P_8 USB20_P8 [33]
E23
[32] PCIE_CRX_DTX_P9 B23 PCIE9_RXP AG1 USB20_N9
[32] PCIE_CTX_DRX_N9 PCIE9_TXN USB2N_9 USB20_N9 [46]
A23 AG2 USB20_P9 2nd Battery
[32] PCIE_CTX_DRX_P9 PCIE9_TXP USB2P_9 USB20_P9 [46]
F25 AH7
[32] PCIE_CRX_DTX_N10 E25 PCIE10_RXN USB2N_10 AH8
[32] PCIE_CRX_DTX_P10 D23 PCIE10_RXP USB2P_10
[32] PCIE_CTX_DRX_N10 C23 PCIE10_TXN AB6 USB2_COMP RC64 1 2 113_0402_1%
[32] PCIE_CTX_DRX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID RC65 1 2 1K_0402_5% +3VS
RC66 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC67 1 2 1K_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
M.2 PCIE_RCOMPP A9 USB_OC0#
SATA/PCIE*4 XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
USB_OC0# [34]
T25 TP@ PROC_PRDY# GPP_E10/USB2_OC1# USB_OC1# [34]

1
T26 TP@ XDP_PREQ# D61 D9 USB_OC2# USB_OC2# [46]
BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# R235 B
E28 J1 10K_0402_5%
[32] PCIE_CRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 EC_WL_OFF# [31]

2
[32] PCIE_CRX_DTX_P11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3
[32] PCIE_CTX_DRX_N11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
[32] PCIE_CTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2
[32] PCIE_CRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
[32] PCIE_CRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4
[32] PCIE_CTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 SATA_GP2 [32]
[32] PCIE_CTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 PCH_SATALED#
GPP_E8/SATALED# PCH_SATALED# [33] +3VALW
8 OF 20

0222 change net name SKL-U_BGA1356

When PCIE8/SATA1A is used @ RPC8
as SATA Port 1 (ODD), then USB_OC2# 8 1
PCIE11/SATA1B (M.2 SSD) USB_OC1# 7 2
cannot be used as SATA USB_OC0# 6 3
USB_OC3# 5 4
Port 1.
10K_0804_8P4R_5%

+3VS

PCH_SATALED# 1 2
RC68 10K_0402_5%
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 12 of 66
5 4 3 2 1
 5 4 3 2 1

Follow 543977_SKL_PDDG_Rev0_91
CC24 10PF ->22us(Spec:<= 65us)
+1.2V +1.0VS_VCCIO
UC1N SKL-U
Rev_1.0
CPU POWER 3 OF 4
AU23 AK28
AU28 VDDQ_AU23 VCCIO AK30
Vinafix.com
I(Max) : 0.16 A(+1.0V_VCCST)
AU35
AU42
VDDQ_AU28
VDDQ_AU35
VCCIO
VCCIO
AL30
AL42
+1.0VALW TO +1.0V_VCCST RON(Max) : 25 mohm BB23
BB32
VDDQ_AU42
VDDQ_BB23
VCCIO
VCCIO
AM28
AM30
D V drop : 0.004 V D
BB41 VDDQ_BB32 VCCIO AM42 +VCCSA
+1.0VS_VCCIO BB47 VDDQ_BB41 VCCIO
BB51 VDDQ_BB47 AK23
VDDQ_BB51 VCCSA AK25
VCCSA G23
+1.0V_VCCST AM40 VCCSA G25
VDDQC VCCSA G27
A18 VCCSA G28
+5VALW +1.0VALW +1.0V_VCCST VCCST VCCSA J22
UC12 A22 VCCSA J23
VCCSTG_A22 VCCSA J27
1 7 AL23 VCCSA K23
2 VIN VOUT 8 VCCPLL_OC VCCSA K25
VIN VOUT VCCSA

0.1U_0201_10V6K
RC69 1 K20 K27
VCCPLL_K20 VCCSA

CC26
1 2 EN_1.0V_VCCSTU 3 6 K21 K28
[44,45,54] SYSON 47K_0402_5% ON CT VCCPLL_K21 VCCSA K30
VCCSA
0.1U_0402_25V6

10P_0402_50V8J
1
1

2
CC29

4 CC27 AM23
VBIAS VCCIO_SENSE

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 5 AM22
CC24 GND VSSIO_SENSE

CC25
9
2

GND 2 H21 VSSSA_SENSE

VSSSA_SENSE VSSSA_SENSE [59]
H20 VCCSA_SENSE
2 2 VCCSA_SENSE VCCSA_SENSE [59]
TPS22967DSGR_SON8_2X2 14 OF 20
SKL-U_BGA1356
@ Trace Length Match < 25 mils

C C

+1.0VALW TO +1.0VS_VCCIO
+5VALW +1.0VALW I(Max) : 3.04 A(+1.0VS_VCCIO)
+1.0V_VCCST +1.0VS_VCCIO
RON(Max) : 6.2 mohm
V drop : 0.019 V
PSC Side BSC Side
0.1U_0201_10V6K

1U_0402_6.3V6K

1 1
CC33

CC34

UC13
1
@ 2 VIN1 +1.0VS_VCCIO
2 2 VIN2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
7 6 +1.0VS_VCCIO_STG RC71 1 1 1
VIN thermal VOUT 1 2

CC35

CC36

CC37
3 0_0805_5%
VBIAS @
1 2 2 2
4 5
SUSP# RC72 1 2 0_0402_5% ON GND CC38
[44,45,54,63] SUSP# @ 0.1U_0201_10V6K
2
0.1U_0402_25V6

TPS22961DNYR_WSON8
1

CC39

B @ B
Close to A18 Close to K20 Close to A22
2

+1.0VS_VCCIO +1.2V

BSC Side PSC Side BSC Side PSC Side BSC Side
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC41

CC42

10P_0402_25V8J

CC54

CC55
CC40

CC43

CC44

CC45

CC46

CC47

CC48

CC49

CC50

CC51

CC52

CC53
CC96
@ @ @ RF@ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Underneath CPU Close to CPU Close to AL23 Close to AM40 Close to CPU Underneath CPU
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(8/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 13 of 66
5 4 3 2 1
 5 4 3 2 1

Follow 543016_SKL_U_Y_PDG_1_0
Vinafix.com
D +1.0VALW +1.0V_APLL D
+1.0VALW +1.0VALW +1.8VALW
+1.0V_PRIM_CORE UC1O SKL-U
LC1 Rev_1.0 +3VALW
MURATA BLM15EG221SN1D CPU POWER 4 OF 4
1 2 RC73 CC58 1 2 1U_0402_6.3V6K AB19
SM01000HC00 1 2 AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3V_1.8V_PGPPA
R_0402 RF@ 1 0_0805_5% @ P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16
Imax : 2.57A VCCPGPPC

1U_0402_6.3V6K
CC59 1 +1.0V_PRIM_CORE AF18 Y15
AF19 VCCPRIM_CORE VCCPGPPD T16
0.1U_0201_10V K X5R VCCPRIM_CORE VCCPGPPE
2

CC60
V20 AF16 VCCPGPPF support 1.8V only

RF@
@ V21 VCCPRIM_CORE VCCPGPPF AD15
2 VCCPRIM_CORE VCCPGPPG
CC56 1 2 1U_0402_6.3V6K DCPDSW AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
Follow 543016_SKL_U_Y_PDG_1_0 CC57 1 2 1U_0402_6.3V6K K17 T1 +1.0VALW
L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1
Close to K17 VCCMPHYAON_1P0
+1.0V_AMPHYPLL +1.0V_MPHYGT AA1 CC61 1 2 1U_0402_6.3V6K
N15 VCCATS_1P8
+1.0V_MPHYGT VCCMPHYGT_1P0_N15
RC74 N16 AK17
RC75 1 2 N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
1 2 0_0805_5% P15 VCCMPHYGT_1P0_N17 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
22U_0603_6.3V6M

1U_0402_6.3V6K
0_0603_5% Imax : 3.5A P16 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14

22U_0603_6.3V6M

1U_0402_6.3V6K
1 1 1 1
CC62

CC63

CC65

CC66
+1.0V_AMPHYPLL K15 BB10 DCPRTC CC64 1 2 0.1U_0201_10V6K
L15 VCCAMPHYPLL_1P0 DCPRTC
@ @ VCCAMPHYPLL_1P0 A14
2 2 2 2 VCCCLK1 +1.0V_CLK6_24TBT
+1.0V_APLL V15
@ VCCAPLL_1P0 K19
AB17 VCCCLK2
Y18 VCCPRIM_1P0_AB17 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL

+3VALW AD17 N20 +1.0V_CLK4_F100OC

AD18 VCCDSW_3P3_AD17 VCCCLK4
+1.0V_CLK5_F24NS AJ17 VCCDSW_3P3_AD18 L19
C VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS C
Follow 543016_SKL_U_Y_PDG_1_0
RC76 +3VALW +3.3V_HDA AJ19 A10
+3.3V_HDA VCCHDA VCCCLK6 +1.0V_CLK6_24TBT
1 2
0_0603_5% RC77 RF@ +3VALW AJ16 AN11
VCCSPI GPP_B0/CORE_VID0
22U_0603_6.3V6M

MURATA BLM15EG221SN1D AN13

GPP_B1/CORE_VID1

0.1U_0201_10V K X5R
1 2 AF20
1
HD Audio : 3.3V or 1.5V VCCSRAM_1P0
CC67

SM01000HC00 AF21
T19 VCCSRAM_1P0
R_0402 1
I2S : 1.8V or 3.3V VCCSRAM_1P0

CC68
RF@
@ T20
2 VCCSRAM_1P0
AJ21
2 VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
+3VALW +1.0VALW VCCAPLLEBB_1P0 15 OF 20
+1.0V_CLK4_F100OC
Follow 543016_SKL_U_Y_PDG_1_0 +3V_1.8V_PGPPA SKL-U_BGA1356
RC78 @
1 2 2 2 2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
0_0603_5% @ @
22U_0603_6.3V6M

CC69

CC70

CC71
1 1 1 1
CC72

+3VALW
@ LPC 3.3V
2 RC80 RTC Bat t er y
1 2
0_0402_5% Close to AJ21 Close to AF20 Close to N18
+3VL_RTC +RTCBATT

W=20mils
+1.0V_CLK6_24TBT RC81 1 2 0_0402_5%
+1.8VS_3VS_PGPPA
B Follow 543016_SKL_U_Y_PDG_1_0 1 B
RC82 CC73
1 2 1U_0402_6.3V6K
Follow 543016_SKL_U_Y_PDG_1_0
0_0603_5%
2
22U_0603_6.3V6M

+3VS +1.0VALW +3VALW +1.8VALW +3VALW Delete CC77 , CC78 for DDR layout modify
1U_0402_6.3V6K

1 1
CC75
CC74

LPC 3.3V
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@ @ RC84 Saf t y s ugges t i on r emove EE s i de , Keep PW
R s i de
2 2 1 2 1 1 1 1 1 1
CC76

CC77

CC78

CC79

CC80

CC81

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V6K
0_0402_5% 1 1 1

CC82

CC83

CC84
@ @ @ @ @ @ @
2 2 2 2 2 2
2 2 2

Close to AG15 Close to Y16 Close to T16 Close to AK17

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(9/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 14 of 66
5 4 3 2 1
 5 4 3 2 1

+VCCCORE +VCCCORE +VCC_GT_+VCC_CORE +VCCGT +VCCGT +VCC_GT_+VCC_CORE

UC1M SKL-U
UC1L SKL-U Rev_1.0
Rev_1.0 CPU POWER 2 OF 4

A30 Vinafix.com
VCC_A30
CPU POWER 1 OF 4

VCC_G32
G32 A48
VCCGT
VCCGT
VCCGT
N70
N71
A34 G33 A53 R63
A39 VCC_A34 VCC_G33 G35 A58 VCCGT VCCGT R64
D D
A44 VCC_A39 VCC_G35 G37 A62 VCCGT VCCGT R65
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
AM37 VCC_AM35 VCC_K38 K40 AC67 VCCGT VCCGT W64
AM38 VCC_AM37 VCC_K40 K42 AC68 VCCGT VCCGT W65
G30 VCC_AM38 VCC_K42 K43 AC69 VCCGT VCCGT W66
VCC_G30 VCC_K43
Trace Length Match < 25 mils VCCGT VCCGT
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
RSVD VCC_SENSE VCCCORE_SENSE [59] VCCGT VCCGT
E33 J43 W69
+1.0VS_VCCOPC AK32 VSS_SENSE VSSCORE_SENSE [59] VCCGT VCCGT
J45 W70
RSVD B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
AB62 VIDALERT# A63 VR_SVID_CLK J48 VCCGT VCCGT Y62
VCCOPC_AB62 VIDSCK VR_SVID_CLK [59] VCCGT VCCGT
P62 D64 VR_SVID_DATA J50
+1.8VALW V62 VCCOPC_P62 VIDSOUT J52 VCCGT
VCCOPC_V62 G20 J53 VCCGT AK42
VCCSTG_G20
ALERT signal must be routed between CLK and DATA signals VCCGT VCCGTX_AK42
1 U23@ 2 +1.8V_VCCOPC H63 J55 AK43
RC85 0_0402_5% VCC_OPC_1P8_H63 +1.0VS_VCCIO J56 VCCGT VCCGTX_AK43 AK45 +VCCGT
For GT3 SKU VCCGT VCCGTX_AK45
G61 +VCCGT J58 AK46
VCC_OPC_1P8_G61 J60 VCCGT VCCGTX_AK46 AK48
C VCCOPC_SENSE AC63 K48 VCCGT VCCGTX_AK48 AK50 C
[63] VCCOPC_SENSE VCCOPC_SENSE VCCGT VCCGTX_AK50
VSSOPC_SENSE AE63 K50 AK52 1 SKL@ 2
[63] VSSOPC_SENSE VSSOPC_SENSE VCCGT VCCGTX_AK52
1 2 K52 AK53 RC86 0_0402_5%
AE62 RC87 SKL@ 0_0402_5% K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
0309 K52 and AK52 KEEP NC VCCGT VCCGTX_AK58
AL63 K58 AK60
AJ62 VCCEOPIO_SENSE 563377_KBL_MOW_WW09_March_2017 K60 VCCGT VCCGTX_AK60 AK70
VSSEOPIO_SENSE 12 OF 20 ------------------------- L62 VCCGT VCCGTX_AK70 AL43
VCCGT VCCGTX_AL43
SLK will connection add structure L63
VCCGT VCCGTX_AL46
AL46
SKL-U_BGA1356 L64 AL50
L65 VCCGT VCCGTX_AL50 AL53
@ VCCGT VCCGTX_AL53
L66 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
SVID ALERT N66 VCCGT
VCCGT
VCCGTX_AU58
VCCGTX_AU63
AU63
+1.0V_VCCST N67 BB57
Place the PU VCCGT VCCGTX_BB57
N69 BB66 For GT3 SKU
resistors close to CPU VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62 VCCGTX_SENSE T29 TP@
[59] VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE
1

VSSGT_SENSE J69 AL61 VSSGTX_SENSE T30 TP@

[59] VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
RC88 13 OF 20
56_0402_5%
B SKL-U_BGA1356 B
Trace Length Match < 25 mils
@
2

SOC_SVID_ALERT# 1 2 (To VR)

VR_ALERT# [59]
RC89 220_0402_5%
For CPU GT3 SKU

+1.0VS_VCCOPC
+1.0V_VCCST BSC Side BSC Side
SVID DATA Place the PU
resistors close to CPU
1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
RC90 1 1 1 1 1 1 1
100_0402_5%

CC85

CC86

CC87

CC88

CC89

CC90

CC91
U23@

U23@

U23@

U23@

U23@

U23@

U23@
2

2 2 2 2 2 2 2

VR_SVID_DATA
VR_SVID_DATA [59] (To VR)

A Close to AE62,AG62 Close to AB62,P62,V62 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(10/12)Power,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 15 of 66
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D D
UC1P SKL-U UC1Q SKL-U
Rev_1.0 Rev_1.0 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3 Rev_1.0
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
C AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 C
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46
VSS VSS VSS VSS @
AJ4 AR35 B30 E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
B AK27 VSS VSS AR5 B58 VSS VSS F1 B
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(11/12)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 16 of 66
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D D

UC1S SKL-U UC1T SKL-U

Rev_1.0 Rev_1.0
RESERVED SIGNALS-1 SPARE

T33 TP@ CFG0 E68 BB68 AW69 F6

CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 AW68 RSVD_AW69 RSVD_F6 E3 42E_SOC_XTAL24_IN_R
T34 TP@ CFG[1] RSVD_TP_BB69 RSVD_AW68 RSVD_E3
T35 TP@ CFG2 D65 AU56 C11
CFG3 D67 CFG[2] AK13 AW48 RSVD_AU56 RSVD_C11 B11
T36 TP@ CFG[3] RSVD_TP_AK13 RSVD_AW48 RSVD_B11
T37 TP@ CFG4 E70 AK12 42E_SOC_XTAL24_OUT_R C7 A11
CFG5 C68 CFG[4] RSVD_TP_AK12 RSVD_U12 U12 RSVD_C7 RSVD_A11 D12
T38 TP@ CFG[5] RSVD_U12 RSVD_D12
T31 TP@ CFG6 D68 BB2 RSVD_U11 U11 C12
CFG7 C67 CFG[6] RSVD_BB2 BA3 H11 RSVD_U11 RSVD_C12 F52
T39 TP@ CFG[7] RSVD_BA3 RSVD_H11 RSVD_F52
T32 TP@ CFG8 F71
CFG9 G69 CFG[8] 20 OF 20
T40 TP@ CFG[9]
T41 TP@ CFG10 F70 AU5
CFG11 G68 CFG[10] TP5 AT5 SKL-U_BGA1356
T42 TP@ CFG[11] TP6
T43 TP@ CFG12 H70 @
CFG13 G71 CFG[12]
T44 TP@ CFG[13]
T45 TP@ CFG14 H69 D5
CFG15 G70 CFG[14] RSVD_D5 D4
T46 TP@ CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
T47 TP@ CFG[16] RSVD_C2
T48 TP@ CFG17 F63 +1.8VALW
CFG[17] B3
CFG18 E66 RSVD_B3 A3
T49 TP@ CFG[18] RSVD_A3
T50 TP@ CFG19 F66
C
CFG[19] AW1 RSVD_U12 RC91 1 @ 2 0_0402_5% C
CFG_RCOMP E60 RSVD_AW1
CFG_RCOMP E1 RSVD_U11 RC92 1 @ 2 0_0402_5%
XDP_ITP_PMODE E8 RSVD_E1 E2
T51 TP@ ITP_PMODE RSVD_E2 2
@
AY2 BA4 CC92
AY1 RSVD_AY2 RSVD_BA4 BB4 1U_0402_6.3V6K
RSVD_AY1 RSVD_BB4 1
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69 +3VS
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 LPM_ZVM# 1 U23@ 2
C71 RSVD_AY3 RC93 10K_0402_5%
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
For 2+3e Solut i on
A52 RSVD_C54 D54 LPM_ZVM#
RSVD_A52 RSVD_D54 PM_MSM#
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56 LPM_ZVM#
B RSVD_J68 ZVM# LPM_ZVM# [63] B
F65 AW71
G65 VSS_F65 RSVD_TP AW70 42E_SOC_XTAL24_IN_R 1 2 42E_SOC_XTAL24_IN
VSS_G65 RSVD_TP RC94 EMI@ 33_0201_1%
F61 AP56 PM_MSM# T52 TP@
E61 RSVD_F61 MSM# C64 SKL_CNL# +1.0V_VCCST
RSVD_E61 PROC_SELECT# 42E_SOC_XTAL24_OUT_R 1 2 42E_SOC_XTAL24_OUT 1 2
19 OF 20 1 @ 2 RC95 EMI@ 33_0201_1% RC96 U42@ 1M_0402_5%
RC97 100K_0402_5%
1 2 CFG_RCOMP SKL-U_BGA1356
RC98 49.9_0402_1% @ YC3 U42@ SJ10000UJ00
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0 24MHZ_18PF_XRCGB24M000F2P51R0
1 2 CFG4
RC99 1K_0402_5% Stuff 100k(RC97) for Cannonlake. 3 1
3 1
NC NC

27P_0402_50V8J
CC93 U42@

27P_0402_50V8J
CC94 U42@
Un-stuff 100k(RC97) for Skylake 1 1
4 2

2 2
Display Port Presence Strap

1 : Disabled; No Physical Display Port

attached to Embedded Display Port
CFG4
0 : Enabled; An external Display Port device is
A connected to the Embedded Display Port A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(12/12)CFG,RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 17 of 66
5 4 3 2 1
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+DDR_VREF_CA +DDR_VREF_CA +DDR_VREF_CA

+DDR_VREF_CA

U2 U3 U4
U5
M1 G2 DDR_A_D5 M1 G2 DDR_A_D25 M1 G2 DDR_A_D40

0.047U_0402_25V7K

0.047U_0402_25V7K

0.047U_0402_25V7K
VREFCA DQL0 F7 DDR_A_D6 VREFCA DQL0 F7 DDR_A_D29 VREFCA DQL0 F7 DDR_A_D43 M1 G2 DDR_A_D56

0.047U_0402_25V7K
DQL1 H3 DDR_A_D1 DQL1 H3 DDR_A_D27 DQL1 H3 DDR_A_D44 VREFCA DQL0 F7 DDR_A_D58
DDR_A_MA0 P3 DQL2 H7 DDR_A_D2 DDR_A_MA0 P3 DQL2 H7 DDR_A_D26 DDR_A_MA0 P3 DQL2 H7 DDR_A_D42 DQL1 H3 DDR_A_D57
A0 DQL3 A0 DQL3 A0 DQL3 DQL2

1
DDR_A_MA1 P7 H2 DDR_A_D4 DDR_A_MA1 P7 H2 DDR_A_D24 DDR_A_MA1 P7 H2 DDR_A_D41 DDR_A_MA0 P3 H7 DDR_A_D59

CD1

CD2

CD3
A1 DQL4 A1 DQL4 A1 DQL4 A0 DQL3

1
DDR_A_MA2 R3 H8 DDR_A_D7 DDR_A_MA2 R3 H8 DDR_A_D31 DDR_A_MA2 R3 H8 DDR_A_D46 DDR_A_MA1 P7 H2 DDR_A_D61

CD4
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2 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D0 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D28 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D45 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D62

2
DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D3 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D30 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D47 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D60

2
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D63
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA7 R8 A6 A3 DDR_A_D13 DDR_A_MA7 R8 A6 A3 DDR_A_D16 DDR_A_MA7 R8 A6 A3 DDR_A_D37 DDR_A_MA6 P2 A5
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D14 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D18 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D39 DDR_A_MA7 R8 A6 A3 DDR_A_D52
D A8 DQU1 A8 DQU1 A8 DQU1 A7 DQU0 D
DDR_A_MA9 R7 C3 DDR_A_D9 DDR_A_MA9 R7 C3 DDR_A_D17 DDR_A_MA9 R7 C3 DDR_A_D32 DDR_A_MA8 R2 B8 DDR_A_D55
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D15 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D23 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D35 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D53
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D8 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D20 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D34 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D54
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D10 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D22 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D33 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D49
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D12 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D21 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D36 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D50
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D11 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D19 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D38 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D48
A14/WE DQU7 A14/WE DQU7 A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D51
DDR_A_BA0 N2 DDR_A_BA0 N2 DDR_A_BA0 N2 A14/WE DQU7
[7,18,20] DDR_A_BA0 DDR_A_BA1 BA0 [7,18,20] DDR_A_BA0 DDR_A_BA1 BA0 [7,18,20] DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA0
N8 B3 +1.2V N8 B3 +1.2V N8 B3 +1.2V N2 +1.2V
[7,18,20] DDR_A_BA1 BA1 VDD [7,18,20] DDR_A_BA1 BA1 VDD [7,18,20] DDR_A_BA1 BA1 VDD [7,18,20] DDR_A_BA0 DDR_A_BA1 BA0
B9 B9 B9 N8 B3
VDD VDD VDD [7,18,20] DDR_A_BA1 BA1 VDD
+1.2V E2 D1 +1.2V E2 D1 +1.2V E2 D1 B9
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E2 VDD D1
DML/DBIL VDD DML/DBIL VDD DML/DBIL VDD +1.2V DMU/DBIU VDD
J1 J1 J1 E7 G7
VDD J9 VDD J9 VDD J9 DML/DBIL VDD J1
VDD L1 VDD L1 VDD L1 VDD J9
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 VDD L1
[7,18] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD [7,18] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD [7,18] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD
K8 R1 K8 R1 K8 R1 K7 L9
[7,18] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD [7,18] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD [7,18] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD [7,18] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD
K2 T9 K2 T9 K2 T9 K8 R1
[7,18,20] DDR_A_CKE0 CKE VDD [7,18,20] DDR_A_CKE0 CKE VDD [7,18,20] DDR_A_CKE0 CKE VDD [7,18] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD
K2 T9
[7,18,20] DDR_A_CKE0 CKE VDD
A1 A1 A1
VDDQ A9 VDDQ A9 VDDQ A9 A1
VDDQ C1 VDDQ C1 VDDQ C1 VDDQ A9
VDDQ D9 VDDQ D9 VDDQ D9 VDDQ C1
VDDQ F2 VDDQ F2 VDDQ F2 VDDQ D9
VDDQ F8 VDDQ F8 VDDQ F8 VDDQ F2
DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 VDDQ F8
[7,20] DDR_A_ODT0 ODT VDDQ ODT VDDQ ODT VDDQ VDDQ
DDR_A_CS#0 L7 G9 DDR_A_CS#0 L7 G9 DDR_A_CS#0 L7 G9 DDR_A_ODT0 K3 G1
[7,18,20] DDR_A_CS#0 DDR_A_MA16 CS VDDQ [7,18,20] DDR_A_CS#0 DDR_A_MA16 CS VDDQ [7,18,20] DDR_A_CS#0 DDR_A_MA16 CS VDDQ DDR_A_CS#0 ODT VDDQ
L8 J2 L8 J2 L8 J2 L7 G9
DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ [7,18,20] DDR_A_CS#0 DDR_A_MA16 CS VDDQ
M8 J8 M8 J8 M8 J8 L8 J2
CAS VDDQ CAS VDDQ CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8
B2 B2 B2 CAS VDDQ
VSS E1 VSS E1 VSS E1 B2
VSS E9 VSS E9 VSS E9 VSS E1
VSS G8 VSS G8 VSS G8 VSS E9
DDR_A_DQS#1 A7 VSS K1 DDR_A_DQS#2 A7 VSS K1 DDR_A_DQS#4 A7 VSS K1 VSS G8
DDR_A_DQS1 B7 DQSU_c VSS K9 DDR_A_DQS2 B7 DQSU_c VSS K9 DDR_A_DQS4 B7 DQSU_c VSS K9 DDR_A_DQS#6 A7 VSS K1
DDR_A_DQS#0 F3 DQSU_t VSS M9 DDR_A_BG1_R DDR_A_DQS#3 F3 DQSU_t VSS M9 DDR_A_BG1_R DDR_A_DQS#5 F3 DQSU_t VSS M9 DDR_A_BG1_R DDR_A_DQS6 B7 DQSU_c VSS K9
DDR_A_DQS0 G3 DQSL_c VSS N1 DDR_A_DQS3 G3 DQSL_c VSS N1 DDR_A_DQS5 G3 DQSL_c VSS N1 DDR_A_DQS#7 F3 DQSU_t VSS M9 DDR_A_BG1_R
DQSL_t VSS T1 DQSL_t VSS T1 DQSL_t VSS T1 DDR_A_DQS7 G3 DQSL_c VSS N1
MEMRST# P1 VSS MEMRST# P1 VSS MEMRST# P1 VSS DQSL_t VSS T1
RESET RESET RESET MEMRST# P1 VSS
1 2 RD23 F9 1 2 RD22 F9 1 2 RD21 F9 RESET
240_0402_1% ZQ 240_0402_1% ZQ 240_0402_1% ZQ 1 2 RD20 F9
240_0402_1% ZQ
C C
1

1
M_A_ACT# L3 A2 X76@ X76@ M_A_ACT# L3 A2 M_A_ACT# L3 A2
[7,20] M_A_ACT# ACT VSSQ ACT VSSQ ACT VSSQ

1
DDR_A_BG0 M2 A8 RD29 RD35 DDR_A_BG0 M2 A8 X76@ X76@ DDR_A_BG0 M2 A8 X76@ X76@ M_A_ACT# L3 A2
[7,20] DDR_A_BG0 BG0 VSSQ BG0 VSSQ BG0 VSSQ ACT VSSQ

1
N9 C9 0_0402_5% 0_0402_5% N9 C9 RD30 RD36 N9 C9 RD31 RD37 DDR_A_BG0 M2 A8 X76@ X76@
DDR_A_ALERT# P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2 0_0402_5% 0_0402_5% DDR_A_ALERT# P9 TEN VSSQ D2 0_0402_5% 0_0402_5% N9 BG0 VSSQ C9 RD32 RD38
[7] DDR_A_ALERT# ALERT VSSQ ALERT VSSQ ALERT VSSQ TEN VSSQ
DDR_A_PARITY T3 D8 DDR_A_PARITY T3 D8 DDR_A_PARITY T3 D8 DDR_A_ALERT# P9 D2 0_0402_5% 0_0402_5%
[7,20] DDR_A_PARITY
2

PAR VSSQ E3 PAR VSSQ E3 PAR VSSQ E3 DDR_A_PARITY T3 ALERT VSSQ D8

2
T7 VSSQ E8 T7 VSSQ E8 T7 VSSQ E8 PAR VSSQ E3

2
B1 NC VSSQ F1 B1 NC VSSQ F1 B1 NC VSSQ F1 T7 VSSQ E8
+2.5V VPP VSSQ +2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ
R9 H1 R9 H1 R9 H1 +2.5V B1 F1
VPP VSSQ H9 VPP VSSQ H9 VPP VSSQ H9 R9 VPP VSSQ H1
96-BALL VSSQ 96-BALL VSSQ 96-BALL VSSQ VPP VSSQ H9
SDRAM DDR4 SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 SDRAM DDR4
X76@ X76@ X76@ K4A8G165WB-BCPB_FBGA96
X76@

[7,20] DDR_A_MA[0..16]

[7] DDR_A_DQS#[0..7]

[7] DDR_A_DQS[0..7]

[7] DDR_A_D[0..63] 0606 add Data mapping

CLOCK TERMINATION +0.6VS
X76@ U2 DQ U3 DQ U4 DQ U5 DQ
DDR_A_BG1 1 RD33 2 DDR_A_BG1_R
[7] DDR_A_BG1 DDR_A_BG1_R [20]
0_0402_5% DQL0 D3 DQL0 D19 DQL0 D35 DQL0 D51
DDR_A_CLK0 RD18 1 2 36_0402_1% DQL1 D1 DQL1 D17 DQL1 D33 DQL1 D49
DDR_A_CLK#0 RD19 1 2 36_0402_1%
DQL2 D2 DQL2 D18 DQL2 D34 DQL2 D50
DQL3 D0 DQL3 D16 DQL3 D32 DQL3 D48
+1.2V TABLE
DQL4 D7 DQL4 D23 DQL4 D39 DQL4 D55
SDP DDP DQL5 D5 DQL5 D21 DQL5 D37 DQL5 D53
B
DDR_A_ALERT#RD2 2 1 49.9_0402_1% DQL6 D6 DQL6 D22 DQL6 D38 DQL6 D54 B

INTEL suggest 50ohm 1% RD29 ASM NA

RD30 ASM NA DQL7 D4 DQL7 D20 DQL7 D36 DQL7 D52
RD31 ASM NA DQU0 D10 DQU0 D26 DQU0 D42 DQU0 D58
RD32 ASM NA
DQU1 D8 DQU1 D24 DQU1 D40 DQU1 D56
DQU2 D11 DQU2 D27 DQU2 D43 DQU2 D59
RD3
RD33 NA ASM
DQU3 D9 DQU3 D25 DQU3 D41 DQU3 D57
DDR_DRAMRST# 1 2 MEMRST#
[7,19] DDR_DRAMRST#
0_0402_5% DQU4 D14 DQU4 D30 DQU4 D46 DQU4 D62
RD34 NA ASM
1 DQU5 D13 DQU5 D29 DQU5 D45 DQU5 D61
CD5
0.1U_0201_10V6K DQU6 D15 DQU6 D31 DQU6 D47 DQU6 D63
@
2
RD35 0_5% 243_1% DQU7 D12 DQU7 D28 DQU7 D44 DQU7 D60
RD36 0_5% 243_1%
RD37 0_5% 243_1%
RD38 0_5% 243_1%

LOGIC
+1.2V
2

RD4
1.8K_0402_1%
RD5 +DDR_VREF_CA
2.7_0402_1%
1

2 1
[7] +0.6V_VREFCA
A A

1
CD6
0.022U_0402_16V7K
2
1

RD6 RD7
24.9_0402_1% 1.8K_0402_1%
2

LA-D301P
Security Classification Compal Secret Data
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 ON BOARD CHIPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 15, 2017 Sheet 18 of 66
5 4 3 2 1
 A B C D E

[7] DDR_B_DQS#[0..7]

[7] DDR_B_D[0..63]
+1.2V +1.2V
[7] DDR_B_DQS[0..7]
JDIMM2 ME@

[7] DDR_B_MA[0..16] DDR_B_D14

1
3 VSS1
DQ5
VSS2
DQ4
2
4 DDR_B_D11
Reverse Type
DDR_B_BA0 5 6
[7] DDR_B_BA0 DDR_B_BA1 DDR_B_D15 VSS3 VSS4 DDR_B_D10
7 8
[7] DDR_B_BA1 DDR_B_BG0 9 DQ1 DQ0 10
2-3A to 1 DIMMs/channel
[7] DDR_B_BG0 DDR_B_BG1 DDR_B_DQS#1 VSS5 VSS6
11 12
[7] DDR_B_BG1 DDR_B_DQS1 DQS0_c DM0_n/DBI0_n
13 14

Vinafix.com 15 DQS0_t VSS7 16 DDR_B_D8

DDR_B_D13 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D9 +1.2V
DDR_B_CLK0 DDR_B_D12 21 VSS10 DQ2 22
[7] DDR_B_CLK0 DDR_B_CLK#0 DQ3 VSS11 DDR_B_D4
23 24
[7] DDR_B_CLK#0 DDR_B_CLK1 DDR_B_D1 VSS12 DQ12
1 25 26 1
[7] DDR_B_CLK1 DDR_B_CLK#1 DQ13 VSS13 DDR_B_D0
27 28
[7] DDR_B_CLK#1 DDR_B_D5 VSS14 DQ8 +DIMM_VREF_DQ
29 30
31 DQ9 VSS15 32 DDR_B_DQS#0
VSS16 DQS1_c

2
DDR_B_CKE0 33 34 DDR_B_DQS0
[7] DDR_B_CKE0 DDR_B_CKE1 DM1_n/DBI_n DQS1_t
35 36 RD8
[7] DDR_B_CKE1 DDR_B_CS#0 DDR_B_D2 VSS17 VSS18 DDR_B_D6
37 38 1K_0402_1%
[7] DDR_B_CS#0 DDR_B_CS#1 DQ15 DQ14
39 40 RD9
[7] DDR_B_CS#1 DDR_B_D3 41 VSS19 VSS20 42 DDR_B_D7 20mil 2_0402_1%

1
43 DQ10 DQ11 44 2 1
SOC_SMBDATA DDR_B_D21 VSS21 VSS22 DDR_B_D20 [7] +0.6V_B_VREFDQ
45 46
[8] SOC_SMBDATA SOC_SMBCLK DQ21 DQ20
47 48
[8] SOC_SMBCLK DDR_B_D16 VSS23 VSS24 DDR_B_D17
49 50 1
51 DQ17 DQ16 52
DDR_B_ODT0 DDR_B_DQS#2 53 VSS25 VSS26 54 CD7
[7] DDR_B_ODT0 DDR_B_ODT1 DDR_B_DQS2 DQS2_c DM2_n/DBI2_n
55 56 0.022U_0402_16V7K
[7] DDR_B_ODT1 DQS2_t VSS27 DDR_B_D19 2
57 58
DDR_B_D23 59 VSS28 DQ22 60
DQ23 VSS29

2
61 62 DDR_B_D18
DDR_B_D22 63 VSS30 DQ18 64 RD10 RD11
Note: DQ19 VSS31 DDR_B_D28
Layout Note: 65 66 24.9_0402_1% 1K_0402_1%
Check voltage tolerance of DDR_B_D29 67 VSS32 DQ28 68
Place near JDIMM1 VREF_DQ at the DIMM socket 69 DQ29 VSS33 70 DDR_B_D24

1
DDR_B_D25 71 VSS34 DQ24 72
73 DQ25 VSS35 74 DDR_B_DQS#3
75 VSS36 DQS3_c 76 DDR_B_DQS3
77 DM3_n/DBI3_n DQS3_t 78
DDR_B_D30 79 VSS37 VSS38 80 DDR_B_D31
+1.2V 81 DQ30 DQ31 82
DDR_B_D26 83 VSS39 VSS40 84 DDR_B_D27
85 DQ26 DQ27 86
87 VSS41 VSS42 88
CB5/NC CB4/NC
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

89 90
91 VSS43 VSS44 92
1 1 1 1 1 1 1 1 CB1/NC CB0/NC
@ 93 94
VSS45 VSS46
CD8

CD9

CD10

CD11

CD12

CD13

CD14

CD15

1 2 95 96
1
RD25 2
240_0402_1% 97 DQS8_c DM8_n/DBI_n/NC 98
2 2 2 2 2 2 2 2 RD24 @ 240_0402_1% 99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
DDR_B_CKE0 109 VSS52 RESET_n 110 DDR_B_CKE1
4 as near side of the DIMM close to VDD pins CKE0 CKE1
111 112 1
DDR_B_BG1 113 VDD1 VDD2 114 CD80
2 +1.2V DDR_B_BG0 BG1 ACT_n M_B_ACT# [7] 2
115 116 0.1U_0201_10V6K
BG0 ALERT_n DDR_B_ALERT# [7]
117 118 @
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11 2
A12 A11
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_B_MA9 121 122 DDR_B_MA7

123 A9 A7 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
1 1 1 1 1 1 1 1 A6 A4
CD17

CD18

CD19

CD20

CD21

CD22

CD23

CD24

129 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134
2 2 2 2 2 2 2 2 135 A1 EVENT_n/NF 136
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
DDR_B_CLK#0 139 CK0_t CK1_t/NF 140 DDR_B_CLK#1
141 CK0_c CK1_c/NF 142
143 VDD11 VDD12 144 DDR_B_MA0
[7] DDR_B_PARITY PARITY A0

DDR_B_BA1 145 146 DDR_B_MA10

147 BA1 A10/AP 148
DDR_B_CS#0 149 VDD13 VDD14 150 DDR_B_BA0
DDR_B_MA14 151 CS0_n BA0 152 DDR_B_MA16
153 WE_n/A14 RAS_n/A16 154 +DIMM_VREF_DQ
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15 RD15
DDR_B_CS#1 157 ODT0 CAS_n/A15 158 DDR_B_MA13 DDR_DRAMRST#_R 1 2
CS1_n A13 DDR_DRAMRST# [7,18]
159 160 0_0402_5%
DDR_B_ODT1 161 VDD17 VDD18 162
163 ODT1 C0/CS2_n/NC 164
165 VDD19 VREFCA 166
Place these caps on the VTT plane close to DIMM 167 C1, CS3_n,NC SA2 168
0309 change 0ohm
DDR_B_D37 169 VSS53 VSS54 170 DDR_B_D36
171 DQ37 DQ36 172
+0.6VS DDR_B_D33 173 VSS55 VSS56 174 DDR_B_D32
175 DQ33 DQ32 176
DDR_B_DQS#4 177 VSS57 VSS58 178
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180
181 DQS4_t VSS59 182 DDR_B_D39
VSS60 DQ39
10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1 DDR_B_D38 183 184

DQ38 VSS61
CD29

CD30

10P_0402_25V8J

CD25 CD26 CD27 CD28 185 186 DDR_B_D35

CD81 DDR_B_D34 187 VSS62 DQ35 188
DQ34 VSS63
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

@RF@ 189 190 DDR_B_D44

2 2 2 2 2 2 2 DDR_B_D41 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D45
3 3
DDR_B_D40 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_B_DQS#5
199 VSS68 DQS5_c 200 DDR_B_DQS5
201 DM5_n/DBI5_n DQS5_t 202
DDR_B_D43 203 VSS69 VSS70 204 DDR_B_D47
205 DQ46 DQ47 206
DDR_B_D42 207 VSS71 VSS72 208 DDR_B_D46
209 DQ42 DQ43 210
DDR_B_D52 211 VSS73 VSS74 212 DDR_B_D53
213 DQ52 DQ53 214
DDR_B_D49 215 VSS75 VSS76 216 DDR_B_D48
217 DQ49 DQ48 218
DDR_B_DQS#6 219 VSS77 VSS78 220
DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222
223 DQS6_t VSS79 224 DDR_B_D54
DDR_B_D55 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_B_D51
+2.5V DDR_B_D50 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_B_D60
DDR_B_D61 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_B_D57
DDR_B_D56 237 VSS86 DQ57 238 +3VS
239 DQ56 VSS87 240 DDR_B_DQS#7
+2.5V 241 VSS88 DQS7_c 242 DDR_B_DQS7 +0.6VS
+3VS 243 DM7_n/DBI7_n DQS7_t 244
DDR_B_D59 245 VSS89 VSS90 246 DDR_B_D63
DQ62 DQ63
10U_0603_6.3V6M

1 1 1 247 248
VSS91 VSS92

2
10P_0402_25V8J

CD55 CD32 DDR_B_D58 249 250 DDR_B_D62

CD82 251 DQ58 DQ59 252 RD27
VSS93 VSS94
1U_0402_6.3V6K

@RF@ SOC_SMBCLK 253 254 SOC_SMBDATA 10K_0402_5%

2 2 2 255 SCL SDA 256
257 VDDSPD SA0 258

1
259 VPP1 VTT 260
VPP2 SA1
1 1

1
CD31
CD54 0.1U_0201_10V6K 261 RD26
2.2U_0402_6.3V6M GND1 262
GND2 0_0402_5%
2 2
@

2
DEREN_40-42272-26001RHF

close to DIMM
4 4

JDIMM Connector PN
SP07001GK00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_DIMM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 19 of 66
A B C D E
 5 4 3 2 1

[7,18] DDR_A_MA[0..16]

+0.6VS

Vinafix.com RP1
D
DDR_A_MA1 1 8 D
DDR_A_MA5 2 7
DDR_A_MA7 3 6
DDR_A_MA9 4 5
+1.2V
36_0804_8P4R_5%

CD56

CD57

CD58

CD59

CD60

CD61

CD62

CD33

CD34

CD35

CD36

CD37

CD38

CD39

CD40

CD41
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RP2
DDR_A_MA13 1 8
DDR_A_MA8 2 7
DDR_A_PARITY 3 6
[7,18] DDR_A_PARITY
DDR_A_MA11 4 5

36_0804_8P4R_5%
4 as near each on board RAM device as possible

RP3
DDR_A_CKE0 1 8
[7,18] DDR_A_CKE0 DDR_A_MA16 2 7
Follow MA51 [7,18] DDR_A_ODT0
DDR_A_ODT0 3 6
M_A_ACT# 4 5
[7,18] M_A_ACT#

1 36_0804_8P4R_5%
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1
CD42

CD43

CD44

CD45

CD46
+ CD63
330U_D2_2V_Y
@ SGA00009S00
2 2 2 2 2 2
330U 2V H1.9 DDR_A_MA2 1 2
9mohm POLY RD28 36_0201_1%

DDR_A_BG1_R 1 2
[18] DDR_A_BG1_R
RD34 X76@ 36_0201_1%

RP5
DDR_A_BG0 1 8
C [7,18] DDR_A_BG0 C
DDR_A_MA10 2 7
DDR_A_MA3 3 6
DDR_A_BA1 4 5
[7,18] DDR_A_BA1
36_0804_8P4R_5%

RP6
DDR_A_MA14 1 8
DDR_A_CS#0 2 7
[7,18] DDR_A_CS#0 DDR_A_MA15 3 6
DDR_A_MA12 4 5
+2.5V +0.6VS
36_0804_8P4R_5%
CD64

CD65

CD66

CD67

CD68

CD69

CD70

CD71

CD79

CD78

CD77

CD76

CD75

CD74

CD73

CD72
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RP7
DDR_A_MA4 1 8
DDR_A_BA0 2 7
[7,18] DDR_A_BA0 DDR_A_MA0 3 6
2 as near each on board RAM device as possible DDR_A_MA6 4 5
2 as near each on board RAM device as possible
36_0804_8P4R_5%
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1
CD47

10U_0402_6.3V6M

CD48

10U_0402_6.3V6M

CD49

CD50

CD51

CD52

CD53

B B
2 2 2 2 2 2 2
@ @

A A

LA-D301P
Security Classification Compal Secret Data
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 ON BOARD CHIPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 15, 2017 Sheet 20 of 66
5 4 3 2 1
 1 2 3 4 5

Vinafix.com No Use GPU Display Port outpud

UV1A @
A A

UV1F @
+VGA_CORE

AF30 AH30 PCIE_CRX_C_GTX_P1 CV1 1 2 DIS@ 0.22U_0402_6.3V6K PCIE_CRX_GTX_P1 [12] AB11

[12] PCIE_CTX_C_GRX_P1 PCIE_RX0P PCIE_TX0P VARY_BL
AE31 AG31 PCIE_CRX_C_GTX_N1 CV3 1 2 DIS@ 0.22U_0402_6.3V6K PCIE_CRX_GTX_N1 [12] AB12
[12] PCIE_CTX_C_GRX_N1 PCIE_RX0N PCIE_TX0N DIGON

AE29 AG29 PCIE_CRX_C_GTX_P2 CV4 1 2 DIS@ 0.22U_0402_6.3V6K PCIE_CRX_GTX_P2 [12]

[12] PCIE_CTX_C_GRX_P2 PCIE_RX1P PCIE_TX1P
AD28 AF28 PCIE_CRX_C_GTX_N2 CV2 1 2 DIS@ 0.22U_0402_6.3V6K PCIE_CRX_GTX_N2 [12]
[12] PCIE_CTX_C_GRX_N2 PCIE_RX1N PCIE_TX1N AL15
TXCAP_DPA3P AK14
AD30 AF27 PCIE_CRX_C_GTX_P3 CV5 1 2 DIS@ 0.22U_0402_6.3V6K TXCAM_DPA3N
[12] PCIE_CTX_C_GRX_P3 PCIE_RX2P PCIE_TX2P PCIE_CRX_GTX_P3 [12]
AC31 AF26 PCIE_CRX_C_GTX_N3 CV6 1 2 DIS@ 0.22U_0402_6.3V6K PCIE_CRX_GTX_N3 [12] AH16
[12] PCIE_CTX_C_GRX_N3 PCIE_RX2N PCIE_TX2N TX0P_DPA2P AJ15
TX0M_DPA2N
AC29 AD27 PCIE_CRX_C_GTX_P4 CV7 1 2 DIS@ 0.22U_0402_6.3V6K PCIE_CRX_GTX_P4 [12] AL17
[12] PCIE_CTX_C_GRX_P4 PCIE_RX3P PCIE_TX3P TX1P_DPA1P
AB28 AD26 PCIE_CRX_C_GTX_N4 CV8 1 2 DIS@ 0.22U_0402_6.3V6K PCIE_CRX_GTX_N4 [12] AK16
[12] PCIE_CTX_C_GRX_N4 PCIE_RX3N PCIE_TX3N TX1M_DPA1N
AH18
AB30 AC25 TX2P_DPA0P AJ17
AA31 PCIE_RX4P PCIE_TX4P AB25 TX2M_DPA0N
PCIE_RX4N PCIE_TX4N AL19
NC_TXOUT_L3P AK18
AA29 Y23 NC_TXOUT_L3N
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N TMDP

Y30 AB27 AH20

W31 PCIE_RX6P PCIE_TX6P AB26 TXCBP_DPB3P AJ19
PCIE_RX6N PCIE_TX6N TXCBM_DPB3N
AL21
W29 Y27 TX3P_DPB2P AK20
B
V28 PCIE_RX7P PCIE_TX7P Y26 TX3M_DPB2N B
PCIE_RX7N PCIE_TX7N AH22
TX4P_DPB1P AJ21
V30 W24 TX4M_DPB1N
U31 NC#V30 NC#W24 W23 AL23
NC#U31 NC#W23 TX5P_DPB0P AK22
TX5M_DPB0N
U29 V27 AK24
T28 NC#U29 NC#V27 U26 NC_TXOUT_U3P AJ23
NC#T28 NC#U26 NC_TXOUT_U3N

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
2160856030-A0_FCBGA631

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23

N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23

L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
C C

CLOCK
[10] CLK_PCIE_GPU CLK_PCIE_GPU AK30
CLK_PCIE_GPU# AK32 PCIE_REFCLKP
[10] CLK_PCIE_GPU# PCIE_REFCLKN +PCIE_VGS
+3VGS
CALIBRATION
Y22 RV1 1 DIS@ 2 1.69K_0402_1%
UV3 PCIE_CALR_TX
DIS@ RV2 1 DIS@ 2 1K_0402_1% N10 AA22 RV3 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
5

PCIRST# 1
P

[10,27,31,32,36,45] PCIRST# IN1 4 PLT_RST_VGA# AL27

DGPU_HOLD_RST# 2 O PERSTB
[11] DGPU_HOLD_RST# IN2
G

2160856030-A0_FCBGA631
3

RV4
MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
DIS@
2

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2016/12/05 Deciphered Date 2017/12/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M30/M70_PCIE/DP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-E981P
Thursday, June 15, 2017 Sheet 21 of 66
1 2 3 4 5
 1 2 3 4 5

Resistor Divider Lookup Lable

UV1B @ +1.8VGS
0402 1% resistors are equired PS_0[3:1]=001 Strap Name :
R_pu (ohm) R_pd (ohm) Bitd [3:1] PS_0[5:4]=11

1
AF2
PS_0[1] ROM_CONFIG[0]
NC#AF2 AF4 RV5
+3VGS NC#AF4 NC 4.75k 000 8.45K_0402_1%
PS_0[2] ROM_CONFIG[1]
@ 1 N9 AG3 8.45k 2k 001 DIS@ PS_0[3] ROM_CONFIG[2]
T56

2
@ 1 L9 DBG_DATA16 NC#AG3 AG5 PS_0
T57 DBG_DATA15 NC#AG5
@ 1 AE9 DPA 4.53k 2k 010 PS_0[4] N/A
Vinafix.com
T58 DBG_DATA14

1
0.68U_0402_10V
@ 1 Y11 AH3 1
T53 DBG_DATA13 NC#AH3

1
@ 1 AE8 AH1 6.98k 4.99k 011 PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
T59 DBG_DATA12 NC#AH1
DIS@ DIS@ @ 1 AD9 CV9 RV8
T60 DBG_DATA11

2
RV6 RV7 @ 1 AC10 AK3 4.53k 4.99k 100 @ 2K_0402_1%

G
T61 DBG_DATA10 NC#AK3 2
QV1A 47K_0402_5% 47K_0402_5% @ 1 AD7 AK1 DIS@
T62

2
DIS@ @ 1 AC8 DBG_DATA9 NC#AK1
A
T63 DVO 3.24k 5.62k 101 A

2
@ 1 AC7 DBG_DATA8 AK5
VGA_SMB_DA3 T64 DBG_DATA7 NC#AK5
6 1 @ 1 AB9 AM3 3.4k 10k 110

S
[8,39,45,46] SOC_SML1DATA T65 DBG_DATA6 NC#AM3
@ 1 AB8

D
T54 DBG_DATA5
@ 1 AB7 AK6 4.75k NC 111
T55 DBG_DATA4 NC#AK6

5
L2N7002DW1T1G 2N SOT-363 @ 1 AB4 AM5
change to support gen3 11/24

G
T66 DBG_DATA3 NC#AM5
QV1B @ 1 AB2 DPB
T67 DBG_DATA2
DIS@ @ 1 Y8 AJ7 Strap Name :
T68 DBG_DATA1 NC#AJ7 +1.8VGS
@ 1 Y7 AH6 PS_1[3:1]=001
VGA_SMB_CK3 T69 DBG_DATA0 NC#AH6
3 4 Capacitor Divider Lookup Lable

S
[8,39,45,46] SOC_SML1CLK
AK8

D
NC#AK8 PS_1[5:4]=11 PS_1[1] STRAP_BIF_GEN3_EN_A

1
+1.8VGS AL7
L2N7002DW1T1G 2N SOT-363 NC#AL7 DIS@
Cap (nF) Bitd [5:4] RV9
PS_1[2] TRAP_BIF_CLK_PM_EN
W6 8.45K_0402_1% PS_1[3] N/A
V6 NC#W6
680nF 00

2
NC#V6 V4 PS_1
AC6 NC#V4 U5
PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
NC#AC5 NC#U5 82nF 01

1
0.68U_0402_10V
AC5 1 PS_1[5] STRAP_TX_DEEMPH_EN
RV10 RV11 NC#AC6 W3 DIS@
4.7K_0402_5% 4.7K_0402_5% AA5 NC#W3 V2
10nF 10 CV10 RV12
DIS@ DIS@ AA6 NC#AA5 NC#V2 @ 2K_0402_1%
NC#AA6 DPC
Y4
NC 11 2

2
+1.8VGS NC#Y4 W5
NC#W5
BP_0 U1 AA3 PLL_Analog_out
RV13 @ @ 1FB_VDDCI W1 NC#U1 NC#AA3 Y2
T70 NC#W1 NC#Y2

1
2 1 GPIO19_CTF BP_1 U3
Y6 NC#U3 J8 RV14
10K_0402_5% @ 1PLL_Analog_in AA1 NC#Y6 NC#J8 16.2K_0402_1% +1.8VGS
T71 NC#AA1 PS_2[3:1]=000 Strap Name :
2

DIS@
RV15 PS_2[5:4]=11

1
10K_0402_5% PS_2[1] N/A
DIS@ @
I2C RV16 PS_2[2] N/A
1

8.45K_0402_1%
@ 1 R1 PS_2[3] STRAP_BIOS_ROM_EN
T72

2
@ 1 R3 SCL PS_2
+3VGS T73 SDA
PS_2[4] STRAP_BIF_VGA_DIS

1
0.082U_0402_16V
AM26 1
+VGA_CORE R AK26
1 @ 2 U6
GENERAL PURPOSE I/O AVSSN#AK26 +3VGS CV11 RV17
PS_2[5] N/A
RV18 5.11K_0402_5% U10 GPIO_0 AL25 @ 4.75K_0402_1%
T10 GPIO_1 G AJ25 2 DIS@

2
GPIO_2 AVSSN#AJ25

1
1 DIS@ 2 TESTEN VGA_SMB_DA3 U8
B
RV19 1K_0402_5% VGA_SMB_CK3 U7 SMBDATA AH24 RV20 B
DV1 1 2 GPU_GPIO5# T9 SMBCLK B AG25 4.7K_0402_5%
[45] GPU_PROHOT# PCC_GPIO_6 GPIO_5_AC_BATT AVSSN#AG25
T8 @
RB751V_SOD323 T7 GPIO_6 DAC1 AH26

2
DIS@ P10 GPIO_7_BLON HSYNC AJ27 WAKEB
+3VGS P4 GPIO_8_ROMSO VSYNC
GPIO_9_ROMSI

1
P2 +1.8VGS
N6 GPIO_10_ROMSCK AD22 RV21
PS_3[3:1]=000 Strap Name :
1 8 JTAG_TDI_GPU +VGA_CORE N5 GPIO_11 RSET 4.7K_0402_5%
GPIO_12 PS_3[5:4]=11

1
2 7 JTAG_TMS_GPU N3 AG24 DIS@
3 6 JTAG_TCK Y9 GPIO_13 AVDD AE22 X76@
PS_3[1] BOARD_CONFIG[0] (Memory ID)
VRAM Type

2
4 5 JTAG_TRSTB GPU_SVD_R N1 GPIO_14_HPD2 AVSSQ RV22
GPIO_15_PWRCNTL_0 PS_3[2] BOARD_CONFIG[1] (Memory ID)
RPV1 10K_8P4R_5%
GPU_SVD RV23 1 @ 2 0_0402_5% GPU_SVD_R M4
R6 GPIO_16 VDD1DI
AE23
AD23
8.45K_0402_1% Need reference
PS_3[3] BOARD_CONFIG[2] (Memory ID) X76 Schemat i c

2
GPU_SVC RV24 1 @ 2 0_0402_5% GPU_SVC_R W10 GPIO_17_THERMAL_INT VSS1DI PS_3
@ GPIO_18
GPIO19_CTF M2
GPIO_19_CTF FutureASIC/SEYMOUR/PARK PS_3[4] AUD_PORT_CONN_PINSTRAP[1]

1
0.68U_0402_10V
2 1 JTAG_TDO_GPU M1-30/M1-70 colay level circuit GPU_SVC_R P8 AM12 1
P7 GPIO_20_PWRCNTL_1 CEC_1 X76@
RV25 @ 10K_0402_5%
M1-30 must implemented count N8 GPIO_21 CV12 RV27
PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
AK10 GPIO_22_ROMCSB AK12 DIS@ 1 RV26 2 0_0402_5% GPU_SVD @ 4.75K_0402_1%
AM10 GPIO_29 RSVD#AK12 AL11 DIS@ 1 RV28 2 0_0402_5% GPU_SVT GPU_SVD [57] 2 SD034475180

2
+3VGS N7 GPIO_30 RSVD#AL11 AJ11 DIS@ 1 RV29 2 0_0402_5% GPU_SVC GPU_SVT [57]
0608 change [10] GPUCLK_REQ# CLKREQB RSVD#AJ11 GPU_SVC [57]
DIS@ JTAG_TRSTB L6
2 RV72 1 GPU_GPIO5# JTAG_TDI_GPU L5 JTAG_TRSTB
GPU_GPIO5# [64] JTAG_TCK JTAG_TDI
10K_0402_5% L3
JTAG_TMS_GPU L1 JTAG_TCK AL13
JTAG_TDO_GPU K4 JTAG_TMS GENLK_CLK AJ13
TESTEN K7 JTAG_TDO GENLK_VSYNC
AF24 TESTEN
+VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
27MMHz CRYSTAL AB13
W8 GENERICA
SWAPLOCKB

W9 GENERICB
W7 GENERICC AC19 PS_0
RV30 DIS@ AD10 GENERICD PS_0
1M_0402_5% AJ9 GENERICE AD19 PS_1
XTALOUT XTALIN T74 1 AL9 NC#AJ9 PS_1
@ NC#AL9 AE17 PS_2
YV1 SJ10000UI00 AC14 PS_2
27MHZ_10PF_XRCGB27M000F2P18R0 @ 1 PX_EN AB16 HPD1 AE20 PS_3
T75 PX_EN PS_3
1 3
1 3 AE19
C 1 1 C
0612 change DIS@ NC NC DIS@ AC16 TS_A
CV13 DIS@ CV14 DBG_VREFG
12P_0402_50V8J 2 4 12P_0402_50V8J
2 2
DDC/AUX
AE6
PLL/CLOCK DDC1CLK AE5
DDC1DATA
AD2
AUX1P AD4 +VGA_CORE
AUX1N
AC11
DDC2CLK AC13 +1.8VGS
DDC2DATA
XTALIN AM28 AD13
XTALOUT AK28 XTALIN AUX2P AD11
XTALOUT AUX2N
RV31 1 DIS@ 2 10K_0402_5% AC22 AD20 VSSSENSE_VGA
XO_IN NC#AD20

2
RV32 1 DIS@ 2 10K_0402_5% AB22 AC20 VCCSENSE_VGA VSSSENSE_VGA [57]
XO_IN2 NC#AC20 VCCSENSE_VGA [57] RV33 RV34
AE16 10K_0402_5% 10K_0402_5%
NC#AE16 AD16 DIS@ @
+3VGS NC#AD16

1
SEYMOUR/FutureASIC AC1
+1.8VGS T4 DDCVGACLK AC3
DPLUS DDCVGADATA
2

LV1 DIS@ T2 THERMAL GPU_SVD

@ 1 2 13mA DMINUS GPU_SVC
RV35 BLM15BD121SN1D_0402
10K_0402_5% DIS@ GPIO28 R5
CV15 2 1 10U_0603_6.3V6M +TSVDD AD17 GPIO28_FDO Boot-VID Code
1

TSVDD

2
DIS@ AC17
PCC_GPIO_6 1 2 GPU_VRHOT# CV16 2 1 1U_0402_6.3V4Z TSVSS Voltage RV37 RV38
2 RV36 @ 1K_0402_1% GPU_VRHOT# [57] DIS@ SVC SVD Selected (V) 10K_0402_5% 10K_0402_5%
CV17 2 1 0.1U_0201_10V6K @ DIS@
@ 2160856030-A0_FCBGA631

1
CV123 RV39 1 @ 2 10K_0402_5%
0.1U_0402_10V7K 1 0 0 1.1
Peak Current Control (Reversed) Enable MLPS
Conf i r m wit h A MD 0 1 1.0
1 0 0.9
1 1 0.8
D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2016/12/05 Deciphered Date 2017/12/05 M30/M70_MSIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-E981P
Thursday, June 15, 2017 Sheet 22 of 66
1 2 3 4 5
 5 4 3 2 1

+1.8VALW TO +1.8VGS
+1.0VALW TO +PCIE_VGS
Load switch
Vinafix.com UV1E @

D D
AA27 A3
AB24 GND GND A30
No Use GPU Display Port outpud AB32 GND GND AA13
+1.8VGS AC24 GND GND AA16
+1.8VALW AC26 GND GND AB10
+DP_VDDR GND GND
UV1G @ AC27 AB15
AD25 GND GND AB6
GND GND

CV19

CV20
DP POWER NC/DP POWER AD32 AC9
AE27 GND GND AD6
1 1
1U_0402_6.3V6K

GND GND
CV18

1 AG15 AE11 AF32 AD8

@ @ AG16 DP_VDDR#AG15 NC#AE11 AF11 AG27 GND GND AE7
DP_VDDR#AG16 NC#AF11 GND GND

10U_0603_6.3V6M
@ AF16 AE13 AH32 AG12

1U_0402_6.3V4Z
R_short +1.8VGS 2 2 AG17 DP_VDDR#AF16
DP_VDDR#AG17
NC#AE13
NC#AF13
AF13 K28 GND
GND
GND
GND
AH10
2 UV10 DIS@ AG18 AG8 K32 AH28
1 14 +1.8VGS_LS 2 DIS@ 1 AG19 DP_VDDR#AG18 NC#AG8 AG10 L27 GND GND B10
2 VIN1 VOUT1 13 RV41 0_0603_5% AF14 DP_VDDR#AG19 NC#AG10 M32 GND GND B12
DIS@ VIN1 VOUT1 DP_VDDR#AF14 N25 GND GND B14
GND GND

2
DGPU_PWR_EN 2 1 DGPU_PWR_EN_R 3 12 @ 1 2 DIS@ N27 B16
ON1 CT1 2200P_0402_50V7K CV22 CV21 P25 GND GND B18
RV40 GND GND
+5VALW 4 11 0.1U_0201_10V7K P32 B20

1
47.5K_0402_1% VBIAS GND GND GND
0.1U_0201_10V K X5R

AG20 AF6 R27 B22

5 10 @ 1 2 AG21 DP_VDDC#AG20 NC#AF6 AF7 T25 GND GND B24
1 ON2 CT2 DP_VDDC#AG21 NC#AF7 GND GND
2200P_0402_50V7K CV24 +PCIE_VGS +PCIE_VGS AF22 AF8 T32 B26
DIS@ +1.0VALW DP_VDDC#AF22 NC#AF8 GND GND
CV23

6 9 +DP_VDDC AG22 AF9 U25 B6

7 VIN2 VOUT2 8 +PCIE_VGS_LS 2 DIS@ 1 AD14 DP_VDDC#AG22 NC#AF9 U27 GND GND B8
2 VIN2 VOUT2 RV42 0_0603_5% DP_VDDC#AD14 V32 GND GND C1
GND GND

CV26

CV27
15 W25 C32
GPAD 280mA GND GND

2
DIS@ W26 E28
EM5209VF_DFN14_3X2 R_short CV25
1 1
AG14 AE1 W27 GND GND F10
1U_0402_6.3V6K

DP_VSSR NC#AE1 GND GND

CV28

0.1U_0201_10V7K @ @ AH14 AE3 Y25 F12

1
DP_VSSR NC#AE3 GND GND

10U_0603_6.3V6M
AM14 AG1 Y32 F14

1U_0402_6.3V4Z
1 2 2 DP_VSSR NC#AG1 GND GND
AM16 AG6 F16
@ AM18 DP_VSSR NC#AG6 AH5 GND F18
AF23 DP_VSSR NC#AH5 AF10 GND F2
C 2 AG23 DP_VSSR NC#AF10 AG9 GND F20 C
AM20 DP_VSSR NC#AG9 AH8 M6 GND F22
AM22 DP_VSSR NC#AH8 AM6 N13 GND GND F24
AM24 DP_VSSR NC#AM6 AM8 N16 GND GND F26
AF19 DP_VSSR NC#AM8 AG7 N18 GND GND F6
AF20 DP_VSSR NC#AG7 AG11 N21 GND GND
GND F8
AE14 DP_VSSR NC#AG11 P6 GND GND G10
DP_VSSR P9 GND GND G27
R12 GND GND G31
R15 GND GND G8
AF17 AE10 R17 GND GND H14
DPAB_CALR NC#AE10 R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
T18 GND GND H6
2160856030-A0_FCBGA631 T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND

+3VALW to +3VGS V16

V18
GND
GND
GND
Y10
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
GND VSS_MECH TP@ T216
T11 AM1 TP@ T217
AA11 GND VSS_MECH AM32
GND VSS_MECH TP@ T218
M12
+3VALW DIS@ +3VGS N11 GND
V11 GND
GND
B B
S

3 1
2160856030-A0_FCBGA631
1
4.7U_0603_6.3V6K

1U_0402_6.3V6K

@
CV29 DIS@

1 1
QV2 RV43
G
2

CV30

ME2301DC-G_SOT23-3 680_0603_5%
SB000013I00 @
3VGS_EN#

2 2
2

+5VALW
QV3 @
1

D L2N7002WT1G 1N SC-70-3
2
DIS@ G
RV44 DIS@ DGPU_PWR_EN# 1 2 S
3

RV45 10K_0402_5%
20K_0402_5%
+1.8VGS +PCIE_VGS
1

D
1 DIS@
+VGA_CORE
2
[11,45,57,58] DGPU_PWR_EN

2
G CV31
0.1U_0201_10V7K

2
DIS@ QV4 S RV47 RV48
3

L2N7002WT1G 1N SC-70-3 2 RV46 470_0603_5% 470_0603_5%

470_0603_5% @ @
DIS@

1
1

3
DGPU_PWR_EN# D D
[44] DGPU_PWR_EN#

1
D DGPU_PWR_EN# DGPU_PWR_EN#
2 5
DGPU_PWR_EN# 2 G G
G
DIS@ QV5 S S QV6A @ S QV6B @

4
L2N7002WT1G 1N SC-70-3 L2N7002DW1T1G 2N SOT-363 L2N7002DW1T1G 2N SOT-363

A A

Title
<Title>

Size Document Number Rev

CustomLA-E981P 0.1

Date: Thursday, June 15, 2017 Sheet 23 of 66

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D
+VGA_CORE 10uF 1uF 0.1uF D

VDDC 4 30 0
VDDC and VDDCI TDC 28A UV1D @ +1.8VGS
+1.35VS_VRAM 100mA
AM30 +PCIE_PVDD
VDDCI 1 3 3 2A PCIE_PVDD

PCIE
MEM I/O

10U_0603_6.3V6M CV37

1U_0402_6.3V4Z CV45

0.1U_0201_10V6K CV46

0.01U_0402_16V7K CV47
H13 AB23 1 1 1 1
H16 VDDR1 NC#AB23 AC23
VDDR1 NC#AC23

CV32

CV38

CV39

CV40

CV41

CV42

CV43

CV44

CV48

CV33

CV49

CV50

CV51

CV52

CV34

CV35

CV36

CV53
H19 AD24 DIS@ DIS@ DIS@ DIS@
J10 VDDR1 NC#AD24 AE24
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDR1 NC#AE24 2 2 2 2
J23 AE25
+PCIE_VGS 10uF 1uF 0.1uF DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ J24 VDDR1 NC#AE25 AE26
VDDR1 NC#AE26

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
J9 AF25
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 K10 VDDR1 NC#AF25 AG26
K23 VDDR1 NC#AG26
PCIE_VDDC 2A 2 7 0 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25 +PCIE_VGS
BIF_VDDC 0.8A 1 2 0 L13 VDDR1 PCIE_VDDC L26 1A
L20 VDDR1 PCIE_VDDC M22
VDDR1 PCIE_VDDC

CV54

CV55

CV56

CV57

CV58

CV59

CV60

CV61

CV62
L21 N22
L22 VDDR1 PCIE_VDDC N23
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC N24
1 1 1 1 1 1 1 1 1
PCIE_VDDC R22 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
PCIE_VDDC

10U_0603_6.3V6M

10U_0603_6.3V6M
T22

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
+1.8VGS 13mA LEVEL PCIE_VDDC U22 2 2 2 2 2 2 2 2 2
LV2 DIS@ TRANSLATION PCIE_VDDC V22
1 2 +VDD_CT AA20 PCIE_VDDC
+1.35V_MEM_GFX 10uF 2.2uF 0.1uF 0.01uF BLM15BD121SN1D_0402 AA21 VDD_CT
VDD_CT

CV63

CV64

CV65
AB20 AA15
C
AB21 VDD_CT CORE VDDC N15 C
1 1 1 VDD_CT VDDC N17
VDDR1 2A 3 5 5 5 DIS@ DIS@ DIS@ +3VGS VDDC R13
25mA I/O VDDC

10U_0603_6.3V6M

0.1U_0201_10V6K
LV3 DIS@ R16

1U_0402_6.3V4Z
2 2 2 1 2 +VDDR3 AA17 VDDC R18
BLM15BD121SN1D_0402 AA18 VDDR3 VDDC Y21
VDDR3 VDDC

CV66

CV67

CV68

CV69
AB17 T12
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VGS 10uF 1uF 0.1uF 0.01uF 1 1 1 1 VDDR3 VDDC T17
DIS@ DIS@ DIS@ DIS@ V12 VDDC T20
VDDR4 VDDC

10U_0603_6.3V6M
Y12 U13

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 1 1 VDDR4 VDDC U18
VDDC
VDDC
V21
V15
VGA_CORE Caps in power side sheet
VDDC V17
MPLL_PVDD 90mA 1 1 1 VDDC V20
0 VDDC

POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
0 VDDC M11
VDDC N12
VDDC U11
VDD_CT 13mA 1 1 CIS SYMBOL VDDC
1 0 +1.8VGS
LV4 DIS@ 90mA PLL
1 2 +MPLL_PVDD
+DP_VDDR 40mA 1(@) 1(@) 1(@)
CV70

CV71

CV72

BLM15BD221SN1D_2P
0 1 1 1
R21 0.8A
DIS@ DIS@ DIS@ BIF_VDDC U21 +BIF_VDDC
+DP_VDDC 1(@) 1(@) 1(@) 0 BIF_VDDC
10U_0603_6.3V6M

0.1U_0201_10V6K
1U_0402_6.3V4Z

2 2 2 L8
+1.8VGS MPLL_PVDD
B
LV5 DIS@ 75mA ISOLATED
+VGA_CORE
B

1 2 +SPLL_PVDD CORE I/O

CV73

CV74

BLM15BD121SN1D_0402 CV75 M13

H7 VDDCI M15
1 1 1 SPLL_PVDD VDDCI M16
DIS@ DIS@ DIS@ VDDCI M17
+PCIE_VGS VDDCI
VGA_CORE Caps in power side sheet
10U_0603_6.3V6M

0.1U_0201_10V6K

M18
1U_0402_6.3V4Z

2 2 2 LV6 DIS@ 100mA VDDCI M20

1 2 +SPLL_VDDC H8 VDDCI M21
SPLL_VDDC VDDCI

CV76

CV77

CV78
BLM15BD121SN1D_0402 N20
J7 VDDCI
+3VGS 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
DIS@ DIS@ DIS@

10U_0603_6.3V6M

0.1U_0201_10V6K
1U_0402_6.3V4Z
2 2 2
VDDR3 25mA 1 3 0 2160856030-A0_FCBGA631

+PCIE_VGS
RV49
+BIF_VDDC 2 1
0_0805_5%

CV79

CV80

CV81
DIS@
1 2 2
DIS@ DIS@ DIS@

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 1 1

A A

Title
<Title>

Size Document Number Rev

CustomLA-E981P 0.1

Date: Thursday, June 15, 2017 Sheet 24 of 66

5 4 3 2 1
 1 2 3 4 5

Vinafix.com
A A

M_DA[63..0] UV1C @
[26] M_DA[63..0]
GDDR5/DDR3 GDDR5/DDR3
M0_MA[8..0] M_DA0 K27 K17 M0_MA0
[26] M0_MA[8..0] DQA0_0 MAA0_0/MAA_0
M_DA1 J29 J20 M0_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M0_MA2
M1_MA[8..0] M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M0_MA3
[26] M1_MA[8..0] DQA0_3 MAA0_3/MAA_3
M_DA4 G29 G24 M0_MA4
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M0_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M0_MA6
M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M0_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M0_MA8
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
M_DA11 C28 DQA0_10 J14 M1_MA0
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M1_MA1
M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M1_MA2
M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M1_MA3
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M1_MA4
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M1_MA5
M_DA17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 M1_MA6
M_DA18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 M1_MA7
M_DA19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 M1_MA8
+1.35VS_VRAM +1.35VS_VRAM M_DA20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD
M_DA22 D22 DQA0_21 E32 M_WCKA0_0
DQA0_22 WCKA0_0/DQMA0_0 M_WCKA0_0 [26]
M_DA23 F21 E30 M_WCKA0_0#
DQA0_23 WCKA0B_0/DQMA0_1 M_WCKA0_0# [26]
1

1
M_DA24 E21 A21 M_WCKA0_1
DQA0_24 WCKA0_1/DQMA0_2 M_WCKA0_1 [26]
M_DA25 D20 C21 M_WCKA0_1#
DQA0_25 WCKA0B_1/DQMA0_3 M_WCKA0_1# [26]
RV50 RV51 M_DA26 F19 E13 M_WCKA1_0
B DQA0_26 WCKA1_0/DQMA1_0 M_WCKA1_0 [26] B
40.2_0402_1% 40.2_0402_1% M_DA27 A19 D12 M_WCKA1_0#
DQA0_27 WCKA1B_0/DQMA1_1 M_WCKA1_0# [26]
DIS@ DIS@ M_DA28 D18 E3 M_WCKA1_1
M_WCKA1_1 [26]
2

2
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_WCKA1_1#
DQA0_29 WCKA1B_1/DQMA1_3 M_WCKA1_1# [26]
+MVREFDA +MVREFSA M_DA30 A17
M_DA31 C17 DQA0_30 H28 M_EDC_0
DQA0_31 EDCA0_0/QSA0_0 M_EDC_0 [26]
M_DA32 E17 C27 M_EDC_1
DQA1_0 EDCA0_1/QSA0_1 M_EDC_1 [26]
1

1
1 1 M_DA33 D16 A23 M_EDC_2
DQA1_1 EDCA0_2/QSA0_2 M_EDC_2 [26]
M_DA34 F15 E19 M_EDC_3
DQA1_2 EDCA0_3/QSA0_3 M_EDC_3 [26]
RV52 CV82 RV53 CV83 M_DA35 A15 E15 M_EDC_4
DQA1_3 EDCA1_0/QSA1_0 M_EDC_4 [26]
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA36 D14 D10 M_EDC_5
2 DIS@ 2 DQA1_4 EDCA1_1/QSA1_1 M_EDC_5 [26]
DIS@ DIS@ DIS@ M_DA37 F13 D6 M_EDC_6
M_EDC_6 [26]
2

M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_EDC_7

DQA1_6 EDCA1_3/QSA1_3 M_EDC_7 [26]
M_DA39 C13
M_DA40 E11 DQA1_7 H27 M_DBI0#
DQA1_8 DDBIA0_0/QSA0_0B M_DBI0# [26]
M_DA41 A11 A27 M_DBI1#
DQA1_9 DDBIA0_1/QSA0_1B M_DBI1# [26]
M_DA42 C11 C23 M_DBI2#
DQA1_10 DDBIA0_2/QSA0_2B M_DBI2# [26]
M_DA43 F11 C19 M_DBI3#
DQA1_11 DDBIA0_3/QSA0_3B M_DBI3# [26]
M_DA44 A9 C15 M_DBI4#
DQA1_12 DDBIA1_0/QSA1_0B M_DBI4# [26]
M_DA45 C9 E9 M_DBI5#
DQA1_13 DDBIA1_1/QSA1_1B M_DBI5# [26]
M_DA46 F9 C5 M_DBI6#
DQA1_14 DDBIA1_2/QSA1_2B M_DBI6# [26]
M_DA47 D8 H4 M_DBI7#
DQA1_15 DDBIA1_3/QSA1_3B M_DBI7# [26]
M_DA48 E7
M_DA49 A7 DQA1_16 L18 M_ADBI0
DQA1_17 ADBIA0/ODTA0 M_ADBI0 [26]
M_DA50 C7 K16 M_ADBI1
DQA1_18 ADBIA1/ODTA1 M_ADBI1 [26]
RV54 DIS@ RV55 DIS@ M_DA51 F7
49.9_0402_1% 10_0402_1% M_DA52 A5 DQA1_19 H26 M_CLK0
DQA1_20 CLKA0 M_CLK0 [26]
1 2 2 1 DRAM_RST_G M_DA53 E5 H25 M_CLK#0
[26] DRAM_RST DQA1_21 CLKA0B M_CLK#0 [26]
M_DA54 C3
M_DA55 E1 DQA1_22 G9 M_CLK1
DQA1_23 CLKA1 M_CLK1 [26]
1

1 1 M_DA56 G7 H9 M_CLK#1
DQA1_24 CLKA1B M_CLK#1 [26]
@ M_DA57 G6
CV84 RV56 CV85 M_DA58 G1 DQA1_25 G22 M_RAS#0
120P_0402_50V8J DQA1_26 RASA0B M_RAS#0 [26]
5.1K_0402_1% 68P_0402_50V8J M_DA59 G3 G17 M_RAS#1
2 2 DQA1_27 RASA1B M_RAS#1 [26]
DIS@ DIS@ M_DA60 J6
2

M_DA61 J1 DQA1_28 G19 M_CAS#0

C C
DQA1_29 CASA0B M_CAS#0 [26]
M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 [26]
M_DA63 J5
DQA1_31 H22 M_CS0B#0
CSA0B_0 M_CS0B#0 [26]
+MVREFDA K26 J22
+MVREFSA J26 MVREFDA CSA0B_1
MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS1B#0 [26]
Place close to GPU (within 25mm) J25 K13
RV57 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1
and place componment within (5mm) close to each other MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 [26]
J17 M_CKE1
CKEA1 M_CKE1 [26]
G25 M_WE#0
WEA0B M_WE#0 [26]
DRAM_RST_G L10 H10 M_WE#1
DRAM_RST WEA1B M_WE#1 [26]
RV58 @ 1 2 51.1_0402_1% CV86 @1 2 0.1U_0402_16V4Z K8
RV59 @ 1 2 51.1_0402_1% CV87 @1 2 L7 CLKTESTA
0.1U_0402_16V4Z CLKTESTB

2160856030-A0_FCBGA631

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2016/12/05 Deciphered Date 2017/12/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M30/M70_MEM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-E981P
Thursday, June 15, 2017 Sheet 25 of 66
1 2 3 4 5
 5 4 3 2 1

Memory Partition A
UV7 MF=0 X76@ UV8 MF=0 X76@

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

D
[25] M_DA[0..63]
M_DA[0..63]
[25] M_EDC_0
[25] M_EDC_1
[25] M_EDC_3
[25] M_EDC_2
Vinafix.com M_EDC_0
M_EDC_1
M_EDC_3
M_EDC_2
C2
C13
R13
R2
EDC0
EDC1
EDC2
EDC3
EDC3
EDC2
EDC1
EDC0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ0
DQ1
DQ2
DQ3
DQ4
A4
A2
B4
B2
E4
M_DA2
M_DA0
M_DA3
M_DA1
M_DA6 BYTE0
[25] M_EDC_4
[25] M_EDC_5
[25] M_EDC_7
[25] M_EDC_6
M_EDC_4
M_EDC_5
M_EDC_7
M_EDC_6
C2
C13
R13
R2
EDC0
EDC1
EDC2
EDC3
EDC3
EDC2
EDC1
EDC0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ0
DQ1
DQ2
DQ3
DQ4
A4
A2
B4
B2
E4
M_DA38
M_DA37
M_DA36
M_DA39
M_DA33
BYTE4 D

E2 M_DA7 E2 M_DA35
DQ29 DQ5 F4 M_DA5 DQ29 DQ5 F4 M_DA32
M_DBI0# D2 DQ30 DQ6 F2 M_DA4 M_DBI4# D2 DQ30 DQ6 F2 M_DA34
[25] M_DBI0# DBI0# DBI3# DQ31 DQ7 [25] M_DBI4# DBI0# DBI3# DQ31 DQ7
M_DBI1# D13 A11 M_DA15 M_DBI5# D13 A11 M_DA41
[25] M_DBI1# DBI1# DBI2# DQ16 DQ8 [25] M_DBI5# DBI1# DBI2# DQ16 DQ8
M_DBI3# P13 A13 M_DA13 M_DBI7# P13 A13 M_DA43
[25] M_DBI3# M_DBI2# DBI2# DBI1# DQ17 DQ9 M_DA11 [25] M_DBI7# M_DBI6# DBI2# DBI1# DQ17 DQ9 M_DA40
P2 B11 P2 B11
[25] M_DBI2# DBI3# DBI0# DQ18 DQ10 M_DA9 [25] M_DBI6# DBI3# DBI0# DQ18 DQ10 M_DA42
B13 BYTE1 B13
M_CLK0 J12 DQ19 DQ11 E11 M_DA10 M_CLK1 J12 DQ19 DQ11 E11 M_DA44
+1.35VS_VRAM [25] M_CLK0 M_CLK#0 CK DQ20 DQ12 M_DA12 [25] M_CLK1 M_CLK#1 CK DQ20 DQ12 M_DA45
BYTE5
J11 E13 J11 E13
[25] M_CLK#0 M_CKE0 CK# DQ21 DQ13 M_DA8 [25] M_CLK#1 M_CKE1 CK# DQ21 DQ13 M_DA46
J3 F11 J3 F11
[25] M_CKE0 CKE# DQ22 DQ14 M_DA14 [25] M_CKE1 CKE# DQ22 DQ14 M_DA47
F13 F13
DQ23 DQ15 U11 M_DA30 DQ23 DQ15 U11 M_DA62
M0_MA2 H11 DQ8 DQ16 U13 M_DA28 M1_MA2 H11 DQ8 DQ16 U13 M_DA61
M_CLK0 [25] M0_MA2 M0_MA5 BA0/A2 BA2/A4 DQ9 DQ17 M_DA31 [25] M1_MA2 M1_MA5 BA0/A2 BA2/A4 DQ9 DQ17 M_DA63
1 DIS@ 2 K10 T11 K10 T11
[25] M0_MA5 M0_MA4 BA1/A5 BA3/A3 DQ10 DQ18 M_DA29 [25] M1_MA5 M1_MA4 BA1/A5 BA3/A3 DQ10 DQ18 M_DA60
RV60 60.4_0402_1% K11 T13 BYTE3 K11 T13
[25] M0_MA4 M0_MA3 BA2/A4 BA0/A2 DQ11 DQ19 M_DA27 [25] M1_MA4 M1_MA3 BA2/A4 BA0/A2 DQ11 DQ19 M_DA57
H10 N11 H10 N11 BYTE7
[25] M0_MA3 BA3/A3 BA1/A5 DQ12 DQ20 M_DA26 [25] M1_MA3 BA3/A3 BA1/A5 DQ12 DQ20 M_DA58
N13 N13
1 DIS@ 2 M_CLK#0 DQ13 DQ21 M11 M_DA24 DQ13 DQ21 M11 M_DA56
RV61 60.4_0402_1% M0_MA7 K4 DQ14 DQ22 M13 M_DA25 M1_MA7 K4 DQ14 DQ22 M13 M_DA59
[25] M0_MA7 M0_MA1 A8/A7 A10/A0 DQ15 DQ23 M_DA19 [25] M1_MA7 M1_MA1 A8/A7 A10/A0 DQ15 DQ23 M_DA55
H5 U4 H5 U4
[25] M0_MA1 M0_MA0 A9/A1 A11/A6 DQ0 DQ24 M_DA22 [25] M1_MA1 M1_MA0 A9/A1 A11/A6 DQ0 DQ24 M_DA48
H4 U2 H4 U2
[25] M0_MA0 M0_MA6 A10/A0 A8/A7 DQ1 DQ25 M_DA17 [25] M1_MA0 M1_MA6 A10/A0 A8/A7 DQ1 DQ25 M_DA52
K5 T4 K5 T4
[25] M0_MA6 M0_MA8 A11/A6 A9/A1 DQ2 DQ26 M_DA20 [25] M1_MA6 M1_MA8 A11/A6 A9/A1 DQ2 DQ26 M_DA51
J5 T2 BYTE2 J5 T2
+1.35VS_VRAM [25] M0_MA8 A12/RFU/NC DQ3 DQ27 M_DA18 [25] M1_MA8 A12/RFU/NC DQ3 DQ27 M_DA54
N4 N4 BYTE6
A5 DQ4 DQ28 N2 M_DA21 A5 DQ4 DQ28 N2 M_DA50
U5 VPP/NC DQ5 DQ29 M4 M_DA16 U5 VPP/NC DQ5 DQ29 M4 M_DA53
VPP/NC DQ6 DQ30 M2 M_DA23 VPP/NC DQ6 DQ30 M2 M_DA49
DQ7 DQ31 DQ7 DQ31
1 DIS@ 2 M_CLK1 RV63 DIS@ 2 1 1K_0402_1% J1 +1.35VS_VRAM RV64 DIS@ 2 1 1K_0402_1% J1 +1.35VS_VRAM
RV62 60.4_0402_1% RV65 DIS@ 2 1 1K_0402_1% J10 MF RV66 DIS@ 2 1 1K_0402_1% J10 MF
RV67 DIS@ 2 1 121_0402_1% J13 SEN B1 RV68 DIS@ 2 1 121_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
1 DIS@ 2 M_CLK#1 VDDQ F1 VDDQ F1
RV69 60.4_0402_1% M_ADBI0 J4 VDDQ M1 M_ADBI1 J4 VDDQ M1
[25] M_ADBI0 M_RAS#0 ABI# VDDQ [25] M_ADBI1 M_RAS#1 ABI# VDDQ
G3 P1 G3 P1
[25] M_RAS#0 M_CS0B#0 RAS# CAS# VDDQ [25] M_RAS#1 M_CS1B#0 RAS# CAS# VDDQ
G12 T1 G12 T1
[25] M_CS0B#0 M_CAS#0 CS# WE# VDDQ [25] M_CS1B#0 M_CAS#1 CS# WE# VDDQ
L3 G2 L3 G2
[25] M_CAS#0 M_WE#0 CAS# RAS# VDDQ [25] M_CAS#1 M_WE#1 CAS# RAS# VDDQ
L12 L2 L12 L2
[25] M_WE#0 WE# CS# VDDQ [25] M_WE#1 WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
M_WCKA0_0# D5 VDDQ H3 M_WCKA1_0# D5 VDDQ H3
[25] M_WCKA0_0# M_WCKA0_0 WCK01# WCK23# VDDQ [25] M_WCKA1_0# M_WCKA1_0 WCK01# WCK23# VDDQ
D4 K3 D4 K3
[25] M_WCKA0_0 WCK01 WCK23 VDDQ [25] M_WCKA1_0 WCK01 WCK23 VDDQ
M3 M3
M_WCKA0_1# P5 VDDQ P3 M_WCKA1_1# P5 VDDQ P3
[25] M_WCKA0_1# M_WCKA0_1 WCK23# WCK01# VDDQ [25] M_WCKA1_1# M_WCKA1_1 WCK23# WCK01# VDDQ
P4 T3 P4 T3
[25] M_WCKA0_1 WCK23 WCK01 VDDQ [25] M_WCKA1_1 WCK23 WCK01 VDDQ
E5 E5
VDDQ N5 VDDQ N5
C A10 VDDQ E10 A10 VDDQ E10 C
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBA_VREFC0 J14 VREFD VDDQ B12 +FBA_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
DRAM_RST J2 VDDQ K12 +FBA_VREFC0 DRAM_RST J2 VDDQ K12
[25] DRAM_RST RESET# VDDQ RESET# VDDQ
M12 M12
VDDQ VDDQ

1U_0402_6.3V6K
P12 P12
+1.35VS_VRAM VDDQ T12 VDDQ T12
VDDQ 1 VDDQ

CV88 DIS@
G13 G13
H1 VDDQ L13 H1 VDDQ L13
VSS VDDQ VSS VDDQ
2.37K_0402_1%

K1 B14 K1 B14
VSS VDDQ VSS VDDQ
1

B5 D14 2 B5 D14
VSS VDDQ VSS VDDQ
RV70 DIS@

G5 F14 G5 F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
2

D10 VSS VDDQ D10 VSS VDDQ

G10 VSS G10 VSS
+FBA_VREFC0 L10 VSS A1 L10 VSS A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1
VSS VSSQ VSS VSSQ
5.49K_0402_1%

1U_0402_6.3V6K

T10 E1 T10 E1
W=16mils VSS VSSQ VSS VSSQ
1

1 H14 N1 H14 N1
VSS VSSQ VSS VSSQ
RV71 DIS@

CV89 DIS@

K14 R1 K14 R1
+1.35VS_VRAM VSS VSSQ U1 +1.35VS_VRAM VSS VSSQ U1
VSSQ H2 VSSQ H2
2 G1 VSSQ K2 G1 VSSQ K2
2

L1 VDD VSSQ A3 L1 VDD VSSQ A3

G4 VDD VSSQ C3 G4 VDD VSSQ C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
Place near pin J14 of each vram VDD VSSQ VDD VSSQ
D11 R4 D11 R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12
VSSQ E12 VSSQ E12
VSSQ N12 VSSQ N12
VSSQ R12 VSSQ R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 VSSQ H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
B VSSQ A14 VSSQ A14 B
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
K4G80325FB-HC03_FBGA170~D K4G80325FB-HC03_FBGA170~D

+1.35VS_VRAM
+1.35VS_VRAM
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV90

CV91

CV92

CV93

CV94

CV95

CV96

CV97

CV98

CV99

CV100

CV101

CV102

CV103

CV104

CV105

CV106

CV107

CV108

CV109

CV110

CV111

CV112

CV113

CV114

CV115

CV116

CV117

CV118

CV119

CV120

CV121

CV122
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
DIS@

DIS@

DIS@

DIS@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/12/05 Deciphered Date 2017/12/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR5_A0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E981P
Date: Thursday, June 15, 2017 Sheet 26 of 66
5 4 3 2 1
 5 4 3 2 1

TPM 2.0 C462 C458

SE00000SV00

TPM@

SE000000K80

TPM@
Layout Rout i ng

0.1U_0201_10V6K

1U_0402_6.3V6K
LPC LPC

CPU TPM EC Vinafix.com +3VS_TPM

D D
pin9 pin20 pin25

10U_0402_6.3V6M
1 1 1 1

0.1U_0201_10V6K
C464

0.1U_0201_10V6K
C463

0.1U_0201_10V6K
C462

C458 TCM@
TPM/TCP Colay
2 2 2 2 Nat i onz Inf i neon Nat i onz Inf i neon
TCM TPM TCM TPM

TCM@

TCM@

TCM@
Pin1 NC VDD Pin17 NC NC
Pin2 NC GPIO Pin18 LRESET#LRESET#
Pin3 NC NC Pin19 LAD3 LAD3
U61 U61
Pin4 NC NC Pin20 VDD VDD
R5
TPM@
Pin5 NC NC Pin21 LAD2 LAD2
0_0201_5%
SD043000080
Pin6 NC NC Pin22 LCLK LCLK
TPM@ TCM@
+3VS R5 +3VS_TPM TPM TCM
Pin7 NC NC Pin23 LFRAME#LFRAME#
TCM@ SA00007XX30 SA00009FM20 +3VS_TPM
0_0201_5%
Pin8 NC NC Pin24 LAD1 LAD1
SD043000080 U61 @
Pin9 VDD VDD Pin25 VDD VDD
R5 1 @ 2 0_0201_5% 9
20 VDD 1 R427 1 TPM@ 2 0_0201_5%
Pin10 NC VDD Pin26 GND GND
25 VDD NC 2 R3170 1 TPM@ 2 4.7K_0201_5%
VDD NC 3
Pin11 GND NC Pin27 LAD0 LAD0
NC 4
LPC_AD0 27 NC 5
Pin12 NC NC Pin28 NC SERIRQ
[8,45] LPC_AD0 LPC_AD1 LAD0 NC
24 6
[8,45] LPC_AD1 LPC_AD2 21 LAD1 NC 7
Pin13 NC NC Pin29 NC NC
[8,45] LPC_AD2 LPC_AD3 LAD2 NC
19 8
[8,45] LPC_AD3 CK_LPC_TPM 22 LAD3 NC 10 R422 1 TPM@ 2 0_0201_5%
Pin14 NC NC Pin30 NC NC
C [8] CK_LPC_TPM LCLK NC C
12
LPC_FRAME# 23 NC 13
Pin15 NC GND Pin31 NC PP
[8,45] LPC_FRAME# LFRAME# NC
PCIRST# 18 14
[10,21,31,32,36,45] PCIRST# LRESET# NC 15
Pin16 GND GND Pin32 GND GND
NC 17
R426 1 TCM@ 2 0_0201_5% 11 NC 28 R424 1 TPM@ 2 0_0201_5%
1 GND NC SERIRQ [8,45]
C489 16 29
27P_0402_50V8J @ 26 GND NC 30
32 GND NC 31 R425 1 TPM@ 2 4.7K_0201_5%
2 33 GND NC
PGND

Z32H320TC-LPC-Q32401_QFN32_5X5
SA00009FM20
Z32H320TC-LPC-Q32-LC_QFN32_5X5

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/06.23 Deciphered Date 2017/06/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TPM/TCM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E581P
Date: Thursday, June 15, 2017 Sheet 27 of 66

5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_CMOS

Camera R463 1
CMOS@
2 0_0402_5%
LCD Power Circuit +LCDVDD_CONN
Q30
W=60mils
W=20mils W=20mils

D
3 1 1 W=60mils U59 R6

C470 SKL@
+LCDVDD_CONN_R1 +LCDVDD_CONN

4.7U_0603_6.3V6K
SKL@ 1 C3 @ +3VS 5 1 2
LP2301ALT1G_SOT23-3 10U_0603_6.3V6M IN OUT 0_0603_5%
0606 change

0.1U_0201_10V6K

C5
2

G
1

2
D 2 GND D
2

[45] CMOS_ON#
1
SKL@

R7
2
Vinafix.com @
1
C6
[6] PCH_ENVDD
4
EN OC
3

G524B1T11U SOT-23-5 2

1
1 1U_0402_6.3V6K
150K_0402_5% C7 @
0.1U_0201_10V6K 2 R8
100K_0402_5% @
2

2
EMI@
R476 2 1 0_0402_5%
0428 SWAP
EXC24CG900U_4P B+ +LEDVDD
4 3 USB20_N5_R
[12] USB20_N5 4 3 R10 1 2 0_0805_5%

4.7U_0805_25V6-K
1 2 USB20_P5_R
[12] USB20_P5 1 2 W=100mils
L14 @EMI@ R_short eDP PANEL Conn.

C8
1 1

10P_0402_25V8J
R477 2 1 0_0402_5% C497
C C
@RF@ JEDP1 ME@
EMI@ 2 2 1
[6] INVPWM 1
BKOFF# 2
[45] BKOFF# 2
3
4 3
4

2
5
R12 BKOFF# 6 5
100K_0402_5% EDP_HPD 7 6
8 7
W=60mils +LCDVDD_CONN
9 8

1
10 9
11 10
C10 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 12 11
[6] EDP_AUXN 12
C11 1 2 0.1U_0201_10V K X5R EDP_AUXP_C 13
[6] EDP_AUXP 13
EDP_HPD eDP 14
[6] EDP_HPD 14
C12 1 2 0.1U_0201_10V K X5R EDP_TXP0_C 15
[6] EDP_TXP0 EDP_TXN0_C 15
C13 1 2 0.1U_0201_10V K X5R 16
[6] EDP_TXN0 16

1
1 17
C14 1 2 0.1U_0201_10V K X5R EDP_TXP1_C 18 17
[6] EDP_TXP1 EDP_TXN1_C 18
R15 C9 EMI@ C15 1 2 0.1U_0201_10V K X5R 19
[6] EDP_TXN1 19
100K_0402_5% 22P_0402_50V8J 20
2 21 20

2
22 21
+3VS_CMOS 22
B USB20_N5_R 23 B
USB20_P5_R 24 23
25 24
26 25 31
Camera [11] DMIC_DET#
27 26 G1 32
28 27 G2 33
[35] DMIC_CLK 28 G3
[35] DMIC_DAT 29 34
30 29 G4 35
30 G5
ACES_50406-03071-001

eDP Connector PN
SP010015L00

150P_0402_50V8J

150P_0402_50V8J
1 1

C505
EMI@

C502
EMI@
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 28 of 66
5 4 3 2 1
 5 4 3 2 1

ZZZ15 45@
EMI
Near JHDMI1 For HDMI
Vinafix.com
+5V_DSP
U9 HDMI Logo
EMI@ R16 1 2 0_0402_5% +5VS 3
W=40mils RO0000003HM
Near JHDMI1 OUT
D 1 D
1
IN

1
[6] HDMI_CLK-_CK C17 1 2 0.1U_0201_10V6K HDMI_CLK-_CK_C HDMI_CLK-_CONN 1 C18
R17 @EMI@ @ 2 0.1U_0201_10V6K
150_0402_5% C19 GND 2
[6] HDMI_CLK+_CK C20 1 2 0.1U_0201_10V6K HDMI_CLK+_CK_C HDMI_CLK+_CONN 0.1U_0201_10V6K
2 G5250Q1T73U SOT-23

2
EMI@ R18 1 2 0_0402_5%

EMI@ R19 1 2 0_0402_5%

1
[6] HDMI_TX0-_CK C21 1 2 0.1U_0201_10V6K HDMI_TX0-_CK_C HDMI_TX0-_CONN
R20 @EMI@
150_0402_5%
[6] HDMI_TX0+_CK C22 1 2 0.1U_0201_10V6K HDMI_TX0+_CK_C HDMI_TX0+_CONN

2
+3VS
EMI@ R21 1 2 0_0402_5%

EMI@ R22 1 2 0_0402_5%

2
R23

1
C23 1 2 0.1U_0201_10V6K HDMI_TX1-_CK_C HDMI_TX1-_CONN 1M_0402_5% +5V_DSP
[6] HDMI_TX1-_CK

2
R24 @EMI@ Q2

G
150_0402_5% 2N7002K_SOT23-3

1
[6] HDMI_TX1+_CK C24 1 2 0.1U_0201_10V6K HDMI_TX1+_CK_C HDMI_TX1+_CONN JHDMI1 ME@
3 1 HDMI_DET 19
[6] TMDS_B_HPD

2
18 HP_DET

D
+5V

2
17
EMI@ R25 1 2 0_0402_5% R26 HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
20K_0402_5% SCL
EMI@ R27 1 2 0_0402_5% 14
13 Reserved

1
HDMI_CLK-_CONN 12 CEC 20
CK- GND

1
C [6] HDMI_TX2-_CK C25 1 2 0.1U_0201_10V6K HDMI_TX2-_CK_C HDMI_TX2-_CONN 11 21 C
R28 @EMI@ HDMI_CLK+_CONN 10 CK_shield GND 22
150_0402_5% HDMI_TX0-_CONN 9 CK+ GND 23
C26 1 2 0.1U_0201_10V6K HDMI_TX2+_CK_C HDMI_TX2+_CONN 8 D0- GND
[6] HDMI_TX2+_CK D0_shield
HDMI_TX0+_CONN 7

2
HDMI_TX1-_CONN 6 D0+
5 D1-
EMI@ R29 1 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
ACON_HMRA3-AK120C
+3VS
+3VS

R30 1 2 2.2K_0402_5% HDMIDAT_NB

Q3A
HDMI Connector PN
R31 1 2 2.2K_0402_5% HDMICLK_NB DC232003A00
2

L2N7002DW1T1G 2N SC88-6

HDMIDAT_NB(Internal Pull Down): 1 6 HDMICLK_R

[6] HDMICLK_NB
RP8
5

HDMI_TX1-_CK_C 5 4
Display Port C Detected HDMI_TX1+_CK_C 6 3
[6] HDMIDAT_NB 4 3 HDMIDAT_R HDMI_TX2-_CK_C 7 2
HDMI_TX2+_CK_C 8 1
0 = Port C is not detected. Q3B
L2N7002DW1T1G 2N SC88-6 470 +-5% 8P4R
1 = Port C is detected.
RP9
HDMI_CLK-_CK_C 8 1
HDMI_CLK+_CK_C 7 2
+5V_DSP HDMI_TX0-_CK_C 6 3
HDMI_TX0+_CK_C 5 4
R32 1 2 2.2K_0402_5% HDMIDAT_R
470 +-5% 8P4R
B B
R33 1 2 2.2K_0402_5% HDMICLK_R

+3VS

1
D
2
G

ESD S Q4
2N7002K_SOT23-3

3
D1 ESD@ D2 ESD@ D3 ESD@
HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX1-_CONN 9 10 1 1 HDMI_TX1-_CONN

HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX1+_CONN 8 9 2 2 HDMI_TX1+_CONN

HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX0-_CONN 7 7 4 4 HDMI_TX0-_CONN HDMI_TX2-_CONN 7 7 4 4 HDMI_TX2-_CONN

6 6 5 5 HDMI_TX0+_CONN 6 6 5 5 HDMI_TX0+_CONN HDMI_TX2+_CONN 6 6 5 5 HDMI_TX2+_CONN

3 3 3 3 3 3

8 8 8

L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9
SC300003Z00 SC300003Z00 L05ESDL5V0NA-4_SLP2510P8-10-9
SC300003Z00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 29 of 66
5 4 3 2 1
 A B C D E F G H

HDD SATA HDD Conn.

Vinafix.com
1 1

JHDD1 ME@

1
C29 1 2 0.01U_0402_16V7K SATA_CTX_DRX_P0_C 2 GND
[12] SATA_CTX_DRX_P0 SATA_CTX_DRX_N0_C A+
C31 1 2 0.01U_0402_16V7K 3
[12] SATA_CTX_DRX_N0 A-
4
C33 1 2 0.01U_0402_16V7K SATA_CRX_DTX_N0_C 5 GND
[12] SATA_CRX_DTX_N0 SATA_CRX_DTX_P0_C B-
C35 1 2 0.01U_0402_16V7K 6
[12] SATA_CRX_DTX_P0 B+
7
GND

8
9 V33
+5VS +5VS_HDD 10 V33
11 V33
12 GND
R227 13 GND
+5VS_HDD
100mils GND
1 2 14
0_0805_5% 15 V5
16 V5
17 V5
18 GND
19 Reserved
GND

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0201_10V K X5R
20
V12

C37

C38
1 1 1 1 21 24
V12 GND

10P_0402_25V8J

C39
22 23
@ C500 V12 GND
RF@
2 2 2 2 SDAN_603006-022041
DC01000CE00

2
JHDD Connector PN 2

DC01000CE00

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 30 of 66
A B C D E F G H
 A B C D E

Vinafix.com
1 1
+3VS +3VS_WLAN

NGFF for WLAN / BT(Key E) R43 1 2 0_0603_5%

Support ISCT(Intel Smart Connect Technology)

1 1
+3VS_WLAN C46
C47
JWLAN1 ME@ 4.7U_0603_6.3V6K @ 0.1U_0201_10V6K
1 2 2 2
3 GND 3.3VAUX 4
[12] USB20_P6 USB_D+ 3.3VAUX
BT 5 6
[12] USB20_N6 USB_D- LED1#
7 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22 UART_2_CRXD_DTXD_R R44 1 2 0_0402_5%
SDIO_WAKE# UART_RX UART_2_CRXD_DTXD [11]
23
SDIO_RESET#

24 UART_2_CTXD_DRXD_R R45 1 2 0_0402_5%

UART_TX UART_2_CTXD_DRXD [11]
25 26
C48 1 2 0.1U_0402_25V6 PCIE_CTX_C_DRX_P6 27 GND UART_CTS 28
[12] PCIE_CTX_DRX_P6 PETP0 UART_RTS
C49 1 2 0.1U_0402_25V6 PCIE_CTX_C_DRX_N6 29 30 R46 1 2 0_0402_5%
[12] PCIE_CTX_DRX_N6 PETN0 RESERVED EC_TX [45]
31 32 R47 1 2 0_0402_5%
GND RESERVED EC_RX [45]
33 34
[12] PCIE_CRX_DTX_P6 PERP0 RESERVED
2 35 36 2
[12] PCIE_CRX_DTX_N6 PERN0 COEX3
WLAN 37 38
39 GND COEX2 40
[10] CLK_PCIE_WLAN REFCLKP0 COEX1 SUSCLK_R
41 42 R48 1 2 0_0402_5%
[10] CLK_PCIE_WLAN# REFCLKN0 SUSCLK WL_RST# SUSCLK [10]
43 44 R49 1 2 0_0402_5% PCIRST# [10,21,27,32,36,45]
R50 1 2 0_0402_5% WLANCLK_REQ#_R 45 GND PERST0# 46 BT_DISABLE_R R51 1 2 0_0402_5%
[10] WLANCLK_REQ# CLKEQ0# W_DISABLE2# WLBT_OFF# [11]
[36,45] EC_PCIE_WAKE# R52 1 2 0_0402_5% WAKE#_R 47 48 R53 1 2 0_0402_5%
PEWAKE0# W_DISABLE1# EC_WL_OFF# [12]
For ISCT 49 50
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
Note: The real behavior of BT_DISABLE are
57 GND RESERVED 58 BT_DISABLE=LOW, BT=OFF
59 RSRVD/PERP1 RESERVED 60 BT_DISABLE=HIGH, BT=ON
61 RSRVD/PERN1 RESERVED 62
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
67 RESERVED 3.3VAUX
GND

69 68
MTG77 MTG76

CONCR_213EAAA32FA

2
R54
100K_0402_5%
WLAN NGFF Connector PN
SP070011I00

1
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/NEW Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 31 of 66
A B C D E
 A B C D E

M.2 mSATA Conn +3VS_NGFF

1
SATA_GP2
SATA_GP2 [12]
R55
PEDET (SATA_CP0)
Vinafix.com 10K_0402_5%
L : PCIE

2
+3VS_NGFF J1 @ +3VS
H : SATA

1
1 JSSD1 ME@ JUMP_43X39 D 1
1 2 1 2 PE_DTCT 2
3 GND 3P3VAUX 4 1 2 G 2N7002KW_SOT323-3
PCIE_CRX_DTX_N9 5 GND 3P3VAUX 6 Q5
[12] PCIE_CRX_DTX_N9 PERn3 NC
PCIE_CRX_DTX_P9 7 8 S
[12] PCIE_CRX_DTX_P9 PEDET (PE_DTCT)

3
9 PERp3 NC 10 SB000009Q80
GND DAS/DSS#
[12] PCIE_CTX_DRX_N9
PCIE_CTX_DRX_N9
PCIE_CTX_DRX_P9
C50
C51
1
1
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K
PCIE9_L3_TXN_CONN
PCIE9_L3_TXP_CONN
11
13 PETn3 3P3VAUX
12
14 SATA Device GND
[12] PCIE_CTX_DRX_P9 PETp3 3P3VAUX
PCIE_CRX_DTX_N10
15
17 GND 3P3VAUX
16
18
PCIe Device Open
[12] PCIE_CRX_DTX_N10 PERn2 3P3VAUX
PCIE_CRX_DTX_P10 19 20
[12] PCIE_CRX_DTX_P10 PERp2 NC
21 22
PCIE_CTX_DRX_N10 C52 1 2 0.22U_0402_10V6K PCIE10_L2_TXN_CONN 23 GND NC 24
[12] PCIE_CTX_DRX_N10 PETn2 NC
PCIE_CTX_DRX_P10 C53 1 2 0.22U_0402_10V6K PCIE10_L2_TXP_CONN 25 26
[12] PCIE_CTX_DRX_P10 PETp2 NC
27 28
PCIE_CRX_DTX_N11 29 GND NC 30
[12] PCIE_CRX_DTX_N11 PERn1 NC
PCIE_CRX_DTX_P11 31 32
[12] PCIE_CRX_DTX_P11 PERp1 NC
33 34
PCIE_CTX_DRX_N11 C54 1 2 0.22U_0402_10V6K PCIE11_L1_TXN_CONN 35 GND NC 36
[12] PCIE_CTX_DRX_N11 PETn1 NC
PCIE_CTX_DRX_P11 C55 1 2 0.22U_0402_10V6K PCIE11_L1_TXP_CONN 37 38
[12] PCIE_CTX_DRX_P11 PETp1 DEVSLP
39 40
PCIE_CRX_DTX_P12 41 GND NC 42
[12] PCIE_CRX_DTX_P12 PERn0/SATA-B+ NC
PCIE_CRX_DTX_N12 43 44
[12] PCIE_CRX_DTX_N12 PERp0/SATA-B- NC
45 46
PCIE_CTX_DRX_N12 C56 1 2 0.22U_0402_10V6K PCIE12_L0_SATA1_TXN_CONN 47 GND NC 48
[12] PCIE_CTX_DRX_N12 PETn0/SATA-A- NC
PCIE_CTX_DRX_P12 C57 1 2 0.22U_0402_10V6K PCIE12_L0_SATA1_TXP_CONN 49 50 PCIRST#
[12] PCIE_CTX_DRX_P12 PETp0/SATA-A+ PERST# PCIRST# [10,21,27,31,36,45]
51 52
GND CLKREQ# M2CLK_REQ# [10]
CLK_PCIE_M2# 53 54
[10] CLK_PCIE_M2# REFCLKN PEWake#
CLK_PCIE_M2 55 56
[10] CLK_PCIE_M2 REFCLKP NC
57 58
GND NC

59 60
2
PE_DTCT 61 NC SUSCLK(32kHz) 62 2
63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
65 GND 3P3VAUX 66
67 GND 3P3VAUX
GND 68
GND1 1 1
69 RF@
GND2 C58 C59
BELLW_80159-3221 10U_0603_6.3V6M 10P_0402_25V8J
2 2

JSSD Connector PN
SP070018L00

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2015/03/06 Deciphered Date 2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Merlyn LA-D211P
Date: Thursday, June 15, 2017 Sheet 32 of 66
A B C D E
 @
+3VLP LID Power BTN KB +5VS R56 1 2 100_0402_5%

NOVO BTN JKB1 ME@

Keyboard Backlight

100K_0402_5%
1 R57 2 R58 1 2 +KB_VCC 1
+3VALW +3VS 1

2
100K_0402_5% [45] CAPS_LED# 100_0402_5% 2
KSO15 3 2
3

R59
KSO10 4
SW1 +3VLP KSO11 5 4
5

2
1 KSO14 6

1
1 2 KSO13 7 6

0.1U_0201_10V K X5R
1

VDD
[45] NOVO# 7

2
C60 C61 KSO12 8
@ESD@ KSO3 9 8
ESD@ 9
3 4 0.1U_0201_10V6K 3 LID_SW# R60 2 KSO6 10
2 OUTPUT LID_SW# [45] 10
100K_0402_5% KSO8 11
11

2
KSO7 12

GND
ESD

1
D4 KSO4 13 12
TCHC2QR_2P 2
ESD@ ON/OFF# KSO2 14 13
[45] ON/OFF# 14

Vinafix.com
U11 C62 KSI0 15

1
L03ESDL5V0CC3-2_SOT23-3 10P_0402_50V8J KSO1 16 15
SCA00002900 1 KSO5 17 16
17

2
KSI3 18 +5VS +5VS +VCC_KB_LED
ON TOP ON BOTTOM 18

2
D5 KSI2 19
TCS20DLR SOT-23F 3P ESD@ J2 J3 KSO0 20 19
1

SA00008K800 KSI5 21 20
SHORT PADS SHORT PADS

1
21

1
L03ESDL5V0CC3-2_SOT23-3 KSI4 22
SCA00002900 KSO9 23 22 R61 Q6 JKBL1 ME@
KSI6 24 23 10K_0402_5%
24

D
KSI7 25 KBL@ 3 1 1
KSI1 26 25 2 1

ClickPad ESD

2
+TP_VCC +3VS 26 2

10U_0603_6.3V6M

0.1U_0201_10V K X5R
27 ME2301DC-G_SOT23-3 3
28 27 KBL@ 4 3

G
1 1

2
28 4

C63

C64
29 R63
30 29 1 2
30

KBL@
31 0_0402_5%
[45] KB_DEL# 31 2 2

0.01U_0402_16V7K
R468 32 KBL@ 5
4.7K_0402_5% Power BTN 32
1 6 GND
GND

C65
33 R64 2 1 0_0402_5%
JTP1 ME@ GND 34 KBL@
1 SN100004Y00 GND

KBL@
R65 1 2 0_0402_5% +TP_VCC 1
1

1
I2C1_SCL_TP 2 2 CVILU_CF5004FD0RD-10-NH
[11] I2C1_SCL_TP I2C1_SDA_TP 2 LTCX007VP00
3 SW2 ACES_51510-0320N-P01

OUT
[11] I2C1_SDA_TP 3
4 SKQGPAE010_6P
TP_INT# 5 4
[11] TP_INT# R467 1 2 0_0402_5% TP_Disable#_R 6 5 ON/OFF# 1 3 2
[45] TP_DISABLE# 6 [45] KB_BL_PWM IN
JKBL Connector PN

GND
7 2 4 @
GND
8
GND JKB Connector PN Q7 SP01002F900
DTC124EKAT146_SC59-3

5
6

3
ACES_50521-00641-P01 SP01002F900
KSI[0..7]
KSI[0..7] [45]
KSO[0..15]

C68

C69

C67
0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
Click Pad Pin define(Module) 1 1 1
KSO[0..15] [45]

Pin1 VDD_3.3V
3

@ @ @
Pin2 SCL @ESD@ 2 2 2
D6
JTP Connector PN
Pin3 SDA
Pin4 GND
PSOT24C_SOT23-3 SP010020S00 LED
Charge LED
1

Pin5 INT
LED1 +5VALW
Pin6 LID CLOSE R67

ESD PWR LED [45] PWR_LED#

PWR_LED# 1 2 1 2 +5VALW

1
470_0402_5%
R66
LTW-C193TS5-C_WHITE 0_0402_5%
SC50000BB10
LED2 R68

2
DCIN_LED# 1 2 1 2
DCIN LED [45] DCIN_LED#
470_0402_5%
+5VALW

FingerPrint LTW-270US5_WHITE

1
SC50000DD00 LED3
+3VS

WHITE

ORANGE
LED4 R69 LTW-326DSKF-5A_WHI-ORG
PCH_SATALED# 1 2 1 2
HDD LED [12] PCH_SATALED#
470_0402_5%
+5VS

2
ACES_51580-00841-P01
R447 1 FP@ 2 0_0402_5% +3VS_FP 1 LTW-270US5_WHITE WHITE ORANGE
USB20_N8 2 1 SC50000DD00
FP Pin define(Module) [12] USB20_N8 USB20_P8 3 2
Pin1 NC
[12] USB20_P8
4 3
5 4 GND 10
9 P/N:SC500007F00
6 5 GND
Pin2 NC 7 6
R70
8 7 BATT_CHG_LED# 1 2
Pin3 NC 8 [45] BATT_CHG_LED#
470_0402_5%
JFP1 ME@
Pin4 NC
Pin5 GND D7 ESD@ R71
4 3 BATT_LOW_LED# 1 2
Pin6 D+ 4 3 [45] BATT_LOW_LED#
499_0402_1%
JFP Connector PN
Pin7 D- SP01002GM00
Pin8 3.3VCC +3VS_FP

CPU VGA
5
Vbus GND
2 Shielding Clip WLAN Thermal
H9 H10 H11 H12 H23 H18 H13 H1 H2 H3 H4 H5
Larger HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4 HOLEA HOLEA HOLEA HOLEA HOLEA

CLIP1 CLIP2 CLIP3

HOLEA HOLEA HOLEA @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @

1
USB20_N8 6 1 USB20_P8 @ @ @
1

1
6 1 H_4P4 H_2P3 H_2P3 H_4P4 H_2P3 H_3P2 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3
L30ESDL5V0C6-4_SOT23-6
SC300003V00 H14
HOLEA
H15
HOLEA
H16
HOLEA
H17
HOLEA
H22
HOLEA
SSD
Smaller H19
HOLEA
H26 LAN NPTH
FAN Conn CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 @ @ @ @ @

1
HOLEA HOLEA HOLEA HOLEA HOLEA H20 H21
@ @ HOLEA HOLEA H6 H7 H8 H24 H25 H30

1
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
JFAN1 @ @ @ @ @ H_2P3 H_2P3 H_2P3 H_2P3 H_2P3
1

1
+5VS 1 MB_SUP_BRK_25X5 @ @

1
2 1 H_3P2 @ @ @ @ @ @
[45] EC_FAN_PWM

1
3 2 H27 H28 H29
[45] EC_FAN_SPEED +5VS_FAN 3
R72 1 2 4 HOLEA HOLEA HOLEA LANGAN LANGAN H_2P1X2P6N H_2P1X2P6N H_2P1N H_1P5N H_1P5N H_2P5N
0_0603_5% 5 4 H_3P2 H_3P2
6 G1 CLIP9 CLIP10 CLIP11 CLIP12 CLIP13
G2 HOLEA HOLEA HOLEA HOLEA HOLEA @ @ @

1
2 ACES_85204-04001
ME@
C70 @ @ @ @ @
1

10U_0603_6.3V6M H_2P3 H_2P3 H_2P3

1 Security Classification Compal Secret Data Compal Electronics, Inc.
JFAN Connector PN 2011/06/24 2012/07/12 Title
Issued Date Deciphered Date KBD/PWR/CR/LED/TP Conn.
SP02000CW00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 33 of 66
 5 4 3 2 1

USB 3.0 AOU USB 3.0

+5VALWP V330 only W=80mils W=80mils W=80mils W=80mils
NONAOU +5VALW +5V_CHGUSB +5VALW +5V_USB

NONAOU@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

47U_0805_6.3V6M
1 2 U55 NONAOU@ U56
1 1 1 1 1 1 1 1 1 1 C71 1 1
OUT OUT

C519

C520

C521

C522

C523

C524

C525

C526

C527

C528
0.1U_0201_10V K X5R 5 5
@ @ @ @ @ @ @ @ @ @ IN 2 R73 IN 2 R228
4 GND 0_0402_5% USB_EN# 4 GND 0_0402_5%
2 2 2 2 2 2 2 2 2 2 [45,46] USB_EN# EN 3 1 2 EN 3 1 2
OCB USB_OC0# [12] OCB USB_OC1# [12]
NONAOU@
SY6288D20AAC_SOT23-5 SY6288D20AAC_SOT23-5
D 2 D
C248

Vinafix.com
0.1U_0201_10V K X5R
USB20_P1 R232 1 2 0_0402_5% USB20_CH_P1 1
For USB Charger to improve +5VALWP power ripple NONAOU@

USB20_N1 R233 1 2 0_0402_5% USB20_CH_N1

NONAOU@

+5V_USB

+3VALW +5VALW_USBCH +5V_CHGUSB

150U_B2_6.3VM_R35M
AOU control 1 1 1
22U_0603_6.3V6M

22U_0603_6.3V6M

0.1U_0201_10V K X5R

10P_0402_25V8J
@
2

C472
+ C499 C471
1 1 1
R75
C518

C517

C516
R89 RF@ 470P_0402_50V7K
2 2
AOU@

10K_0402_5%

AOU@

10K_0402_5%

AOU@
R74 @ @ @ 0411
10K_0402_5% +5VL +5VALW_USBCH +5VALW R3188 2 RF@ 1 0_0402_5% 2
2 2 2 @
1

2
R231 2 1
L2002 @RF@
0_0603_5% USB3_RX_N2 2 1
[12] USB3_RX_N2 2 1
AOU@ JUSB2 ME@
80mil

D
U12 AOU@ R234 2 1 3 1 1
1 12 0_0603_5% Q28 USB3_RX_P2 3 4 USB20_N2_L 2 VBUS
IN OUT 1 1 [12] USB3_RX_P2 3 4 D-

ME2301DC-G_SOT23-3
USB_CHG_STATUS# 9 10 USB20_CH_P1 AOU@ AOU@ AOU@ USB20_P2_L 3
[45] USB_CHG_STATUS# STATUS# DP_IN D+
USB_OC0# R76 2 @ 1 USB_OC0#_U12 13 11 USB20_CH_N1 C454 C453 DLW21HN900HQ2L_4P 4
0606 add

G
2
0_0402_5% 4 FAULT# DM_IN 2 USB20_N1 22U_0603_6.3V6M 22U_0603_6.3V6M USB3_RX_N2_R 5 GND
[45] USB_CHG_ILIM_SEL USB_CHG_EN 5 ILIM_SEL DM_OUT 3 USB20_P1 USB20_N1 [12] USB3.0 With USB2.0 2 2 R3189 2 1 0_0402_5% USB3_RX_P2_R 6 SSRX- 10
C
[45] USB_CHG_EN USB_CHG_CTL1 6 EN DP_OUT 15 R77 1 AOU@ 2 20K_0402_1%
USB20_P1 [12] For Charge RF@ 7 SSRX+ GND 11 C
[45] USB_CHG_CTL1 USB_CHG_CTL2 CTL1 ILIM_LO USB3_TX_N2_C_R GND GND
7 16 R78 1 2 24.9K_0402_1% 8 12
[45] USB_CHG_CTL2 USB_CHG_CTL3 CTL2 ILIM_HI +5VL 0614 swap L2002,L2003 USB3_TX_P2_C_R SSTX- GND
8 14 AOU@ 9 13
[45] USB_CHG_CTL3 CTL3 GND SSTX+ GND
1 17 AOU@ R3190 2 RF@ 1 0_0402_5%
AOU@ T-PAD R446 1 2 ACON_TARAC-9U1U91
C76 TPS2546RTER QFN 16P
0.1U_0201_10V K X5R SA000064O00 100K_0402_5% L2003 @RF@
2 USB3_TX_N2 C481 2 1 USB3_TX_N2_C 2 1
[12] USB3_TX_N2 2 1
1 USB3.0 Connector PN

1
D
AOU@ 0.1U_0201_10V K X5R
[40,45,52,53,55] 3V/5VALW_PG
2 AOU@ C466 [12] USB3_TX_P2
USB3_TX_P2 2 1 USB3_TX_P2_C 3
3 4
4 DC23300AGB0
G Q29 .1U_0402_16V7K C480
2N7002K_SOT23-3 2 0.1U_0201_10V K X5R DLW21HN900HQ2L_4P
S

3
R3191 2 1 0_0402_5%
RF@

+5V_CHGUSB
USB3.0_Port +5V_CHGUSB

L11 EMI@
JUSB1 ME@ 4 3 USB20_N2_L
[12] USB20_N2 4 3
1
USB20_N1_L 2 VBUS
USB20_P1_L 3 D- 1 2 USB20_P2_L
D+ [12] USB20_P2 1 2
4
GND

150U_B2_6.3VM_R35M
USB3_RX_N1 5 EXC24CG900U_4P
[12] USB3_RX_N1 USB3_RX_P1 SSRX-
6 10
B [12] USB3_RX_P1 SSRX+ GND B
7 11 1 1 1
GND GND

10P_0402_25V8J
C75 2 1 0.1U_0201_10V K X5R USB3_TX_N1_C 8 12 @
[12] USB3_TX_N1 SSTX- GND

C247
C74 2 1 0.1U_0201_10V K X5R USB3_TX_P1_C 9 13 + C498 C246
[12] USB3_TX_P1 SSTX+ GND RF@ 470P_0402_50V7K
ACON_TARAC-9U1U91 2 2
2
0406 Change Conn
USB3.0 Connector PN
DC23300AGB0

ESD
D38 ESD@
USB20_N2_L 4 3 USB20_P2_L
4 3

ESD 4
D8
4
ESD@
3
3
+5V_USB
D39 ESD@
D43 ESD@ USB3_RX_N2_R 1 1 10 9 USB3_RX_N2_R
USB3_RX_N1 1 1 10 9 USB3_RX_N1 +5V_CHGUSB
USB3_RX_P2_R 2 2 9 8 USB3_RX_P2_R 5 2
USB3_RX_P1 2 2 USB3_RX_P1 Vbus GND
9 8
USB3_TX_N2_C_R 4 4 7 7 USB3_TX_N2_C_R
USB3_TX_N1_C 4 4 7 7 USB3_TX_N1_C
5 2 USB3_TX_P2_C_R 5 5 6 6 USB3_TX_P2_C_R
USB3_TX_P1_C 5 5 USB3_TX_P1_C Vbus GND
L13 EMI@ 6 6
A USB20_CH_P1 1 2 USB20_P1_L 3 3 A
1 2 3 3
8
USB20_CH_N1 4 3 USB20_N1_L 8 6 1
4 3 L05ESDL5V0NA-4_SLP2510P8-10-9 6 1
EXC24CG900U_4P L05ESDL5V0NA-4_SLP2510P8-10-9 SC300003Z00 L30ESDL5V0C6-4_SOT23-6
SC300003Z00 SC300004W00
USB20_N1_L 6 1 USB20_P1_L
6 1
L30ESDL5V0C6-4_SOT23-6
SC300004W00

Title
<Title>

Size Document Number Rev

Custom<Doc> <RevCode>

Date: Thursday, June 15, 2017 Sheet 34 of 66

5 4 3 2 1
 A B C D E

CX11802

2.2U_0402_6.3V6M

0.1U_0201_10V6K
1U_0402_6.3V6K

0.1U_0201_10V6K
1 1

C81

C82
1

1
C79

C80
2 2 R439 2 1 0_0402_5%

2
2

+5VS R440 2 1 0_0402_5%

GNDA GNDA +5VS_AVDD R81
+AVDD_CODEC 1 2 0_0603_5%
R441 2 1 0_0402_5%

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
+3VDD_CODEC 1 C455 2 2 1 1
C85 C86

0.1U_0201_10V K X5R

C83

C84
+IOVDD_CODEC R442 2 1 0_0402_5%

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
2 1 1 2 2
1 1
C88 2 1 4.7U_0603_6.3V6K GND GNDA

Vinafix.com

18

24

29

27

28

13
16

11
3

2
7
U60
Combo Jack

VDDO33
VDD_IO
DVDD33

CLASS_D_REF
FILT_1.8V

AVDD_HP

FILT_1.65V

AVDD_3.3V

AVDD_5V

LPWR5.0
RPWR5.0
HGNDB
HGNDA
[9] HDA_RST_AUDIO# 9
RESET# EXT_MIC_SLEEVER83 1 2 100_0402_5% C91 2 1 1U_0402_10V6K
2 1 1 R82 2
W=40mils EXT_MIC_RING2 R84 1 2 100_0402_5% C92 2 1 1U_0402_10V6K
C90 22P_0402_50V8J 33_0402_5% 38 PLUG_IN_R
W=40mils HP_OUTL 1 EMI@ 2 HPOUT_L
@EMI@ @EMI@ JSENSE HP_OUTR R85 1 EMI@ 2 47_0402_5% HPOUT_R
CX11802-33Z
[9] HDA_BITCLK_AUDIO 5 35 R86 47_0402_5%
8 BIT_CLK MICBIASC 34
[9] HDA_SYNC_AUDIO SYNC MICBIASB
1 R87 2 HDA_SDIN0_AUDIO 6
[9] HDA_SDIN0 SDATA_IN
[9] HDA_SDOUT_AUDIO 33_0402_5% 4 33
SDATA_OUT PORT_B_R_LINE 32
PORT_B_L_LINE
R88 1 2 0_0402_5% 39
[45] EC_MUTE# SPKR_MUTE#
2

26 HGNDB
R91 PC_BEEP 10 HGNDB 25 HGNDA
@ 10K_0402_5% PC_BEEP HGNDA 31 EXT_MIC_RING2
1 PORTD_B_MIC 30 EXT_MIC_SLEEVE
[28] DMIC_DAT DMIC_DAT/GPIO1 PORTD_A_MIC
[28] DMIC_CLK 1 R475 2 40
1

33_0402_5% DMIC_CLK/MUSIC_REQ/GPIO0
EMI@ 23 HP_OUTR
37
36 GPIO1/PORTC_R_MIC
PORTA_R
PORTA_L
22 HP_OUTL Combo Jack
MUSIC_REQ/GPIO0/PORTC_L_MIC (Normal Open)
2
SPK_L+ 12
LEFT+
AVEE
21 AVEE 1
wide 60MIL JHP1 ME@ 2
SPK_L- 14 20 HGNDB 1
LEFT- FLY_N 19 C95 1 2 1U_0402_6.3V6K C96 HPOUT_L R460 1 2 HPOUT_L1 4
SPK_R- 15 FLY_P 0_0402_5%
RIGHT- 2.2U_0402_6.3V6M
2

EP_GND
SPK_R+ 17 5
RIGHT+
place close audio codec
PLUG_IN 6
+3VS HPOUT_R R459 1 2 HPOUT_R1 3
41

CX11802-33Z_QFN40_5X5 0_0402_5%
HGNDA 2

1
R94
5.11K_0402_1% DC23000GT00
SINGA_2SJ3127-019111F
EMI

EMI@ C504 470P_0402_50V7K

EMI@ C483 10P_0603_50V8-J

EMI@ C484 10P_0603_50V8-J

EMI@ C485 10P_0603_50V8-J

EMI@ C482 10P_0603_50V8-J

2
Speaker PLUG_IN_R R96 1 2 13.3K_0402_1% PLUG_IN
1 1 1 1 1
ESD Audio Connector PN

3
2

3
Speaker Connector PN DC23000GT00
+3VS → +I OVDD_C ODEC wide 40MIL SP02000RR00
2 2 2 2 2
D40
D41
ESD@
ESD@ PESD5V0U2BT_SOT23-3
PESD5V0U2BT_SOT23-3
0405 Change net name

1
JSPK1 ME@

1
SPK_R+ R79 1 2 0_0603_5% SPK_R+_CONN 1
SPK_R- R80 1 2 0_0603_5% SPK_R-_CONN 2 1
SPK_L+ R421 1 2 0_0603_5% SPK_L+_CONN 3 2
+3VALW +IOVDD_CODEC SPK_L- R420 1 2 0_0603_5% SPK_L-_CONN 4 3
5 4
G1 GNDA
6
G2

EMI
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

R98 1 2 0_0603_5% ACES_50278-00401-001

2
3 1 1 1 1 3
C89

EMI@ C87

EMI@ C456

EMI@ C457

D9
@ESD@
2 2 2 2
Each Platform Power Net Support List：
EMI@

L03ESDL5V0CC3-2_SOT23-3
SCA00002900
0.1U_0201_10V6K

Place near Pin7

1 +1.5VS +1.8VS +3VS +5VS +3VALW
C99

1
3

2
1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5)
D37
@ESD@ AMD Carrizo V V V V V
L03ESDL5V0CC3-2_SOT23-3
SCA00002900 AMD Carrizo-L V V V V V
Intel Broadwell V V V V
ESD Intel Braswell V V V V V
1

Intel Skylake V V V V V
Intel Bay trail-M V V V V V

Each PlaP or m HDA Li nk Volt age Support ( Pi n 7)：

+AVDD_CODEC +3VDD_CODEC
PC Beep 3.3V 1.5V/1.8V
AMD Carrizo V
1 2 1 2 PC_BEEP
[45] BEEP#
R97 4.7K_0402_5% C97 0.1U_0201_10V K X5R AMD Carrizo-L V
[9] HDA_SPKR 1 2 1 2
R99 4.7K_0402_5% C98 0.1U_0201_10V K X5R Intel Broadwell V V
R101 1 2 0_0603_5%
+3VLP R102 1 2 0_0603_5%
+3VS Intel Braswell V
1U_0402_6.3V6K

0.1U_0201_10V6K

4 4
1U_0402_6.3V6K

1 Intel Skylake V V
1
C101

C102
1
C100

Intel Bay trail-M V

2

2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/09/01 Deciphered Date 2015/09/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC3240
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 35 of 66
A B C D E
 5 4 3 2 1

+3VALW +3V_LAN
R103 R104
2 1 2 1

60mil 0_0603_5% W=60mil 0_0603_5%

+LAN_VDD
L1
W=60mils 1.0V
+LAN_SROUT1.05 1 @ 2
2
2.2UH +-5% NLC252018T-2R2J-N Source LL1 CL16,CL17 CL9,CL10 RL11 CL15

0.1U_0201_10V K X5R
C103
Vinafix.com

4.7U_0603_6.3V6K
1
1U_0402_6.3V6K 1 1 RTL8111H LDO X X X O O
1 C104 @ @
0.1U_0201_10V K X5R C105 C106
2
D 2 2 D

Please refer to the table above when using different 1.0V supply source.

LL1, CL16, and CL17 close to Pin24

( Should be place within 200 mils )

+3VS

W=40mils +LAN_VDD
RJ-45 CONN.
Rising t i me ( 10 %~90 %) 0. 5 ms => +3V_L AN <=100 ms

1
+3V_LAN R105
2 1 +LAN_VDDREG R106
+3V_LAN

0.1U_0201_10V K X5R
1K_0402_5% JLAN1 ME@

4.7U_0603_6.3V6K
W=60mils

1U_0402_6.3V6K
0_0603_5%

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
1 1
C107 C113 1 1 1 1 1 12

2
GND

@
@ C109 C110 C117 C111 C112 ISOLATE# RJ45_TX3- 8
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
PR4- 11
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

1 1 1 1 2 2 GND
@ @ RJ45_TX3+ 7
C114 C115 C116 C108 2 2 2 2 2 PR4+
R107 RJ45_RX1- 6
2 2 2 2 15K_0402_5% PR2-
RJ45_TX2- 5
PR3-
Close to Pin23 RJ45_TX2+ 4
PR3+
Pin3 Pin8 Pin22 Pin30 Pin22 RJ45_RX1+ 3
Pin20 PR2+
RJ45_TX0- 2
PR1- 10
RJ45_TX0+ 1 GND
CL2 close to Pin 11, only 8107E LDO mode unpop PR1+ 9
CL3 close to Pin 32 GND
C C
SANTA_130460-3

LANGAN
LAN Connector PN
DC23400DP00
+LAN_VDD +LAN_VDD
U57
Close to Pin17 Pin18
LAN_MDIP0 1 17 PCIE_CRX_C_DTX_P5 C118 1 2 0.1U_0201_10V K X5R PCIE_CRX_DTX_P5 [12]
LAN_MDIN0 2 MDIP0 HSOP 18 PCIE_CRX_C_DTX_N5 C119 1 2 0.1U_0201_10V K X5R
MDIN0 HSON PCIE_CRX_DTX_N5 [12]
3 19
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# PCIRST# [10,21,27,31,32,45]
LAN_MDIN1 5 MDIP1 ISOLATEB 21
MDIN1 LANWAKEB EC_PCIE_WAKE# [31,45]
LAN_MDIP2 6 22
LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG
8 MDIN2 VDDREG 24 +LAN_SROUT1.05 +3V_LAN
LAN_MDIP3 9 AVDD10 REGOUT 25
LAN_MDIN3 10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPO 27 R108 10K_0402_5%
+3V_LAN AVDD33 LED0
12 28 XTLO
EMI [10] LANCLK_REQ#
[12] PCIE_CTX_C_DRX_P5
[12] PCIE_CTX_C_DRX_N5
13
14
15
CLKREQB
HSIP
HSIN
CKXTAL1
CKXTAL2
AVDD10
29
30
31 2.49K_0402_1% 2
XTLI

1 R109
reserved GPIO pin
EMI@ R110 1 2 0_0402_5% [10] CLK_PCIE_LAN 16 REFCLK_P RSET 32
[10] CLK_PCIE_LAN# REFCLK_N AVDD33 +3V_LAN
33
EMI@ R111 1 2 0_0402_5% GND

RTL8111H-CG_QFN32_4X4

LANGAN

@EMI@ C120 1 2 0.1U_0201_10V K X5R

B
@EMI@ C121 1 2 0.1U_0201_10V K X5R ESD B

D10 ESD@
LANGAN LAN_MDIN3 4 3 LAN_MDIP2
4 3

+V_DAC 1
TL1
24 MCT
EMI
+3V_LAN TCT1 MCT1 R112 C124

1
C122
2 XTLO
EMI LAN_MDIP0

LAN_MDIN0
2

3
TD1+ MX1+
23

22
RJ45_TX0+

RJ45_TX0-
1

75_0805_5%
2 1 2

0.01U_0402_25V7K
5 2 C123 TD1- MX1- EMI@
Vbus GND EMI@
10P_0402_50V8J 1 2 +V_DAC 4 21
TCT2 MCT2 LANGAN
0.01U_0402_25V7K LAN_MDIP1 5 20 RJ45_RX1+
TD2 MX2+
1

EMI@
Y1 LAN_MDIN1 6 19 RJ45_RX1-
OSC

NC

25MHZ_10PF_5YEA25000102IF50Q3 TD2- MX2-

+V_DAC 7 18 2 1
SJ10000E500 TCT3 MCT3
OSC

LAN_MDIP3 6 1 LAN_MDIN2 LAN_MDIP2 8 17 RJ45_TX2+ D11 EMI@

NC

6 1 TD3+ MX3+ BS4200N-C-LV_SMB-F2

L30ESDL5V0C6-4_SOT23-6 LAN_MDIN2 9 16 RJ45_TX2- SCV00001H00
2

TD3- MX3-
C125 SC300003V00 +V_DAC 10 15
1 2 XTLI TCT4 MCT4

10P_0402_50V8J
LAN_MDIN1 4
D12 ESD@
3 LAN_MDIP0
LAN_MDIP3

LAN_MDIN3
11

12
TD4+ MX4+
14

13
RJ45_TX3+

RJ45_TX3-
EMI
4 3 TD4- MX4-

NS892407

+3V_LAN
A A

FOR 10/100 data transferring 2013/08/27

5 2
Vbus GND

Security Classification Compal Secret Data Compal Electronics, Inc.

LAN_MDIP1 6 1 LAN_MDIN0 2011/06/24 2012/07/12 Title
6 1 Issued Date Deciphered Date
L30ESDL5V0C6-4_SOT23-6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_RTL8111H / RTL8107E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
SC300003V00 C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D061P
Date: Thursday, June 15, 2017 Sheet 36 of 66
5 4 3 2 1
 5 4 3 2 1

Card Reader

Vinafix.com
U62-1 U62-2
D D

X76@ X76@
GENSYS Cardreader RTS5146 Cardreader
SA0000AVM00 SA0000AW900

+CARD_3V3
JCR1 ME@
+CARD_3V3
+CARD_3V3 4
SD_CMD 2 VDD
U62 @ SD_CLK 1 EMI@ 2 SD_CLK_R 5 CMD
USB20_CR_N7 3 1 R471 0_0402_5% 3 CLK
USB20_CR_P7 4 DM AV18 7 C474 6 VSS1
DP CARD_3V3 1 1 C473 VSS2

0.1U_0201_10V K X5R

4.7U_0603_6.3V6K
SD_CD# 10 16 SDREG SD_D0 7
15 SD_CD# SDREG SD_D1 8 DAT0
+3VS MS_INS# 11 SD_WP 2 2 SD_D2 9 DAT1
SP1 2 2 DAT2
9 13 SD_D0 C475 C476 SD_D3 1
R457 SD_D1 12 GPIO SP2 14 1U_0402_6.3V6K CD/DAT3
SD_DAT1 SP3 1U_0402_6.3V6K
6.2K_0402_1% 17 12
R464 1 2 2 SP4 18 SD_CLK 1 1 GND 13
1 2 +3VS_CR 5 RREF SP5 19 SD_WP 11 GND 14
0_0402_5% 6 3V3_IN1 SP6 20 SD_CMD SD_CD# 10 W/P GND 15
8 3V3_IN2 SP7 21 CD GND
3V3_IN3 SP8 SD_D3
0.1U_0201_10V6K
4.7U_0402_6.3V6M

22 T-SOL_156-1001902605~D
SP9 Close to connector 1

5P_0402_50V9

C503 EMI@
C 24 23 SD_D2 C
48MHz_In SP10
2 2
25
GND

1
C478 C477 2
RTS5146-GR_ QFN24_4X4 R472
Cardreader Connector PN
1 1
SA0000AW900 0_0402_5% SP07001AC10
X76@

2
Cardreader RTS5146 PN
SA0000AW900

EMI@
R455 2 1 0_0402_5%

L15 @EMI@
4 3 USB20_CR_N7
[12] USB20_N7 4 3

1 2 USB20_CR_P7
[12] USB20_P7 1 2
EXC24CG900U_4P

EMI@
R456 2 1 0_0402_5%

B B

A A

0329 move

Title
<Title>

Size Document Number Rev

Custom<Doc> <RevCode>

Date: Thursday, June 15, 2017 Sheet 37 of 66

5 4 3 2 1
 5 4 3 2 1

+3VS +3VS +3VS

Vinafix.com

100K_0402_5%

100K_0402_5%
0.01U_0201_6.3V7K

0.01U_0201_6.3V7K
0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

1
1 2 2 2 1

TYPEC@
+3VS
C126 C127 C128 C129 C130
D D
2 1 1 1 2

R113 2

R438 2
2.2K_0201_5%

2.2K_0201_5%

4.7K_0201_5%
1

1
U13

R114 2

R115 2

R116 2
5
21 VDD33 50
VDD33 OUT1_D0p DMUX_TYPEC_DP2_P0 [40]
30 49
VDD33 OUT1_D0n DMUX_TYPEC_DP2_N0 [40]
51
57 VDD33 47
VDD33 OUT1_D1p DMUX_TYPEC_DP2_P1 [40]
46
OUT1_D1n DMUX_TYPEC_DP2_N1 [40]
C131 1 2 0.1U_0201_6.3V6K DDIP2_0P_C 6 45 Type-C MUX
[6] DDI2_TX0+_CK DDIP2_0N_C IN_D0p OUT1_D2p DMUX_TYPEC_DP2_P2 [40]
C132 1 2 0.1U_0201_6.3V6K 7 44
[6] DDI2_TX0-_CK IN_D0n OUT1_D2n DMUX_TYPEC_DP2_N2 [40]
C133 1 2 0.1U_0201_6.3V6K DDIP2_1P_C 9 42
[6] DDI2_TX1+_CK DDIP2_1N_C IN_D1p OUT1_D3p DMUX_TYPEC_DP2_P3 [40]
C134 1 2 0.1U_0201_6.3V6K 10 41
[6] DDI2_TX1-_CK IN_D1n OUT1_D3n DMUX_TYPEC_DP2_N3 [40]
C135 1 2 0.1U_0201_6.3V6K DDIP2_2P_C 12
[6] DDI2_TX2+_CK DDIP2_2N_C IN_D2p
C136 1 2 0.1U_0201_6.3V6K 13 40
[6] DDI2_TX2-_CK IN_D2n OUT2_D0p DMUX_CRT_DP2_P0 [39]
39
DDIP2_3P_C OUT2_D0n DMUX_CRT_DP2_N0 [39]
C137 1 2 0.1U_0201_6.3V6K 15 CTR MUX
[6] DDI2_TX3+_CK DDIP2_3N_C IN_D3p
C138 1 2 0.1U_0201_6.3V6K 16 37
[6] DDI2_TX3-_CK IN_D3n OUT2_D1p DMUX_CRT_DP2_P1 [39]
36
OUT2_D1n DMUX_CRT_DP2_N1 [39]
35
4 OUT2_D2p 34
3 IN_CA_DET OUT2_D2n
[6] DDIP2_HPD IN_HPD
2 32
@ TP1 PS8338_PI1 1 I2C_CTL_EN OUT2_D3p 31
PS8338_PI0 60 Pl1/SCL_CTL OUT2_D3n
Pl0/SDA_CTL
0223 link to Type-C MUX
26 +3VS
OUT1_AUXp_SCL DMUX_TYPEC_DP2_AUXP [40]
22 27
[6] DDIP2_CTRLCLK IN_DDC_SCL OUT1_AUXn_SDA DMUX_TYPEC_DP2_AUXN [40]
C 23 C
[6] DDIP2_CTRLDATA DDIP2_AUXP_C IN_DDC_SDA
C139 1 2 0.1U_0201_6.3V6K 24 28
[6] DDIP2_AUXP IN_AUXp OUT2_AUXp_SCL DMUX_CRT_DP2_AUXP [39]

2
C140 1 2 0.1U_0201_6.3V6K DDIP2_AUXN_C 25 29
[6] DDIP2_AUXN IN_AUXn OUT2_AUXn_SDA DMUX_CRT_DP2_AUXN [39]
R117
59 43 @ 4.7K_0201_5%
58 CFG0 OUT1_CA_DET 48
PS8338_PC10 CFG1 OUT1_HPD DMUX_TYPEC_DP2_HPD [40]
56

1
PS8338_PC11 55 PC10 33
PS8338_PC20 54 PC11 OUT2_CA_DET 38
PS8338_PC21 PC20 OUT2_HPD DMUX_CRT_DP2_HPD [39]
53
PC21 18
SW PS8338_PEQ DDI_PRIORITY [9]
11 8
19 GND PEQ 14
52 GND PD 17
61 GND CEXT 20
PAD(GND) REXT

R118 TYPEC@

R437
R119

R120

C141

R121
PS8338BQFN60GTR-A0_QFN60_5X9
PS8338BQFN60GTR-A1_QFN60_5X9

1
2

2
R415
150K_0402_5%
1

2
1M_0201_5%

4.99K_0201_1%

1
2.2U_0402_6.3V6M

1M_0201_5%

100K_0402_5%

100K_0402_5%
PEQ
(INT PD) R122 R123
+3VS TABLE : Automatic Switching Mode (CFG0 = H)
HEQ 14.5dB ASM NO_ASM
SW (DDI_PRIORITY2)
LLEQ 8.5dB ASM ASM R122 1 @ 2 4.7K_0201_5% PS8338_PEQ R123 1 @ 2 4.7K_0201_5%
L Port 1 has higher priority when both ports are plugged
LEQ 11.5dB NO_ASM NO_ASM LOGIC R124 1 @ 2 4.7K_0201_5% PS8338_PC10 R125 1 @ 2 4.7K_0201_5% H Port 2 has higher priority when both ports are plugged
B B

R126 1 @ 2 4.7K_0201_5% PS8338_PC11 R127 1 @ 2 4.7K_0201_5%

PC10 PC20 R128 1 @ 2 4.7K_0201_5% PS8338_PC20 R129 1 @ 2 4.7K_0201_5%

(INT PD) (INT PD)
R130 1 @ 2 4.7K_0201_5% PS8338_PC21 R131 1 @ 2 4.7K_0201_5%

R124 R125 R128 R129 R132 1 @ 2 4.7K_0201_5% PS8338_PI1 R133 1 @ 2 4.7K_0201_5%

PI1
R134 1 @ 2 4.7K_0201_5% PS8338_PI0 (INT PD) R132 R133
AUX interception DIS
Output 800mV & 0dB ASM NO_ASM ASM NO_ASM
Auto test EN
& Offset cancellation EN ASM NO_ASM
AUX interception DIS
Output 400mV & 0dB ASM ASM ASM ASM
Auto test DIS
& Offset cancellation DIS ASM ASM
AUX interception EN NO_ASM NO_ASM NO_ASM NO_ASM LOGIC

Auto test DIS

& Offset cancellation EN NO_ASM NO_ASM LOGIC

PC11 PC21
(INT PD) (INT PD)
PI0
(INT PD) R134
R126 R127 R130 R131
A A
Auto EQ DIS ASM
Swing +20% ASM NO_ASM ASM NO_ASM
Auto EQ EN NO_ASM LOGIC

Swing -16.7% ASM ASM ASM ASM

Security Classification Compal Secret Data Compal Electronics, Inc.

Swing default NO_ASM NO_ASM NO_ASM NO_ASM LOGIC
2014/11/04 2016/12/31 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDI DEMULTIPLEXER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C581P
Date: Thursday, June 15, 2017 Sheet 38 of 66
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

+3VS +3VS_AVCC +3VS_VDD +3VS

R137 1 2 0_0402_5% +3VS_AVCC +3VS_VDD 0_0402_5% 2 1 R138

0.1U_0201_10V K X5R
2

C142
+3VS +5V_DSP
+3VS

Pin 4 & 25 Need conect same

net name(VCCK12) for vendor suggest U14
C 1 20 2.2U_0402_6.3V6M 1 2 C143 C
C144 2 1 0.1U_0201_10V K X5R VCCK_12 4 AVC33 VDD_DAC_33
14 AVCC_12 25 VCCK_12 0.1U_0201_10V K X5R 1 2 C149
VCC_33 VCCK_12

[38] DMUX_CRT_DP2_AUXP C145 1 2 0.1U_0201_10V K X5R DP_CRT_AUXP 2 26 0.1U_0201_10V K X5R 1 2 C150

C146 1 2 0.1U_0201_10V K X5R DP_CRT_AUXN 3 AUX_P PVCC_33
[38] DMUX_CRT_DP2_AUXN AUX_N 4.7U_0805_25V6-K 1 2 C147
C148 1 2 0.1U_0201_10V K X5R DP_CRT_P0 5 17 0.1U_0201_10V K X5R 1 2 C151
[38] DMUX_CRT_DP2_P0 LANE0_P HVSYNC_PWR
C152 1 2 0.1U_0201_10V K X5R DP_CRT_N0 6 18 VSYNC
[38] DMUX_CRT_DP2_N0 LANE0_N VSYNC
C153 1 2 0.1U_0201_10V K X5R DP_CRT_P1 7 19 HSYNC
[38] DMUX_CRT_DP2_P1 LANE1_P HSYNC
C154 1 2 0.1U_0201_10V K X5R DP_CRT_N1 8
[38] DMUX_CRT_DP2_N1 LANE1_N
+3VS

R139
POL1_SDA
POL2_SCL
10
9 POL1/SPI_CEB
POL2
RTD2166 BLUE_P
21

22
CRT_B

CRT_G
1 @ 2 4.7K_0402_5% 11 GREEN_P
12 GPI1/SPI_CLK 23 CRT_R
13 GPI2/SPI_SI RED_P
GPI3/SPI_SO
CRT_CLK 15 VSYNC R3182 1 2 47_0402_5% CRT_VSYNC
CRT_DATA 16 VGA_SCL
VGA_SDA 27 LDO_EN HSYNC R3183 1 2 47_0402_5% CRT_HSYNC
0_0402_5% 2 @ 1 R140 CRT_SMB_CLK 30 LDO_RSTB 28
[8,22,45,46] SOC_SML1CLK SMB_SCL EXT_CLK_IN
[8,22,45,46] SOC_SML1DATA 0_0402_5% 2 @ 1 R141 CRT_SMB_SDA 29 31
SMB_SDA EXT1.2V_CTRL

C536 2P_0201_25V8B

C537 2P_0201_25V8B
1 1
[38] DMUX_CRT_DP2_HPD 32 24
HPD GND 33
100K_0402_5% 2 @ 1 R142 EPAD_GND
RTD2166-CG_QFN32_4X4 2 2 +5V_DSP

2 2.2K_0402_5%

2 2.2K_0402_5%
+3VS +3VS
B B

ESD
1

+3VS
R143 R144
EMI
4.7K_0402_5%

4.7K_0402_5% @ 4.7K_0402_5% D13 ESD@

1

CRT_CLK 4 3 HSYNC
4 3
R445

CRT
2

R145 1

R146 1
POL2_SCL POL1_SDA
+5V_DSP JVGA1 ME@
LDO_EN:
2

L2 SM01000LU00 6
0: External 1.2V input
1

LDO_EN MURATA BLM15BA220SN1D 0402 11

R444 1: Internal 1.2V input CRT_R EMI@ 1 2 CRT_R_2 1
4.7K_0402_5% L3 SM01000LU00 7
5 2 MURATA BLM15BA220SN1D 0402 CRT_DATA 12
Vbus GND CRT_G EMI@ 1 2 CRT_G_2 2
2

L4 SM01000LU00 8
MURATA BLM15BA220SN1D 0402 CRT_HSYNC 13
CRT_B EMI@ 1 2 CRT_B_2 3
9
CRT_VSYNC 14

R3155

R3156

R3157

EMI@

10P_0603_50V8-J

EMI@

10P_0603_50V8-J

EMI@

10P_0603_50V8-J

EMI@

10P_0603_50V8-J

EMI@

10P_0603_50V8-J

EMI@

10P_0603_50V8-J
4 G 16
R143+R144 : Flash Mode 1 1 1 1 1 1 10 G 17

C155

C156

C157

C467

C468

C469
VSYNC 6 1 CRT_B_2 CRT_CLK 15
6 1

1
5
R143+R444 : ROM Mode Default
L30ESDL5V0C6-4_SOT23-6 2 2 2 2 2 2

75_0402_1%

75_0402_1%

75_0402_1%
CCM_070546HR015M28BZR
SC300003V00

2
D14 ESD@
CRT_R_2 4 3 CRT_DATA
4 3

CRT Connector PN
+5V_DSP DC06000C0B0
A A

5 2
Vbus GND

Security Classification Compal Secret Data Compal Electronics, Inc.

CRT_G_2 6 1 2014/08/16 2015/08/16 Title
6 1 Issued Date Deciphered Date
L30ESDL5V0C6-4_SOT23-6
DP to VGA - RTD2168
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
SC300003V00 Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D061P
Date: Thursday, June 15, 2017 Sheet 39 of 66
5 4 3 2 1
 5 4 3 2 1

dead battery
PD VIN 3.3V LDO
+VBUS_5455 +LDO_VIN +3.3V_IN_5455

U22 TYPEC@
R149 1 2 0_0402_5% 1 5
VIN VOUT

10U_0402_6.3V6M

10U_0402_6.3V6M
TYPEC@

C165

C166
R150 1 1

Vinafix.com 1M_0402_5%

TYPEC@

TYPEC@
2
TYPEC@ GND

2
2 2
3 4
D EN ADJ/NC D

6
AP2204K-3.3TRG1_SOT23-5

0.1U_0402_50V7K
1

TYPEC@

C162
[34,45,52,53,55] 3V/5VALW_PG 2

Q32A 2

1
L2N7002DW1T1G 2N SC88-6
TYPEC@

+3VALW Q33 TYPEC@

ME2301DC-G_SOT23-3

R3171 1 2 0_0402_5% 1 3

S
TYPEC@

G
1 2

1
+3.3V_IN_5455
R3172 R3173
100_0402_5% 200K_0402_1% +5VALW
TYPEC@ TYPEC@ +VBUS_5455

1
+5VALW +VCON_IN_5455

2
TYPEC@ R3179

2
1 R3175 2 10K_0402_5%
R147 1 2 0_0603_5% 3V/5VALW_PG 5 Q32B 0_0603_5% TYPEC@
+5VALW

10U_0603_6.3V6M
C159

10U_0603_25V6M
C532
TYPEC@ L2N7002DW1T1G 2N SC88-6 1 2

2
10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 TYPEC@ OCP_DET_5455

4
C158

C217

Q1 TYPEC@ TYPEC@
TYPEC@ TYPEC@ TYPEC@ U15 TYPEC@
Close to Pin10

1
LP2301ALT1G_SOT23-3 2 1 13 1
IN OUT
1

2
2 2 D
R245
GPIO9 2 @ 47K_0402_5%
G R220 @
S 0_0402_5% VBUS_EN_5455 2 12 VLIM_1114
3

2
EN VLIM
1

R219 FRS_5455 FRS_5455 3 11 ILIM_1113

47K_0603_1% Dead battery function Cfig. pin. FRS ILIM

1
TYPEC@ 6 10
SYMBOL Tie to GND to disable dead battery ‘ Rd’ . R244 VBUS_DSCHG 7 DISC1 DV/DT
2

C DISC2 C
Floating to enable dead battery ‘ Rd’ 100K_0402_5% 9 IMON_1113
PD+MUX @ 5
VREG
IMON

0.1U_0402_50V7K
Support 3.3V IN version @ 1 8 OCP_DET_5455
DB_CFG R157 1 2 0_0402_5%

2
FAULTB

TYPEC@

C533
U16 TYPEC@
+LDO_3V3_5455 +3.3V_IN_5455 R3176
4 14
+VCON_IN_1_5455 100K_0402_5% GND SRC
10 Realtek TYPEC@
VCON_IN TYPEC@

1
2

C535 100P_0402_25V8K

C534 1000P_0402_50V7K
TYPEC@ 20 C168 1 2 220P_0402_25V8J DPS1113FIA-13_QFN18_4X4 1 1
RTS5455 DB_CFG

TYPEC@

TYPEC@
R156 1 2 0_0402_5% 25 R3180 R3177 R3178

2
C167 TYPEC@ 5V_IN 9 PD_CC1 100K_0402_5% 27K_0402_5% 54.9K_0402_1%
CC1 PD_CC1 [41]
2 1 26 11 PD_CC2 TYPEC@ TYPEC@ TYPEC@
LDO_3V3 CC2 PD_CC2 [41] 2 2
4.7U_0603_6.3V6K C169 1 2 220P_0402_25V8J

2
TYPEC@ C170 1 2 0.22U_0402_10V6K USB3_RX_P4_C 39 ISP Channel via CCs TYPEC@
[12] USB3_RX_P4 SSRX_1P/2N
TYPEC@ C171 1 2 0.22U_0402_10V6K USB3_RX_N4_C 40 TYPEC@
[12] USB3_RX_N4 SSRX_1N/2P 15 USB3_DP_MTX_DRX_P2 C172 2 1 0.22U_0402_16V7K USB3_DP_MTX_C_DRX_P2
C_TX2_1P/2N USB3_DP_MTX_C_DRX_P2 [41]
TYPEC@ C173 1 2 0.22U_0402_10V6K USB3_TX_P4_C 41 14 USB3_DP_MTX_DRX_N2 C174 2 1 0.22U_0402_16V7K USB3_DP_MTX_C_DRX_N2
From USB3.1 [12] USB3_TX_P4
TYPEC@ C175 1 2 0.22U_0402_10V6K USB3_TX_N4_C 42 SSTX_1P/2N C_TX2_1N/2P USB3_DP_MTX_C_DRX_N2 [41]
[12] USB3_TX_N4 SSTX_1N/2P TYPEC@
19 USB3_DP_MRX_DTX_P2
C_RX2_1P/2N USB3_DP_MRX_DTX_P2 [41]
TYPEC@ C176 1 2 0.1U_0201_6.3V6KDMUX_TYPEC_DP2_P0_C 35 18 USB3_DP_MRX_DTX_N2
USB3_DP_MRX_DTX_N2 [41]
[38] DMUX_TYPEC_DP2_P0 DP0_1P/2N C_RX2_1N/2P
TYPEC@ C177 1 2 0.1U_0201_6.3V6KDMUX_TYPEC_DP2_N0_C 36 10Gps 3:2 MUX
[38] DMUX_TYPEC_DP2_N0 DP0_1N/2P TYPEC@
TYPEC@ C178 1 2 0.1U_0201_6.3V6KDMUX_TYPEC_DP2_P1_C 43 13 USB3_DP_MTX_DRX_P1 C179 2 1 0.22U_0402_16V7K USB3_DP_MTX_C_DRX_P1 USB3_DP_MTX_C_DRX_P1 [41]
[38] DMUX_TYPEC_DP2_P1 DP1_1P/2N C_TX1_1P/2N
TYPEC@ C180 1 2 0.1U_0201_6.3V6KDMUX_TYPEC_DP2_N1_C 44 12 USB3_DP_MTX_DRX_N1 C181 2 1 0.22U_0402_16V7K USB3_DP_MTX_C_DRX_N1 USB3_DP_MTX_C_DRX_N1 [41]
[38] DMUX_TYPEC_DP2_N1 DP1_1N/2P C_TX1_1N/2P
From DP MUX TYPEC@ C182 1 2 0.1U_0201_6.3V6KDMUX_TYPEC_DP2_P2_C 45 TYPEC@
[38] DMUX_TYPEC_DP2_P2 DP2_1P/2N
TYPEC@ C183 1 2 0.1U_0201_6.3V6KDMUX_TYPEC_DP2_N2_C 46 17 USB3_DP_MRX_DTX_P1
USB3_DP_MRX_DTX_P1 [41]
[38] DMUX_TYPEC_DP2_N2 DP2_1N/2P C_RX1_1P/2N USB3_DP_MRX_DTX_N1
16 USB3_DP_MRX_DTX_N1 [41]
TYPEC@ C184 1 2 0.1U_0201_6.3V6KDMUX_TYPEC_DP2_P3_C 37 C_RX1_1N/2P
[38] DMUX_TYPEC_DP2_P3 DP3_1P/2N
TYPEC@ C185 1 2 0.1U_0201_6.3V6KDMUX_TYPEC_DP2_N3_C 38
[38] DMUX_TYPEC_DP2_N3 DP3_1N/2P

TYPEC@ C186 1 2 0.1U_0201_10V6K SOC_DP1_AUXP_C 1 3 AUX_SBU1

[38] DMUX_TYPEC_DP2_AUXP AUX_P/MGPIO4 SBU1/MGPIO6 AUX_SBU1 [41]
TYPEC@ C187 1 2 0.1U_0201_10V6K SOC_DP1_AUXN_C 2 4 AUX_SBU2
[38] DMUX_TYPEC_DP2_AUXN AUX_N/MGPIO5 Low Speed MUX SBU2/MGPIO7 AUX_SBU2 [41]

TO SOC DMUX_TYPEC_DP2_HPD 34
[38] DMUX_TYPEC_DP2_HPD HPD
ISP Channel via USB Billboard
1

5 7
R171 H_DP/DCI_DATA/MGPIO2 BC1.2 Switch C_DP/BB_DP VBUS_DSCHG
6 8
100K_0402_5% H_DM/DCI_CLK/MGPIO3 C_DM/BB_DM
B B
TYPEC@ EC_SMB_DA2 31 30 SNK_PS_EN
[45] EC_SMB_DA2 SM_SDA/GPIO6 I2C_SCL/GPIO7 SNK_PS_EN [50]
EC_SMB_CK2 32 29 FRS_5455
[45] EC_SMB_CK2
2

PD_INT 33 SM_SCL/GPIO5 I2C_SDA/GPIO8 28 GPIO9

[45] PD_INT SM_INT/GPIO4 I2C_INT/GPIO9 27 VBUS_EN_5455
I2C_EN/GPIO10
AUX_SBU1
24 22 OCP_DET_5455
REXT MGPIO8/ IMON AUX_SBU2
21 VMON_5455
MGPIO9/ VMON
47 23 LOC_PWR_MON
1

R164 E-PAD MGPIO10/ LOC_PWR_MON

1
6.2K_0402_1% +LDO_3V3_5455 +5VALW
TYPEC@ RTS5455-GR_QFN46_6P5X4P5 R163 R165
1M_0402_5% 1M_0402_5%
@ @ +VBUS_5455
2

1
1
R224
R169 R221 @ 590K_0402_1%
200K_0402_1% 10K_0402_5% TYPEC@
TYPEC@ SD034590380

2
2
VMON_5455 LOC_PWR_MON

2
R172
R223
VBUS Discharge 10K_0402_1%
TYPEC@
R222 10K_0402_5%
10K_0402_5% TYPEC@

2
TYPEC@

1
+VBUS_5455
1

0314_Add
R168 Connect 'LOC_PWR' net to local power for F/W to
decide if C port can become provider via PR_SWAP.
100_2010_1% Leave floating if no local power exists in the
@ system or in the application that 545x can only
A be powered on by local power. A
2
1

D
VBUS_DSCHG 2 Q9 @
G IRLML2030TRPBF_SOT23-3
SB00001J300
1

S
3

R173
100K_0402_5%
@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

Close to USB typeC(JTYPEC2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Type-C_RTS5455
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E521P
Date: Thursday, June 15, 2017 Sheet 40 of 63
5 4 3 2 1
 5 4 3 2 1

+VBUS_5455_CONN +VBUS_5455_CONN

JUSBC1 ME@ EXC24CG900U_4P

A1 B12 USB20_P4 4 3 USB20_P4_L
GND GND [12] USB20_P4 4 3

[40] USB3_DP_MTX_C_DRX_P1 USB3_DP_MTX_C_DRX_P1 A2 B11 USB3_DP_MRX_DTX_P1 USB3_DP_MRX_DTX_P1 [40]

Vinafix.com
USB3_DP_MTX_C_DRX_N1 A3 SSTXP1 SSRXP1 B10 USB3_DP_MRX_DTX_N1 USB20_N4 1 2 USB20_N4_L
[40] USB3_DP_MTX_C_DRX_N1 SSTXN1 SSRXN1 USB3_DP_MRX_DTX_N1 [40] [12] USB20_N4 1 2
C188 1 2 0.47U_0402_25V6K A4 B9 C189 1 2 0.47U_0402_25V6K L5 EMI@
TYPEC@ VBUS VBUS TYPEC@
PD_CC1_CONN A5 B8 AUX_SBU2_CONN
D CC1 SBU2 D
USB20_P4_L A6 B7 USB20_N4_L
USB20_N4_L A7 DP1 DN2 B6 USB20_P4_L D44 ESD@
DN1 DP2 USB3_DP_MTX_C_DRX_P1 1 1 USB3_DP_MTX_C_DRX_P1
10 9
AUX_SBU1_CONN A8 B5 PD_CC2_CONN

Bottom
SBU1 CC2 USB3_DP_MTX_C_DRX_N1 2 2 USB3_DP_MTX_C_DRX_N1
9 8

TOP
C190 1 2 0.47U_0402_25V6K A9 B4 C191 1 2 0.47U_0402_25V6K
VBUS VBUS USB3_DP_MRX_DTX_N2 4 4 USB3_DP_MRX_DTX_N2
TYPEC@ TYPEC@ 7 7
USB3_DP_MRX_DTX_N2 A10 B3 USB3_DP_MTX_C_DRX_N2
[40] USB3_DP_MRX_DTX_N2 SSRXN2 SSTXN2 USB3_DP_MTX_C_DRX_N2 [40]
USB3_DP_MRX_DTX_P2 A11 B2 USB3_DP_MTX_C_DRX_P2 USB3_DP_MRX_DTX_P2 5 5 6 6 USB3_DP_MRX_DTX_P2
[40] USB3_DP_MRX_DTX_P2 SSRXP2 SSTXP2 USB3_DP_MTX_C_DRX_P2 [40]
A12 B1 3 3
GND GND
8
1 2
3 GND GND 4
5 GND GND 6 L05ESDL5V0NA-4_SLP2510P8-10-9
GND GND
SC300003Z00
DRAPH_UB11126-A5A0B-1H
D46 ESD@
USB3_DP_MRX_DTX_P1 1 1 10 9 USB3_DP_MRX_DTX_P1

USB3_DP_MRX_DTX_N1 2 2 9 8 USB3_DP_MRX_DTX_N1
Type-C Connector PN USB3_DP_MTX_C_DRX_N2 4 4 7 7 USB3_DP_MTX_C_DRX_N2
TMP DC231703291
USB3_DP_MTX_C_DRX_P2 5 5 6 6 USB3_DP_MTX_C_DRX_P2

3 3

L05ESDL5V0NA-4_SLP2510P8-10-9
SC300003Z00
U64 TYPEC@ +VBUS_5455_CONN
C
7 ESD for USBC1 Lines and Control C

RPD_G1
6
lines
RPD_G2 D45 ESD@

2
4 3
PD_CC1 12 4 PD_CC1_CONN D25 4 3
[40] PD_CC1 CC1 C_CC1 PESD24VS2UT_SOT23-3
[40] PD_CC2 PD_CC2 11 TPD8S300 5 PD_CC2_CONN ESD@ 0612 change
CC2 C_CC2
AUX_SBU1 15 1 AUX_SBU1_CONN
[40] AUX_SBU1

1
SBU1 C_SBU1 +5VALW
AUX_SBU2 14 2 AUX_SBU2_CONN
[40] AUX_SBU2 SBU2 C_SBU2
5 2
Vbus GND
20
D1
TYPEC@ 19
+LDO_3V3_5455 0.1U_0402_50V7K 2 1 C192 3 D2
VBIAS 17
10 D3
VPWR 16
D4 USB20_N4_L 6 1 USB20_P4_L
R174 6 1
TYPEC@ 2 1 9 18 L30ESDL5V0C6-4_SOT23-6
FLT GND1 8 SC300004W00
1 GND2 13
C193 10K_0201_5% GND3 21
PAD
0.1U_0201_6.3V6K
2 TYPEC@
TPD8S300_QFN20_3X3

B B
PD_CC1 R3192 1 @ESD@ 2 0_0201_5% PD_CC1_CONN

PD_CC2 R3193 1 @ESD@ 2 0_0201_5% PD_CC2_CONN

AUX_SBU1 R3194 1 @ESD@ 2 0_0201_5% AUX_SBU1_CONN

AUX_SBU2 R3195 1 @ESD@ 2 0_0201_5% AUX_SBU2_CONN

PD_CC1 AUX_SBU1
PD_CC2 AUX_SBU2
3

D50 D51

ESD@ ESD@
PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
1

A A

Security Classification Compal Secret Data

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Type-C_RTS5455_CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 15, 2017 Sheet 41 of 63
5 4 3 2 1
 5 4 3 2 1

+5VALW
+VCON_IN_5441 +5VALW +5V_IN_5441

R176 1 2 0_0603_5% R177 1 2 0_0603_5%

Vinafix.com
D D

+5V_IN_5441

CC1_5441 CC2_5441 +VCON_IN_5441 +LDO_3V3_5441

1 1
1 1 1 1
C198 C199
220P_0402_25V8J 220P_0402_25V8J C196 C197 C200 C201
2 2 0.1U_0201_10V K X5R 4.7U_0603_6.3V6K 10U_0603_6.3V6M 0.1U_0201_10V K X5R
2 2 2 2

13

19

20
U18
USB3_MRX_DTX_P1 1

VCON_IN

5V_IN

LDO_3V3
[43] USB3_MRX_DTX_P1 USB3_MRX_DTX_N0 C_RX2_1N/2P CC2_5441
2 14
[43] USB3_MRX_DTX_N0 USB3_MRX_DTX_P0 C_RX1_1P/2N CC2 VBUS_EN_5441 CC2_5441 [43]
3 15
[43] USB3_MRX_DTX_P0 USB3_RX_N3 USB3_RX_N3_C C_RX1_1N/2P VBUS_EN OCP_DET_5441
C202 1 2 0.1U_0201_10V6K 4 16
[12] USB3_RX_N3 USB3_RX_P3 USB3_RX_P3_C SSRX_1P/2N OCP_DET VMON_5441
C204 1 2 0.1U_0201_10V6K 5 17
[12] USB3_RX_P3 USB3_TX_N3 USB3_TX_N3_C SSRX_1N/2P VMON
C203 1 2 0.1U_0201_10V6K 6 18 1 2
[12] USB3_TX_N3 USB3_TX_P3 USB3_TX_P3_C SSTX_1P/2N REXT
C205 1 2 0.1U_0201_10V6K 7 R178 6.2K_0402_1%
[12] USB3_TX_P3 USB3_MTX_C_DRX_N0C206 USB3_MTX_DRX_N0 SSTX_1N/2P
1 2 0.1U_0201_10V6K 8
[43] USB3_MTX_C_DRX_N0 USB3_MTX_C_DRX_P0C207 USB3_MTX_DRX_P0 C_TX1_1P/2N TYPEC_LIMIT_CTL1
1 2 0.1U_0201_10V6K 9 21 TYPEC_LIMIT_CTL1 [45]
[43] USB3_MTX_C_DRX_P0 USB3_MTX_C_DRX_P1C208 USB3_MTX_DRX_P1 C_TX1_1N/2P RP_SEL_M1 TYPEC_LIMIT_CTL0
1 2 0.1U_0201_10V6K 10 22 TYPEC_LIMIT_CTL0 [45]
[43] USB3_MTX_C_DRX_P1 USB3_MTX_C_DRX_N1C209 USB3_MTX_DRX_N1 C_TX2_1N/2P RP_SEL_M0
1 2 0.1U_0201_10V6K 11 23
[43] USB3_MTX_C_DRX_N1 CC1_5441 C_TX2_1P/2N NC USB3_MRX_DTX_N1
[43] CC1_5441 12 24 USB3_MRX_DTX_N1 [43]
CC1 C_RX2_1P/2N 25
GND

RTS5448-GR QFN 24P TYPE-C

Change to RTS5448 for Customer request
Pin to Pin with RTS5441
0419B
C C

+LDO_3V3_5441 +LDO_3V3_5441

0 0 OFF Mode
2

R225 R226
4.7K_0402_5% 4.7K_0402_5%
1

TYPEC_LIMIT_CTL1 TYPEC_LIMIT_CTL0
1

R184 @ R185 @
10K_0402_5% 10K_0402_5%
2

Rp configuration

+VBUS_5441 +5V_IN_5441 +5V_IN_5441

1
1

R188
R186 R187 @ 10K_0402_5%
200K_0402_1% 10K_0402_5%
2

B B
2

VMON_5441 VBUS_EN_5441 OCP_DET_5441

1

+5VALW +VBUS_5441
@
R189 R190 R191
10K_0402_5% 10K_0402_5% 10K_0402_5%

22U_0603_6.3V6M
C529

0.1U_0603_16V7K
C211
2 2
2

U21
5 1 1 1
IN OUT
For C_VBUS For C_VBUS
power switch enable pin power switch enable pin OCP_DET_5441 3
VBUS_EN_5441 4 FLAG 2
EN(#EN) GND
G518A1TO1U TSOT-23 5P
SA0000AOU00

10U_0603_6.3V6M
C210
1
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Type-C_RTS5441
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C581P
Date: Thursday, June 15, 2017 Sheet 42 of 63
5 4 3 2 1
 5 4 3 2 1

L7 EMI@
USB20_P3 1 2 USB20_P3_L
[12] USB20_P3 1 2

USB20_N3 4 3 USB20_N3_L
[12] USB20_N3 4 3
+VBUS_5441 +VBUS_5441 EXC24CG900U_4P

JUSBC2
Vinafix.com
ME@
A1 B12 D47 ESD@
D GND GND USB3_MTX_C_DRX_P0 1 1 USB3_MTX_C_DRX_P0 D
10 9
USB3_MTX_C_DRX_P0 A2 B11 USB3_MRX_DTX_P0
[42] USB3_MTX_C_DRX_P0 SSTXP1 SSRXP1 USB3_MRX_DTX_P0 [42]
USB3_MTX_C_DRX_N0 A3 B10 USB3_MRX_DTX_N0 USB3_MTX_C_DRX_N0 2 2 9 8 USB3_MTX_C_DRX_N0
[42] USB3_MTX_C_DRX_N0 SSTXN1 SSRXN1 USB3_MRX_DTX_N0 [42]
C213 1 2 0.47U_0402_25V6K A4 B9 C214 1 2 0.47U_0402_25V6K USB3_MRX_DTX_N1 4 4 7 7 USB3_MRX_DTX_N1
VBUS VBUS
CC1_5441_CONN A5 B8 USB3_MRX_DTX_P1 5 5 6 6 USB3_MRX_DTX_P1
CC1 SBU2
USB20_P3_L A6 B7 USB20_N3_L 3 3
USB20_N3_L A7 DP1 DN2 B6 USB20_P3_L
DN1 DP2 8
A8 B5 CC2_5441_CONN

Bottom
SBU1 CC2

TOP
C215 1 2 0.47U_0402_25V6K A9 B4 C216 1 2 0.47U_0402_25V6K L05ESDL5V0NA-4_SLP2510P8-10-9
VBUS VBUS
SC300003Z00
[42] USB3_MRX_DTX_N1 USB3_MRX_DTX_N1 A10 B3 USB3_MTX_C_DRX_N1 USB3_MTX_C_DRX_N1 [42]
USB3_MRX_DTX_P1 A11 SSRXN2 SSTXN2 B2 USB3_MTX_C_DRX_P1
[42] USB3_MRX_DTX_P1 SSRXP2 SSTXP2 USB3_MTX_C_DRX_P1 [42]
A12 B1
GND GND

1 2
3 GND GND 4
ESD Diode structure should be located 5 GND GND 6
as close as possible to connector GND GND D48 ESD@
USB3_MRX_DTX_P0 1 1 10 9 USB3_MRX_DTX_P0
DRAPH_UB11126-A5A0B-1H
USB3_MRX_DTX_N0 2 2 9 8 USB3_MRX_DTX_N0

USB3_MTX_C_DRX_N1 4 4 7 7 USB3_MTX_C_DRX_N1
CC1_5441_CONN
+VBUS_5441 CC2_5441_CONN USB3_MTX_C_DRX_P1 5 5 6 6 USB3_MTX_C_DRX_P1
Type-C Connector PN
TMP DC231703291 3 3

2
3

2
C
D33 C
D32 L05ESDL5V0NA-4_SLP2510P8-10-9
ESD@
ESD@ PESD5V0U2BT_SOT23-3 SC300003Z00
PESD5V0U2BT_SOT23-3

1
1
ESD for USBC2 Lines and Control
lines
U65 D49 ESD@
4 3
7 4 3
RPD_G1
6
RPD_G2 0612 change
+VBUS_5441
[42] CC1_5441 CC1_5441 12 4 CC1_5441_CONN
CC1 C_CC1
CC2_5441 11 TPD8S300 5 CC2_5441_CONN
[42] CC2_5441 CC2 C_CC2 5 2
15 1 Vbus GND
SBU1 C_SBU1
14 2
SBU2 C_SBU2

20
D1
19 USB20_P3_L 6 1 USB20_N3_L
+LDO_3V3_5441 0.1U_0402_50V7K 2 1 C507 3 D2 6 1
VBIAS 17 L30ESDL5V0C6-4_SOT23-6
10 D3 SC300004W00
VPWR 16
D4
R3158
2 1 9 18
B FLT GND1 8 B
1 GND2 13
C506 10K_0201_5% GND3 21
PAD
0.1U_0201_6.3V6K
2
TPD8S300_QFN20_3X3

0614 add CC1_5441 R3196 1 @ESD@ 2 0_0201_5% CC1_5441_CONN

CC2_5441 R3197 1 @ESD@ 2 0_0201_5% CC2_5441_CONN

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Type-C_RTS5441_CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C581P
Date: Thursday, June 15, 2017 Sheet 43 of 63
5 4 3 2 1
 A B C D E

+5VALW
+3VALW

10U_0603_6.3V6M
1 1 +3VALW to +3VS

C221
C220
@ +3VS
0.1U_0201_10V6K U19 J4
2 2 1 14 +3VALW_3VS 2 1 R194 1 @ 2 470_0603_5%

Vinafix.com 2 VIN1 VOUT1 13 2 1

VIN1 VOUT1

1
D

10U_0603_6.3V6M

0.1U_0201_10V6K

6.8P_0402_50V8B
JUMP_43X79
R3174 1 2 0_0402_5% 3 12 1 2 C223 1 1 1 2 SUSP
[13,45,54,63] SUSP# ON1 CT1

C222
470P_0402_50V7K C224 C492 G
4 11 @ @RF@ S Q11 @

3
1 VBIAS GND 2N7002H_SOT23-3 1
+5VALW 5 10 1 2 C225 2 2 2
ON2 CT2 220P_0402_50V7K
6 9 +5VALW_5VS
VIN2 VOUT2

10U_0603_6.3V6M
7 8
VIN2 VOUT2

0.1U_0402_10V6K
C515 @
1 1 1

C227
C226 15
@ GPAD +5VS
0.1U_0201_10V6K EM5209VF_DFN14_2X3 J5
2 2 2 2 1
2 1

10U_0603_6.3V6M

0.1U_0201_10V6K
JUMP_43X79
+5VALW to +5VS 1 1 1

C228

10P_0402_25V8J
C229
@ C493
@RF@
2 2 2

For RF team request

+5VS +5VS +5VS +5VS +3VS +3VS +5VS

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C508 @RF@

C509 @RF@

C510 @RF@

C511 @RF@

C512 @RF@

C513 @RF@

C514 @RF@
1 1 1 1 1 1 1

2 2 2 2 2 2 2

2 2
+5VALW +3VS +5VALW +5VALW +VCCGT +5VS +5VALW

C540 @RF@
1 2 +1.0VALW +3VALW
[9] HDA_RST#
10P_0402_25V8J
1 1
@RF@ @RF@
C541 @RF@ C544 C545
1 2 2P_0201_25V8B 2P_0201_25V8B
[9,45] ME_EN 2 2
10P_0402_25V8J

C542 @RF@
1 2
[9] HDA_BIT_CLK
+5VS +0.6VS 10P_0402_25V8J

1
C543 @RF@
R195 R196 1 2
[9] HDA_SYNC
@ @
100K_0402_5% 470_0402_5% 10P_0402_25V8J

2
SUSP

1
D D
Q12 Q13
SUSP# 2 @ SUSP 2 @
G G
S S

3
2N7002H_SOT23-3 2N7002H_SOT23-3

3 3

+5VALW

2
@
R197
220K_0402_5% +1.35VS_VRAM

1
SYSON#

@ Q14 R198
DRC2124E0L NPN MINI3-G3-B 1 470_0603_5%
OUT @

1 2
D
2 2 DGPU_PWR_EN#
[13,45,54] SYSON IN DGPU_PWR_EN# [23]
G
GND

S Q15

3
2N7002H_SOT23-3
@
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 44 of 66
A B C D E
 +3VLP +EC_VCCA
+3VLP

L8
FBMA-L11-160808-601LMT_2P R199 1 2 0_0402_5% +3VLP_EC
1 2

C230
0.1U_0201_10V6K
1 Vinafix.com
1 2 2 ECAGND
L9 +5VALW
1 1
+EC_VCCA

0.1U_0201_10V6K
C233

0.1U_0201_10V6K
C234
FBMA-L11-160808-601LMT_2P
USB_EN# R200 1 2 10K_0402_5%

ECAGND 2 2

111
125
22
33
96

67
9
U54
+3VS

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
KB_DEL# R466 1 2 10K_0402_5%
1 21
[40] PD_INT GATEA20/GPIO00 GPIO0F VCCST_PWRGD [10]
2 23 BEEP#
[8] KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# [35]
3 26
[8,27] SERIRQ SERIRQ GPIO12 EC_FAN_PWM [33]
4 27 TP@ T220
[8,27] LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
LPC_AD3 5
[8,27] LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output
[8,27] LPC_AD2 LPC_AD1 LPC_AD2 VCIN1_BATT_TEMP
8 63
[8,27] LPC_AD1 LPC_AD0 LPC_AD1 BATT_TEMP/AD0/GPIO38 VCIN1_BATT_TEMP [49]
+3VLP 10 LPC & MISC 64 +3VLP
[8,27] LPC_AD0 LPC_AD0 AD1/GPIO39 VCIN1_BATT_DROP [52]
65
ADP_I/AD2/GPIO3A CUST_TEMP3 ADP_I [51]
R206 12 AD Input 66
EC_SMB_CK1 [8] CK_LPC_KBC CLK_PCI_EC AD3/GPIO3B
1 2 13 75
@ [10,21,27,31,32,36] PCIRST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 CUST_TEMP2 ADP_ID [48] PD_INT
2.2K_0402_5% 1 2 37 76 R450 1 2 4.7K_0402_5%
R207 +3VLP R203 330K_0402_5% EC_SCI# 20 EC_RST# IMON/AD5/GPIO43 TYPEC@
[6,10] EC_SCI# EC_SCII#/GPIO0E
1 2 EC_SMB_DA1 1 38
[8] CLKRUN# GPIO1D
2.2K_0402_5%
R448 EC_SMB_CK2
1 2 C239 @ 68
DAC_BRIG/GPIO3C CMOS_ON# [28]
TYPEC@ 0.1U_0402_10V6K DA Output 70
4.7K_0402_5% 2 KSO[0..15] EN_DFAN1/GPIO3D TP_DISABLE# [33]
KSI0 55 71
R449 EC_SMB_DA2 [33] KSO[0..15] KSI0/GPIO30 IREF/GPIO3E DGPU_PWR_EN [11,23,57,58] VCIN1_BATT_TEMP 1
1 2 KSI1 56 72 2
KSI[0..7] KSI1/GPIO31 CHGVADJ/GPIO3F USB_EN# [34,46]
KSI2 57 C238 100P_0402_50V8J
4.7K_0402_5% [33] KSI[0..7] KSI2/GPIO32
TYPEC@ KSI3 58 83
R3168 1 2 0_0201_5% NONTYPEC@ KSI4
KSI5
KSI6
59
60
61
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
84
85
86
ACC_INT [46]
BATT_SWITCH# [65]
DCIN_LED# [33]
ESD
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D AC_IN_TYPE [51]
R3169 1 2 0_0201_5% NONTYPEC@ KSI7 62 87
KSI7/GPIO37 TP_CLK/GPIO4E USB_CHG_ILIM_SEL [34]
KSO0 39 88 TP@ T214 VCCST_PWRGD 1 2
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F C240 100P_0402_50V8J
+3VS KSO2 41 KSO1/GPIO21
KSO2/GPIO22 ESD@
KSO3 42 97
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 ENBKL [6]
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 SYS_PWROK [10]
Q31A TYPEC@ KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109
ME_EN [9,44]
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH1 [49]
2

L2N7002DW1T1G 2N SC88-6 KSO7 46 SPI Device Interface

KSO8 47 KSO7/GPIO27

[8,22,39,46] SOC_SML1CLK SOC_SML1CLK 1 6 EC_SMB_CK2 KSO9

KSO10
48
49
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
SPIDI/GPIO5B
SPIDO/GPIO5C
119
120
EC_SPI_MISO [8]
EC_SPI_MOSI [8]
ESD
5

KSO11 50 SPI Flash ROM SPICLK/GPIO58 126

KSO11/GPIO2B EC_SPI_CLK [8]
KSO12 51 128 SYSON
SOC_SML1DATA EC_SMB_DA2 KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# [8]
[8,22,39,46] SOC_SML1DATA 4 3 KSO13 52
KSO14 53 KSO13/GPIO2D
KSO14/GPIO2E

1
Q31B TYPEC@ KSO15 54 73 CUST_TEMP1 1
L2N7002DW1T1G 2N SC88-6 81 KSO15/GPIO2F ENBKL/AD6/GPIO40 74
[33] KB_DEL# KSO16/GPIO48 PECI_KB930/AD7/GPIO41 BATT_TEMP_S [65]
82 89 @ R209 C242
[22] GPU_PROHOT# KSO17/GPIO49 FSTCHG/GPIO50 EC_MUTE# [35]
90 100K_0402_5% 0.1U_0201_10V6K
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# [33] 2
91 CAPS_LED# [33] @ESD@

2
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92
[49,51,65] EC_SMB_CK1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54 PWR_LED# [33]
EC_SMB_DA1 78 93
[49,51,65] EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# [33]
[40] EC_SMB_CK2 79 SM Bus 95 SYSON
EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON [13,44,54]
+3VALW [40] EC_SMB_DA2 80 121
EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON [59]
127
PM_SLP_S4#/GPIO59 AC_PRESENT_R [10]
1 2 EC_PCIE_WAKE# VCOUT1_PROCHOT# R211 1 2 0_0402_5%
R208 1K_0402_5% 6 100
[10] PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# [10]
14 101
[34] USB_CHG_CTL1 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 3V/5VALW_PG [34,40,52,53,55]
1 2 VCIN1_AC_IN 15 102 R212 1 2 0_0402_5% H_PROCHOT# [6]
[10] EC_CLEAR_CMOS# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 AC_OFF [48] [59] VR_HOT#
C241 100P_0402_50V8J 16 103
[34] USB_CHG_CTL3 GPIO0A H_PROCHOT#_EC/GPXIOA06 VCOUT1_PROCHOT# [51,64]
1 2 17 104
[34] USB_CHG_EN GPIO0B VCOUT0_PH/GPXIOA07 VCOUT0_MAIN_PWR_ON [53]
R210 @ 4.7K_0402_5% 18 GPO BKOFF#/GPXIOA08 105 BKOFF#
[34] USB_CHG_CTL2 GPIO0C BKOFF# [28]
19 GPIO 106 TYPEC_LIMIT_CTL1 [42] 1
[34] USB_CHG_STATUS# GPIO0D PBTN_OUT#/GPXIOA09
25 107 @
+3VS [33] KB_BL_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 TYPEC_LIMIT_CTL0 [42]
28 108 C244
[33] EC_FAN_SPEED FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 EC_PCIE_WAKE# [31,36]
T219 TP@ 29 47P_0402_50V8J
ESD 1 2 EC_FAN_SPEED
[31] EC_TX
[31] EC_RX
EC_TX
EC_RX
PCH_PWROK
30
31
32
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17 AC_IN/GPXIOD01
110
112
AC_IN
EC_ON
R213 1 2 0_0402_5% VCIN1_AC_IN
VCIN1_AC_IN [51,64]
SUSP#
2

PCH_PWROK [10] PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON [53]

R215 10K_0402_5% 34 114 ON/OFF# [33]
[33] NOVO# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW#
36 GPI 115
[59] VR_PWRGD NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# [33]
1

2
ESD@ 116 SUSP#
SUSP#/GPXIOD05 SUSP# [13,44,54,63]
C243 117 R443
100P_0402_50V8J GPXIOD06 5VLDO_EN [52]
118 PECI R214 1 2 43_0402_1% @ 100K_0402_5%
H_PECI [6]
2

PECI_KB9012/GPXIOD07
AGND/AGND
122
[10] PBTN_OUT# XCLKI/GPIO5D
123 124 +V18R R217 1 2 0_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND

[10,54] PM_SLP_S4# +3VLP

1
XCLKO/GPIO5E V18R
1
GND0

C245
4.7U_0603_6.3V6K
KB9022QA_LQFP128_14X14 2
11
24
35
94
113

69
ECAGND

NTC
Thermal Decided Thermal Decided Thermal Decided
+EC_VCCA +EC_VCCA +EC_VCCA
16.5K_0402_1%

16.5K_0402_1%

16.5K_0402_1%
1

1
DIS@

DIS@
R416

R417

R418
2

CUST_TEMP1 CUST_TEMP2 CUST_TEMP3

1

RTS1 RTS2 RTS3 DIS@

100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K

SL200002H00 SL200002H00 SL200002H00

Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2014/09/01 Deciphered Date 2015/09/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC_NPCE388N
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Thursday, June 15, 2017 Sheet 45 of 66
 5 4 3 2 1

Kionix KX023-1025
APS G-Sensor SDO/ADDR
Address
R/W
+3VS +3VS VDD 3Fh/3Eh
+3VS
VSS 3Dh/3Ch
Vinafix.com

10U_0603_6.3V6M
0.1U_0201_10V6K

0.1U_0201_10V6K
2

2
APS@

APS@
C395

C396

C397
@

1
D D

1
2
R408
0_0402_5%

14
1
@ U58 APS@

IO VDD

VDD
1
8
SOC_SML1CLK 4 NCS
[8,22,39,45] SOC_SML1CLK SCLK/SCL
SOC_SML1DATA 6
[8,22,39,45] SOC_SML1DATA ACC2_SA0 SDI/SDA
7
SDO/ADDR 11 ACC_INT
INT1 ACC_INT [45]
9 ACC_INT2 TP@ T205
INT2

2
16
R409 15 NC5
0_0402_5% 10 NC4 13
APS@ 2 NC3 TRIG
NC1

GND1

GND2
3

1
NC2

KX023-1025_LGA16_3X3

12
2nd Battery USB2_CONN
C C

W=80mils W=80mils
+5VALW +5V_U2

USB PWR U63 BATT2@

1
5 OUT
IN 2 R462
USB_EN# 4 GND 0_0402_5%
[34,45] USB_EN# EN 3 1 2
OCB USB_OC2# [12]
SY6288D20AAC_SOT23-5 BATT2@
+5V_U2
2
C486
0.1U_0201_10V K X5R
1 BATT2@
1
+
1
C488 @
BATT2@ C487
150U_B2_6.3VM_R35M 470P_0402_50V7K
2 2

L12 EMI@
1 2 USB20_P9_L
[12] USB20_P9 1 2 0413
4 3 USB20_N9_L
[12] USB20_N9 4 3
EXC24CG900U_4P
B B
JUSB3 ME@
1
USB20_N9_L 2 VBUS
USB20_P9_L 3 D-
4 D+
GND
5
6 GND
7 GND
8 GND

ESD GND
PS_608013-004221

D42 ESD@
USB20_N9_L 4 3 USB20_P9_L
4 3
USB2.0 Connector PN
DC23300H300
+5V_U2

5 2
Vbus GND

6 1
6 1
L30ESDL5V0C6-4_SOT23-6
SC300004W00

A A

Title
<Title>

Size Document Number Rev

C <Doc> <RevCode>

Date: Thursday, June 15, 2017 Sheet 46 of 66

5 4 3 2 1
 5 4 3 2 1

DRVON ISL95808HRZ-T 5100mA

+VCCSA
PU1152
DRVON CSD97396Q4M 21000mA
+VCCCORE 1916mA EM5209VF 1916mA
PU1101 DGPU_PWR_EN +PCIE_VGS
21000mA
UV10 RV42 UV1
DRVON U42@
CSD97396Q4M 18000mA 3140mA 3140mA
TPS22961DNY
PU1102 SUSP# +1.0VS_VCCIO
U23@ UC13 RC71
DRVON CSD97396Q4M 18000mA
+VCCGT +1.0VALW 240mA EM5209VF 240mA

D
ADAPTER
DGPU_MAIN_EN
PU1151
ISL62771HRTZ-T
PU801
Vinafix.com
28000mA
+VGA_CORE
SYSON

2574mA
UC12
+1.0V_PRIM_CORE
+1.0V_VCCST
UC1
D

RC73
DGPU_MAIN_EN SY8286RAC 3840mA 1.35VS_VRAM 2124mA +1.0V_MPHYGT
PU901 PJ902 UV1
RC74
PGOOD SY8288RAC 10000mA 10000mA
+1VALWP 2130mA
PU602 PJ604 +1.0VALW
CHARGER UC1
S3：DDR_ VTT_ P G_ CT RL
1000mA 1000mA
+0.6VSP +0.6VS
PJ504
B+ SY8210AQVC
S 5 ：S Y S ON PU501 8000mA 8000mA 2000mA
+1.2VP +1.2V
PJ503 UC1
BATTERY +1.2V 500mA
6000mA +1.2V +5V_DSP
U9
JDIMM2,U2~U5

5V_3V_EN SY8288CRAC 11800mA PJ405 11800mA

+5VALWP
PU402 PJ407 SUSP# 5000mA 2000mA
EM5209VF
5000mA
+5VS +5VS_HDD
U19 J5 R227
USB_CHG_EN PI5USB2546ZHEX 2000mA +5V_CHGUSB 500mA
2000mA
+FAN
+5VALW Q28 U12 (AOU) MB-TYPE_A (U12) R72
USB_EN# SY6288D20AAC 1100mA 1000mA
1100mA
+5VS_AVDD
U55(Non-AOU) R81
C
VBUS_EN_5455 NX5P3290UK 3000mA +VBUS_5455 1000mA C

3000mA
+VCC_KB_LED
U15 MB-TYPE_C (U15) Q6
VBUS_EN_5441 NX5P3090UK 3000mA +VBUS_5441
3000mA U21 MB-TYPE_C (U21)
USB_EN# SY6288D20AAC 1100mA +5V_USB
1100mA U56 SB-TYPE_A(U56)
500mA
+VCON_IN_5455
R147

ENLDO_3V5V SY8288CRAC 100mA 100mA 100mA AP2204K 100mA

+5VLP +5VL +3.3V_IN_5455
PU402 PJ406 D15 U22 R148

ENLDO_3V5V SY8286BRAC 100mA 100mA PR8 100mA 100mA 100mA

+3VL +3VLP +CHGRTC +RTCBATT +3VL_RTC
PU401 PJ404 PR10 PD2 RC81

5V_3V_EN SY8286BRAC 5000mA 5000mA

+3VALWP 1000mA
PU401 PJ403 +3V_LAN
R103
1500mA
+3VALW DGPU_PWR_EN 25mA
ME2301DC-G
+LEDVDD 25mA
+3VGS
R10 QV2 UV1
3V/5VALW_PG RT9059GQW 611mA 600mA
611mA
+1.8VALWP
PU601 PJ603
B
SUSP# EM5209VF 5000mA 500mA B

5000mA
+3VS_FP +1.8VALW
U19 J4 R447
311mA EM5209VF 311mA
DGPU_PWR_EN
+1.8VGS
UV50 RV41 UV1
285mA
TP_VCC
R65
1850mA
+3VS_NGFF
J1
25mA
+3VS_TPM
R5
500mA
+3VS_WLAN
R43

200mA
+IOVDD_CODEC
+3VS R98
200mA
+AVDD_CODEC
R101
200mA
+3VDD_CODEC
R102
Audio

200mA
+3VS_AVCC
A R137 A

200mA
+3VS_VDD
R138
CRT

PCH_ENVDD G524B1T11U 1500mA

1500mA
+LCDVDD_CONN
U59
CMOS_ON# LP2301ALT1G 500mA
500mA
+3VS_CMOS
Q30 Security Classification Compal Secret Data Compal Electronics, Inc.
2014/08/21 2015/08/21 Title
Issued Date Deciphered Date Power Rail
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D561P
Date: Thursday, June 15, 2017 Sheet 47 of 66
5 4 3 2 1
 5 4 3 2 1

VIN_MUX
+19V_ADPIN EMI@ PL1
5A_Z120_25M_0805_2P
+19V_VIN
@Conn@ PF1 1 2 PQ1
JDCIN1 7A_32VDC_0437007.WRML AON7401_DFN8-5
PD1
1 ADPIN 1 2 1
1 2 2 2
2 3

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
EMI@ PL2 3 5 1
3 4 5A_Z120_25M_0805_2P 3
4 5
5 Vinafix.com
1 2

1
EMI@ PC1

EMI@ PC2

EMI@ PC3

EMI@ PC4

4
SDT8A100P5-13D_POWERDI5-3

1
200K_0402_5%
6
GND

PR1
7

2
GND

1
100_0402_5%
D D

1
PR2
ACES_50299-00501-003 PC5
0.01U_0402_25V7K

2
2
PC6
1 2

5600P_0402_25V7K

1
PR4 +19V_VIN PR3
100K_0402_5%
1 2
+3VALW ADP_ID [45]

2
750_0402_1%

1
680P_0603_50V7K
.1U_0402_16V7K

PR5
1

154K_0402_1%
PC7

@EMI@ PC8
2

2
2

6
PQ2A D
2
G
2N7002KDW_SOT363-6
S

1
3

1
C PQ2B D C
5 PC9 PR6
[45] AC_OFF G 0.1U_0402_25V6 24K_0402_1%

2
1
2N7002KDW_SOT363-6
PR7 S

2
100K_0402_5%

BOM Structure Table

Item BOM Structure
For U22 U22@
For U23e U23@
For U42 U42@
For DIS VGA@
Support Type-C PD PD@

B B
For EMI EMI@
For DIS of EMI VGA_EMI@
For U23e of EMI U23_EMI@
For U42 of EMI U42_EMI@
For RF RF@
For DIS of RF VGA_RF@
+CHGRTC +3VLP
For U23e of RF U23_RF@
PR8 For U42 of RF U42_RF@
S SCH DIO BAS40CW SOT-323 1 2

PD2
2 1.5K_0603_5%
1

+RTCBATT 1
3 PR9
45.3K_0603_1%
2

@Conn@
PR10
JRTC1
1 2 1
2 1
1K_0603_5% 3 2
4 G1
G2
A CVILU_CI4402M1HRT-NH A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 48 of 66
5 4 3 2 1
 5 4 3 2 1

EMI@

M_BATA M_VMB PL3 5A_Z120_25M_0805_2P

@Conn@ 1 2 M_BATT_IN
JBATT1 PF2
1
2
1
2
3 EC_SMCA
Vinafix.com 1

15A_32V_0501015.WR
2
EMI@
PL4
3 4 EC_SMDA 1 2
D 4 5 D
5 6 5A_Z120_25M_0805_2P
6 7
7 PH201 under CPU botten side :

1
8
8 9 PC10 EMI@ PC11 EMI@
GND CPU thermal protection at 93 +-3 degree C

1
10 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND

100_0402_1%

100_0402_1%
11
GND 12 Recovery at 56 +-3 degree C
GND

PR11

PR12
2

2
DRAPH_WS33081-S3201-1H

+EC_VCCA
EC_SMB_CK1 [45,51,65]

16.5K_0402_1%
EC_SMB_DA1 [45,51,65]

1
PR13
1 2
+3VLP

2
PR14 200K_0402_1% [45] VCIN0_PH1
1 2
VCIN1_BATT_TEMP [45]
PR15

1
10K_0402_5%
PH1
100K +-1% 0402 B25/50 4250K

2
C C

ECAGND

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 49 of 66
5 4 3 2 1
 5 4 3 2 1

+VBUS_5455_CONN PD@ +VBUS_5455

Vinafix.com AON7401_DFN8-5
PD@ PQ3 VIN_MUX

PF3 1 PD@ PD3

D D
1 2 2 2
3 5 1
5A_32V_0438005.WR 3

PDS5100H-13_POWERDI5-3

4
1
200K_0402_5%
PR16

100_0402_5%
1

1
PR17
PD@ PD@ PD@
PD@ PC12 PC13 PC14

2
10U_0603_25V6M 10U_0603_25V6M 0.01U_0402_25V7K

2
PD@
PD@

2
PC15
1 2

5600P_0402_25V7K

1
PR18 PD@
100K_0402_5%

2
PD@ PQ4
C C
1

2
[40] SNK_PS_EN
VGS(th)=0.8V~1.5V
1

PD@
3

PR19 LSK3541G1ET2L_VMT3

ON -> SNK_PS_EN: 1 100K_0402_5%

OFF -> SNK_PS_EN: 0

2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- TYPE-C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 50 of 66
5 4 3 2 1
 A B C D

Module model information

+19V_CHG
ISL9237_V1.mdd for dual layer
VIN_MUX
PR101
1 4

2 3

2200P_0402_25V7K

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6

10U_0603_25V6M
VIN_MUX +19V_VIN
Vinafix.com 0.01_1206_1%

1
CSIN_CHG_R
CSIP_CHG_R

@EMI@ PC101

EMI@ PC102

PC103

PC104

PC105

PC106
2

2
1 1

1
PR102 PR103
2.2_0402_1% 2.2_0402_1%
4.12V

2
1

1
PR104 PR105 PC107
4.7U_0603_25V6K

CSIP_ISL9237
392K_0402_1% 511K_0402_1%

CSIN_ISL9237
>0.8V 1 2
2

1U_0402_25V6K

1U_0402_25V6K
ACIN_ISL9238 CMIN_ISL9238 B+

1
PC108

PC109
PC110

2
0.1U_0402_25V6

0.1U_0402_25V6

10U_0603_25V6M
1 2
1

1
1

1
PC111

PC112

PR106 PR107 PC113 PC114

0.22U_0603_25V7K 10U_0603_25V6M

2
100K_0402_1% 100K_0402_1% 1 2
2

2
2

1
PC115
PR108 10U_0603_25V6M
2.2_0603_5% 1 2

PC116

2
10U_0603_25V6M
1 2

CSIP_ISL9237

CSIN_ISL9237

BST1_ISL9237
PR109

HG1_CHG

LX1_CHG

LG1_CHG
4.7_0402_5%
1 2 VDD_ISL9238
PD101 HG1_CHG HG2_CHG
BAT54CW_SOT323-3
2 PR110
VIN_MUX 2_1206_5% PU101

16

15

14

13

12

11

10

33
9
1 1 2 ISL9538HRTZ-T_TQFN32_4X4
2
PQ102 2

ADP

CSIP

CSIN

ASGATE

BOOT1

UGATE1

PHASE1

LGATE1

PAD
B+
3 PC117 6 V ～2 3 V 5V PQ101
AON6994_DFN5X6D-8-7
PQ103
1U_0603_25V6 PC118
+8.4V_BATT+

1
1 2 DCIN_ISL9238 17 8 VDDP_ISL9238 1 2 AON6962_DFN5X6D-8-7 PR111 AON7401_DFN8-5
DCIN VDDP 0.005_1206_1% 1 BATT+

D1

G1

D1

G1
2 1 VDD_ISL9238 18 7 LG2_CHG PL102 2
PC119 1U_0402_6.3V6K VDD LGATE2 1U_0402_6.3V6K 2.2UH_PCMB103T-2R2MS_13A_20% 1 4 3 5
5V ACIN_ISL9238 19 6 LX2_CHG 7 LX1_CHG 1 2 LX2_CHG 7
ACIN PHASE2 D2/S1 D2/S1 2 3
CMIN_ISL9238 20 5 HG2_CHG

4
CMIN UGATE2 PC120 PR113

G2

G2
S2

S2

S2

S2

S2

S2
4.7_1206_5%

4.7_1206_5%
PR112 1 2 0_0402_5% 21 4 BST2_ISL9237 1 2 1 2
[45,49,65] EC_SMB_DA1 SDA BOOT2

10U_0603_25V6M

10U_0603_25V6M
@EMI@ PR117
BGATE_ISL9238

3
PR116
PR114 1 2 0_0402_5% 22 3 0.22U_0603_25V7K 2.2_0603_5%
[45,49,65] EC_SMB_CK1 SCL VSYS

1
PC121

PC122

1
PR115 1 2 0_0402_5% PROCHOT#_ISL9238 23 2 CSOP_ISL9237
PROCHOT# CSOP
AMON/BMON

[45,64] VCOUT1_PROCHOT# PC123

1SNUB_CHG1 2

1SNUB_CHG2 2

2
@EMI@
BATGONE

24 1 CSON_ISL9237 4700P_0402_25V7K

2
ACOK CSON PR120
CMOUT

BGATE
COMP
PROG

PSYS

VBAT

0_0402_5%
1 2 B+

680P_0402_50V7K

680P_0402_50V7K
VDD_ISL9238

VDD_ISL9238

25

26

2 PR121 1 27

28

29

PSYS_ISL9237 30

31

32

H >0.9V --> Battery remove

82.5K_0402_1%

PC125

PC126
L <0.4V --> Battery present 1 2
BGATE_ISL9238
VBAT1_ISL9237
AMON_ISL9237

2
BATGONE @ PC124 0.1U_0402_25V6

@EMI@

@EMI@
1

733kHz / 2 Cell
PR118 PR122
100K_0402_1% 100K_0402_5% LG1_CHG LG2_CHG
2

@ PC127 1U_0402_25V6K
[45,64] VCIN1_AC_IN [45] AC_IN_TYPE 1 2
1

PR119 PR132
0_0402_5%

200K_0402_1% 200K_0402_1% COMP_ISL9237

1

PR123

PR124
2

1 2 CSOP_CHG_R
1
1K_0402_1%

1_0402_1%
1
PR125

560P_0402_50V7K

@
2

PC128
1U_0603_25V6 PR126
2
1

3 3
PC129

1_0402_1%
2

1 2 CSON_CHG_R
0.022U_0402_25V7K

2
1

1
PC130

@
PR127 1 2
1K_0402_1%
2

@ PC131 0.22U_0402_25V6K
2

0.1U_0402_25V6

[59] I_SYS
1
PC132
2

PR128
1 2 BATT+

[45] ADP_I 100_0402_5%

1

@ PC133
0.1U_0402_25V6
2

Close to EC ADP_I pin

+3VLP
1

PR129
10K_0402_5%
2

BATGONE
4 4

PR131
3

D PQ104B 0_0402_5%
PR130 5 1 2 GS [65]
6

0_0402_5% PQ104A D G
1 2 2 2N7002KDW_SOT363-6
1

[65] GM G S @
4

2N7002KDW_SOT363-6 PC135
1

@ S 0.1U_0402_25V6
1

PC134
0.1U_0402_25V6
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 51 of 66
A B C D
 5 4 3 2 1

Vfb=2V

PR451
30K_0402_1%
1 2
B+ 5V_B+
PR452
20K_0402_1%

@ PJ402
Vinafix.com 1 2

4.7U_0603_10V6K
1 2
1 2
5V_B+

2
D D

PC451
JUMP_43X118

39K_0402_1%
1
10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K

0.1U_0402_25V6
@ PJ408

10U_0603_25V6M

10U_0603_25V6M

PR453
1 2
1 2

1
PC461

PC462

PC416

PC417

EMI@ PC418

@EMI@ PC419
JUMP_43X118

5V_FB1

CS1 2
2

2
PU402

21
5

1
RT6575DGQW(2)_WQFN20_3X3

CS2

FB2

LDO3

FB1

CS1

GND
PQ451
6 20 5V_3V_EN [53] AON6994_DFN5X6D-8-7
EN2 EN1

1
PL402
7 19

D1

G1
PGOOD VCLK 3.3UH_PIMB104T-3R3MS_10A_20%

8 18 LX_5V 7 LX_5V 1 2
PHASE2 PHASE1 PR454 PC456 D2/S1 +5VALWP
2.2_0603_5% 0.1U_0402_25V6

RF@
9 17 BST_5V 1 2 BST_5V_1 1 2

G2

S2

S2

S2
BOOT2 BOOT1

4.7_1206_5%
1

3
10 16 UG_5V + PC457
UGATE2 UGATE1

PR406
Rising 4.6V 4.9V 220U_6.3V_M

LGATE2

LGATE1
Falling 3.2V 3.7V

2
2

LDO5

BYP1

LX_5V_2
VIN
5V_B+

RF@

680P_0603_50V7K
11

12

13

14

15
PQ452

1
AO3413_SOT23-3 LG_5V
Fsw=300KHz

PC428
C C
VIN_3V5V ESR=18m

D
3 1

2
+5VALWP

0.1U_0603_25V7K
G
2
PR463

1
PC459
200K_0402_5%
1 2
+5VLP

2
@ Typ: 175mA
PC463
5V_B+ Min: 100mA

4.7U_0603_10V6K
1 2
5.75V +3VLP

1
PC460
0.1U_0402_25V6 PR462
100K_0402_5%

2
1

PR413 PR461

1 2
100K_0402_5%
47.5K_0402_1%
2

1V VCIN1_BATT_DROP[45] [45] 5VLDO_EN 2

1

PR414 PC431 PQ455

1000P_0402_25V8J
2

10K_0402_1% LSK3541G1ET2L_VMT3
2

@ PJ407
1 2
1 2
JUMP_43X118

@ PJ405
1 2
+5VALWP 1 2 +5VALW
JUMP_43X118
B B
@ PJ406
JUMP_43X39
1 2
+5VLP 1 2 +5VL
Vout = Vfb*[1+(Rt/Rb)]
= 2*[1+(30K/20K)]
=5V
+5VALWP +3VLP +3VLP
+5VALWP
1

@
PR457
Imax=10.5A,Ipeak=12.4A ;Fsw=300KHz
10K_0402_5% Iocp=(Rcs1*Itrip)/Rdson
1

PR458 PR459
Rds : L/S --> typ:2.8mohm ; max: 3.5mohm
Itrip=9~11 uA
2

200K_0402_1% 100K_0402_5%
PQ453 3V/5VALW_PG [34,40,45,53,55]
Iocp=16.49A
2

Output Cap. ESR=18mohm

Delta IL=[(Vin-Vo)/L]*[(Vout/Vin)*T]=2.04A
2
PQ454
1

LSK3541G1ET2L_VMT3
2
1

PR460
1

100K_0402_1% PC464 LSK3541G1ET2L_VMT3

0.1U_0402_25V6
2

A A
2

Vth: 0.8V～
1.5V

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 52 of 66
5 4 3 2 1
 A B C D E

Vinafix.com
1 1
keep short pad,
snubber is for EMI only.

B+ 3V_B+ PU401
SY8286BRAC_QFN20_3X3 PR401 PC402
@ PJ401 0_0402_5% 0.1U_0201_10V6K
1 2 BST_3V 1 2 BST_3V_R 1 2 Use 7x7x3 size when the layout space is enough.
1 2

10U_0603_25V6M

10U_0603_25V6M
2200P_0402_50V7K
JUMP_43X118

1
0.1U_0402_25V6
PL401

@EMI@ PC404

EMI@ PC405

PC403

PC406
1.5UH_6A_20%_5X5X3_M

IN

IN

IN

IN

BS
2

2
LX_3V6 20 LX_3V 1 4
LX LX +3VALWP
7 19 2 3
GND LX

4.7_1206_5%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
PR402
RF@
8 18
GND GND

PC407

PC408

PC409

PC410
9 17
+3VLP +3VL

2
PG LDO

1
10 16

3V_SN2
NC NC PC412

OUT
EN2

EN1
1
21

NC
4.7U_0603_6.3V6M

FF

2
GND

680P_0603_50V7K
PR403

11

12

13

14

15

1
RF@
100K_0402_5%
3.3V LDO 150mA~300mA Vout is 3.234V~3.366V

PC413
0413
[34,40,45,52,55] 3V/5VALW_PG

2
RF Request
ENLDO_3V5V PC414 PR404
Iocp=8A
2 1000P_0402_25V8J 1K_0402_1%
TDC=6A 2
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2

EN1 and EN2 dont't be floating.

EN :H>0.8V ; L<0.4V Fsw : 600K Hz @ PJ403
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118

@ PJ404
JUMP_43X39
1 2
+3VL 1 2 +3VLP

3 3
PR407
499K_0402_1%
1 2 ENLDO_3V5V
B+
1

PR408
1

150K_0402_1% PC426
1U_0402_16V6K
2
2

PR409
2.2K_0402_5%
[45] EC_ON 1 2
PR410
0_0402_5%
[45] VCOUT0_MAIN_PWR_ON 1 2

5V_3V_EN
5V_3V_EN [52]
1M_0402_1%

4.7U_0402_6.3V6M
1

EN1 and EN2 dont't be floating.

1
PR412

PC430

EN :H>0.8V ; L<0.4V
Fsw : 600K Hz
2

4 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 53 of 66
A B C D E
 5 4 3 2 1

0.6V +/- 1.5%

DDR_B+
OCP 2A
B+ @ PJ501
1 2 PU501
1 2
+3VALW

2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6
JUMP_43X118 10 19
IN OT

@EMI@ PC502

EMI@ PC503
Vinafix.com +1.2VP

1
13 18 PR501 PC501
BYP PG

PC504

PC505
0_0603_5% 0.1U_0603_25V7K
14 12 BST_DDR 1 2 BST_DDR_R 1 2 PL501

2
VCC BS

PC506
1U_0402_6.3V6K
D 1UH_11A_20%_7X7X3_M D

2.2U_0402_6.3V6M
4 11 LX_DDR 1 2
VTTGND LX

1
PC507
9 16
PGND FB

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
RF@
15 8 +1.2VP PC508 PR502

2
SGND VDDQSNS

1
PC509

PC510

PC511

PC512

PC513

PC514
22U_0603_6.3V6M 4.7_1206_5%
+3VALW 7 1 2

1 2
VLDOIN

2
ILMT_DDR 17 6 RF@
ILMT VTT +0.6VSP PC517
2

1 5 680P_0402_50V7K

2
@ PR503 S5 VTTSNS

EN_DDR
10K_0402_5% 2 3 0413
S3 VTTREF RF Request
OCP 12A
1

22U_0603_6.3V6M
1U_0402_16V6K
SY8210AQVC_QFN19_4X3
ILMT_DDR PR504

1
PC518
0_0402_5% PC520

PC519
1 2 330P_0402_50V7K

EN_0.6VSP
[13,44,45,54] SYSON
2

0.1U_0402_10V7K
1 2

2
@ PC521
@ PR505 Fsw : 600K Hz
+1.2VP

1
1M_0402_5%
PR506
0_0402_5% FB_DDR 1 2

PR507
0.6V
1

1
102K_0402_1%

2
PR508
@ PR509 100K_0402_1%
C 0_0402_5% EN :H>0.8V ; L<0.4V C

2
1 2
[13,44,45,63] SUSP#

0.1U_0402_10V7K
1

1
1M_0402_5%
PR510

@ PC522
PR511 @ PJ503

2
0_0402_5% +1.2VP 1 2 +1.2V
1 2 1 2

2
[7] DDR_VTT_PG_CTRL JUMP_43X118

@ PJ504
1 2
+0.6VSP 1 2 +0.6VS
JUMP_43X39

B
+5VALW B

RT9059GQW_WDFN10_3X3

10 1
+3VALW @ PJ502 9 VDD VOUT 2
1 2 2.5V_VIN 8 VIN VOUT 3
1 2 7 VIN VOUT 4 +2.5VP
VIN ADJ/NC

10U_0603_25V6M
43K_0402_1%
JUMP_43X79 2.5V_EN 6 5
EN PGOOD
1

1
10U_0603_25V6M

1U_0603_25V6K

PC525
1

1
PC523

PC524

PR512

11
PAD
2

PU502
2

PJ505
2

@
+2.5VP 1 2 +2.5V
1 2
0.8V
1

JUMP_43X79
20K_0402_1%
PR514

PR513 0_0402_5%
[13,44,45,54] SYSON 1 2
2

EN :H>1.2V ; L<0.4V
@ PR515 0_0402_5%
[10,45] PM_SLP_S4# 1 2
.1U_0402_16V7K
@ PC526
1

A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 1.2VP/0.6VSP/2.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 54 of 66
5 4 3 2 1
 A B C D E

Vinafix.com
1
+5VALW 1

RT9059GQW_WDFN10_3X3

10 1
+3VALW @ PJ601 9 VDD VOUT 2
1 2 1.8V_VIN 8 VIN VOUT 3
1 2 7 VIN VOUT 4 +1.8VALWP PJ603
VIN ADJ/NC +1.8VALW

10U_0603_25V6M
25.5K_0402_1%
JUMP_43X79 1.8V_EN 6 5 1 2
EN PGOOD +1.8VALWP @ 1 2

1
10U_0603_25V6M

1U_0603_25V6K

PC603
1

1
PC601

PC602

PR602
11
PAD JUMP_43X39

2
PU601

2
0.8V

20K_0402_1%
PR603
+1.8VALWP
PR601

2
1 2
[34,40,45,52,53] 3V/5VALW_PG
PR604
100K_0402_5%
0_0402_5%

.1U_0402_16V7K
1 2

@ PC604
EN :H>1.2V ; L<0.4V

1
2
1.8V_PGOOD

2 2

0413
RF Request

keep short pad, RF@ PR606 RF@ PC605

1V_B+ snubber is for EMI only. 4.7_1206_5% 680P_0603_50V7K
3 3
1 2 SNUB_1V 1 2
PU602
@ PJ602
B+ 1
1 2
2 2
IN PG
9 PR607
0_0402_5%
PC606
0.1U_0201_10V6K
Use 7x7x3 size when the layout space is enough.
2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M

BST_1V 2 BST_1V_R 1
0.1U_0402_25V6

JUMP_43X118 3 1 1 2
IN BS PL601
1

1
EMI@ PC607

@EMI@ PC608

+1VALWP
PC609

PC620

4 6 LX_1V 1 4
IN LX
2

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
5 19 2 3
IN LX

14K_0402_1%

1
PC610

PC611

PC612

PC614

PC615

PC613

PC616
7 20
GND LX

PR608
0.68UH_7.9A_20%_5X5X3_M
8 14 FB_1V R1

2
GND FB @ @

2
PR609 18 17 LDO_3V
0_0402_5% GND VCC
1

1.8V_PGOOD 1 2 EN_1V 11 10
EN NC PC617 FB=0.6V

1
ILMT_1V 13 12 2.2U_0402_6.3V6M
2

ILMT NC
1

1
1M_0402_1%

0.1U_0402_25V6

PR611
PR610

@ PC618

15 16 20K_0402_1%
+3VALW BYP NC Vout=0.6V* (1+R1/R2) R2
2

+3VALW
21 =0.6*(1+(14/20)) @ PJ604

2
PAD JUMP_43X118
2

EN :H>0.8V ; L<0.4V 1 2
SY8286RAC_QFN20_3X3 Vout=1.02V +1VALWP 1 2 +1.0VALW
1

PC619
1

1U_0402_6.3V6K
2

PR612
10K_0402_5%

Fsw : 500K Hz
2

4
OCP 12.5A 4

The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.
Security Classification Compal Secret Data Compal Electronics, Inc.
Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 1.8VALWP/1VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 55 of 66
A B C D E
 A B C D E

Vinafix.com
1 1

2 2

BLANK

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BLANK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 56 of 66
A B C D E
 5 4 3 2 1

Vinafix.com
D D

41.2K_0402_1%
VGA@ PR802

10K_0402_1%

10K_0402_1%
VGA@ PR803

VGA@ PR804
2

2
1

1
+5VS

VGA@

41

40

39

38

37

36

35

34

33

32

31
PU801

TP

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
VGA@ PR805
VR_ON 100K_0402_1%
1 2 1 30 BST2_GFX
High > 1.6V VGA@ PR806 NTC_NB BOOT2
Low < 1V 1 2
100K_0402_1%
2
IMON_NB UGATE2
29 UG2_GFX

3 28 LX2_GFX
[22] GPU_SVC SVC PHASE2
[22] GPU_VRHOT# +5VS
4 27 LG2_GFX
@VGA@ PR807 VR_HOT_L LGATE2
VGA@ PR808 +3VS 1 2 5 26
[22] GPU_SVD SVD VDDP
+1.8VGS 0_0402_5% 100K_0402_1% ISL62771HRTZ-T_TQFN40_5X5
1 2 VDDIO_VGA 6 25 1 2
VDDIO VDD
0.1U_0402_25V6K
1

@VGA@ PC803

7 24 LG1_GFX VGA@
[22] GPU_SVT SVT LGATE1

1U_0603_10V6K

1U_0603_10V6K
VGA@ PR810 PR801

VGA@ PC804

VGA@ PC802
1 2ENABLE_GFX 8 23 LX1_GFX 1_0603_5%
[11,23,45,58] DGPU_PWR_EN
2

ENABLE PHASE1

1
0_0402_5%
DGPU_PWROK 9 22 UG1_GFX VGA_B+
PWROK UGATE1 @ PJ801

2
1 2 IMON 10 21 BST1_GFX 1 2
IMON BOOT1 +3VS 1 2 B+

10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K

0.1U_0402_25V6K
VGA@ PR811

@VGA_EMI@
VGA@ PC806

VGA@ PC807
PGOOD
133K_0402_1% JUMP_43X118
ISUMN
ISUMP

COMP
ISEN2

ISEN1

VGA_EMI@
VSEN

PC808
NTC

RTN

1 2 FB @ PJ802

1
PC809
C VGA@ PC805 VGA@ 1 2 C
1000P_0402_50V7K PR813 VGA@ PR814 1 2
11

12

13

14

15

16

17

18

19

10.5K_0402_1% 27.4K_0402_1% 20 @VGA@ PR812 JUMP_43X118

2
1 2 NTC_GFX_R 1 2 NTC_GFX 100K_0402_1%
UG1_GFX

2
VGA@
ISUMN_GFX

COMP_VGA
ISEN2_GFX

ISEN1_GFX

VSEN_VGA

PH801 DGPU_PWROK
FB_VGA

PH1002 near APU_CORE H/S mos DGPU_PWROK [11,58]

RTN_GFX

1 2 VGA@ PR815 VGA@ PC810

1
VRHOT Assert Threshold : 0.64V 2.2_0603_1% 0.22U_0603_25V7K
470K_0402_5%_B25/50 4700K VGA@ PC811 BST1_GFX
1 2BST1_GFX_R1 2
TSENSE Bias Current : 30uA SH000011H00 (DCR:0.98mohm +/-5%)

D1

G1
.22U_0402_6.3V6K
PH1002=27.4K, 110C active ISUMN_GFX_R 1 2
Reset Threshold: 0.66V, 98C active LX1_GFX 7 LX1_GFX 1 4
110C Assert Threshold: PR1031=27.4K VGA@ PC812
.22U_0402_6.3V6K
D2/S1
2 3
+VGA_CORE
100C Assert Threshold: PR1031=16.9K 1 2 VGA@ PQ802 VGA_RF@ VGA@ PR817

G2
S2

S2

S2

1
AON6962_DFN5X6D-8-7 PR816 3.65K_0603_1%
VGA@ PC814 4.7_1206_5% ISUMP_GFX 1 2 VGA@ PL801

6
VGA@ PC813 VGA@ PR818 220P_0402_50V8J @VGA@ PR819 0.24UH_22A_+-20%_ 7X7X3_M
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1%
ISUMP_GFX 1 2 1 2 1 2 1 2 VGA@ PR821
1 2ISUMP_GFX_NTC

2
10K_0402_1%
330P_0402_50V7K
2.61K_0402_1%

@VGA@ PC815

SNB_VGA ISEN1_GFX 1
0.15U_0402_10V6K

VGA@ VGA@ 2
1

1
VGA@ PR820

VGA@ PR823 PR824 PC816

LG1_GFX

1
VGA@ PC819
11K_0402_1%

.022U_0402_25V4

1K_0402_1% 137K_0402_1% 390P_0402_50V7K

1
VGA@ PR822

VGA@ PC818

1 2 1 2 1 2 VGA_RF@ VGA@ PR825

2
1

0413 PC817 1_0402_1%

2
VGA@ VGA@ RF Request 680P_0603_50V7K ISUMN_GFX_R 1 2
PR826 PC820
2

2K_0402_1% 330P_0402_50V7K
2

1 2 1 2
PH1003 near GFX_CORE chokeVGA@ PH802
10K_0402_5%_B25/50 4250K PR1058=3.65K, PR1040=2.1K and
VGA@ PR827 VGA@ PR828
PR1046=604 to set loadline -2.1mV/A
2

ISUMN_GFX_R
562_0402_1%
1 2
10_0402_5%
1 2
+VGA_CORE
+VGA_CORE
VGA@ PR830
1

@VGA@ PR829 @VGA@ PC822 0_0402_5%

VGA@ PC821 100_0402_1% 1000P_0402_50V7K 1 2
VCCSENSE_VGA [22]

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M
0.1U_0402_25V6 1 2 1 2 1 1 1
2

VGA@ PR831
+ + +

VGA@ PC823

VGA@ PC824

VGA@ PC825
0_0402_5%
PR1046 set 750 ohm to OCP 43.75A 1 2
VSSSENSE_VGA [22]
0.01U_0402_50V7K

2 2 2
VGA@ PC826
1

1 2

VGA@ PR832
2

PR1058=3.65K, PR1040=2.1K and 10_0402_5%

B B
PR1046=487 to set loadline -2.1mV/A
while PR1046=487 to set OCP 56A VGA_B+
for EDC 45A application.

2200P_0402_50V7K

0.1U_0402_25V6K
@VGA_EMI@ PC829

VGA_EMI@ PC830
10U_0603_25V6M

10U_0603_25V6M
VGA@ PC827

VGA@ PC828

1
1

2
2

2
UG2_GFX

VGA@ PR833 VGA@ PC831

2

+VGA_CORE 2.2_0603_1%
BST2_GFX1
0.22U_0603_25V7K
2BST2_GFX_R1 2
SH000011H00 (DCR:0.98mohm +/-5%)
D1

G1

LX2_GFX 7 LX2_GFX 1 4
D2/S1
+VGA_CORE
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2 3
VGA_RF@ VGA@ PR835
G2
S2

S2

S2
1

1
VGA@ PC832

VGA@ PC833

VGA@ PC834

VGA@ PC835

VGA@ PC836

VGA@ PC837

VGA@ PC838

VGA@ PC839

VGA@ PC840

VGA@ PC841

VGA@ PC842

VGA@ PC843

VGA@ PC844

VGA@ PC845

VGA@ PC846

VGA@ PC847

VGA@ PQ803 PR834 3.65K_0603_1%

AON6962_DFN5X6D-8-7 4.7_1206_5% ISUMP_GFX
1 2 VGA@ PL802
3

0.24UH_22A_+-20%_ 7X7X3_M
2

LG2_GFX VGA@ PR836

2

10K_0402_1%
SNB_VGA2 ISEN2_GFX 1 2
1

GFX_core
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0413 VGA_RF@ VGA@ PR837

TDC 30(1H1L)
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

RF Request PC848 1_0402_1%

2
VGA@ PC856

VGA@ PC857

VGA@ PC858

VGA@ PC859

VGA@ PC860

VGA@ PC861

VGA@ PC862

680P_0603_50V7K ISUMN_GFX_R 1 2
Peak Current 45A
1

1
VGA@ PC849

VGA@ PC850

VGA@ PC851

VGA@ PC852

VGA@ PC853

VGA@ PC854

VGA@ PC855

OCP current > 56A

Load line -2.1mV/A
2

FSW=400kHz
DCR 0.98mohm +/-5%
TYP MAX
H/S Rds(on) :11.7mohm , 14mohm
L/S Rds(on) :2.7mohm , 3.3mohm
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 57 of 66
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

@VGA@ PR908
C C
0_0402_5%
1 2
DGPU_PWROK [11,57]

EN :H>0.8V ; L<0.4V
VGA@ PR902
88.7K_0402_1%
EN_1.35V 1 2 DGPU_PWR_EN
DGPU_PWR_EN [11,23,45,57]
1

VGA@ PC902
VGA@ PR903 0.1U_0402_10V7K
1M_0402_1% 0413
2

RF Request

B+_1.35V
2

keep short pad, VGA_RF@ PR904 VGA_RF@ PC903

snubber is for EMI only. 4.7_1206_5% 680P_0603_50V7K
1 2 SNUB_1.35V 1 2
VGA@ PU901
@ PJ901 SY8286RAC_QFN20_3X3
B+ 1
1 2
2 2
IN PG
9 VGA@ PR901 VGA@ PC901 Use 7x7x3 size when the layout space is enough.
0.1U_0402_25V6

0_0402_5% 0.1U_0201_10V6K
2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M
VGA@ PC906

VGA@ PC914

JUMP_43X118 3 1 BST_1.35V 1 2 BST_1.35V_R1 2

IN BS
1

1
VGA_EMI@ PC904

@VGA_EMI@ PC905

VGA@ PL901 @ PJ902

4
IN LX
6 LX_1.35V 1 2
+1.35VGSP +1.35VGSP
JUMP_43X118
1 2
+1.35VS_VRAM
2

1 2

330P_0402_50V7K
22.6K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
5 19 1UH_6.6A_20%_5X5X3_M
IN LX

VGA@ PR905
LDO_3V_1.35V

1
VGA@ PC907

VGA@ PC908

VGA@ PC909

VGA@ PC910

VGA@ PC911
7 20
GND LX
8 14 FB_1.35V R1

2
GND FB
2

@VGA@

2
PR906 18 17 LDO_3V_1.35V
GND VCC
0_0402_5%

1
EN_1.35V 11 10
EN NC VGA@ PC912 FB=0.6V
1

1
ILMT_1.35V ILMT_1.35V 13 12 2.2U_0402_6.3V6M

2
ILMT NC
15 16 VGA@ PR907
+3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 18K_0402_1%
21 =0.6*(1+(22.6/18))

2
PAD
OCP 9.5A
B
Vout=1.353V B
1

VGA@ PC913
1U_0402_6.3V6K
2

Fsw : 500K Hz

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 1.35VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 58 of 66
5 4 3 2 1
 5 4 3 2 1

+1.0V_VCCST +5VS CPU_B+ PC1020 PR1007 PR1031 PR1042 PC1034 PR1055 PR1058 PR1049 PR1048 PR1041
+VCCST
U22@ U22@ U22@ U22@ U22@ U22@ U22@ U22@ U22@ U22@
PR1001 0.047U_0402_25V 90.9k_0402_1% 1.91k_0402_1% 374_0402_1% 0.047U_0402_25V 93.1k_0402_1% 1.54k_0402_1% 383_0402_1% 0_0402_5% 0_0402_5%
12.1K_0402_1%

1
0.1U_0402_10V7K
1 2

1_0402_5%
PR1003

PR1002
PC1002
0_0402_5% PC1003 PC1020 U23@ PR1007 U23@ PR1031 U23@ PR1042 U23@ PC1034 U23@ PR1055 U23@ PR1058 U23@ PR1049 U23@ PR1048 U23@

45.3_0402_1%
PC1001

100_0402_1%
4700P_0402_25V7K

2
1

1
PR1005

PR1006
1 2 1U_0402_16V6K

2
Vinafix.com
1 2
D U22@ SE102104K00 SD034887280 SD034255180 SD034442080 SE00000MJ00 SD034100380 SD034154180 SD034383080 SD028000080 D
PR1007 0.1U_0402_10V7K 88.7K_0402_1% 2.55K_0402_1% 442_0402_1% 0.047U_0402_25V7K 100K_0402_1% 1.54K_0402_1% 383_0402_1% 0_0402_5%

2
90.9K_0402_1% PR1008
1 2 10_0402_1% 1 2 PC1020 U42@ PR1007 U42@ PR1031 U42@ PR1042 U42@ PC1034 U42@ PR1055 U42@ PR1058 U42@ PR1049 U42@ PR1041 U42@
1 2 ISL95829_SVID_DATA PR1015
[15] VR_SVID_DATA ICCMAX of IA
PR1009 PC1004
70A for U42
0_0402_5% 0.22U_0603_16V7K 33A for U22 & U23e
PC1005 PH1001 1 2 ISL95829_SVID_ALERT#
[15] VR_ALERT#
330P_0402_50V7K 470K_0402_5%_ TSM0B474J4702RE NTC of GT at 100 deg
1 2 1 2 [15] VR_SVID_CLK 1 2 ISL95829_SVID_CLK SE00000MJ00 SD034909280 SD000009O80 SD034374080 SE102104K00 SD034887280 SD00000J380 SD034475080 SD028000080
PR1011 49.9_0402_1% 0.047U_0402_25V7K 90.9K_0402_1% 1.91K_0402_1% 374_0402_1% 0.1U_0402_10V7K 88.7K_0402_1% 3.09K_0402_1% 475_0402_1% 0_0402_5%
PR1012 PR1013
27.4K_0402_1% 10.2K_0402_1% 1 2
1 2 1 2 [45] VR_HOT# PR1014 100_0402_1%

PC1006 +3VS PR1015

1
165K_0402_1%

34K_0402_1%

150K_0402_1%
1000P_0402_50V7K 1.91K_0402_1%

PR1016

PR1017

PR1018
1 2 1 2
PC1007 PR1019
47P_0402_50V8J PR1020 110K_0402_1%
1 2 0_0402_5%

2
1 2
PC1009 PR1024 [45] VR_PWRGD OCP of SA at 10A
820P_0402_25V7 2K_0402_1% PR1021 PR1022
1 2 1 2 1 2 1 2 0_0402_5% 665_0402_1% RC Match of SA
1 2 PR1014 1 2
[45] VR_ON ICCMAX of GT ISUMN_SA [61]
PC1008 PR1023 FB to GND of GT
70A for U23e

1
8200P_0402_25V7K 3.6K_0402_1% VR_ON
33A for U22 & U42
PU1001 PC1011 PR1028 PH1002

0.01UF_0402_25V7K
PC1010 PR1025 [51] I_SYS ISL95829AHRTZ-T_TQFN48_6X6 2200P_0402_50V7K 1K_0402_1% 10K_0402_5%_B25/50 4250K
+VCCGT

0.033U_0402_16V7K
680P_0402_50V7K 1K_0402_1% PR1027 PR1023

48
47
46
45
44
43
42
41
40
39
38
37

11K_0402_1%
1
1 2 1 2 P_SYS 34K_0402_1% ICCMAX of SA is 7A 1 2 1 2

2
1

1
PC1012
PR1062 1 2 100_0402_1% 1 2

PC1013

PR1029
VR_ENABLE
VR_READY
VR_HOT#
SCLK
ALERT#
SDA

PROG1
PROG2
PROG3
PROG4
VCC
VIN
U22@

1
PR1031 PWM_SA [61] PC1014

1
PR1060 0_0402_5% 1.91K_0402_1% .1U_0402_16V7K PR1067 1 2 100_0402_1%

2
[15] VCCGT_SENSE 1 2 1 2 FCCM_SA [61] PR1032

2
C 1 36 2.61K_0402_1% C
1 2 Droop of GT at 2.65mV/A 2 PSYS PROG5 35
[15] VSSGT_SENSE IMON_B PWM_C
PR1061 0_0402_5% 3 34

2
NTC_B FCCM_C
1

4 33 PR1064
1 2 5 COMP_B ISUMN_C 32 0_0402_5%
PC1015 ISUMP_SA [61]
PR1063 100_0402_1% 6 FB_B ISUMP_C 31 1 2
0.01UF_0402_25V7K VSSSA_SENSE [13]
2

7 RTN_B RTN_C 30 1 2 1 2
ISUMP_B FB_C

1
8 29
9 ISUMN_B COMP_C 28 PR1033 PC1016 PC1017
ISEN1_B IMON_C

4.42K_0402_1%
10 27 316_0402_1% 1500P_0402_50V7K Comp of SA 0.01UF_0402_25V7K
[60,61] ISUMP_GT

2
11 ISEN2_B PWM3_A 26 PR1065
PWM3_VCORE

2K_0402_1%
FCCM_B PWM2_A

1
PR1035
12 25 1 2 0_0402_5%
2.61K_0402_1%

PWM1_B PWM1_A
1

1 2

PR1036
PWM2_VCORE [60] IMON of SA VCCSA_SENSE [13]
10K_0402_5%_B25/50 4250K

0.047U_0402_25V7K

0.033U_0402_16V7K

Cn of GT PR1037
PR1034

330P_0402_50V7K
U22@ 1.69K_0402_1%

ISUMN_A
ISUMP_A
PWM2_B

COMP_A

ISEN1_A
ISEN2_A
ISEN3_A
FCCM_A
1

+VCCSA
PC1021

IMON_A

68P_0402_50V8J
49 set the LL of SA at 10.3mV/A
PR1038
11K_0402_1%

NTC_A

RTN_A

2
+5VS EP
1

1
PWM1_VCORE [60]

115K_0402_1%
PC1020

PR1039

PC1023
FB_A
2

1
PC1024
PR1040 PC1022 1 2

8200P_0402_25V7K

680P_0402_50V7K
1K_0402_1% 2200P_0402_50V7K FCCM_VCORE [60] PR1066 100_0402_1%
2

2
1

1 2 1 2
2

13
14
15
16
17
18
19
20
21
22
23
24

2
1

1
PH1003

PC1025
PC1026
2
U22@
U22@ PR1041

2
PR1042 0_0402_5%
2

374_0402_1%

2
[60,61] ISUMN_GT 1 2
1 2
OCP of GT at 66.71A 0_0402_5% PR1045
+5VS
.1U_0402_16V7K
PC1027
1

U23@ PC1028 U22@ Comp of SA

0.022U_0402_25V7K ISEN2_GT [60,61] 1 2
1 2 0_0402_5% PR1048 U42@
2

1 2

PC1029 0.022U_0402_25V7K ISUMN_VCORE [60]

U23@ PC1030 [60] ISEN2_VCORE
0.022U_0402_25V7K 1 2 Cn of IA

.1U_0402_16V7K
ISEN1_GT [60,61]

1
B 1 2 B

0.033U_0402_16V7K

0.047U_0402_25V7K
U22@ PC1031 0.022U_0402_25V7K PH1004

PC1032
PR1049 383_0402_1% [60] ISEN1_VCORE U42@ U22@ 10K_0402_5%_B25/50 4250K

11K_0402_1%
[60,61] FCCM_GT

1
PC1033
1 2

1
PC1034

PR1051
[61] PWM1_GT

2
OCP of Vcore at 83.2A
[60] PWM2_GT 1 2 1 2

1
2
PC1035 PR1050 PR1052
2200P_0402_50V7K 1K_0402_1% 5.49K_0402_1%

RC Comp of IA

2
ISUMP_VCORE [60]
NTC of CORE at 100 deg
1 2 VSSCORE_SENSE [15]
PR1053
10.2K_0402_1% 1 2 1 2 PR1068

1
1 2 PC1037 0_0402_5%
PR1054 Comp of IA PC1036 0.01UF_0402_25V7K
470K_0402_5%_ TSM0B474J4702RE

316_0402_1% 1500P_0402_50V7K 1 2
330P_0402_50V7K

2
1

PR1071 100_0402_1%

2K_0402_1%
27.4K_0402_1%
1

1
U22@ 1 2
PC1039

PH1005

PR1055
PR1056

PR1057
1

93.1K_0402_1% U22@
2

68P_0402_50V8J

PR1059 PR1058 PR1069

2

2.26K_0402_1% 1.54K_0402_1% 0_0402_5%

2

2
1
PC1040

1 2 VCCCORE_SENSE [15]
Droop of CORE at 1.8mV/A
680P_0402_50V7K
2

+VCCCORE
2

1 2
PC1043
1

PC1042 PR1070 100_0402_1%

2200P_0402_50V7K
2
2

Comp of IA

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- CPU Controller
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 59 of 66
5 4 3 2 1
 5 4 3 2 1

+5VS CPU_B+

DCR 0.9m ohm +-5%

PU1101 Idc = 37A +VCCCORE
13 6
14 NC VIN 12 Isat = 41A
[59] PWM1_VCORE 1 VCC VIN
2 PWM
[59,60] FCCM_VCORE FCCM
2 1 2 1 3 10 PL1101

Vinafix.com 4 BOOT GL 9 0.15UH_NA__35A_20%

GH GL

1
PC1102 PR1101 8 IA_LX1 1 4
0.1U_0603_25V7M 2.2_0603_1% 5 VSWH
VSWH 11 2 3

2
PGND

RF@ PR1102
PC1101 7
D
4.7U_0603_10V6K PGND D

1
2200P_0402_50V7K

4.7_1206_5%
AOZ5048QI_QFN24_5X3P5
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6
1

1
PC1168

PC1169

PC1105

PC1106

EMI@ PC1107

EMI@ PC1108
2

2
680P_0603_50V7K
RF@ PC1111

100K_0402_1%

100K_0402_1%
2

3.65K_0603_1%
U42@ PR1103

U42@ PR1106
2.2_0402_1%
B+ CPU_B+

1
0413

PR1104
RF Request

PR1105
2

2
@ PJ1001 [59] ISEN1_VCORE
JUMP_43X118
1 2
1 2
[59] ISUMP_VCORE

1 1
@ PJ1002 [59] ISUMN_VCORE
JUMP_43X118 + PC1103 + PC1104
1 2 33U_25V_M 33U_25V_M
1 2 ISEN2_VCORE
2 2

C C
+5VS CPU_B+
U23@ PR1107
0_0402_5%
1 2
[59] PWM2_GT
U42@ PR1108
0_0402_5% U42@
1 2 PU1102
[59] PWM2_VCORE 13 6
U23@ PR1109 14 NC VIN 12
0_0402_5% 1 VCC VIN
1 2 2 PWM
[59,61] FCCM_GT FCCM
2 1 2 1 3 10 U42@ PL1105
U42@ PR1111 4 BOOT GL 9 0.15UH_NA__35A_20%
GH GL
1

0_0402_5% U42@ PC1113 U42@ PR1110 8 PWM2_PH 1 2

1 2 U42@ PC1112 0.1U_0603_25V7M 2.2_0603_1% 5 VSWH
[59,60] FCCM_VCORE VSWH

1
4.7_1206_5%
4.7U_0603_10V6K 11
2

PGND

PR1112
7

U42_RF@
PGND
AOZ5048QI_QFN24_5X3P5 PL1103 & PL1107 change footprint to
NEC_MPCH0730LR15_2P for co-lay

2
PU1102 U23@
DCR 0.9m ohm +-5%

680P_0603_50V7K
Idc = 37A

100K_0402_1%

100K_0402_1%
1
2200P_0402_50V7K

PC1114

U42@ PR1114

U42@ PR1115
3.65K_0603_1%
U42_RF@

U42@ PR1113

U42@ PR1116
Isat = 41A

2.2_0402_1%
1

1
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

U42_EMI@ PC1117

U42_EMI@ PC1118
0.1U_0402_25V6
1

1
U42@ PC1170

U42@ PC1171

U42@ PC1115

U42@ PC1116

SA0000AWU00

2
AOZ5048QI_QFN24_5X3P5
0413
2

RF Request

2
[59] ISEN2_VCORE

B B
ISUMP_VCORE

ISUMN_VCORE

ISEN1_VCORE

PC1170 U23@ PC1171 U23@ PC1115 U23@ PC1116 U23@

+VCCGT

U23@ PL1106
0.15UH_NA__35A_20%
SE00000X200 SE00000X200 SE00000X200 SE00000X200 PWM2_PH 1 2
10U_0603_25V6M 10U_0603_25V6M 10U_0603_25V6M 10U_0603_25V6M
DCR 0.9m ohm +-5%
Idc = 37A
PC1112 U23@ PR1110 U23@ PC1113 U23@
Isat = 41A
100K_0402_1%
U23@ PR1117
3.65K_0603_1%

U23@ PR1118

U23@ PR1119

U23@ PR1120
2.2_0402_1%

100K_0402_1%
1

1
SE00000MA00 SD014220B80 SE042104M80
4.7U_0603_10V6K 2.2_0603_1% 0.1U_0603_25V7M
2

PC1117 U23_EMI@ PC1118 U23_EMI@

[59,61] ISUMP_GT

[59,61] ISEN2_GT
SE00000G880 SE074222K80
A 0.1U_0402_25V6 2200P_0402_50V7K A

[59,61] ISUMN_GT
PR1112 U23_RF@ PC1114 U23_RF@

[59,61] ISEN1_GT

SD001470B80 SE025681K80
4.7_1206_5% 680P_0603_50V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- VCCCORE,VCCGT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 60 of 66
5 4 3 2 1
 5 4 3 2 1

VCC_GT (U-line 22) VCC_GT Merged(GT+GTx)(U-line 23e)

TDC 18A TDC 35A
Peak Current 31A Peak Current 64A
OCP current 37A OCP current 74A

+5VS Vinafix.com CPU_B+

D D

PU1151
13 6
14 NC VIN 12 +VCCGT
1 VCC VIN
[59] PWM1_GT PWM
2
[59,60] FCCM_GT FCCM
1 2 1 2 3 10 PL1151
4 BOOT GL 9 0.15UH_NA__35A_20%
GH GL
1
PC1151 PC1152 PR1151 8 GT_LX1 1 4
4.7U_0603_10V6K 0.1U_0603_25V7M 2.2_0603_1% 5 VSWH
VSWH

RF@ PR1152
11 2 3
2
PGND

4.7_1206_5%
7
PGND DCR 0.9m ohm +-5%

1
AOZ5048QI_QFN24_5X3P5 Idc = 37A
Isat = 41A

2
680P_0603_50V7K
2200P_0402_50V7K

RF@ PC1157
0.1U_0402_25V6
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

EMI@ PC1155

EMI@ PC1156
1

1
PC1172

PC1173

PC1159

PC1154

3.65K_0603_1%

U23@ PR1154

U23@ PR1156
2.2_0402_1%
100K_0402_1%

100K_0402_1%
1

1
0413
2

PR1153
RF Request

PR1155
2

2
[59,60] ISUMP_GT

C C
[59,60] ISEN1_GT

[59,60] ISUMN_GT

[59,60] ISEN2_GT

VCC_SA
CPU_B+ TDC 5A
Peak Current 5.1A
OCP current 7A
2200P_0402_50V7K
0.1U_0402_25V6
@EMI@ PC1160

@EMI@ PC1161

10U_0603_25V6M

10U_0603_25V6M
1

1
PC1163

PC1164

+5VS
2

B B

PC1165
1 2
PU1152
1U_0603_10V6K PQ1151
4

1
AON7934_DFN3X3A8-10
6
VCC UGATE
1 SA_HG +VCCSA
D1

D1

D1

G1

7 2 PR1157 2 1 2.2_0603_1% PL1153

[59] FCCM_SA FCCM BOOT 0.47UH_NA__12.2A_20%
3 8 SA_LX 10 9 1 2
[59] PWM_SA PWM PHASE D1 D2/S1
2 1 PC1166

RF@ PR1158
4 5 SA_LG
GND LGATE

1
4.7_1206_5%
0.1U_0603_25V7K
G2
TP

S2

S2

S2

ISL95808HRZ-T_DFN8_2X2
DCR 6.2m ohm +-5%
9

Idc = 12.2A

3.65K_0603_1%
1

1
0_0402_5%
2 Isat = 16A

PR1159

PR1160
680P_0603_50V7K
RF@ PC1167

2
1

0413
RF Request
2

[59] ISUMP_SA

[59] ISUMN_SA

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/03/09 Deciphered Date 2018/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- VCCGT,VCCSA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 61 of 66
5 4 3 2 1
 A

D
+VCCCORE

+VCCCORE
+VCCSA
2 1

PC1347
1U_0201_6.3V6M
2 1

PC1348
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1 2 1

1
2 1 PC1338
22U_0603_6.3V6M PC1331 PC1306 PC1274 PC1255 PC1227 PC1201
PC1349 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1

Vinafix.com
2 1 2 1 2 1 2 1 2 1

1
5

5
2 1 PC1339
22U_0603_6.3V6M PC1332 PC1307 PC1275 PC1256 PC1228 PC1202
PC1350 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1 2 1

1
2 1 PC1340
22U_0603_6.3V6M PC1333 PC1308 PC1276 PC1257 PC1229 PC1203
PC1351 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 2 1 2 1 2 1 2 1 2 1 2 1

1
2 1 PC1341
22U_0603_6.3V6M PC1334 PC1309 PC1277 PC1258 PC1230 PC1204
PC1352 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1 2 1
2

1
2 1 PC1342
22U_0603_6.3V6M PC1335 PC1310 PC1278 PC1259 PC1231 PC1205
PC1353 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1 2 1
2

2 1 PC1343
22U_0603_6.3V6M PC1336 PC1311 PC1279 PC1260 PC1232 PC1206
PC1354 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1 2 1
2

PC1344
22U_0603_6.3V6M PC1337 PC1312 PC1280 PC1261 PC1233 PC1207
1U_0201 * 8 pcs
22U_0603 * 9 pcs
VCCSA Place on CPU Back Side

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1
2

PC1345
22U_0603_6.3V6M PC1313 PC1281 PC1234 PC1208
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2

PC1346
22U_0603_6.3V6M PC1314 PC1282 PC1235 PC1209
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

PC1315 PC1283 PC1236 PC1210

10P_0402_25V8J
PC1355
0413

RF@

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1
RF Request

PC1316 PC1284 PC1237 PC1211

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1317 PC1285 PC1238 PC1212

4

4
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

PC1318 PC1286

330U_B2
1U_0201 * 43 pcs
22U_0603 * 31 pcs
U42
330U_B2
1U_0201 * 38 pcs
22U_0603 * 26 pcs
U22&U23
VCCCORE Place on CPU Back Side
1U_0201_6.3V6M 1U_0201_6.3V6M

+VCCCORE
2 1 2 1

PC1319 PC1287
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1

1
+
PC1320 PC1288
1U_0201_6.3V6M 1U_0201_6.3V6M PC1253
2 1 2 1 330U_B2_2.5VM_R9M

* 2 pcs

* 1 pcs
PC1321 PC1289
1U_0201_6.3V6M 1U_0201_6.3V6M

1
+

U42@
2 1 2 1

PC1322 PC1290 PC1254

1U_0201_6.3V6M 1U_0201_6.3V6M 330U_B2_2.5VM_R9M
2 1 2 1

PC1323 PC1291

1
+
1U_0201_6.3V6M 1U_0201_6.3V6M

220U_D7_2VM_R4.5M
PC1658
@
+VCCGT

+VCCGT
3

3
+VCCCORE

2 1 2 1 2 1 2 1 2 1
+VCCGT

PC1324 PC1292 PC1264 PC1239 PC1213

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

2 1 2 1 2 1 2 1 2 1
Issued Date

PC1325 PC1293 PC1265 PC1240 PC1214

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
SOLDER_PREFORMS_0402

SOLDER_PREFORMS_0402

SOLDER_PREFORMS_0402

SOLDER_PREFORMS_0402

PC1326 PC1294 PC1266 PC1241 PC1215

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U22@

U22@

U42@

U42@

2 1 2 1 2 1 2 1 2 1
1

PC1327 PC1295 PC1267 PC1242 PC1216

1

1
VCC_CORE output cap(36.4), VCC_GT output cap(36.5), VCC_SA output cap(36.6), VCC_IAGT out cap(36.7)

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PR1204

PR1203

PR1202

PR1201

2 1 2 1 2 1 2 1 2 1
2

+VCC_GT_+VCC_CORE

PC1328 PC1296 PC1268 PC1243 PC1217

2

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2017/03/09

2 1 2 1 2 1 2 1 2 1

PC1329 PC1297 PC1269 PC1244 PC1218

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

PC1330 PC1298 PC1270 PC1245 PC1219

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
Compal Secret Data

PC1299 PC1271 PC1246 PC1220

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
SOLDER_PREFORMS_0402

PR1204 U23@

SOLDER_PREFORMS_0402

PR1203 U23@
SX000000300

SX000000300

PC1300 PC1272 PC1247 PC1221

Deciphered Date
2

2
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1301 PC1273 PC1248 PC1222

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

PC1302 PC1249 PC1223

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

PC1303 PC1250 PC1224

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2018/06/30

2 1 2 1 2 1

PC1304 PC1251 PC1225

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

PC1305 PC1252 PC1226

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
330U_B2
1U_0201 * 21 pcs
22U_0603 * 38 pcs
U23
330U_B2
1U_0201 * 16 pcs
22U_0603 * 33 pcs
U22&U42
VCCGT Place on CPU Back Side
+VCCGT
Custom
Date:

Size Document Number

Title

U23@
2

1
+
VE
PWR- CPU BACK SIDE MLCC
Compal Electronics, Inc.
Thursday, June 15, 2017

PC1262
330U_B2_2.5VM_R9M
* 2 pcs

* 1 pcs
2

1
+

PC1263
330U_B2_2.5VM_R9M
1

1
2

1
+
220U_D7_2VM_R4.5M
PC1659
@
Sheet
62
of
66

Rev
0.1

D
 5 4 3 2 1

Vinafix.com MODE=GND (VCCIO)

D MODE=Float (VCCPCH) D
MODE=100Kohm to GND (EDRAM/EOPIO)
U23@ MODE=150Kohm to GND (Others)
U23@
PR1501 PR1511

[17] LPM_ZVM# 1 2 LP#_+VCCIOP 1 2

0_0402_5% 100K_0402_1%
U23@ U23@
PR1502 PC1501
2.2_0402_1% 0.1U_0402_25V6
BST_+VCCIOP 1 2 BST_R_+VCCIOP 1 2
OCP 7A
U23@ U23@

9
PU1501 PL1501
@ PJ1502 0.68UH_7.9A_20%_5X5X3_M

LP#

MODE

BST
B+ 1
1 2
2 1
VIN SW
8 SW_VCCIOP 1 2
+1.0VS_VCCOPCP

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6
JUMP_43X79 EN_+VCCIOP 5 12 U23@ 1 2
EN VOUT
1

1
PC1502

PC1503

PC1511
PR1503 6.8_0402_5%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
C1_+VCCIOP 3 2
C1 PGND
2

1
PC1504

PC1505

PC1506
C0_+VCCIOP 4 11
U23@ U23@ C0 AGND

3V3
U23_EMI@

PG

2
NB681GD-Z_QFN13_2X3

13

10
EMC
U23@ U23@ U23@
U23@ PR1506

1
C 0_0402_5% @U23@ C
2 1 PR1507 VCCOPC_SENSE [15]
[13,44,45,54] SUSP#
10K_0402_5% U23@ PR1508
+3VALW 0_0402_5%
0.1U_0402_25V6

2 1

2
1
VSSOPC_SENSE [15]
PC1509

1
U23@
PC1510
2

1U_0402_6.3V6K

2
@

+3VALW
+3VALW @ PJ1501
1 2
+1.0VS_VCCOPCP 1 2 +1.0VS_VCCOPC
Fsw : 750K Hz JUMP_43X118
1

U23@ @U23@
PR1504 PR1505
20K_0402_1% 20K_0402_1%
2

B B
C1_+VCCIOP

C0_+VCCIOP
1

@U23@ U23@
PR1509 PR1510
20K_0402_1% 20K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- VCCOPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 63 of 66
5 4 3 2 1
 A B C D

Vinafix.com
1 1

PD1601
M_BATT_IN 2 1
VS
RB751V-40_SOD323-2

PD1602
PU1601
S_BATT_IN 2 1 1
VCC VOUT
5
VL
2
RB751V-40_SOD323-2 GND
3 4
NC EN

RT9069-33GB_SOT23-5

PR1601
1 2
2 2

100K_0402_5%

+3VGS
1

@VGA@ Pull high on HW side

1

VGA@ PR1680
PR1681 10K_0402_5%
10K_0402_5%
2

GPU_GPIO5# [22]
2

3 VGA@ 3

PQ1660A
6

D
2
G
1

2N7002KDW_SOT363-6
S
1

2 VGA@
[45,51] VCOUT1_PROCHOT# PQ1661
RUM001L02_VMT3
3

VGA@
PQ1660B
3

D
5
[45,51] VCIN1_AC_IN G
2N7002KDW_SOT363-6
S
4

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Battery Select (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 64 of 66
A B C D
 5 4 3 2 1

BATT+

Battery Select S_BATT

S_BATT_IN S_VMB
M_BATT_IN
PQ1651 P5 PQ1652 PQ1653 P4 PQ1654
AON7401_DFN8-5 EMZB08P03V_EDFN3X3-8-5 EMZB08P03V_EDFN3X3-8-5 AON7401_DFN8-5
1 1 1 1 EMI@ PL1651 @Conn@
2 2 2 2 5A_Z120_25M_0805_2P PF1651 JBATT2
5 3 3 5 5 3 3 5 2 1 1 2 1
EMI@ PL1652 2 1
5A_Z120_25M_0805_2P 15A_32V_0501015.WR EC_SMCA2 3 2
2 1 EC_SMDA2 4 3

4
JBATT2_Pin5 5 4

Vinafix.com 6 5
6

1
EMI@ EMI@ 7
PR1651 PR1652 PC1651 PC1652 8 7
9 GND
39.2K_0402_1% 39.2K_0402_1% 1000P_0603_50V7K 1000P_0603_50V7K

2
GND

1
D D

100_0402_1%

100_0402_1%
ALLTO_C144PF-K07H9-L

PR1653

PR1654
BATTA_ON BATTB_ON

PR16551 2 PR1656 1 2

2
22K_0402_5% 22K_0402_5%

EC_SMDA2

JBATT2_Pin5

S_BATT

EC_SMCA2
1

1
N28 2 PQ1655 N30 2 PQ1656 [45,49,51] EC_SMB_CK1
PMBT2222A_SOT23-3 PMBT2222A_SOT23-3
[45,49,51] EC_SMB_DA1

AZC199-02SPR7G_SOT23-3

AZC199-02SPR7G_SOT23-3
A/D

2
PD1651 PD1652 1 2 @ @

2
+3VLP
1N4148WS-7-F_SOD323-2 1N4148WS-7-F_SOD323-2 PD1702 PD1701
PR1658 PR1659 PR1657 200K_0402_1%

1
10K_0402_5% 10K_0402_5%

1
2 1 N29 2 1 N31 1 2

1
[45] BATT_TEMP_S PR1660 10K_0402_5%

1
0419
PQ1657 PQ1658 ESD Request
LTC015EUBFS8TL_UMT3F LTC015EUBFS8TL_UMT3F
2 GS 2
[51] GM GM [51] GS
1

1
PR1661 PR1662
10K_0402_5% 10K_0402_5%

3
2

2
74HC253_Y1 74HC253_Y2

VL VS S_BATT_IN
PU1651
VL Second Battery Detector
7

9
74HC153PW_TSSOP16
C 2Cell (2S1P) C

2
High:6.080V
1Y

2Y

PR1663 PC1653 PR1664

16 8 100K_0402_1% 0.01U_0402_50V7K 330K_0402_1% Low :5.881V

2
VCC GND
PR1666

8
PU1652A
PR1665

1
1

1E#
2E#
3 N34 2 1 N38
1I0
1I1
1I2
1I3

2I0
2I1
2I2
2I3

S0
S1

P
PC1654 2 1 N431 +
O

2
0.1U_0201_10V6K 2
2

6
5
4
3

10
11
12
13

14
2
1
15
- 4.7K_0402_1%

1
4.7K_0402_5% PR1667
LM393DG_SO8 422K_0402_1% PC1655

4
100P_0402_25V8K

2
PR1668

1
N32 2 1
2

PR1670
PR1669
1 2 N41 5.6M_0603_5%
0_0201_5%
100K_0402_5% VL
1

1 2
PR1671 VL M_BATT_IN
100K_0402_5%
VS Main Battery Detector
2Cell (2S1P)

1
PR1673
High:6.080V
1

2
10K_0402_5%
PR1672 PR1674 Low :5.881V
100K_0402_1% 330K_0402_1%
PR1676

2
8
PU1652B
PR1675
2

1
5 N35 2 1 N37

P
N33 2 1 N457 + 4.7K_0402_1%
O

2
6 N36
-
G

1
4.7K_0402_5% PR1677
LM393DG_SO8 422K_0402_1% PC1656
4

100P_0402_25V8K

2
1
PR1679

1
PC1657
2 1 1000P_0402_25V8J

2
1

PQ1659
5.6M_0603_5%
LTC015EUBFS8TL_UMT3F
B B
2
[45] BATT_SWITCH#
3

BATT_SWITCH#
High: M_BATT (A)
Low : S_BATT (B)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Battery Select (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 65 of 66
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

Change PR1201,PR1202,PR1203,PR1204 from 0.0002_0805_5% to

1 62 SOLDER_PREFORMS_0402 0606A SIV

2 Follow battery connector change

Vinafix.com
49 Change JBATT1 from SUYIN_125022HB008M200ZL to DRAPH_WS33081-S3201-1H
0606A SIV
D D

3 Adjust 1V voltage to meet ripple spec. 55 Change PR608 from 14.3K_0402_1% to 14K_0402_1% 0606A SIV

4 64 Change PR1680.2 net from VGA_PROCHOT# to GPU_GPIO5# 0606A SIV

60 1. Change PU1101,PU1102,PU1151 from CSD97396Q4M to AOZ5048QI 0606A SIV

5
61 2. Change PC1101,PC1112,PC1151 from 1U_0603_10V6K to 4.7U_0603_10V6K

52 1. Change PC457 from SF000006500 to SF000006R00

60 2. Change PC1103,PC1104 from SF000006800 to SF000007200 0606A SIV
6
54 3. Change PL501 from SH00000PJ00 to SH00000YE00
63 4. Change PL1501 from SH00000UE00 to SH00000Z300
60 5. Change PL1101,PL1105,PL1106,PL1151 from SH00000X700 to SH00001EF00
61 6. Change PL1153 from SH000015M00 to SH00001ED00

7 57 Change PU801.4 netname from GPU_PROCHOT# to GPU_VRHOT# 0607B SIV

8 HW request. Avoid +1VALW turn on twice. 55 Change PU601 PGood pull high from +3VALW to +1.8ALWP 0609A SIV
C C

9 62 Reserve 220u D7 4.5mohm poscap on +VCCCORE and +VCCGT power rails 0612A SIV
(PC1658,PC1659)

55 1. Add PC620 for +1VALW input cap 0612A SIV

10
58 2. Add PC914 for +1.35VGSP input cap
63 3. Add PC1511 for +1.0VS_VCCOPCP input cap

11 64 1. Change PD1601 from 1N4148WS-7-F_SOD323-2 to RB751V-40_SOD323-2 0614A SIV

2. Delete PQ1601,PR1602,PD1603

1. PR902 change from 0 to 88.7K

12 For HW sequence request. 58 2. PC902 change to 0.1uF and pop. 0614B SIV

13 During EC autoload, need turn on power LED 53 Add PR461 for pull high 5VLDO_EN to +3VLP 0614B SIV

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Title
Issued Date 2017/03/09 Deciphered Date 2018/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VE
Date: Thursday, June 15, 2017 Sheet 66 of 66
5 4 3 2 1