Daniel Adalberto Martínez Vega: Universidad Tecnológica de Altamira
Daniel Adalberto Martínez Vega: Universidad Tecnológica de Altamira
Daniel Adalberto Martínez Vega: Universidad Tecnológica de Altamira
TECNOLÓGICA
DE ALTAMIRA
Digital electronic
There is a NAND gate in the diagram, whose output is connected to all the reset inputs of
the JK flip flops (3), and its inputs are connected to the outputs of 2 JK flip flops, the
second and fourth, this is so that When both JK flip flops have a high value, from the
output a 0 in the NAND gate, this 0 will go to the reset of all the JK flip flops, this condition
will be after 9, since at the input of the NAND gate there will be two 1. That is why you see
a vertical line, since having a 0 in the clear, all take the value of 0 in their outputs.
There is the table of combinations with their respective outputs, which are forming the
numbers.
3- Which is the function of NAND?
Clean the JK flip flops, on the gate inputs are the second and fourth JK flip flops, these two
are only active (with a 1.5 volt output) once, which would be after the display shows the 9,
it would go from a combination of 1001, to 1010, where the ones are those that are
connected to the NAND, for this it would send a 0, and the clear of the flip flop would
restart the account.