MISCELLANEOUS -TOPICS

MISCELLANOUS TOPICS: -
MAGNITUDE COMPARATOR: -
Introduction
A magnitude digital comparator is a combinational circuit that compares two digital or binary numbers
in order to find out whether one binary number is equal, less than or greater than the other binary
number. We logically design a circuit for which we will have two inputs one for A and other for B and
have three output terminals, one for A > B condition, one for A = B condition and one for A < B
condition.
1) 1-Bit Magnitude Comparator:

A comparator used to compare two bits is called a single bit comparator. It consists of two inputs each
for two single bit numbers and three outputs to generate less than, equal to and greater than between
two binary numbers. The truth table for a 1-bit comparator is given below:
From the above truth table logical expressions for each output can be expressed as follows:
A>B:AB'
A<B:A'B
A=B:A'B'+AB=(AXNORB) =
By using these Boolean expressions, we can implement a logic circuit for this comparator as given
below :
2) 2-Bit Magnitude Comparator:

A comparator used to compare two binary numbers each of two bits is called a 2-bit magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to and greater than
between two binary numbers.
The truth table for a 2-bit comparator is given below:
From the above truth table logical expressions for each output can be expressed as follows:
A>B:A1B1’+A0B1’B0’+A1A0B0’
A=B:A1’A0’B1’B0’+A1’A0B1’B0 +A1A0B1B0 +A1A0’B1B0’
:A1’B1’(A0’B0’+A0B0)+A1B1 (A0B0 +A0’B0’)
:(A0B0 +A0’B0’)(A1B1 +A1’B1’)
:(A0 Ex-NorB0)(A1 Ex-NorB1)
A < B : A1’B1 + A0’B1B0 + A1’A0’B0
By using these Boolean expressions, we can implement a logic circuit for this comparator as given
below
Implementation of Full Adder using Half Adder
From the logic diagram of the full adder using half adders, it is clear that we require two XOR
gates, two AND gates and one OR gate for the implementation of a full adder circuit using half-
adders.
IMPLEMENTATION OF 8:1 MUX BY USING 4:1 MUX
Let us implement 8x1 MUX by using 4x1 MUX. This is a special case in MUX tree. We require 8x1
MUX which has 8 data lines.
Master-Slave JK Flip Flop
A JK flip flop is a type of 1-bit memory element having inputs namely J and K, one clock input,
and two output specified by Q and Q'. The JK flip flop is an improved version of SR flip flop
which does not have forbidden state. To avoid the forbidden or indeterminate state, the outputs
of the JK flip flop are fed back to its inputs.
However, due to these feedback paths, a new problem is raised in the circuit, which is called
race around condition. Race around condition in the JK flip is a major problem in which the
outputs of flip flop are toggled continuously till the end of applied clock signal.
To avoid the problem of race around condition in JK flip flop, we use the JK flip flop in
the Master and Slave Mode. Hence, the JK flip flop is called Master-Slave Flip Flop.
So, let us start with the basic construction of the master-slave JK flip flop.
What is a Master-Slave JK Flip Flop?
Master Slave JK Flip Flop is a combination of two JK flip flops which are connected in the
cascaded manner as shown in Figure-1.
In this combination of two JK flip flop, one acts as a master flip flop and the other acts as
a slave flip flop. In this master-slave flip flop, the outputs of the master JK flip flop are
connected to the inputs of the slave JK flip flop. The outputs of the slave flip flop are fed back
to the inputs of the master JK flip flop.
In the master-slave JK flip flop, a NOT gate (Inverter) is also used which is connected to clock
signal in a manner that the inverted clock signal is applied to the slave flip flop.
Therefore, when clock signal to master flip flop is 0, then for slave flip flop the clock signal is
1, and if the clock signal to master flip flop is 1, then for the slave flip flop it 0.
Operation of Master-Slave JK Flip Flop
When the clock pulse goes to high, the slave flip flop becomes inactive and the inputs J and K
can control the state of the system.
When the clock pulse goes back to low, the information is transferred from master flip flop to
the slave flip flop, and the final output of the system is obtained.
From the circuit, it is clear that the master flip flop is positive level triggered and the slave flip
flop is negative level triggered. Consequently, the master flip flop responds before the slave
flip flop. Now, let us discuss the operation of the master-slave JK flip flop for different
combinations of inputs J and K.
 When J = 0 and K = 0, both JK flip flops remains inactive and hence the output Q
remains unchanged. This is called Hold State of the master-slave JK flip flop.
 When J = 0 and K = 1, the output Q' of the master flip flop is high and goes to the input
K of the slave flip flop. The clock signal forces the slave flip flop to reset. Therefore,
the slave flip flop has the same output has the master flip flop, i.e., high Q' and low Q.
This is called reset state of the master-slave JK flip flop.
 When J = 1 and K = 0, the output Q of the master flip flop is high and goes to the input
J of the slave flip flop, the negative transition of the clock signal sets the slave flip flop.
Hence, this is called the set state of the master-slave JK flip flop.
 When J = 1 and K = 1, for this input combination, the master flip flop toggles on the
positive transition of the clock pulse and the slave flip flop toggles on the negative
transition of the clock pulse. Hence, the problem of the race around condition of the JK
flip flop is solved.
Timing diagram of master slave
PRIORITY ENCODER: -
The Priority Encoder solves the problems mentioned above by

allocating a priority level to each input. The priority encoders output
corresponds to the currently active input which has the highest priority.
So when an input with a higher priority is present, all other inputs with
a lower priority will be ignored.

MISCELLANEOUS -TOPICS

Uploaded by

Copyright:

Available Formats

MISCELLANEOUS -TOPICS

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MISCELLANEOUS -TOPICS

Uploaded by

Copyright:

Available Formats

MISCELLANOUS TOPICS: -

1) 1-Bit Magnitude Comparator:

2) 2-Bit Magnitude Comparator:

The Priority Encoder solves the problems mentioned above by

You might also like