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Clock Schematic

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5 4 3 2 1

5.0V

D D

R5 R6 R7 R8
10K 10K 10K 10K

R3 R4 SW5 Time Set Key


10K 10K
U4 U3

31
40
SW6 Alarm Set Key
1 6 1 30

EA/VPP
VCC
Y4 X1 SCL P1.0 ALE/PROG
2 X2 SDA 5 2 P1.1 PSEN 29
32.768Khz 7 14 SW7 Increment Value
SQW/OUT P3.4/T0
P3.0/RXD 10
39 P0.0/AD0 P3.1/TXD 11
3 38 12 SW8 Decrement Value
GND

VBAT P0.1/AD1 P3.2/INT0


8 VCC 37 P0.2/AD2 P3.3/INT1 13
36 P0.3/AD3 P1.3 4 J2
35 P0.4/AD4 P1.2 3
BT2 DS1307
4

C 34 P0.5/AD5 P1.4 5 16 C
3V Li Battery 33 P0.6/AD6 15
32 P0.7/AD7 P2.7/A15 28 14
6 P1.5 P2.6/A14 27 13
C4 7 26 12
P1.6 P2.5/A13
10uF 8 P1.7 P2.4/A12 25 11
9 24 10 LS2
C5 RST P2.3/A11
P2.2/A10 23 9
19 XTAL1 P2.1/A9 22 8
R1 21 7 1
10K P2.0/A8 Positive
P3.5/T1 15 6
33pF Y3
C6 P3.6/WR 16 R2 5 2
11.0592Mhz 17 4

GND
P3.7/RD Negative Alarm Buzzer
18 XTAL2 3
2
1
20
33pF AT89C51 1K

B 2x16 LCD B

A A

Title
Schematic For Digital Clock with Alarm

Size Document Number Rev


A 1 1b

Date: Tuesday, September 05, 2006 Sheet 1 of 1


5 4 3 2 1

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