IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO.

2, JUNE 2011 207

Overview on ESD Protection Designs of

Low-Parasitic Capacitance for RF ICs
in CMOS Technologies
Ming-Dou Ker, Fellow, IEEE, Chun-Yu Lin, Member, IEEE, and Yuan-Wen Hsiao, Member, IEEE

Abstract—CMOS technology has been widely used to imple-

ment radio-frequency integrated circuits (RF ICs). However, the
thinner gate oxide in nanoscale CMOS technology seriously de-
grades the electrostatic discharge (ESD) robustness of RF ICs.
Therefore, on-chip ESD protection designs must be added at all
input/output pads in RF circuits against ESD damages. To min-
imize the impacts from ESD protection circuit on RF perfor-
mances, ESD protection circuit at input/output pads must be
carefully designed. An overview on ESD protection designs with
low parasitic capacitance for RF circuits in CMOS technology
is presented in this paper. The comparisons among these ESD
protection designs are also discussed. With the reduced parasitic
capacitance, ESD protection circuit can be easily combined or
co-designed with RF circuits. As the operating frequencies of RF Fig. 1. Signal loss at input and output pads of IC with ESD protection devices.
circuits increase, on-chip ESD protection designs for RF applica-
tions will continuously be an important design task. cuit is damaged by ESD, it cannot be recovered and the RF
Index Terms—Electrostatic discharge (ESD), ESD protec- functionality is lost. Therefore, on-chip ESD protection design
tion circuits, low capacitance, radio-frequency integrated circuit must be provided for all I/O pads in RF ICs.
(RF IC). However, ESD protection devices cause RF performance
degradation with several undesired effects [2]–[5]. Parasitic
I. I NTRODUCTION capacitance is one of the most important design considerations
for RF ICs. Conventional ESD protection devices with large
R ADIO-FREQUENCY integrated circuits (RF ICs) have
been widely designed and fabricated in CMOS processes
due to the advantages of high integration and low cost for mass
dimensions have the parasitic capacitance which is too large to
be tolerated for RF front-end circuits. As shown in Fig. 1, the
production. Electrostatic discharge (ESD), which has become parasitic capacitance of ESD protection devices causes signal
one of the most important reliability issues in IC products, loss from the pad to ground. Moreover, the parasitic capacitance
must be taken into consideration during the design phase of all also changes the input matching condition. Consequently, RF
ICs, including the RF front-end circuits [1]. In the RF front- performance is deteriorated.
end circuits, the input/output (I/O) pads are usually connected To mitigate the performance degradation caused by ESD
to the gate terminal or silicided drain/source terminal of the protection devices, some design techniques had been developed
metal-oxide-semiconductor field-effect transistor (MOSFET), to reduce the parasitic capacitance of ESD protection devices.
which leads to a very low ESD robustness if no appropriate The ESD protection circuit with reduced parasitic capacitance
ESD protection design is applied. Once the RF front-end cir- can be easily combined or co-designed with RF circuits [6]–[8].
In this paper, the RF ESD protection designs with low parasitic
Manuscript received May 18, 2010; revised November 10, 2010; accepted
capacitance in CMOS processes are reviewed.
January 5, 2011. Date of publication January 13, 2011; date of current ver-
sion June 15, 2011. This work was supported by National Science Council,
Taiwan, under Contract NSC 98-2221-E-009-113-MY2; by Ministry of Eco- II. D ESIGN C ONSIDERATION FOR ESD P ROTECTION
nomic Affairs, Taiwan, under Grant 99-EC-17-A-01-S1-104; and by the “Aim
for the Top University Plan” of National Chiao-Tung University and Ministry To achieve effective ESD protection, the voltage across the
of Education, Taiwan. ESD protection device during ESD stresses should be carefully
M.-D. Ker is with the Institute of Electronics, National Chiao-Tung Uni-
versity, Hsinchu 300, Taiwan, and also with the Department of Electronic
designed [9]–[12]. Fig. 2 shows the ESD design window of an
Engineering, I-Shou University, Kaohsiung 84001, Taiwan (e-mail: mdker@ IC, which is defined by the power supply voltage (VDD ) of
ieee.org). the IC, the failure level of ESD protection device, and the gate-
C.-Y. Lin is with the National Chiao-Tung University, Hsinchu 300, Taiwan
(e-mail: cy.lin@ieee.org). oxide breakdown voltage (VBD ) of MOSFET. First, the trigger
Y.-W. Hsiao is with the Richtek Technology Corporation, Hsinchu 30288, voltage (Vt1 ) and holding voltage (Vh ) of ESD protection
Taiwan. device must be lower than the gate-oxide breakdown voltage
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. of MOSFET to prevent the internal circuits from damage
Digital Object Identifier 10.1109/TDMR.2011.2106129 before the ESD protection device is turned on during ESD

1530-4388/$26.00 © 2011 IEEE

208 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011

Fig. 3. Conventional ESD protection scheme.

Fig. 2. ESD design window defined by the power supply voltage (VDD ) of
the IC, the failure level of ESD protection device, and the gate-oxide breakdown
voltage (VBD ) of the MOSFET.

stresses. Second, the trigger voltage and holding voltage of the

ESD protection device must be higher than the power supply
voltage of the IC to prevent the ESD protection devices from
being mistriggered under normal circuit operating conditions.
Moreover, the turn-on resistance (Ron ) of ESD protection
device should be minimized to reduce the joule heat generated
in the ESD protection device and the clamping voltage of
the ESD protection device during ESD stresses. As CMOS
technology is continuously scaled down, the power supply
voltage is decreased and the gate oxide becomes thinner, which Fig. 4. Simulated S21 -parameters of conventional ESD protection scheme
leads to reduced gate-oxide breakdown voltage of MOSFET. with 500-fF ESD devices, and ESD protection scheme with stacked 500-fF ESD
devices (equivalent to 250 fF).
Typically, the gate-oxide breakdown voltage is decreased to
only ∼5 V in a 65-nm CMOS process with gate-oxide thickness
of ∼ 20 Å [13]. As a result, the ESD design window becomes
much narrower in nanoscale CMOS technologies. Furthermore, parasitic capacitances of the ESD protection devices. However,
ESD protection circuits need to be quickly turned on during ESD robustness needs to be maintained, so the minimum de-
ESD stresses in order to provide efficient discharging paths in vice dimensions of ESD protection devices cannot be shrunk
time. unlimitedly.

III. S OLUTIONS TO RF ESD P ROTECTION D ESIGNS

B. Stacked ESD Protection Devices
A. Conventional ESD Protection Circuit
In order to reduce the parasitic capacitance from ESD pro-
The conventional on-chip ESD protection scheme is shown tection devices without sacrificing ESD robustness, the ESD
in Fig. 3, where two ESD protection devices at I/O pad are protection devices in stacked configuration had been presented,
assisted with the power-rail ESD clamp circuit to prevent as shown in Fig. 5 [16], [17]. With two stacked ESD pro-
internal circuits from ESD damage [7], [14], [15]. In Fig. 3, tection devices, the overall equivalent parasitic capacitance
the ESD protection devices at I/O pad can be realized with theoretically becomes CESD /2, where CESD is the parasitic
STI diodes [14], poly diodes [15], silicon-controlled rectifier capacitance of each ESD protection device. The simulated S21 -
(SCR) devices [7], or other low-capacitance ESD protection de- parameters of the stacked ESD protection devices are also
vices. Fig. 4 shows the simulated insertion loss (S21 -parameter) shown in Fig. 4. More stacked ESD devices lead to more signifi-
of the conventional ESD protection scheme with 500-fF cant parasitic capacitance reduction. Besides reducing parasitic
capacitance. capacitance, using stacked configuration can also reduce the
However, this scheme is only suitable for small ESD pro- leakage current of ESD protection devices under normal circuit
tection devices because the parasitic capacitance of the ESD operating conditions. Although stacked ESD protection devices
protection device is directly contributed at the I/O pad. The can reduce the parasitic capacitance and leakage current, this
device dimensions of ESD protection devices should be de- technique is adverse to ESD protection because the overall turn-
creased to reduce the parasitic capacitance at I/O pad, which on resistance and the clamping voltage of the stacked ESD
in turn reduces RF performance degradation caused by the protection devices during ESD stresses are increased as well.
KER et al.: OVERVIEW ON ESD PROTECTION DESIGNS FOR RF ICS IN CMOS TECHNOLOGIES 209

Fig. 7. ESD protection design with the parallel LC resonator, where the
inductor LESD provides ESD current path between VDD and the I/O pad.

Fig. 5. Stacked ESD protection devices to reduce the parasitic capacitance.

Fig. 8. ESD protection design with LC tanks.

Fig. 6. Ideal parallel LC resonator and the simulated S21 -parameters under the inductor cannot only resonate with the parasitic capacitance
different frequencies. of the ESD protection device but also serve as an ESD pro-
tection device by itself. In this configuration, the parallel LC
C. Parallel LC Resonator resonator can be realized as shown in Fig. 7. The inductor
(LESD ) serves as an ESD protection device between I/O pad
The technique of using parallel LC resonator to reduce and VDD , while the capacitive ESD protection device provides
equivalent parasitic capacitance is also called the impedance ESD current path between I/O pad and VSS . The inductor
cancellation. In such a resonator, the resonant frequency and the parasitic capacitance of the ESD protection device are
(ωo ) is designed to resonate at the operating frequency of the RF front-
1 end circuit to minimize performance degradation caused by the
ωo = √ (1) ESD protection device. With an inductor directly connected
LCESD
between the I/O pad and VDD , the ESD protection device is
where L and CESD denote the added parallel inductance and reverse-biased with the largest possible dc voltage under normal
parasitic capacitance of ESD protection device, respectively. An circuit operating conditions, which leads to the minimum the
ideal parallel LC resonator and the simulated S21 -parameters parasitic p-n junction capacitance in the ESD protection device.
under different frequencies are shown in Fig. 6. The signal The placement of the inductor and the ESD protection device
loss at the resonant frequency is ideally zero, which means can be interchanged to provide the same function. Since the
that the equivalent capacitance at the resonant frequency is inductor is dc short, a dc blocking capacitor (Cblock ) is required
zero. With the parallel LC network resonating at the operating to provide a separated dc bias for the internal circuits.
frequency, the shunt impedance of the resonator becomes very
large, which can effectively suppress signal loss. Therefore, the
D. LC Tank
ESD protection design using parallel LC resonator can mitigate
the impacts on RF performances for circuits operating in a LC tank has been reported for low-capacitance ESD pro-
narrow frequency band. Based on this concept, the on-chip tection design, which consists of an inductor, a capacitor, and
spiral inductor had been designed to resonate with the parasitic an ESD diode [20]–[22]. As shown in Fig. 8, a pair of the
capacitance of ESD protection devices [18], [19]. Furthermore, LC tanks is placed at the I/O pad. One LC tank consists of
210 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011

Fig. 9. Simulated S21 -parameters of ESD protection scheme with LC tanks.

Fig. 11. ESD protection design with the series LC resonator.

Fig. 10. Ideal series LC resonator and the simulated S21 -parameters under
different frequencies.

the inductor LP and the capacitor CP is placed between the

I/O pad and ESD diode DP . Another LC tank consists of the
inductor LN and the capacitor CN is placed between the I/O Fig. 12. ESD protection design with modified series LC resonator, where only
pad and ESD diode DN . The ESD diodes DP and DN are one inductor is connected in series with two ESD protection devices.
used to block the steady leakage current path from VDD to VSS
under normal circuit operating conditions. Furthermore, the is totally lost. However, at frequencies above the resonant
capacitors CP and CN can also be realized by ESD protection frequency, the inductor dominates the magnitude of impedance.
devices. The simulated S21 -parameters of the LC tanks are Therefore, the magnitude of impedance increases to reduce the
shown in Fig. 9. At the resonant frequency of the LC tank, signal loss significantly. Thus, wideband ESD protection can
there is ideally infinite impedance from the signal path to the be achieved by designing the application band of the series LC
ESD diode. Consequently, the parasitic capacitances of the ESD resonator to cover the frequency band of the RF signal. During
protection devices are isolated, which can mitigate the parasitic ESD stresses, the ESD current can be discharged through the
effects from the ESD protection devices. To further reduce the inductor and the ESD protection device. ESD protection design
parasitic capacitance from the ESD protection devices, two or utilizing the series LC resonator is shown in Fig. 11, where a
more LC tanks can be stacked to provide better impedance pair of the series LC resonators is placed at the I/O pad [23].
isolation at resonant frequency, and the impacts of the ESD ESD current paths from the I/O pad to both VDD and VSS
protection devices can be significantly reduced. are provided by the inductors and the series ESD protection
devices.
To reduce the inductors used in the series LC resonators, a
E. Series LC Resonator
modified design using only one inductor is shown in Fig. 12
For the wideband RF front-end circuits, the series LC [18]. One inductor is connected in series with two ESD protec-
resonator can be used for ESD protection. The simulated S21 - tion devices connected to VDD and VSS , respectively. Because
parameter of an ideal series LC resonator under different fre- the capacitance in the series LC resonator is the sum of the
quencies is shown in Fig. 10. With series inductance (LESD ) parasitic capacitances of these two ESD protection devices, the
and capacitance (CESD ), the resonant frequency (ωo ) is iden- inductance used in Fig. 12 is smaller than that used in Fig. 11
tical to that shown in (1). There is a notch at the resonant under the same resonant frequency. Consequently, total cost can
frequency where the signal loss is very large, and the signal be reduced in this modified design.
KER et al.: OVERVIEW ON ESD PROTECTION DESIGNS FOR RF ICS IN CMOS TECHNOLOGIES 211

Fig. 13. ESD protection design with impedance matching by using shunt and
series components. Fig. 15. Simulation results of ESD protection design with impedance
matching.

Fig. 14. Example of ESD protection design with impedance matching. Fig. 16. Inductive ESD protection design.

ESD protection devices at the operating frequency by using

F. Impedance Matching the inductance of L. The simulated S21 -parameters of the
To achieve satisfactory ESD robustness, the size of ESD ESD protection design with impedance matching are shown
protection devices must be large enough. However, parasitic in Fig. 15.
effects increase with the dimensions of ESD protection de-
vices. To solve this dilemma, ESD protection devices can be
G. Inductive ESD Protection
treated as a part of the impedance matching network at the
I/O pad. By co-designing the ESD protection circuit and the ESD protection design for RF circuits by using inductor
impedance matching network, large ESD protection devices can as the ESD protection device had been reported. In Fig. 16,
be used to achieve high ESD robustness without sacrificing RF the ESD protection inductor (LESD ) is placed between the
performance [24]. The impedance matching technique of ESD input pad and VSS [27]–[30]. The simulated S21 -parameters
protection device had been proposed. Fig. 13 illustrates the idea of the inductive ESD protection under different frequencies are
of matching the parasitic effects of ESD protection devices [25]. shown in Fig. 17. Inductors exhibits higher impedance at higher
In this configuration, ESD current can be discharged from the frequencies. Since the frequency component of ESD is much
I/O pad through the ESD protection devices to VDD and VSS . lower than that of the RF signal, the inductor can pass the ESD
The combined impedance of the shunt and series impedance current while block the RF signal. To efficiently sink the ESD
is designed to provide impedance matching at the I/O pad with current, the metal width of the ESD protection inductor should
ESD protection. The shunt and series impedance can be realized be wide enough to enhance the current handling capability and
by various components. to reduce the parasitic series resistance. However, inductors
One example of ESD protection design with impedance realized very wide metal traces occupy large chip area. This is
matching technique is shown in Fig. 14 [26], which uses in- the main design concern in the inductor-based ESD protection.
ductance to match the parasitic capacitances of ESD protection Besides, a dc blocking capacitor (Cblock ) is needed in this
devices. The ESD protection devices are placed next to the design to provide a separated dc bias for the internal circuits.
I/O pad, and provide ESD protection for the internal circuits. Another inductor-based ESD protection design is shown in
The inductive component L, which can be an inductor or a Fig. 18 [31]. The ESD protection inductor can be merged with
transmission line, is connected in series with the signal line, the gate inductor to save the chip area since the typical low-
and matches the parasitic capacitances of the ESD protection noise amplifier (LNA) needs a gate inductor connected between
devices. The design goal is to neutralize the capacitance of the input pad and the gate terminal of the input MOS transistor.
212 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011

Fig. 17. Simulation results of inductive ESD protection and T-coil-based ESD Fig. 19. ESD protection design with T-coil.
protection.

Fig. 20. ESD protection with T-diode.

Fig. 18. Inductive ESD protection design with transformer.
protection design for a high-speed transmitter [33]. The return
The ESD protection inductor is placed under the gate inductor
loss of the transmitter was improved with the T-coil which
to form a transformer. Consequently, the transformer-based
compensated the parasitic effects of the SCR.
ESD protection design provides not only the gate inductor in
The simulated S21 -parameters of the T-coil-based ESD pro-
the impedance matching network but also the ESD protection
tection under different frequencies are also shown in Fig. 17.
for the input pad.
Since the T-coil-based ESD protection design can overcome
the band-limiting problems in the narrowband ESD protection
H. T-Coil circuits, they are suitable for wideband RF front-end circuits.
The ESD protection design with T-coil for wideband appli- However, the design concern for the T-coil-based ESD protec-
cations had been reported. As shown in Fig. 19, with proper tion is the inductor LESD which must be realized by wide metal
impedance matching design, this circuit can provide a purely trace and in turn occupies large chip area.
resistive input impedance of RT [32]. Once the following Another wideband LNA with the transformer plus diode
expressions hold, the input impedance Zin remains resistive at (T-diode) had been reported, as shown in Fig. 20 [34]. This is
all frequencies another T-coil-based ESD protection design. In this design, the
  capacitor CB in the T-diode can be realized with the parasitic
CESD RT2 1 capacitance between the inductors LESD and L2 .
LESD = L2 = 1+ 2 (2)
4 4ζ
CESD I. Distributed ESD Protection
CB = (3)
16ζ 2
4ζ 2 − 1 The π-model ESD protection scheme had been presented to
k= 2 (4) achieve wideband impedance matching with ESD protection
4ζ + 1
devices. The ESD protection devices are divided into two
where ζ is the damping factor of the network transfer function sections and are impedance matched by the transmission line
VX /Iin . With proper design, large ESD protection devices can or inductor, as shown in Fig. 21 [35], [36].
be used without degrading RF performance. The NMOS and Another distributed ESD protection scheme had been pre-
PMOS transistors with gate-coupled technique are used in the sented, as shown in Fig. 22 [37]. With the ESD protection
first ESD protection design with T-coil [32]. The SCR has also devices divided into small sections and matched by the trans-
been used as the ESD protection device in the T-coil-based ESD mission lines, such a distributed ESD protection scheme can
KER et al.: OVERVIEW ON ESD PROTECTION DESIGNS FOR RF ICS IN CMOS TECHNOLOGIES 213

Fig. 21. π-model ESD protection scheme.

Fig. 24. Simulation results of π-model ESD protection scheme and distrib-
uted ESD protection scheme with equal-size ESD diodes.

Fig. 22. Distributed ESD protection scheme with equal-size ESD diodes.

Fig. 25. Measurement results of distributed ESD protection scheme with

decreasing-size ESD diodes on S11 - and S21 -parameters.

circuit passes 2-kV human body model (HBM) ESD test with
only 2-dB insertion loss in 60-GHz band.

IV. D ISCUSSION AND C OMPARISON

Fig. 23. Distributed ESD protection scheme with decreasing-size ESD diodes. The reported ESD protection designs for RF circuits have
been reviewed in previous section. The comparison among
achieve wideband impedance matching. The number of ESD various ESD protection designs for RF front-end circuits is
protection devices can be varied to optimize the performance. summarized in Table I. The evaluated parameters are explained
In Fig. 22, the ESD protection diodes are equally divided as following.
into three sections. However, most of ESD current is expected • Suggested Operating Frequencies:
to flow through the first section which is closest to the I/O Each ESD protection circuit is suggested to be used in
pad. To improve ESD robustness of distributed ESD protection different frequencies, such as < 5 GHz, < 10 GHz, or
scheme, the modified design of the decreasing-size distributed > 5 GHz. Some of the ESD protection circuits can only
ESD protection scheme had been reported. The decreasing- be used in a specific narrow band.
size distributed ESD protection scheme is shown in Fig. 23,
which allocates the ESD protection devices with decreasing • Design Complexity:
sizes from the I/O pad to the internal circuit [38]. With larger
ESD protection devices close to the I/O pad, ESD robustness – “Low”: The stand-alone ESD protection device is
is improved. It had also been verified that good wideband the ESD protection circuit without extra inductive
impedance matching is still maintained in this ESD protection component.
scheme. The simulated S21 -parameters of the π-model ESD – “Moderate”: The stand-alone ESD protection de-
protection scheme and distributed ESD protection scheme with vice is the ESD protection circuit without extra
equal-size ESD diodes are compared in Fig. 24. inductive component, but the layout of the ESD
Recently, the distributed ESD protection scheme has been protection device needs careful consideration.
reported to protect 60-GHz broadband RF circuits [39]. Fig. 25 – “High”: Besides the ESD protection device, extra
shows the measurement results on the S11 - and S21 -parameters inductive components are needed, and the auxiliary
of this distributed ESD protection circuit. This ESD protection components should be carefully designed.
214 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011

TABLE I
C OMPARISON A MONG ESD P ROTECTION D ESIGNS FOR RF C IRCUITS

• Equivalent Parasitic Capacitance: • HBM / CDM Robustness:

– “∼0 at Designed Frequency”: The equivalent par- – “Poor”: The HBM or charged device model (CDM)
asitic capacitance of the ESD protection circuit ESD robustness is poor due to the higher clamping
at the I/O pad can be very small with proper voltage at internal circuits.
design. – “Good”: The HBM or CDM ESD robustness is
– “Dozens ∼ Hundreds of fF”: The equivalent par- good due to the moderate clamping voltage at in-
asitic capacitance of the ESD protection circuit at ternal circuits.
the I/O pad is about dozens of fF or hundreds of fF, – “Better”: The HBM or CDM ESD robustness is
according to the used ESD protection devices and better due to the lower clamping voltage at internal
fabrication processes. circuits.

• Signal Loss: • Area Efficiency:

– “∼0 at Designed Frequency”: The simulated S21 - – “Poor”: The area efficiency of the ESD protection
parameters of the ESD protection circuit closed to design is poor.
0 dB at its operating frequencies. – “Good”: The area efficiency of the ESD protection
– “Worse at High Frequency”: The simulated S21 - design is good.
parameters of the ESD protection circuit are worse
at high frequency. The different RF front-end circuits have different require-
– “Worst at High Frequency”: The simulated S21 - ments on operating frequency, matching, noise, and other
parameters of the ESD protection circuit are distant specifications for the designs. The comparison of suggested
from 0 dB at high frequency. operating frequencies, design complexity, equivalent parasitic
capacitance, signal loss, clamping voltage at internal circuits,
• Clamping Voltage at Internal Circuits: HBM/CDM robustness, and area efficiency among various ESD
protection designs in Table I can provide the useful information
– “RESD ”: The clamping voltage seen at the internal for RF circuit designers to apply ESD protection solution to
circuits under ESD stress consists of the clamping their RF circuits.
voltage of one resistive/capacitive ESD protection The figure of merit used to compare the RF performance and
device. ESD robustness is (signal loss) × (clamping voltage at internal
– “LESD ”: The clamping voltage seen at the internal circuits). With the lower signal loss and clamping voltage at
circuits under ESD stress consists of the clamping internal circuits, the ESD protection design will be more suit-
voltage of one inductive ESD protection device. able for RF circuits. The conventional ESD protection circuit
KER et al.: OVERVIEW ON ESD PROTECTION DESIGNS FOR RF ICS IN CMOS TECHNOLOGIES 215

Fig. 26. Sample layout of (a) conventional ESD protection circuit (Fig. 3), (b) stacked ESD protection devices (Fig. 5), (c) parallel LC resonator (Fig. 7), (d) LC
tank (Fig. 8), (e) series LC resonator (Fig. 12), (f) impedance matching (Fig. 14), (g) inductive ESD protection (Fig. 16), (h) T-coil (Fig. 20), and (i) distributed
ESD protection (Fig. 21).

or stacked ESD protection devices may be suitable for some protection, the internal circuits can be clamped to the clamping
RF circuits operated with lower frequencies. As the operating voltage of one resistive/capacitive ESD protection device. The
frequencies of RF front-end circuits increase, on-chip ESD inductive ESD protection will clamp the internal circuits to the
protection designs with extra inductive components are needed. clamping voltage of one inductor. The LC tank and series LC
According to Table I, the reported ESD protection designs with resonator exist higher clamping voltage, since the ESD cur-
additional components can lower the equivalent parasitic capac- rent paths consist of one inductor and one resistive/capacitive
itance and signal loss at the I/O pad and mitigate the impacts ESD protection device. With the lower clamping voltage at
caused by the ESD protection circuit. By utilizing the proper internal circuits, the ESD protection design performed better
design, the ESD protection device can be realized with large ESD robustness, particularly in nanoscale CMOS processes
device dimensions to achieve good ESD robustness because with thinner gate oxide. It should be noted that the inductor has
the parasitic capacitance from the ESD protection device can large voltage overshoots during the CDM ESD stress, which
be compensated or cancelled. By using the scheme of parallel typically has a fast rise time of < 1 ns [40]. Therefore, the LC
LC resonator, impedance matching, T-coil, or distributed ESD tank, series LC resonator, and inductive ESD protection must be
216 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011

carefully selected to prevent from the large voltage overshoots

during CDM ESD stress. Besides, ESD protection designs
with extra inductive components substantially increase the chip
area, so the area efficiency of the schemes C ∼ I in Table I
are all poor. The fabrication costs also raise as the chip area
increase.
In nanoscale CMOS technology, the thinner gate oxide and
the silicided drain/source terminal seriously degrade the ESD
robustness of RF circuits. The clamping voltage across the RF
circuits under ESD stress must be reduced to improve ESD
robustness of the RF circuits. Therefore, the ESD current path
of ESD protection circuit must be shortened. Among the ESD
protection schemes in the literature, the conventional ESD pro-
tection circuit [14], impedance matching [24], inductive ESD
protection [27], [29], [31], T-Coil [33], [34], and distributed
ESD protection [39] with lower clamping voltage have been
verified in sub-100 nm CMOS processes with oxide thickness
of < 20 Å. Besides, the series LC resonator [23], inductive ESD
protection [27], and distributed ESD protection [39] have been
designed to operate with frequencies > 20 GHz. Therefore, Fig. 27. (a) Layout top view and (b) device cross-sectional view, of p+n-well
some ESD protection designs, such as inductive ESD protec- diode in waffle layout structure.
tion and distributed ESD protection, are still useful for RF
circuits fabricated in advanced CMOS processes and operating
at higher frequencies in the future. tion, the used LESD is 1.1 nH, and each ESD diode is 100 fF.
It should be note that the ESD inductors must be realized
with wide metal traces and occupy large chip area, so the
inductors usually dominate the layout area of ESD protection
V. L AYOUT E XAMPLES OF RF ESD circuits.
P ROTECTION D EVICES Besides, the resistive/capacitive ESD protection devices used
With various conditions, such as different ESD protection de- in every circuit can be carefully drawn to reduce their parasitic
vices, inductors, capacitors, pad styles, operating frequencies, capacitance in layout. The waffle layout structures for diodes
and fabrication processes, the layout style of every RF ESD pro- and SCR devices have been presented [41]–[43]. The ESD
tection scheme should be different. In this section, the sample protection device with the maximum ratio of perimeter to
layout of every RF ESD protection circuit operating at 5 GHz area is preferred because it has the maximum ratio of ESD
is provided in Fig. 26(a)–(i). The used resistive/capacitive ESD robustness to parasitic capacitance. Fig. 27 shows the layout top
protection devices are STI diodes, and the other used devices view and cross-sectional view of two waffle p+n–well diodes
include spiral inductors and metal-insulator-metal capacitors. connected in parallel. The p+ diffusions are implemented in the
The circuits are arranged with the pad style of ground-signal- n-well region and surrounded by the n+ diffusions. The arrows
ground and power-ground-power. in Fig. 27 show the ESD current paths. The ESD currents can
Fig. 26(a)–(i) show the sample layout of the conventional be discharged through four directions from each p+ diffusion.
ESD protection circuit (Fig. 3), stacked ESD protection devices Under the same parasitic capacitance, the waffle diodes have
(Fig. 5), parallel LC resonator (Fig. 7), LC tank (Fig. 8), the better ESD robustness than the traditional ESD diodes.
modified series LC resonator (Fig. 12), impedance match- In other words, the parasitic capacitance of ESD protection
ing (Fig. 14), inductive ESD protection (Fig. 16), T-diode devices in waffle layout can be reduced under the same ESD
(Fig. 20), and π-model ESD protection (Fig. 21), respectively. robustness.
In Fig. 26(c), the LESD and CESD used in parallel LC resonator Although the sample layout of RF ESD protection designs
are 1 nH and 1 pF, respectively; therefore, the resonant fre- are provided in this section, the actual layout in real case must
quency is ∼5 GHz. In Fig. 26(d), the LP and CP (LN and be carefully considered to optimize both RF performance and
CN ) used in LC tank are also 1 nH and 1 pF, respectively, to ESD robustness simultaneously.
resonate at ∼5 GHz, so the parasitic effects of diodes (DP and
DN ) are isolated at ∼5 GHz. In Fig. 26(e), the larger LESD
VI. C ONCLUSION
(6 nH) and CESD (1.5 pF) are used in modified series LC
resonator to resonate at < 2 GHz, and the application band A comprehensive overview in the field of ESD protection de-
covers 5 GHz. In Fig. 26(g), the large LESD (5 nH) is also sign for RF front-end circuits has been presented. To optimize
needed in inductive ESD protection to behave high impedance both RF performance and ESD robustness simultaneously, the
at 5 GHz. In Fig. 26(h), the LESD (0.42 nH), L2 (0.42 nH), undesired parasitic effects from ESD protection devices must
CB (42 fF), and DP and DN (500 fF) are used to realize ESD be minimized or cancelled. Furthermore, the ESD protection
protection with T-diode. In Fig. 26(i) of π-model ESD protec- circuits and RF front-end circuits can be co-designed to achieve
KER et al.: OVERVIEW ON ESD PROTECTION DESIGNS FOR RF ICS IN CMOS TECHNOLOGIES 217

both good circuit performance and high ESD robustness. The [23] B. Huang, C. Wang, C. Chen, M. Lei, P. Huang, K. Lin, and H. Wang,
on-chip ESD protection designs for RF circuits will continu- “Design and analysis for a 60-GHz low-noise amplifier with RF ESD
protection,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 2, pp. 298–
ously be an important design task, as the operating frequencies 305, Feb. 2009.
of RF circuits increase. [24] T. Chang, J. Chen, L. Rigge, and J. Lin, “ESD-protected wideband CMOS
LNAs using modified resistive feedback techniques with chip-on-board
packaging,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1817–
1826, Aug. 2008.
R EFERENCES [25] B.-S. Huang and M.-D. Ker, “New matching methodology of low-noise
amplifier with ESD protection,” in Proc. IEEE Int. Symp. Circuits Syst.,
[1] S. Voldman, ESD: RF Technology and Circuits. Hoboken, NJ: Wiley, 2006, pp. 4891–4894.
2006. [26] Y.-W. Hsiao and M.-D. Ker, “A 5-GHz differential low-noise ampli-
[2] A. Wang, H. Feng, R. Zhan, H. Xie, G. Chen, Q. Wu, X. Guan, Z. Wang, fier with high pin-to-pin ESD robustness in a 130-nm CMOS process,”
and C. Zhang, “A review on RF ESD protection design,” IEEE Trans. IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp. 1044–1053,
Electron Devices, vol. 52, no. 7, pp. 1304–1311, Jul. 2005. May 2009.
[3] M.-D. Ker and C.-M. Lee, “Interference of ESD protection diodes on RF [27] K. Raczkowski, S. Thijs, W. Raedt, B. Nauwelaers, and P. Wambacq, “50-
performance in giga-Hz RF circuits,” in Proc. IEEE Int. Symp. Circuits to-67 GHz ESD-protected power amplifiers in digital 45 nm LP CMOS,”
Syst., 2003, pp. 297–300. in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2009,
[4] K. Gong, H. Feng, R. Zhan, and A. Wang, “A study of parasitic effects of pp. 382–383.
ESD protection on RF ICs,” IEEE Trans. Microw. Theory Tech., vol. 50, [28] Y.-D. Shiu, B.-S. Huang, and M.-D. Ker, “CMOS power amplifier with
no. 1, pp. 393–402, Jan. 2002. ESD protection design merged in matching network,” in Proc. IEEE Int.
[5] C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and P. Mortini, Electron., Circuits Syst. Conf., 2007, pp. 825–828.
“Investigation on different ESD protection strategies devoted to 3.3 V [29] D. Linten, S. Thijs, M. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos,
RF applications (2 GHz) in a 0.18 μm CMOS process,” J. Electrostat., A. Mercha, S. Jenei, S. Donnay, and S. Decoutere, “A 5-GHz fully inte-
vol. 54, no. 1, pp. 55–71, Jan. 2002. grated ESD-protected low-noise amplifier in 90-nm RF CMOS,” IEEE J.
[6] X. Guan, X. Wang, L. Lin, G. Chen, A. Wang, H. Liu, Y. Zhou, H. Chen, Solid-State Circuits, vol. 40, no. 7, pp. 1434–1442, Jul. 2005.
L. Yang, and B. Zhao, “ESD-RFIC co-design methodology,” in Proc. [30] P. Leroux and M. Steyaert, “A 5 GHz CMOS low-noise amplifier with
IEEE Radio Freq. Integr. Circuits Symp., 2008, pp. 467–470. inductive ESD protection exceeding 3 kV HBM,” in Proc. Eur. Solid-State
[7] W. Soldner, M. Streibl, U. Hodel, M. Tiebout, H. Gossner, D. Schmitt- Circuits Conf., 2004, pp. 295–298.
Landsiedel, J. Chun, C. Ito, and R. Dutton, “RF ESD protection [31] J. Borremans, S. Thijs, P. Wambacq, Y. Rolain, D. Linten, and M. Kuijk,
strategies—Codesign vs. low-C protection,” Microelectron. Reliab., “A fully integrated 7.3 kV HBM ESD-protected transformer-based 4.5–
vol. 47, no. 7, pp. 1008–1015, Jul. 2007. 6 GHz CMOS LNA,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 344–
[8] V. Vassilev, S. Thijs, P. Segura, P. Leroux, P. Wambacq, G. Groeseneken, 353, Feb. 2009.
M. Natarajan, M. Steyaert, and H. Maes, “Co-design methodology to [32] S. Galal and B. Razavi, “Broadband ESD protection circuits in CMOS
provide high ESD protection levels in the advanced RF circuits,” in Proc. technology,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2334–2340,
EOS/ESD Symp., 2003, pp. 195–203. Dec. 2003.
[9] S. Voldman, ESD: Circuits and Devices. Hoboken, NJ: Wiley, 2006. [33] M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G. Bueren, L. Rodoni,
[10] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, T. Morf, T. Toifl, and M. Schmatz, “A T-coil-enhanced 8.5 Gb/s high-
2nd ed. Hoboken, NJ: Wiley, 2002. swing SST transmitter in 65 nm bulk CMOS with −16 dB return loss
[11] A. Wang, On-Chip ESD Protection for Integrated Circuits. Norwell, over 10 GHz bandwidth,” IEEE J. Solid-State Circuits, vol. 43, no. 12,
MA: Kluwer, 2002. pp. 2905–2920, Dec. 2008.
[12] S. Dabral and T. Maloney, Basic ESD and I/O Design. Hoboken, NJ: [34] D. Linten, S. Thijs, M. Okushima, M. Scholz, J. Borremans, M. Dehan,
Wiley, 1988. and G. Groeseneken, “A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD
[13] G. Boselli, J. Rodriguez, C. Duvvury, and J. Smith, “Analysis of ESD protected DC-to-16.1 GHz wideband LNA in 90 nm CMOS,” in Proc.
protection components in 65-nm CMOS technology: Scaling perspective EOS/ESD Symp., 2009, pp. 352–357.
and impact on ESD design windows,” in Proc. EOS/ESD Symp., 2005, [35] L. Moreno, D. Gomez, J. Gonzalez, D. Mateo, X. Aragones, R. Berenguer,
pp. 43–52. and H. Solar, “A low-power RF front-end for 2.5 GHz receivers,” in Proc.
[14] M. Tsai, S. Hsu, F. Hsueh, C. Jou, S. Chen, and M. Song, “A wideband IEEE Int. Symp. Circuits Syst., 2008, pp. 976–979.
low noise amplifier with 4 kV HBM ESD protection in 65 nm RF CMOS,” [36] M.-D. Ker, B.-J. Kuo, and Y.-W. Hsiao, “Optimization of broad-
IEEE Microw. Wireless Compon. Lett., vol. 19, no. 11, pp. 734–736, band RF performance and ESD robustness by π-model distributed
Nov. 2009. ESD protection scheme,” J. Electrostat., vol. 64, no. 2, pp. 80–87,
[15] D. Linten, S. Thijs, W. Jeamsaksiri, M. Natarajan, V. Heyn, V. Vassilev, Feb. 2006.
G. Groeseneken, A. Scholten, G. Badenes, M. Jurczak, S. Decoutere, [37] C. Ito, K. Banerjee, and R. Dutton, “Analysis and design of dis-
S. Donnay, and P. Wambacq, “Design-driven optimisation of a 90 nm RF tributed ESD protection circuits for high-speed mixed-signal and RF
CMOS process by use of elevated source/drain,” in Proc. Eur. Solid-State ICs,” IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1444–1454,
Device Res. Conf., 2003, pp. 43–46. Aug. 2002.
[16] M.-D. Ker and C.-Y. Chang, “ESD protection design for CMOS RF inte- [38] M.-D. Ker and B.-J. Kuo, “Decreasing-size distributed ESD protection
grated circuits using polysilicon diodes,” Microelectron. Reliab., vol. 42, scheme for broadband RF circuits,” IEEE Trans. Microw. Theory Tech.,
no. 6, pp. 863–872, Jun. 2002. vol. 53, no. 2, pp. 582–589, Feb. 2005.
[17] M.-D. Ker, T.-Y. Chen, and C.-Y. Chang, “ESD protection design [39] C.-Y. Lin, L.-W. Chu, M.-D. Ker, T.-H. Lu, P.-F. Hung, and H.-C. Li,
for CMOS RF integrated circuits,” in Proc. EOS/ESD Symp., 2001, “Self-matched ESD cell in CMOS technology for 60-GHz broadband RF
pp. 346–354. applications,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2010,
[18] S. Hyvonen, S. Joshi, and E. Rosenbaum, “Comprehensive ESD protec- pp. 573–576.
tion for RF inputs,” Microelectron. Reliab., vol. 45, no. 2, pp. 245–254, [40] J. Manouvrier, P. Fonteneau, C. Legrand, P. Nouet, and F. Azais, “Char-
Feb. 2005. acterization of the transient behavior of gated/STI diodes and their asso-
[19] S. Hyvonen, S. Joshi, and E. Rosenbaum, “Cancellation technique to ciated BJT in the CDM time domain,” in Proc. EOS/ESD Symp., 2007,
provide ESD protection for multi-GHz RF inputs,” Electron. Lett., vol. 39, pp. 165–174.
no. 3, pp. 284–286, Feb. 2003. [41] C.-T. Yeh, M.-D. Ker, and Y.-C. Liang, “Optimization on layout style of
[20] M.-D. Ker and Y.-W. Hsiao, “Impedance-isolation technique for ESD pro- ESD protection diode for radio-frequency front-end and high-speed I/O
tection design in RF integrated circuits,” IEICE Trans. Electron., vol. E92- interface circuits,” IEEE Trans. Device Mater. Rel., vol. 10, no. 2, pp. 238–
C, no. 3, pp. 341–351, Mar. 2009. 246, Jun. 2010.
[21] M.-D. Ker, C.-I. Chou, and C.-M. Lee, “A novel LC-tank ESD protection [42] K. Bhatia, N. Jack, and E. Rosenbaum, “Layout optimization of ESD
design for giga-Hz RF circuits,” in Proc. IEEE Radio Freq. Integr. Circuits protection diodes for high-frequency I/Os,” IEEE Trans. Device Mater.
Symp., 2003, pp. 115–118. Rel., vol. 9, no. 3, pp. 465–475, Sep. 2009.
[22] M.-D. Ker and C.-M. Lee, “ESD protection design for giga-Hz RF CMOS [43] M.-D. Ker and C.-Y. Lin, “Low-capacitance SCR with waffle layout struc-
LNA with novel impedance-isolation technique,” in Proc. EOS/ESD ture for on-chip ESD protection in RF ICs,” IEEE Trans. Microw. Theory
Symp., 2003, pp. 204–213. Tech., vol. 56, no. 5, pp. 1286–1294, May 2008.
218 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011

Ming-Dou Ker (S’92–M’94–SM’97–F’08) received Chun-Yu Lin (S’06–M’09) was born in Taiwan, in
the Ph.D. degree from the Institute of Electronics, 1984. He received the B.S. degree from the De-
National Chiao-Tung University, Hsinchu, Taiwan, partment of Electronics Engineering, and the Ph.D.
in 1993. degree from the Institute of Electronics, National
He worked as the Department Manager with the Chiao-Tung University, Hsinchu, Taiwan, in 2006
VLSI Design Division, Computer and Communica- and 2009, respectively.
tion Research Laboratories, Industrial Technology Since 2009, he has been a Postdoctoral Researcher
Research Institute (ITRI), Hsinchu. Since 2004, he of National Chiao-Tung University. His current re-
has been a Full Professor with the Department of search interests include ESD protection designs and
Electronics Engineering, National Chiao-Tung Uni- biomimetic circuit designs. From 2010, he has also
versity. From 2008, he was rotated to be Chair Pro- served as the Secretary-General of Taiwan ESD
fessor and Vice President of I-Shou University, Kaohsiung, Taiwan. Now, he Association.
has been the Distinguished Professor in the Department of Electronics Engi-
neering, National Chiao-Tung University. During 2010–2011, he served as the
Executive Director of National Science and Technology Program on System-
on-Chip in Taiwan. Starting from 2011, he also served as the Executive Director
of National Science and Technology Program on Nano Technology in Taiwan.
In the technical field of reliability and quality design for microelectronic circuits
and systems, he has published over 400 technical papers in international jour-
nals and conferences. He has proposed many solutions to improve the reliability
and quality of integrated circuits, which have been granted with 177 U.S.
patents and 153 Taiwan patents. He had been invited to teach and/or to consult
the reliability and quality design for integrated circuits by hundreds of design
houses and semiconductor companies in the worldwide IC industry. His current
research interests include reliability and quality design for nanoelectronics and Yuan-Wen Hsiao (S’03–M’08) was born in Taiwan,
gigascale systems, high-speed and mixed-voltage I/O interface circuits, on- in 1982. He received the B.S. degree from the De-
glass circuits for system-on-panel applications, and biomimetic circuits and partment of Electronics Engineering, and the Ph.D.
systems for intelligent prosthesis. degree from the Institute of Electronics, National
Prof. Ker has served as a member of the Technical Program Committee Chiao-Tung University, Hsinchu, Taiwan, in 2004
and the Session Chair of numerous international conferences for many years. and 2008, respectively.
He ever served as the Associate Editor for the IEEE Transactions on VLSI In 2009, he was with Richtek Technology
Systems, 2006–2007. He was selected as the Distinguished Lecturer in the IEEE Corporation, Hsinchu, Taiwan, as a Senior Engineer.
Circuits and Systems Society (2006–2007) and in the IEEE Electron Devices His current research interests include analog circuit
Society (2008–present). He was the President of Foundation in Taiwan ESD design, ESD protection design for RF ICs and high-
Association. In 2009, he was awarded as one of the top ten Distinguished speed I/O interface circuits, and ESD issues in IC
Inventors in Taiwan. products.