TECHNICAL ARTICLE

| Share on Twitter | Share on LinkedIn | Email

A Review of Wideband RF Receiver

Architecture Options
Peter Delos
Analog Devices, Inc.

Introduction
The heterodyne receiver has been the standard receiver option of choice The heterodyne approach is well proven and provides exceptional perfor-
for decades. In recent years, the rapid advance of analog-to-digital mance. The implementation is to mix to an intermediate frequency (IF).
converter (ADC) sampling rates, the inclusion of embedded digital The IF is chosen at a high enough frequency to allow practical filters in
processing, and the integration of matched channels now offers options the operating band to provide good image rejection and LO isolation.
for the receiver architect that were not practical only a few years ago. It is also common to add an additional mixing stage to lower the frequency
where very high dynamic range ADCs are available. Additionally, the
This article compares the benefits and challenges of three common receiver gain is distributed at different frequencies, which minimizes the
receiver architectures: a heterodyne receiver, a direct sampling receiver, risk of oscillation in high gain receivers. Through proper frequency
and a direct-conversion receiver. Additional consideration on spurious planning, the heterodyne receiver can be made with very good spurious
system noise and dynamic range is also discussed. The intention is not energy and noise performance. Unfortunately, this architecture is the most
to promote one option over others—but rather describe the pros and cons complicated. It typically requires the most power and the largest physical
of the options, and encourage the designer to select, through engineering footprint relative to the available bandwidth. In addition, frequency planning
discipline, the architecture most appropriate for the application. can be quite challenging at large fractional bandwidths. These challenges
are significant with the modern quest toward low size, weight, and
Architecture Comparison power (SWaP), combined with the desire for wide bandwidth, and lead
Table 1 compares the heterodyne, direct sampling, and direct-conversion to designers considering other architecture options when possible.
architectures. The basic topology is shown along with some of the benefits
a. Heterodyne with 2nd Nyquist IF Sampling
and challenges of each architecture. Downconversion
LO Clock
Aliasing

Table 1. Receiver Architecture

a. Heterodyne Comparison
with 2 Nyquist IF Sampling nd

Rx Downconversion
ADC
LO Clock
Aliasing
Type Configuration Benefits
a. Heterodyne with 2nd Nyquist IF0 Sampling
Fs/2 Fs Challenges
Fc High-Side
Downconversion LO =
Heterodyne Rx LO Clock  Proven trusted + 3SWaP
Fc Fs/4
ADC Aliasing
High performance
b. Direct Sampling with Digital Downconversion  Many filters
Clock  OptimumFs/2spurious
0Digital Fs noise Fc High-Side
Rx Downconversion
 High dynamic range Aliasing LO =
ADC I
 EMI immunity Fc + 3 Fs/4
Rx
NCO with Digital0Downconversion
ADC Sampling
b. Direct Fs/2 Fs Fc High-Side
Direct Sampling Clock  No mixing Digital  ADCLO = bandwidth
input
Q  Practical Fc + 3 Fs/4
I0 at L-, S-band Aliasing
Downconversion  Gain not distributed across frequency
b. Direct Sampling with Digital Downconversion NCO Fs/2 Fs
Rx Clock Digital
ADC NCO
I Downconversion Aliasing
c. Direct-Conversion/Zero IF
Rx Q
Direct-Conversion ADC NCO Clock  Maximum 0ADC bandwidth
NCO Fs/2
 Image
Fs rejection
I
 Simplest wideband option • I/Q balance
ADC Q Downconversion  In-band IF harmonics
c. Direct-Conversion/Zero IF 0 NCO Fs/2 Fs  LO radiation
Rx 0 LO
90
Clock  EMI immunity (IP2)
Q  DC and 1/f noise
c. Direct-Conversion/ZeroADC
IF I –Fs –Fs/2 0 Fs/2 Fs LO
ADC Downconversion
Clock
Rx 0I
90 LO
ADC Downconversion
Q
Rx ADC
0 LO –Fs –Fs/2 0 Fs/2 Fs LO
90
Q
ADC
–Fs –Fs/2 0 Fs/2 Fs LO

Visit analog.com
 2 A Review of Wideband RF Receiver Architecture Options

The direct sampling approach has long been sought after. The obstacles The image rejection challenges of the direct-conversion architecture can
have been operating the converters at speeds commensurate with direct be quite difficult to overcome in a discrete implementation. With further
RF sampling and achieving large input bandwidth. In this architecture, all integration combined with digitally assisted processing, the I/Q channels
the receiver gain is at the operating band frequency, so careful layout is can be well matched, leading to much improved image rejection. The
required if large receiver gain is desired. Today converters are available receiver section of the recently released AD9371 is a direct-conversion
for direct sampling in higher Nyquist bands at both L- and S-band. receiver and shown in Figure 2—note the similarity to Figure 1c.
Advances are continuing and C-band sampling will soon be practical,
with X-band sampling to follow. AD9371
Rx1+ Rx1
Direct-conversion architectures provide the most efficient use of the data Rx1– Rx2 LPF
Decimation,

JESD204B
pFIR, AGC,
converter bandwidth. The data converters operate in the first Nyquist, Rx2+ ADC DC Offset,
where performance is optimum and low-pass filtering is easier. The two Rx2– LPF
QEC, Tuning,
RSSI, Overload
data converters work together sampling I/Q signals, thus increasing the ADC
user bandwidth without the challenges of interleaving. The dominant
Microcontroller
challenge that has plagued direct-conversion architecture for years has Rx_EXTLO+ LO RF
been to maintain I/Q balance for acceptable levels of image rejection, LO Rx_EXTLO–
External
Generator Synthesizer

leakage, and dc offsets. In recent years, the advanced integration of the Option
entire direct-conversion signal chain, combined with digital calibrations, Figure 2. Receiver section of the AD9371: A monolithic direct-conversion receiver.
has overcome these challenges and the direct-conversion architecture is
well positioned to be a very practical approach in many systems. Spurious Noise
Frequency Plan Perspective Any design with frequency translation requires much effort to minimize
unwanted frequencies folding in-band. This is the art of frequency
Figure 1 illustrates block diagrams and frequency plan examples of the planning and involves a balance of available components and practical
three architectures. Figure 1a is an example of a heterodyne receiver with a filter design. Some of the spur folding concerns are briefly discussed
high-side LO mixing the operating band to the 2nd Nyquist zone of the ADC. and the designer is referred to the references for further explanation.
The signal is further aliased to the 1st Nyquist zone for processing. Figure 1b
shows a direct sampling receiver example. The operating band is sampled 1st Nyquist 2nd Nyquist 3rd Nyquist

in the 3rd Nyquist zone and aliases to the 1st Nyquist, then an NCO is placed
in the center of the band, digitally downconverting to baseband, followed 1.0

by filtering and decimation, reducing the data rate commensurate with the
channel bandwidth. Figure 1c is a direct-conversion architecture example. 0.8
1st Nyquist Output Frequency

By mating the dual ADC with a quadrature demodulator, Channel 1 samples

the I (in phase) signal and Channel 2 samples the Q (quadrature) signal.
0.6
Many modern ADCs support all three architectures. For example,
the AD9680 is a dual, 1.25 GSPS ADC with programmable digital
downconversion. A dual ADC of this type supports 2-channel heterodyne 0.4
and direct sampling architectures, or the converters can work as a pair
in a direct-conversion architecture.
0.2
a. Heterodyne with 2nd Nyquist IF Sampling
Downconversion
LO Clock
Aliasing
0
0 0.5 1 1.5 2 2.5 3
Rx Input Frequency (Relative to Nyquist Bands)
ADC

0 Fs/2 Fs Fc High-Side Fundamental

LO = 2nd Harmonic
Fc + 3 Fs/4 3rd Harmonic
b. Direct Sampling with Digital Downconversion Figure 3. ADC frequency folding.
Clock Digital
I Downconversion Aliasing Figure 3 shows the folding of the ADC input frequency and the first two
Rx
ADC NCO
harmonics as a function of input frequency relative to the Nyquist band
frequencies. For channel bandwidths much less than the Nyquist
Q bandwidth, a goal for the receiver designer is to select operating points
0 NCO Fs/2 Fs
that place the folded harmonics out of the channel bandwidth.

c. Direct-Conversion/Zero IF
Clock

I
ADC Downconversion

Rx 0
90 LO

Q
ADC
–Fs –Fs/2 0 Fs/2 Fs LO
Figure 1. Frequency plan examples.
 Visit analog.com 3

The receiver downconversion mixer has additional complications. Any The selection of receiver gain prior to the ADC and determining the
mixer creates harmonics inside the device. These harmonics all mix required ADC SNR is a balance of the overall receiver noise figure and
together and create additional frequencies. This effect is illustrated in instantaneous dynamic range. Figure 5 provides a representation of the
Figure 4. parameters to be considered. For illustrative purposes, the receiver noise
LO is shown to be shaped by the antialiasing filter prior to the ADC. The ADC
noise is shown as flat white noise and the signal of interest is shown as
• Fundamental at LO – RF or RF – LO
RF IF • Spurs at nRF ± mLO a continuous wave (CW) tone at –1 dBFS.
1.0

Signal at –1 dBFS

0.8

Amplitude (dBm or dBFs)

Noise Limited Dynamic Range
= Signal – Noise Power in
Frequency (FIF/FLO)

0.6 Channel Bandwidth

ADC Sensitivity Loss

0.4

0.2

0
0 0.5 1 1.5 2 Frequency (ADC Nyquist Band)
Frequency (FRF/FLO)
Total Noise
LO – RF, RF – LO Receiver Noise
1st Order Spurs ADC Noise
2nd Order Spurs
3rd Order Spurs Figure 5. Receiver + ADC noise.
Figure 4. Downconversion mixer spurious. First, common units of either dBm or dBFS are needed. Converting the
Figure 3 and Figure 4 only plot spurs up to the third order. In practice, ADC noise from dBFS to dBm is known from the converter full-scale level
these are spurs of additional higher order, which quickly creates a and the converter noise density. In addition, noise power is proportional to
spurious-free, dynamic range issue for the designer. For narrow fractional bandwidth, so a common bandwidth unit is needed. Some designers will
bandwidths, meticulous frequency planning can overcome the mixer use the channel bandwidth, here we normalize to a 1 Hz bandwidth and
spurious problems. As bandwidths increase, the mixer spurious problem noise powers are /Hz.
becomes a dominant obstacle. As ADC sampling frequencies increase, it ADC noise(dBm/Hz) = ADC full scale(dBm) +
is sometimes more practical for a direct sampling architecture (4)
ADC noise density(dBFS/Hz)
to have lower spurious performance.
The total noise is calculated as
Receiver Noise Total Noise (dBm/Hz) =
Much receiver design effort is placed on minimizing noise figure (NF).  (5)
 Receiver Noise (dBm/Hz) ADC Noise (dBm/Hz)
Noise figure is a measure of the degradation in signal to noise ratio.

10log10  10 10 + 10 10 
(S/N)In


F= , standardized at 290 K (TO)
(S/N)Out (1) This leads to the concept of ADC sensitivity loss. ADC sensitivity loss is a
measure of the receiver noise degradation due to the ADC. To minimize
NF = 10logF this degradation, the receiver noise is desired to be well above the ADC
noise. The limitation comes in the form of dynamic range and larger
The impact of a component or subsystem noise figure is that the output
receiver gain limits the maximum signal received without ADC saturation.
noise power is increased above the level of thermal noise and gain by the
noise figure. ADC Sensitivity Loss (dB) = Total Noise (dBm/Hz)
–
(6)
Term Gain/NF Receiver Noise (dBm/Hz)

(2) Thus, the receiver designer faces a constant challenge of balancing
dynamic range vs. noise figure.

Noise Power Out = –174 dBm/Hz + Gain(dB) + NF(dB)

Cascaded noise figure is calculated as

F2 – 1 F3 – 1
FTotal = F1 + + +
Gain1 Gain1 × Gain2
(3)
FN – 1
…+
Gain1 × Gain2 × … × GainN– 1
Conclusion
The heterodyne, direct sampling, and direct-conversion receiver
architectures have been reviewed with emphasis on benefits and About the Author
challenges of each architecture. Recent trends and considerations in Peter Delos is a technical lead at Analog Devices, Inc., in the
receiver design have also been presented. With the worldwide desire Aerospace and Defense Group. He received his B.S.E.E. from
for more bandwidth, combined with the advancement of GSPS data Virginia Tech in 1990 and M.S.E.E. from NJIT in 2004. He has
converters, it is anticipated that many varied receiver designs will over 25 years of industry experience.
proliferate well into the future.
Most of his career has been spent designing advanced RF/analog
systems at the architecture level, PWB level, and IC level. His career
References
includes various positions in the Naval nuclear power submarine
Delos, Peter. “Receiver Design Considerations in Digital Beamforming program and at Lockheed Martin, Moorestown, NJ, in multiple radar
Phased Arrays.” Microwaves and RF, 2014. and EW programs. In 2016, he accepted his current position with
Harris, Jonathan. “What’s Up with Digital Downconverters Part 1 and 2.” Analog Devices in Greensboro, NC.
Analog Dialogue, 2016.
Henderson, Bert. “Mixers in Microwave Systems.” WJ Tech-Note, 1990.
Kester, Walt. “Analog-Digital Conversion.” Analog Devices, 2004. Online Support
McClanning, Kevin and Tom Vito. “Radio Receiver Design.” New York,
Community
Noble Publishing, 2000. Engage with the
Analog Devices technology experts in our online support
Razavi, Behazd. “Design Considerations for Direct-Conversion Receivers.” community. Ask your tough design questions, browse FAQs,
IEEE, 1997. or join a conversation.
Fundamentals of RF and Microwave Noise Figure Measurements. Keysight
Application Note. Visit ez.analog.com

Analog Devices, Inc. Analog Devices, Inc. Analog Devices, Inc. Analog Devices, Inc. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and
Worldwide Headquarters Europe Headquarters Japan Headquarters Asia Pacific Headquarters registered trademarks are the property of their respective owners.
Ahead of What’s Possible is a trademark of Analog Devices.
Analog Devices, Inc. Analog Devices, Inc. Analog Devices, KK Analog Devices TA15507-0-2/17
One Technology Way Otl-Aicher-Str. 60-64 New Pier Takeshiba 5F, Sandhill Plaza
P.O. Box 9106 80807 München South Tower Building 2290 Zuchongzhi Road analog.com
Norwood, MA 02062-9106 Germany 1-16-1 Kaigan, Minato-ku, Zhangjiang Hi-Tech Park
U.S.A. Tel: 49.89.76903.0 Tokyo, 105-6891 Pudong New District
Tel: 781.329.4700 Fax: 49.89.76903.157 Japan Shanghai, China 201203
(800.262.5643, U.S.A. only) Tel: 813.5402.8200 Tel: 86.21.2320.8000
Fax: 781.461.3113 Fax: 813.5402.1064 Fax: 86.21.2320.8222