5 4 3 2 1

Model : MX0/M40/50 EI0

D

Mobile Dothan with INTEL 915GM / ICH6-M Chipset D

P/N:37GM50100-C0

PG01 INDEX PG21 LANRTL8100CL

C
PG02 SYSTEM BLOCK DIAGRAM PG22 1394 TSB43AB22A C

PG03 POWER DIAGRAM & SEQUENCE PG23 MINIPCI (Wirless) / CRT & AUDIO CONN
PG04 GPIO & POWER CONSUMPTION PG24 EC IT8510E / BIOS / Keyboard & TP CONN
PG05 CPU Banias/Dothan-1/2 PG25 CPU_CORE
PG06 CPU Banias/Dothan-2/2 PG26 1.5V / 1.8V / 2.5V / 0.9V
PG07 CLOCK GEN ICS954206 PG27 +3.3V / +5V / +12V
PG08 NB_Alviso Host-1/5 PG28 BATT IN / Charger
PG09 NB DDRCLK_VGA_PCIEXPR-2/5 PG29 VCC SW / +1.05VS / +1.5VS
PG10 NB DDR_MEM SYSTEM-3/5 PG30 +1.05VS
PG11 NB POWER-4/5 PG31 MDC BD
PG12 NB VSS_NCTF-5/5 PG32 SWITCH BD 1/3
PG13 DDR2 CHANNELA,B SODIMM0,1 PG33 SWITCH BD 2/3
B PG14 DDR2 Terminate / Smart Power PG34 SWITCH BD 3/3 B

PG15 SB ICH-6M-1/3 PG35 Appendix A. Ver. History

PG16 SB ICH-6M-2/3
PG17 SB ICH-6M-3/3
PG18 DC IN / CARD BUS / FAN / MIC / BLUETOOH
PG19 LCD / INVERTER / USB / TV / IO
PG20 SATA HDD / CD-ROM

A A

UNIWILL COMPUTER CORP.

Title

MX0/M40/50EI0
Size Document Number Rev
Custom INDEX C
3017
Date: Tuesday, August 09, 2005 Sheet 1 of 35
5 4 3 2 1
 5 4 3 2 1

M50EI0
CPU
BLOCK DIAGRAM Dothan
Socket 478 THERMAL
EC
D
ADM1032 D

HOST BUS
333/400MHZ DDR2 RAM BUS

North Bridge CRT

INTEL LCD
SODIMM0 915GM
SODIMM1
+1.8V_DDR
+1.8V_DDR
+1.25V_DDR terminal
S-Video TV
+1.25V_DDR terminal
DMI
AC97/AZALIA
RTC
Daugher BD-2 PCI BUS South Bridge
AUDIO CODEC MDC INTEL
C
ICH6-M C

ALC880

AMPLIFIER SATA
MIC RJ11
TPA6011A4 PCIE NEW CARD
USB
Daugher BD-1
LINE OUT * 1 PHDD 2.5"
INTERNAL MIC * 1 +5V USB*8
SPK SPDIF OUT * 1 LAN MASTER
RTL8100CL

MINI PCI PATA USB*4 CARD READER

( Wireless ) CRYSTAL GL817E
RJ45 25M HZ Daugher BD-2

DVD LPC BUS

B ROM B

+5V
CRYSTAL PRIMARY
14.318MHz PCMCIA IEEE-1394A
MASTER
TI1410 TSB43AB22A
Daugher BD-3
(Reserve)
Clock Gen
CRYSTAL CRYSTAL
ICS K/B CONTROLLER
24.576M Hz 32.768K Hz
ICS954127 ITE 8510

X-BUS PS2/IIC

INT K/B T/P FAN CHARGER BATTERY

FLASH ROM IR
A
Daugher BD-4 A

(Reserve)

UNIWILL COMPUTER CORP.

Title

MX0/M40/50EI0
Size Document Number Rev
C
3017 SYSTEM BLOCK DIAGRAM
Date: Tuesday, August 09, 2005 Sheet 2 of 35
5 4 3 2 1
 5 4 3 2 1

POWER BLOCK DIAGRAM

VID0 VIN +2.5V_DDR
VID1 VIN
D D
VID2 RSS090N03 RT9173B +1.25V_DDR
VID3 SC451
PWM IC RSS090N03 CPU_CORE
VID4 SI4362
VID5 High / Low Side MOS

POWER Sequence
VIN +5VA
+3VA,+5VA,+12VA
Ctrl. MOS

PWRSW
RSS090N03 AO4422 +5V
Ctrl. MOS
. +3.3VS_ON
High / Low Side MOS +5VS,+12VS
C
SI2302 +5VS C
+3.3VS

SC1404 +12VA . +1.5VS_ON

PWM IC Ctrl. MOS 1ms
+1.5VS

SI2301 +12VS . +1.05VS_ON

. +1.8V_DDR_ON
+1.8VS 1ms

VIN +3.3VS 1ms

+1.05VS
+3.3VA
50ms
Ctrl. MOS Ctrl. MOS . RSMRST# 10ms
+2.5VS_SYSTEM . PWRBTN# 1s
RSS090N03 AO4422 RT9173B
. +5V_ON
High / Low Side MOS AO4422 +3.3V +5V
5.8ms

B B
40ms
Ctrl. MOS Ctrl. MOS +3.3V
+1.8V_SYSTEM
+2.5V
RT9173B
. +1.8V_ON
VIN +1.5VS +1.8V
Ctrl. MOS
+1.05V

RSS090N03 AO4422 +1.5V +1.5V

. Vcore_ON 7ms

High / Low Side MOS

Vcore

+1.8V_DDR . PWROK/VR_PWRGD 110ms

ISL6227 +1.8VS_DDR H_PWRGD

PWM IC Ctrl. MOS
VIN
A
PCIRST#/PLTRST# A
AO4422 +0.9V_DDR
CPURST#

RSS090N03
. EC Control Pin UNIWILL COMPUTER CORP.
High / Low Side MOS JP13 +1.8V_SYSTEM Title

MX0/M40/50EI0
Size Document Number Rev
Custom POWER DIAGRAM C
3017
Date: Tuesday, August 09, 2005 Sheet 3 of 35
5 4 3 2 1
 5 4 3 2 1

ICH6-M ITE8510E ITE8510E CPU ITE8510E

GPIO GPIO GPIO CPU CORE(V)ICC(mA) W TEMP(　)
VCC ICC(mA) W TEMP(　)
GPI6 BM_BUSY# GPCF0 TURBO#/PHOTO GPC0 PWROK 2.0G 1.525 35.7 54.3 69
+3.3V 300 1 70
GP7 GPCF1 SILENT#/TV GPC1 BAT2_SMBCLK 2.2G 1.525 37.5 57.1 70
GP8 EC_EXTSMI# GPCF2 BAT_SEL GPC2 BAT2_SMBDAT 2.26G 1.525 38.1 58.0 70
GPI11 SMB_ALERT# GPCF3 BAT_THROT_EN GPC3 2.4G 1.525 39.3 59.8 71
D GPI12 GPCF4 TP_CLK GPC4 2.5G 1.525 40 61.0 72 D

GPI13 GPCF5 TP_DATA GPC5 A/W_LED3# 2.53G 1.525 40.4 61.5 72 CLOCK GENERATOR
GPO18 PM_STPPCI_ICH# GPCF6 MAIL#/DVD GPC6 CHG_ON 2.6G 1.525 41.05 62.6 72
VCC ICC(mA) W TEMP(　)
GPO19 GPCF7 BROWSER#/MP3 GPC7 SILENT_LED# 2.66G 1.525 43.35 66.1 74
+3.3V 180 0.594 70
GPO20 PM_STPCPU_ICH# GPI0 SCROLL# 2.8G 1.525 44.86 68.4 75
GPO21 TPM_EN GPI1 CAPS# 3.06G 1.525 55.9 85.2 81
GPO23 GPI2 NUM#
GPIO24 GPI3 CHGLED_ON#
GPIO25 GPI4 A/W_LED1# ADM1032
GPIO26 SATA0_GP GPI5 SUSLED_ON#
VCC ICC W TEMP(　)
GPIO27 GPI6 A/W_LED2#
MCHE +3.3V 170uA 0.56mW 150
GPIO28 GPH0 +1.8V_DDR_ON
GPIO29 PNLSW1 GPH1 +1.8V_ON VCC ICC(mA) W TEMP(　)
GPIO30 PNLSW2 GPH2 +1.05VS_ON +3.3V 108.19 0.357
GPIO31 PNLSW0 GPH3 +3.3VS_ON +3.3VA 501.3 1.254
GPIO32 PM_CLKRUN# GPH4 +5V_ON +2.5V 1390 2.502
70
C GPIO33 GPH5 SET_V +1.5V 33.4 0.084 C

GPIO34 GPH6 +1.5VS_ON +VCCP 10 0.018

+VCC_GMCH_CORE
GPH7 VCORE_ON 266 0.452
GPG4
GPG5 LCDSW
GPG6 MUTE#
GPG7 EXTTS#0
GPB0 CELERON_VO_DET
GPB1 TURBO_LED#
GPB2 PM_RSMRST# SB INT_PIRQ List
GPB3 BAT_SMBCLK INT_PIRQA CARD BUS ICH6-M
GPB4 BAT_SMBDAT INT_PIRQB Mini PCI VCC ICC(mA) W TEMP(　)
GPB5 H_A20GATE INT_PIRQC 1394 +3.3V 96 0.315
GPB6 H_RCIN# INT_PIRQD LAN +3.3VA 275 0.909
GPB7 RFLED_ON# INT_PIRQE CARD BUS(op) +1.5V 487 0.876
70
GPE0 INT_PIRQF Mini PCI +1.5VA 27 0.049
B GPE1 CPU_BSEL0 INT_PIRQG NC +3.3VA_RTC 0.003 0.00001 B

GPE2 TP_BTU INT_PIRQH NC

GPE3 TP_BTD
GPE4 PWRSW
GPE5 LID#
GPE6 RF_OFF
GPE7 PM_SLP_S3#
GPD0 ADAP_IN
GPD1 AW#/CD
GPD2 PCI_RST#/PLT_RST#
GPD3 EC_EXTSMI#
GPD4
GPD5
GPD6 CLKREQ#
GPD7 EC_PREST#
GPA0 BTL_BEEP
A GPA1 EC_VID1 A

GPA2 EC_VID2
GPA3 EC_VID3
GPA4 EC_VID4
GPA5 SMP1_EN# UNIWILL COMPUTER CORP.
GPA6 SMP2_EN# Title

GPA7 PWRBTN# MX0/M40/50EI0

Size Document Number Rev
Custom GPIO & POWER CONSU C
3017
Date: Tuesday, August 09, 2005 Sheet 4 of 35
5 4 3 2 1
 5 4 3 2 1

U37A +1.05V U37B

8 H_A#[31:3] 8 H_D#[63:0] H_D#[63:0] 8
H_A#3 P4 N2 H_D#0 A19 Y26 H_D#32
A3# ADS# H_ADS# 8 D0# D32#
H_A#4 U4 L1 H_D#1 A25 AA24 H_D#33
A4# BNR# H_BNR# 8 D1# D33#
H_A#5 V3 J3 R308 H_D#2 A22 T25 H_D#34
A5# BPRI# H_BPRI# 8 D2# D34#
H_A#6 R3 H_D#3 B21 U23 H_D#35
A6# 56 D3# D35#

ADDR GROUP 0
H_A#7 V2 L4 H_D#4 A24 V23 H_D#36
A7# DEFER# H_DEFER# 8 D4# D36#
H_A#8 W1 H2 H_D#5 B26 R24 H_D#37
A8# DRDY# H_DRDY# 8 D5# D37#
H_A#9 T4 M2 Place testpoint on H_D#6 A21 R26 H_D#38
A9# DBSY# H_DBSY# 8 D6# D38#

DATA GRP0
CONTROL
H_A#10 W2 H_D#7 B20 R23 H_D#39

DATA GRP2
D
H_A#11 A10# H_IERR# with a GND H_D#8 D7# D39# H_D#40
D
Y4 A11# BR0# N4 H_BREQ#0 8 C20 D8# D40# AA23
H_A#12 Y1 H_D#9 B24 U26 H_D#41
H_A#13 A12# H_IERR# 0.1" away H_D#10 D9# D41# H_D#42
U1 A13# IERR# A4 D24 D10# D42# V24
H_A#14 AA3 B5 H_D#11 E24 U25 H_D#43
A14# INIT# H_INIT# 15 D11# D43#
H_A#15 Y3 H_D#12 C26 V26 H_D#44
H_A#16 A15# H_RS#[2:0] H_D#13 D12# D44# H_D#45
AA2 A16# LOCK# J2 H_LOCK# 8 H_RS#[2:0] 8 B23 D13# D45# Y23
U3 H_D#14 E23 AA26 H_D#46
8 H_ADSTB#0 ADSTB#0 D14# D46#
8 H_REQ#[4:0] RESET# B11 H_CPURST# H_CPURST# 8
H_D#15 C25 D15# D47# Y25 H_D#47
H1 H_RS#0 C23 W25
RS0# H_RS#1 8 H_DSTBN#0 DSTBN0# DSTBN2# H_DSTBN#2 8
H_REQ#0 R2 K1 C22 W24
REQ0# RS1# H_RS#2 8 H_DSTBP#0 DSTBP0# DSTBP2# H_DSTBP#2 8
H_REQ#1 P3 L2 D25 T24
REQ1# RS2# +1.05V 8 H_DINV#0 DINV0# DINV2# H_DINV#2 8
H_REQ#2 T2 M3
REQ2# TRDY# H_TRDY# 8 8 H_D#[63:0] H_D#[63:0] 8
H_REQ#3 P1
H_REQ#4 REQ3# H_D#16 H_D#48
8 H_A#[31:3] T1 REQ4# HIT# K3 H_HIT# 8 H23 D16# D48# AB25
K4 H_D#17 G25 AC23 H_D#49
H_A#17 HITM# H_HITM# 8 D17# D49#
AF4 H_D#18 L23 AB24 H_D#50
H_A#18 A17# Z0501 H_D#19 D18# D50# H_D#51
AC4 A18# BPM#0 C8 TP1 M26 D19# D51# AC20 Layout note:
H_A#19 AC7 B8 Z0502 R310 H_D#20 H24 AC22 H_D#52
A19# ADDR GROUP 1 BPM#1 TP2 D20# D52#
H_A#20 AC3 A9 Z0503 H_D#21 F25 AC25 H_D#53 Comp1 ,3 connect with Zo = 55
A20# BPM#2 TP3 D21# D53#

DATA GRP1
ITP SIGNALS
H_A#21 AD3 C9 Z0504 56_OP H_D#22 G24 AD23 H_D#54

DATA GRP3
A21# BPM#3 TP4 D22# D54# Ohm,make
H_A#22 AE4 A10 Z0505 H_D#23 J23 AE22 H_D#55
A22# PRDY# TP5 D23# D55#
H_A#23 AD2 B10 Z0506 Modify M30 in R:B H_D#24 M23 AF23 H_D#56 Comp0 ,2 connect with Zo = 27.4
H_A#24 A23# PREQ# TCK H_D#25 D24# D56# H_D#57
AB4 A24# TCK A13 TP6 J25 D25# D57# AD24 Ohm,make
H_A#25 AC6 C12 TDI H_D#26 L26 AF20 H_D#58
A25# TDI TP7 D26# D58#
H_A#26 AD5 A12 TDO R56 H_D#27 N24 AE21 H_D#59 trace length shorter than 0.5"
A26# TDO TP8 +1.05V D27# D59#
H_A#27 AE2 C11 TMS H_D#28 M25 AD21 H_D#60
A27# TMS TP9 D28# D60#
H_A#28 AD6 B13 TRST# 56_0603 H_D#29 H26 AF25 H_D#61 trace length shorter than 0.5"
A28# TRST# TP10 D29# D61#
H_A#29 AF3 A7 DBR# H_D#30 N25 AF22 H_D#62
A29# DBR# TP11 D30# D62#
H_A#30 AE1 R315 H_D#31 K25 AF26 H_D#63
H_A#31 A30# H_PROCHOT# D31# D63#
C AF1 A31# PROCHOT# B17 8 H_DSTBN#1 K24 DSTBN1# DSTBN3# AE24 H_DSTBN#3 8
C
THERM

AE5 B18 H_THERMDA L24 AE25

8 H_ADSTB#1 ADSTB#1 THERMDA H_THERMDC 8 H_DSTBP#1 DSTBP1# DSTBP3# H_DSTBP#3 8
A18 75_1 J26 AD20
THERMDC 8 H_DINV#1 DINV1# DINV3# H_DINV#3 8
15 H_A20M# C2 A20M#
D3 C17 PM_THRMTRIP# E1 P25 COMP0 R71 27.4_1 +1.05V
15 H_FERR# FERR# THERMTRIP# PM_THRMTRIP# 9,15 PSI# COMP0 COMP1
A3 P26 R70 54.9_1
15 H_IGNNE# IGNNE# Z0507 CPU_BSEL0 COMP1 COMP2
A15 TP12 C16 AB2 R76 27.4_1
ITP_CLK1 Z0508 7,24 CPU_BSEL0 MCH_BSEL1 BSEL0 COMP2 COMP3
C6 A16 C14 AB1 R77 54.9_1
H CLK

15 H_STPCLK# STPCLK# ITP_CLK0 TP13 BSEL1 COMP3

D1 B14 +1.05V MISC R307
15 H_INTR LINT0 BCLK1 CLK_CPU_BCLK# 7 TP_CPU_NC1
15 H_NMI D4 LINT1 BCLK0 B15 CLK_CPU_BCLK 7 TP14 B2 NC1 DPRSTP# G1 H_DPRSTP# 15
B4 B7 200_1
15 H_SMI# SMI# TP_NC_2 DPSLP# H_DPSLP# 15
R78 C3 C19
TP15 TP_NC_3 RSVD2 DPWR# H_DPWR# 8
TP16 AF7 RSVD3 PWRGOOD E4 H_PWRGD 15
TP_NC_4 AC1 A6
TP17 TP_NC_5 RSVD4 SLP# H_CPUSLP# 8,15
TP18 E26 RSVD5
100_1
TEST1 C5 TEST1 TP80
H_GTLREF AD26 F23 TEST2
GTLREF0 TEST2 TP81
+1.05V R79

Layout note: 0.5" max length.

H_STPCLK# R305 150_1
200_1
TMS R309 39.2_1
CPU_CORE
TDI R57 150_1

TRST# R311 680

R313
TCK R312 27.4_1
B AUX_OFF# 27 B
100K

C
Z0510 B Q75
2N3904 +1.05V +1.05V
C

E
C336
PM_THRMTRIP# R314 1K Z0509 B Q74 R55 R306
CPU Thermal Sensor 2N3904 1u_6.3V
C34
E

0.1u 470 1K_1

Modify M30 in R:B CPU_BSEL0 MCH_BSEL1
CPU_BSEL0 7,24 MCH_BSEL1 9

R299 R43
Z0511 +3.3V
+3.3V
200_1_0603 C331
1K_1_0603
2.2U_X5R_0603
R616
MCH_BSEL0 9
R617
D
1

U33 100K Modify M30 in R:B

100K Q101
VDD

H_THERMDA 2 7 Z0512 G 2N7002

D+ ADATA SMBDAT_EC 7,24
D

H_THERM#
S

4 THERM# SCLK 8 SMBCLK_EC 7,24

C30 Q100
H_THERMDC 3 6 H_THERM# G 2N7002 C709
GND

A 2200p D- ALERT A
S

C708 0.1u BSEL0 BSEL1

ADM1032
0.1u PSB400 1 0
5

UNIWILL COMPUTER CORP.

PSB533(dafault) 0 0
Z0513 R673 0_0603 Title

ICS954206 BSEL Settings: MX0/M40/50EI0

Modify M30 in R:B Size Document Number Rev
Modify M30 in R:B 01=PSB400(BSEL0=1 BSEL1=0) CPU Banias/Dothan-1/2 C
00=PSB533(BSEL1=0 BSEL0=0) 3017
Date: Tuesday, August 09, 2005 Sheet 5 of 35

5 4 3 2 1
 5 4 3 2 1

U37D
A2 VSS0 VSS97 D13
+1.5V A5 D15
VSS1 VSS98
A8 VSS2 VSS99 D17
A11 VSS3 VSS100 D19
A14 VSS4 VSS101 D21
FSB400 MHz=1.8V A17 VSS5 VSS102 D23
R58 CPU_CORE A20 D26
VSS6 VSS103
FSB533 MHz=1.5V A23 VSS7 VSS104 E3
+1.8V_SYSTEM A26 E6
QT1608RL060 VSS8 VSS105
AA1 VSS9 VSS106 E8
CPU_CORE CPU_CORE AA4 E10
R59 C79 C348 C94 C74 C73 C346 VSS10 VSS107
U37C AA6 VSS11 VSS108 E12
Z0601 AA8 E14
D
4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 VSS12 VSS109 D
AA11 VCC0 VCC59 G5 AA10 VSS13 VSS110 E16
AA13 H22 QT1608RL060_OP AA12 E18
VCC1 VCC60 VSS14 VSS111
AA15 VCC2 VCC61 H6 AA14 VSS15 VSS112 E20
AA17 VCC3 VCC62 J21 AA16 VSS16 VSS113 E22
AA19 VCC4 VCC63 J5 Close to Pin AA18 VSS17 VSS114 E25
AA21 VCC5 VCC64 K22 AA20 VSS18 VSS115 F1
AA5 VCC6 VCC65 U5 AA22 VSS19 VSS116 F4
AA7 V22 C84 C80 C90 C93 C83 C91 AA25 F5
VCC7 VCC66 C339 C43 C340 C338 C39 VSS20 VSS117
AA9 VCC8 VCC67 V6 AB3 VSS21 VSS118 F7
AB10 W21 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 AB5 F9
VCC9 VCC68 VSS22 VSS119

4.7U_10V_0805
AB12 W5 0.1u 0.1u 0.1u 0.1u AB7 F11
VCC10 VCC69 VSS23 VSS120
AB14 VCC11 VCC70 Y22 AB9 VSS24 VSS121 F13
AB16 VCC12 VCC71 Y6 AB11 VSS25 VSS122 F15
AB18 VCC13 AB13 VSS26 VSS123 F17
AB20 F26 Z0603 R316 0 AB15 F19
VCC14 VCCA0 Z0604 R52 0 VSS27 VSS124
AB22 VCC15 VCCA1 B1 AB17 VSS28 VSS125 F21
AB6 N1 C98 C99 C107 C109 C101 C53 C105 C110 C100 C106 AB19 F24
VCC16 VCCA2 VSS29 VSS126
AB8 VCC17 VCCA3 AC26 Reserved for FSB400 MHz AB21 VSS30 VSS127 G2
AC11 VCCA=120mA 1u_6.3V 1u_6.3V 1u_6.3V 1u_6.3V 1u_6.3V 1u_6.3V 1u_6.3V 1u_6.3V 1u_6.3V 1u_6.3V AB23 G6
VCC18 VSS31 VSS128
AC13 VCC19 VCCP0 D10 +1.05V AB26 VSS32 VSS129 G22
AC15 VCC20 VCCP1 D12 AC2 VSS33 VSS130 G23
AC17 VCC21 VCCP2 D14 AC5 VSS34 VSS131 G26
AC19 VCC22 VCCP3 D16 AC8 VSS35 VSS132 H3
POWER

AC9 VCC23 VCCP4 E11 AC10 VSS36 VSS133 H5

AD10 E13 C111 C75 C51 C50 AC12 H21
VCC24 VCCP5 VSS37 VSS134
AD12 VCC25 VCCP6 E15 AC14 VSS38 VSS135 H25
AD14 F10 1u_6.3V 1u_6.3V 1u_6.3V 1u_6.3V AC16 J1
VCC26 VCCP7 VSS39 VSS136
AD16 VCC27 VCCP8 F12 AC18 VSS40 VSS137 J4
AD18 VCC28 VCCP9 F14 AC21 VSS41 VSS138 J6
C AD8 VCC29 VCCP10 F16 AC24 VSS42 VSS139 J22 C
AE11 VCC30 VCCP11 K6 AD1 VSS43 VSS140 J24
AE13 VCC31 VCCP12 L21 AD4 VSS44 VSS141 K2
AE15 L5 AD7 K5

VSS
VCC32 VCCP13 VSS45 VSS142
AE17 VCC33 VCCP14 M22 AD9 VSS46 VSS143 K21
AE19 VCC34 VCCP15 M6 AD11 VSS47 VSS144 K23
AE9 N21 C104 C102 C108 C113 C112 C54 C52 C103 C97 C96 AD13 K26
VCC35 VCCP16 VSS48 VSS145
AF10 VCC36 VCCP17 N5 AD15 VSS49 VSS146 L3
AF12 P22 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P AD17 L6
VCC37 VCCP18 VSS50 VSS147
AF14 VCC38 VCCP19 P6 AD19 VSS51 VSS148 L22
AF16 VCC39 VCCP20 R21 AD22 VSS52 VSS149 L25
AF18 VCC40 VCCP21 R5 AD25 VSS53 VSS150 M1
AF8 VCC41 VCCP22 T22 AE3 VSS54 VSS151 M4
D18 VCC42 VCCP23 T6 AE6 VSS55 VSS152 M5
D20 VCC43 VCCP24 U21 AE8 VSS56 VSS153 M21
D22 VCC44 AE10 VSS57 VSS154 M24
D6 VCC45 VCCQ0 P23 AE12 VSS58 VSS155 N3
D8 VCC46 VCCQ1 W4 AE14 VSS59 VSS156 N6
E17 VCC47 AE16 VSS60 VSS157 N22
E19 VCC48 VID0 E2 H_VID0 14 AE18 VSS61 VSS158 N23
E21 VCC49 VID1 F2 H_VID1 14 AE20 VSS62 VSS159 N26
E5 VCC50 VID2 F3 H_VID2 14 AE23 VSS63 VSS160 P2
E7 VCC51 VID3 G3 H_VID3 14 AE26 VSS64 VSS161 P5
E9 VCC52 VID4 G4 H_VID4 14 AF2 VSS65 VSS162 P21
F18 VCC53 VID5 H4 H_VID5 14 AF5 VSS66 VSS163 P24
F20 VCC54 AF9 VSS67 VSS164 R1
F22 VCC55 AF11 VSS68 VSS165 R4
F6 AE7 Z0605 AF13 R6
VCC56 VCCSENSE TP19 VSS69 VSS166
F8 VCC57 AF15 VSS70 VSS167 R22
G21 AF6 Z0606 AF17 R25
B VCC58 VSSSENSE TP20 +1.05V VSS71 VSS168 B
AF19 VSS72 VSS169 T3
AF21 VSS73 VSS170 T5
AF24 VSS74 VSS171 T21
Layout note : B3 VSS75 VSS172 T23
C55 C45 C37 C78 C89 C77 C95 C59 C92 C76 C86 C82 C87 C85 C81 C63 C64 B6 T26
VSS76 VSS173
VCCSENSE and VSSSENSE line B9 VSS77 VSS174 U2

4.7U_10V_0805

4.7U_10V_0805

4.7U_10V_0805

4.7U_10V_0805
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u B12 U6
VSS78 VSS175
should be of equal length B16 VSS79 VSS176 U22
B19 VSS80 VSS177 U24
B22 VSS81 VSS178 V1
B25 VSS82 VSS179 V4
C1 VSS83 VSS180 V5
C4 VSS84 VSS181 V21
C7 VSS85 VSS182 V25
C10 VSS86 VSS183 W3
C13 VSS87 VSS184 W6
C15 VSS88 VSS185 W22
C18 VSS89 VSS186 W23
C21 VSS90 VSS187 W26
C24 VSS91 VSS188 Y2
D2 VSS92 VSS189 Y5
D5 VSS93 VSS190 Y21
D7 VSS94 VSS191 Y24
D9 VSS95
D11 VSS96

A A

UNIWILL COMPUTER CORP.

Title

MX0/M40/50EI0
Size Document Number Rev
CPU Banias/Dothan-2/2 C
3017
Date: Tuesday, August 09, 2005 Sheet 6 of 35
5 4 3 2 1
 5 4 3 2 1

+3.3VS_CLKVDD +3.3V
B34

D D
C263 C256 C247 C268 C273 QT1608RL600
CLK_PCIE_NEW_CARD R460 49.9_1
0.1u 0.1u 0.1u 0.1u 2.2U_10V_0603
Modify 2 in RB. CLK_PCIE_NEW_CARD# R465 49.9_1
R452 Modify M30 in RB
B33 DOT96_SSC R456 49.9_1
Z0701
2.2_0603 DOT96_SST R454 49.9_1
Modify 2 in RB. C236 C218 QT1608RL600
R196 CLK_CPU_BCLK R438 49.9_1
Y4 VDD_A_CR C242 0.1u 1u_6.3V
R435 CLK_CPU_BCLK# R443 49.9_1
0.1u

1
U22 2.2_0603 1_0603 CLK_MCH_BCLK R447 49.9_1
14.318MHz_SMT

VDD_PCI1

VDD_PCI0
19 11 Z0705 Modify 2 in RB. CLK_MCH_BCLK# R450 49.9_1
C258 VDDSRC VDD_48
28 VDD_PCIEX
34 48 VDD_REF_CR C243 0.1u DREFCLK# R440 49.9_1
1u_6.3V VDD_PCIEX1 VDD_REF
55 Z0706 R171 0_OP DREFCLK R434 49.9_1
RTFS_2 PM_STPPCI# 16
54 Z0707 R175 0_OP
RTFS_1 PM_STPCPU# 16,25
C239 C235 42 CLK_PCIE_ICH# R478 49.9_1
VDD_CPU CPU1 R207 33
CPUCLKT1 41 CLK_MCH_BCLK 8
33p 33p 37 40 CPU#1 R211 33 CLK_PCIE_ICH R477 49.9_1
VDDA CPUCLKC1 CLK_MCH_BCLK# 8
+3.3V
38 44 CPU0 R200 33 CLK_SATA# R449 49.9_1
GNDA CPUCLKT0 CLK_CPU_BCLK 5
43 CPU#0 R202 33
CPUCLKC0 CLK_CPU_BCLK# 5
CLK_SATA R445 49.9_1
R201 XTAL_IN 50 XTAL_IN GCLK R632 49.9_1
C
PCIEXT6 36 C
10K XTAL_OUT 49 35
R203 33 XTAL_OUT PCIEXC6 GCLK# R633 49.9_1
16 CLK_USB48
FSA 12 33
FSA/USB_48 PCIEXT5
PCIEXC5 32
16 GND
R614 4.7K 31 PCIE4 R470 33
24 CLK_BSEL0 PCIEXT4 GCLK 9
R429 4.7K_OP Z0702 FSC 8 30 PCIE#4 R469 33 Place termination close to source IC
5,24 CPU_BSEL0 FSC/PCICLK_F0 PCIEXC4 GCLK# 9
R180 56_OP
18 PCICLK_PCM
R183 56 PCI3 5 26 PCIE3 R461 33
21 PCICLK_LAN PCI3 PCIEXT3 CLK_PCIE_NEW_CARD 18
R172 56 27 PCIE#3 R464 33
23 PCICLK_MINIPCI PCIEXC3 CLK_PCIE_NEW_CARD# 18
R177 56 PCI2 4
22 PCICLK_1394 PCI2
24 PCIE2 R471 33
PCIEXT2 CLK_PCIE_ICH 16
R164 56 PCI1 3 25 PCIE#2 R472 33
16 CLK_PCI PCI1 PCIEXC2 CLK_PCIE_ICH# 16
R159 56 PCI0 56 22
24 CLK_PCI_LPC PCICLK0~ PCIEXT1
PCIEXC1 23
R192 10K FSB PCIF1 9 FSB/PCICLK_F1 PCIE0 R453 33
PCIEXT0 20 DOT96_SST 9
PCIE#0 R457 33
53 RTFS_0 PCIEXC0 21 DOT96_SSC 9 Reserved FOR EMI
R166 0_OP Z0703 46 17 SRC0 R444 33
13,16,17 SB_SMB_CLK SCLK SRC0 CLK_SATA 15 PCICLK_PCM
18 SRC#0 R448 33 C803 10p_OP
SRC0# CLK_SATA# 15
R167 0_OP Z0704 47
13,16,17 SB_SMB_DATA SDATA Modify 3 in RB.
IREF 39 14 DOT96 R433 33
IREF DOT96 DREFCLK 9
R151 0 15 DOT96# R439 33 CODEC_14MHZ R829 0
5,24 SMBCLK_EC DOT96# DREFCLK# 9
13 VSS_48
R152 0 R210 29
5,24 SMBDAT_EC VSS_PCIE
45 CLK_USB48 C248 10p_OP
B VSS_CPU VTT_PWRGD#
B
2 VSS_PCI VTT_PWRGD#/PD 10
475_1 6 RESET# REF R179 22 PCICLK_LAN C227 10p_OP
51 VSS_REF REFOUT 52 CLK_ICH14 16

ICS 954127 R176 33_OP PCICLK_MINIPCI C220 10p_OP

CODEC_14MHZ 23

Modify 3 in RB. PCICLK_1394 C223 10p_OP

CLK_PCI_LPC C216 10p_OP

+3.3V

CLK_PCI C217 10p_OP

R165
10K CLK_ICH14 C226 10p_OP

25 VTT_PWRGD#

A A
Host
FSA FSB FSC Clock
BSEL2 BSEL1 BSEL0 frequency
UNIWILL COMPUTER CORP.
1 0 1 100 Title

1 0 0 133 MX0/M40/50EI0
Size Document Number Rev
CLOCK GEN ICS954206 C
3017
Date: Tuesday, August 09, 2005 Sheet 7 of 35
5 4 3 2 1
 5 4 3 2 1

U34A
H_XRCOMP 5 H_D#[63:0] H_D#0 H_A#3 H_A#[31:3] 5
E4 HD0# HA3# G9
H_D#1 E1 C9 H_A#4
D
R297 H_D#2 HD1# HA4# H_A#5 D
F4 HD2# HA5# E9
H_D#3 H7 B7 H_A#6
24.9_1 H_D#4 HD3# HA6# H_A#7
E2 HD4# HA7# A10
H_D#5 F1 F9 H_A#8
H_D#6 HD5# HA8# H_A#9
E3 HD6# HA9# D8
H_D#7 D3 B10 H_A#10
H_D#8 HD7# HA10# H_A#11
K7 HD8# HA11# E10
H_D#9 F2 G10 H_A#12
H_D#10 HD9# HA12# H_A#13
J7 HD10# HA13# D9
+1.05V H_D#11 J8 E11 H_A#14
H_D#12 HD11# HA14# H_A#15
H6 HD12# HA15# F10
H_D#13 F3 G11 H_A#16
H_D#14 HD13# HA16# H_A#17
K8 HD14# HA17# G13
R295 H_D#15 H5 C10 H_A#18
H_D#16 HD15# HA18# H_A#19
H1 HD16# HA19# C11
54.9_1 H_D#17 H2 D11 H_A#20
H_D#18 HD17# HA20# H_A#21
K5 HD18# HA21# C12
H_D#19 K6 B13 H_A#22
H_XSCOMP H_D#20 HD19# HA22# H_A#23
J4 HD20# HA23# A12
H_D#21 G3 F12 H_A#24
H_D#22 HD21# HA24# H_A#25
H3 HD22# HA25# G12
H_D#23 J1 E12 H_A#26
+1.05V H_D#24 HD23# HA26# H_A#27
L5 HD24# HA27# C13
H_D#25 K4 B11 H_A#28 +1.05V
H_D#26 HD25# HA28# H_A#29
J5 HD26# HA29# D13
H_D#27 P7 A13 H_A#30
R300 H_D#28 HD27# HA30# H_A#31
L7 HD28# HA31# F13
H_D#29 J3 R42
221_1 H_D#30 HD29#
P5 HD30# HADS# F8 H_ADS# 5
C H_XSWING H_D#31 L3 B9 100_1 C
H_D#32 HD31# HADSTB#0 H_ADSTB#0 5
U7 HD32# HADSTB#1 E13 H_ADSTB#1 5
H_D#33 V6 J11 H_VREF
H_D#34 HD33# HVREF
R6 HD34# HBNR# A5 H_BNR# 5
R298 C328 H_D#35 R5 D5
H_D#36 HD35# HBPRI# H_BPRI# 5
P3 E7 C27 R41
H_D#37 HD36# HBREQ0# H_BREQ#0 5
100_1 0.1u T8 H10
H_D#38 HD37# HCPURST# H_CPURST# 5
R7 0.1u 200_1
H_D#39 HD38#
R8 HD39#
H_D#40 U8 HD40#

HOST
H_D#41 R4 AB1
H_D#42 HD41# HCLKINN CLK_MCH_BCLK# 7
T4 HD42# HCLKINP AB2 CLK_MCH_BCLK 7
H_D#43 T5
H_D#44 HD43# H_DBSY# 5
R1 HD44# HDBSY# C6 H_DEFER# 5
H_D#45 T3 E6
H_D#46 HD45# HDEFER# H_DINV#0 H_DINV#[3:0] 5
+1.05V V8 H8
H_D#47 HD46# HDINV#0 H_DINV#1
U6 HD47# HDINV#1 K3
H_D#48 W6 T7 H_DINV#2
H_D#49 HD48# HDINV#2 H_DINV#3
U3 HD49# HDINV#3 U5 H_DPWR# 5
R304 H_D#50 V5 G6
H_D#51 HD50# HDPWR# H_DRDY# 5
W8 HD51# HDRDY# F7 H_DSTBN#[3:0] 5
54.9_1 H_D#52 W7 G4 H_DSTBN#0
H_D#53 HD52# HDSTBN#0 H_DSTBN#1
U2 HD53# HDSTBN#1 K1
H_D#54 U1 R3 H_DSTBN#2
H_YSCOMP H_D#55 HD54# HDSTBN#2 H_DSTBN#3
Y5 HD55# HDSTBN#3 V3 H_DSTBP#[3:0] 5
H_D#56 Y2 G5 H_DSTBP#0
H_D#57 HD56# HDSTBP#0 H_DSTBP#1
V4 HD57# HDSTBP#1 K2
H_D#58 Y7 R2 H_DSTBP#2
H_D#59 HD58# HDSTBP#2 H_DSTBP#3
W1 HD59# HDSTBP#3 W4
H_D#60 W3 F6 Z0801
B HD60# HEDRDY# TP21 B
+1.05V H_D#61 Y3 D4
H_D#62 HD61# HHIT# H_HIT# 5
Y6 HD62# HHITM# D6 H_HITM# 5
H_D#63 W2 B3
HD63# HLOCK# Z0802 H_LOCK# 5
HPCREQ# A11 TP22 H_REQ#[4:0] 5
R49 H_XRCOMP C1 A7 H_REQ#0
H_XSCOMP HXRCOMP HREQ#0 H_REQ#1
C2 HXSCOMP HREQ#1 D7
221_1 H_XSWING D1 B8 H_REQ#2
H_YSWING H_YRCOMP HXSWING HREQ#2 H_REQ#3
T1 HYRCOMP HREQ#3 C7
H_YSCOMP L1 A8 H_REQ#4
H_YSWING HYSCOMP HREQ#4 H_RS#0 H_RS#[2:0] 5
P1 HYSWING HRS0# A4
C5 H_RS#1
C40 HRS1# H_RS#2
HRS2# B4
R48 G8 H_CPUSLP#_GMCH R32 0_OP
HCPUSLP# H_CPUSLP# 5,15
0.1u B5
HTRDY# H_TRDY# 5
100_1

ALVISO_90

H_YRCOMP

R53

24.9_1

A A

UNIWILL COMPUTER CORP.

Title

MX0/M40/50EI0
Size Document Number Rev
NB_Alviso Host-1/5 C
3017
Date: Tuesday, August 09, 2005 Sheet 8 of 35
5 4 3 2 1
 5 4 3 2 1

U34G R21 24.9_1

U34B

MISC
Modify M30 in RB. H24 D36 PEG_COMP
SDVOCTRL_DATA EXP_COMPI +1.5V
16 DMI_TXN[3:0] H25 SDVOCTRL_CLK EXP_ICOMPO D34
DMI_TXN0 AA31 G16 CFG0 AB29
DMI_TXN1 AB35 DMIRXN0 CFG0 7 GCLK# GCLKN
H13 AC29 E30 PEG_RXN15
DMI_TXN2 AC31 DMIRXN1 CFG1 MCH_BSEL1 5 7 GCLK GCLKP EXP_RXN0
G14 F34 PEG_RXN14
DMI_TXN3 AD35 DMIRXN2 CFG2 Z0901 MCH_BSEL0 5 EXP_RXN1
F16 TP23 G30 PEG_RXN13
DMIRXN3 CFG3 Z0902 R22 75_1 Z0937 EXP_RXN2 PEG_RXN12
F15 A15 H34

CFG/RSVD
16 DMI_TXP[3:0] CFG4 TP24 TVDAC_A EXP_RXN3
DMI_TXP0 Y31 G15 C16 J30 PEG_RXN11
DMI_TXP1 AA35 DMIRXP0 CFG5 CFG5 12 19 TV_DAC_B TVDAC_B EXP_RXN4 PEG_RXN10
DMIRXP1 CFG6 E16 CFG6 12 19 TV_DAC_C A17 TVDAC_C EXP_RXN5 K34
DMI_TXP2 AB31 D17 R38 TVIREF J18 L30 PEG_RXN9

TV
D
DMI_TXP3 AC35 DMIRXP2 CFG7 Z0903 CFG7 12 TV_REFSET EXP_RXN6 D
J16 TP25 B15 M34 PEG_RXN8
DMIRXP3 CFG8 4.99K_1 TV_IRTNA EXP_RXN7 PEG_RXN7
16 DMI_RXN[3:0] CFG9 D15 CFG9 12 B16 TV_IRTNB EXP_RXN8 N30
DMI_RXN0 AA33 E15 Z0904 B17 P34 PEG_RXN6
TP26

DMI
DMI_RXN1 AB37 DMITXN0 CFG10 Z0905 TV_IRTNC EXP_RXN9 PEG_RXN5
DMITXN1 CFG11 D14 TP27 EXP_RXN10 R30
DMI_RXN2 AC33 E14 Z0906 T34 PEG_RXN4
DMITXN2 CFG12 TP28 EXP_RXN11
DMI_RXN3 AD37 H12 Z0907 U30 PEG_RXN3
DMITXN3 CFG13 TP29 EXP_RXN12
C14 Z0908 V34 PEG_RXN2
16 DMI_RXP[3:0] CFG14 TP30 EXP_RXN13
DMI_RXP0 Y33 H15 Z0910 W30 PEG_RXN1
DMITXP0 CFG15 TP31 EXP_RXN14
DMI_RXP1 AA37 J15 E24 Y34 PEG_RXN0
DMI_RXP2 AB33 DMITXP1 CFG16 Z0911 CFG16 12 23 CRT_CLK DDCCLK EXP_RXN15
DMITXP2 CFG17 H14 TP32 23 CRT_DATA E23 DDCDATA
DMI_RXP3 AC37 G22 E21 D30 PEG_RXP15
DMITXP3 CFG18 CFG18 12 23 MB_CRT_B BLUE EXP_RXP0 PEG_RXP14
CFG19 G23 CFG19 12 D21 BLUE# EXP_RXP1 E34
D23 Z0912 C20 F30 PEG_RXP13
CFG20 TP33 23 MB_CRT_G GREEN EXP_RXP2
MA_CK0 AM33 G25 Z0913 B20 G34 PEG_RXP12
13 MA_CK0 TP34

VGA
SM_CK0 RSVD21 GREEN# EXP_RXP3

PCI-EXPRESS GRAPHICS
MA_CK1 AL1 G24 Z0914 A19 H30 PEG_RXP11
13 MA_CK1 SM_CK1 RSVD22 TP35 23 MB_CRT_R RED EXP_RXP4
J17 Z0915 B19 J34 PEG_RXP10
RSVD23 TP36 RED# EXP_RXP5
MB_CK3 AJ34 A31 Z0916 R12 39 NB_VSYNC H21 K30 PEG_RXP9
13 MB_CK3 SM_CK3 RSVD24 TP37 23 CRT_VSYNC VSYNC EXP_RXP6
MB_CK4 AF6 A30 Z0917 R11 39 NB_HSYNC G21 L34 PEG_RXP8
13 MB_CK4 SM_CK4 RSVD25 TP38 23 CRT_HSYNC HSYNC EXP_RXP7
D26 Z0918 CRTIREF J20 M30 PEG_RXP7
RSVD26 TP39 REFSET EXP_RXP8
D25 Z0919 R40 249_1 N34 PEG_RXP6
RSVD27 TP40 EXP_RXP9
MA_CK#0 AN33 AE11 Z0920 P30 PEG_RXP5
13 MA_CK#0 SM_CK0# RSVD28 TP41 EXP_RXP10
MA_CK#1 AK1 AE10 Z0921 R34 PEG_RXP4
13 MA_CK#1 SM_CK1# RSVD29 TP42 EXP_RXP11

MUXING
AC10 Z0922 T30 PEG_RXP3
RSVD30 TP43 EXP_RXP12
MB_CK#3 AJ33 AD10 Z0923 U34 PEG_RXP2
13 MB_CK#3 SM_CK3# RSVD31 TP44 EXP_RXP13
MB_CK#4 AF5 Z0938 E25 V30 PEG_RXP1
13 MB_CK#4 SM_CK4# TP45 LBKLT_CRTL EXP_RXP14
F25 W34 PEG_RXP0
19 EN_BL Z0939 LBKLT_EN EXP_RXP15
TP46 C23 LCTLA_CLK
AP21 Z0940 C22 E32 PEG_TXN15
13,14 MA_CKE0 SM_CKE0 TP47 LCTLB_DATA EXP_TXN0 PEG_TXN14
13,14 MA_CKE1 AM21 SM_CKE1 19 LDDC_CLK F23 LDDC_CLK EXP_TXN1 F36
C AH21 J23 F22 G32 PEG_TXN13 C
13,14 MB_CKE2 SM_CKE2 BM_BUSY# BM_BUSY# 16 19 LDDC_DATA LDDC_DATA EXP_TXN2 PEG_TXN12
AK21 J21 PM_EXTTS#0 A C F26 H36

PM
13,14 MB_CKE3 SM_CKE3 EXT_TS0# EXTTS#0 24 19 EN_LCD L_IBG LVDD_EN EXP_TXN3 PEG_TXN11
H22 PM_EXTTS#1 D7 BAT54 C33 J32
EXT_TS1# LIBG EXP_TXN4

LVDS
AN16 F5 Z0924 C A R17 1.5K_1 Reserved C31 K36 PEG_TXN10
DDR
13,14 MA_CS#0 SM_CS0# THRMTRIP# PM_THRMTRIP# 5,15 Reserved LVBG EXP_TXN5 PEG_TXN9
AM14 AD30 D28 BAT54_OP F28 L32
13,14 MA_CS#1 SM_CS1# PWROK DELAY_VR_PWRGOOD 16 LVREFH EXP_TXN6
13,14 MB_CS#2 AH15 SM_CS2# RSTIN# AE29 Z0925 PLT_RST# 16,17,20,24
Reserved F27 LVREFL EXP_TXN7 M36 PEG_TXN8
AG16 R63 100 N32 PEG_TXN7
13,14 MB_CS#3 SM_CS3# EXP_TXN8 PEG_TXN6
DREF_CLKN A24 DREFCLK# 7 19 LA_CLK- B30 LACLKN EXP_TXN9 P36
As short as possible A23 B29 R32 PEG_TXN5
M_OCDCOMP0 DREF_CLKP DREFCLK 7 19 LA_CLK+ LACLKP EXP_TXN10 PEG_TXN4
AF22 SM_OCDCOMP0 DREF_SSCLKN C37 DOT96_SSC 7 19 LB_CLK- C25 LBCLKN EXP_TXN11 T36
CLK

M_OCDCOMP1 AF16 D37 C24 U32 PEG_TXN3

SM_OCDCOMP1 DREF_SSCLKP DOT96_SST 7 19 LB_CLK+ LBCLKP EXP_TXN12 PEG_TXN2
EXP_TXN13 V36
W32 PEG_TXN1
R64 R65 EXP_TXN14 PEG_TXN0
13,14 MA_ODT0 AP14 SM_ODT0 19 LA_DATA0- B34 LADATAN0 EXP_TXN15 Y36
13,14 MA_ODT1 AL15 SM_ODT1 NC1 AP37 Z0926 TP50 19 LA_DATA1- B33 LADATAN1
13,14 MB_ODT2 AM11 SM_ODT2 NC2 AN37Z0927 TP51 19 LA_DATA2- B32 LADATAN2
40.2_1 40.2_1
13,14 MB_ODT3 AN10 SM_ODT3 NC3 AP36 Z0928 TP52 R27 R26 R20
EXP_TXP0 D32 PEG_TXP15
NC4 AP2 Z0929 TP53 EXP_TXP1 E36 PEG_TXP14
M_RCOMPN AK10 AP1 Z0930 A34 F32 PEG_TXP13
SMRCOMPN NC5 TP54 19 LA_DATA0+ LADATAP0 EXP_TXP2
M_RCOMPP AK11 AN1 Z0931 0_OP 0_OP 1K_OP A33 G36 PEG_TXP12
SMRCOMPP NC6 TP55 19 LA_DATA1+ LADATAP1 EXP_TXP3
NC

AF37 SMVREF0 NC7 B1 Z0932 TP56 19 LA_DATA2+ B31 LADATAP2 EXP_TXP4 H32 PEG_TXP11
AD1 SMVREF1 NC8 A2 Z0933 TP57 EXP_TXP5 J36 PEG_TXP10
+1.8V_MB SMXSLEW AE27 B37 Z0934 K32 PEG_TXP9
SMXSLEWIN NC9 TP58 EXP_TXP6
AE28 SMXSLEWOUT NC10 A36 Z0935 TP59 +1.5V
19 LB_DATA0- C29 LBDATAN0 EXP_TXP7 L36 PEG_TXP8
SMYSLEW AF9 A37 Z0936 D28 M32 PEG_TXP7
SMYSLEWIN NC11 TP60 19 LB_DATA1- LBDATAN1 EXP_TXP8
AF10 Reserved for spread clock C27 N36 PEG_TXP6
SMYSLEWOUT 19 LB_DATA2- LBDATAN2 EXP_TXP9 PEG_TXP5
R328 P32
EXP_TXP10 PEG_TXP4
EXP_TXP11 R36
150_1 ALVISO_90 C28 T32 PEG_TXP3
19 LB_DATA0+ LBDATAP0 EXP_TXP12 PEG_TXP2
B 19 LB_DATA1+ D27 LBDATAP1 EXP_TXP13 U36 B
0.05A M_VREF_MCH C26 V32 PEG_TXP1
19 LB_DATA2+ LBDATAP2 EXP_TXP14
W36 PEG_TXP0
C351 C355 EXP_TXP15
R327
0.1u 0.1u ALVISO_90
150_1

MA_CK0
+1.8V_MB MA_CK#0

R334 80.6_1 MA_CK1

M_RCOMPN MA_CK#1

MB_CK3
MB_CK#3
+1.05V MB_CK4
MB_CK#4
R35 10K
CFG0
C937 C936 C935 C934 C933 C932 C931 C930
A A
Host 10P 10P 10P 10P 10P 10P 10P 10P

M_RCOMPP CFG0 CFG1 CFG2 Clock

+2.5V_SYSTEM frequency
R33 10K R335 UNIWILL COMPUTER CORP.
PM_EXTTS#0 1 0 1 100
80.6_1 Add in R:C for EMI Title
R34 10K
PM_EXTTS#1 1 0 0 133 MX0/M40/50EI0
Size Document Number Rev
NB DDRCLK_VGA_PCIEXPR-2/5 C
3017
Date: Tuesday, August 09, 2005 Sheet 9 of 35
5 4 3 2 1
 5 4 3 2 1

D D
13 MA_DQ[63:0] U34C 13 MB_DQ[63:0] U34D
MA_DQ0 MA_BA0 MA_BA[2:0] 13,14 MB_DQ0 MB_BA0 MB_BA[2:0] 13,14
AG35 SADQ0 SA_BS0# AK15 AE31 SBDQ0 SB_BS0# AJ15
MA_DQ1 AH35 AK16 MA_BA1 MB_DQ1 AE32 AG17 MB_BA1
MA_DQ2 SADQ1 SA_BS1# MA_BA2 MB_DQ2 SBDQ1 SB_BS1# MB_BA2
AL35 SADQ2 SA_BS2# AL21 AG32 SBDQ2 SB_BS2# AG21
MA_DQ3 AL37 MB_DQ3 AG36
SADQ3 MA_DM0 MA_DM[7:0] 13 MB_DQ4 SBDQ3
MA_DQ4 AH36 AJ37 AE34
MA_DQ5 SADQ4 SA_DM0 MA_DM1 MB_DQ5 SBDQ4 MB_DM0 MB_DM[7:0] 13
AJ35 SADQ5 SA_DM1 AP35 AE33 SBDQ5 SB_DM0 AF32
MA_DQ6 AK37 AL29 MA_DM2 MB_DQ6 AF31 AK34 MB_DM1
MA_DQ7 SADQ6 SA_DM2 MA_DM3 MB_DQ7 SBDQ6 SB_DM1 MB_DM2
AL34 SADQ7 SA_DM3 AP24 AF30 SBDQ7 SB_DM2 AK27
MA_DQ8 AM36 AP9 MA_DM4 MB_DQ8 AH33 AK24 MB_DM3
MA_DQ9 SADQ8 SA_DM4 MA_DM5 MB_DQ9 SBDQ8 SB_DM3 MB_DM4
AN35 SADQ9 SA_DM5 AP4 AH32 SBDQ9 SB_DM4 AJ10
MA_DQ10 AP32 AJ2 MA_DM6 MB_DQ10 AK31 AK5 MB_DM5
MA_DQ11 SADQ10 SA_DM6 MA_DM7 MB_DQ11 SBDQ10 SB_DM5 MB_DM6
AM31 SADQ11 SA_DM7 AD3 AG30 SBDQ11 SB_DM6 AE7
MA_DQ12 AM34 MB_DQ12 AG34 AB7 MB_DM7
MA_DQ13 SADQ12 MA_DQS0 MA_DQS[7:0] 13 MB_DQ13 SBDQ12 SB_DM7
AM35 SADQ13 SA_DQS0 AK36 AG33 SBDQ13 MB_DQS[7:0] 13
MA_DQ14 AL32 AP33 MA_DQS1 MB_DQ14 AH31 AF34 MB_DQS0
MA_DQ15 SADQ14 SA_DQS1 MA_DQS2 MB_DQ15 SBDQ14 SB_DQS0 MB_DQS1
AM32 SADQ15 SA_DQS2 AN29 AJ31 SBDQ15 SB_DQS1 AK32
MA_DQ16 AN31 AP23 MA_DQS3 MB_DQ16 AK30 AJ28 MB_DQS2
MA_DQ17 SADQ16 SA_DQS3 MA_DQS4 MB_DQ17 SBDQ16 SB_DQS2 MB_DQS3
AP31 SADQ17 SA_DQS4 AM8 AJ30 SBDQ17 SB_DQS3 AK23
MA_DQ18 AN28 AM4 MA_DQS5 MB_DQ18 AH29 AM10 MB_DQS4
MA_DQ19 SADQ18 SA_DQS5 MA_DQS6 MB_DQ19 SBDQ18 SB_DQS4 MB_DQS5
AP28 SADQ19 SA_DQS6 AJ1 AH28 SBDQ19 SB_DQS5 AH6
MA_DQ20 AL30 AE5 MA_DQS7 MB_DQ20 AK29 AF8 MB_DQS6
MA_DQ21 SADQ20 SA_DQS7 MB_DQ21 SBDQ20 SB_DQS6 MB_DQS7
AM30 SADQ21 MA_DQS#[7:0] 13 AH30 SBDQ21 SB_DQS7 AB4
MA_DQ22 AM28 AK35 MA_DQS#0 MB_DQ22 AH27
MA_DQ23 SADQ22 SA_DQS0# MA_DQS#1 MB_DQ23 SBDQ22 MB_DQS#0 MB_DQS#[7:0] 13
AL28 AP34 AG28 AF35

DDR SYSTEM MEMORY A

MA_DQ24 SADQ23 SA_DQS1# MA_DQS#2 MB_DQ24 SBDQ23 SB_DQS0# MB_DQS#1
AP27 AN30 AF24 AK33

DDR SYSTEM MEMORY B

MA_DQ25 SADQ24 SA_DQS2# MA_DQS#3 MB_DQ25 SBDQ24 SB_DQS1# MB_DQS#2
AM27 SADQ25 SA_DQS3# AN23 AG23 SBDQ25 SB_DQS2# AK28
MA_DQ26 AM23 AN8 MA_DQS#4 MB_DQ26 AJ22 AJ23 MB_DQS#3
MA_DQ27 SADQ26 SA_DQS4# MA_DQS#5 MB_DQ27 SBDQ26 SB_DQS3# MB_DQS#4
C AM22 SADQ27 SA_DQS5# AM5 AK22 SBDQ27 SB_DQS4# AL10 C
MA_DQ28 AL23 AH1 MA_DQS#6 MB_DQ28 AH24 AH7 MB_DQS#5
MA_DQ29 SADQ28 SA_DQS6# MA_DQS#7 MB_DQ29 SBDQ28 SB_DQS5# MB_DQS#6
AM24 SADQ29 SA_DQS7# AE4 AH23 SBDQ29 SB_DQS6# AF7
MA_DQ30 AN22 MB_DQ30 AG22 AB5 MB_DQS#7
MA_DQ31 SADQ30 MAA_A0 MAA_A[13:0] 13,14 MB_DQ31 SBDQ30 SB_DQS7#
AP22 SADQ31 SA_MA0 AL17 AJ21 SBDQ31 MBA_A[13:0] 13,14
MA_DQ32 AM9 AP17 MAA_A1 MB_DQ32 AG10 AH17 MBA_A0
MA_DQ33 SADQ32 SA_MA1 MAA_A2 MB_DQ33 SBDQ32 SB_MA0 MBA_A1
AL9 SADQ33 SA_MA2 AP18 AG9 SBDQ33 SB_MA1 AK17
MA_DQ34 AL6 AM17 MAA_A3 MB_DQ34 AG8 AH18 MBA_A2
MA_DQ35 SADQ34 SA_MA3 MAA_A4 MB_DQ35 SBDQ34 SB_MA2 MBA_A3
AP7 SADQ35 SA_MA4 AN18 AH8 SBDQ35 SB_MA3 AJ18
MA_DQ36 AP11 AM18 MAA_A5 MB_DQ36 AH11 AK18 MBA_A4
MA_DQ37 SADQ36 SA_MA5 MAA_A6 MB_DQ37 SBDQ36 SB_MA4 MBA_A5
AP10 SADQ37 SA_MA6 AL19 AH10 SBDQ37 SB_MA5 AJ19
MA_DQ38 AL7 AP20 MAA_A7 MB_DQ38 AJ9 AK19 MBA_A6
MA_DQ39 SADQ38 SA_MA7 MAA_A8 MB_DQ39 SBDQ38 SB_MA6 MBA_A7
AM7 SADQ39 SA_MA8 AM19 AK9 SBDQ39 SB_MA7 AH19
MA_DQ40 AN5 AL20 MAA_A9 MB_DQ40 AJ7 AJ20 MBA_A8
MA_DQ41 SADQ40 SA_MA9 MAA_A10 MB_DQ41 SBDQ40 SB_MA8 MBA_A9
AN6 SADQ41 SA_MA10 AM16 AK6 SBDQ41 SB_MA9 AH20
MA_DQ42 AN3 AN20 MAA_A11 MB_DQ42 AJ4 AJ16 MBA_A10
MA_DQ43 SADQ42 SA_MA11 MAA_A12 MB_DQ43 SBDQ42 SB_MA10 MBA_A11
AP3 SADQ43 SA_MA12 AM20 AH5 SBDQ43 SB_MA11 AG18
MA_DQ44 AP6 AM15 MAA_A13 MB_DQ44 AK8 AG20 MBA_A12
MA_DQ45 SADQ44 SA_MA13 MB_DQ45 SBDQ44 SB_MA12 MBA_A13
AM6 SADQ45 AJ8 SBDQ45 SB_MA13 AG15
MA_DQ46 AL4 AN15 MB_DQ46 AJ5
MA_DQ47 SADQ46 SA_CAS# MA_CAS# 13,14 MB_DQ47 SBDQ46
AM3 SADQ47 SA_RAS# AP16 MA_RAS# 13,14 AK4 SBDQ47 SB_CAS# AH14 MB_CAS# 13,14
MA_DQ48 AK2 AF29 MB_DQ48 AG5 AK14
MA_DQ49 SADQ48 SA_RCVENIN# MB_DQ49 SBDQ48 SB_RAS# MB_RAS# 13,14
AK3 SADQ49 SA_RCVENOUT# AF28 AG4 SBDQ49 SB_RCVENIN# AF15
MA_DQ50 AG2 AP15 MB_DQ50 AD8 AF14
MA_DQ51 SADQ50 SA_WE# MA_WE# 13,14 MB_DQ51 SBDQ50 SB_RCVENOUT#
AG1 SADQ51 AD9 SBDQ51 SB_WE# AH16 MB_WE# 13,14
MA_DQ52 AL3 MB_DQ52 AH4
MA_DQ53 SADQ52 MB_DQ53 SBDQ52
AM2 SADQ53 AG6 SBDQ53
MA_DQ54 AH3 MB_DQ54 AE8
MA_DQ55 SADQ54 MB_DQ55 SBDQ54
AG3 SADQ55 AD7 SBDQ55
MA_DQ56 AF3 MB_DQ56 AC5
B
MA_DQ57 SADQ56 MB_DQ57 SBDQ56 B
AE3 SADQ57 AB8 SBDQ57
MA_DQ58 AD6 MB_DQ58 AB6
MA_DQ59 SADQ58 MB_DQ59 SBDQ58
AC4 SADQ59 AA8 SBDQ59
MA_DQ60 AF2 MB_DQ60 AC8
MA_DQ61 SADQ60 MB_DQ61 SBDQ60
AF1 SADQ61 AC7 SBDQ61
MA_DQ62 AD4 MB_DQ62 AA4
MA_DQ63 SADQ62 MB_DQ63 SBDQ62
AD5 SADQ63 AA5 SBDQ63

ALVISO_90 ALVISO_90

A A

UNIWILL COMPUTER CORP.

Title

MX0/M40/50EI0
Size Document Number Rev
NB DDR_MEM SYSTEM-3/5 C
3017
Date: Tuesday, August 09, 2005 Sheet 10 of 35
5 4 3 2 1
 5 4 3 2 1

1.05V--->3700mA
1.5V--->6750mA +VGA_NB
U34E B19
T29 F17 TVDACA_FB
VCC0 VCCA_TVDACA0 +3.3V
R29 E17 C310 C311 QT1608RL060
C44 C35 C25 C57 C46 C58 VCC1 VCCA_TVDACA1
N29 VCC2 VCCA_TVDACB0 D18
C605 C606 C607 C608 M29 C18 22nF 0.1u 120mA
VCC3 VCCA_TVDACB1

4.7U_10V_X5R_0805

4.7U_10V_X5R_0805

4.7U_10V_X5R_0805
0.1u 0.1u 0.1u K29 F18
0.1u 0.1u 0.1u 0.1u VCC4 VCCA_TVDACC0 60mA
J29 VCC5 VCCA_TVDACC1 E18
V28 D30 +1.5V
VCC6 B21 R332 1K
U28 VCC7 VCCA_TVBG H18
T28 G18 Z1130 TVDACB_FB Z1115 C A
VCC8 VSSA_TVBG C313 C317
R28 VCC9
P28 VCC10 VCCD_TVDAC D19 Z1126 QT1608RL060 C8 C320
D Total 320mA N28 H17 22nF 0.1u BAT54 D
VCC11 VCCDQ_TVDAC 0.1u 4.7U_10V_0805
Modify 4 in RB. M28 VCC12
+1.5V L28 B26 B20
VCC13 VCCD_LVDS0 +1.5V
K28 B25 TVDACC_FB
150mA B51 VCC14 VCCD_LVDS1 C312 C316
J28 VCC15 VCCD_LVDS2 A25
H28 60mA QT1608RL060
VCC16
G28 VCC17 VCCA_LVDS A35 Z1111 22nF 0.1u
QT1608RL060 V27 VCC18 VSSALVDS B36 Z1127
C56 C358 U27 B22
VCC19 VCCHV0 B4
Modify M30 in RB T27 VCC20 VCCHV1 B21
0.1u 0.1u R27 A21 ATVBG_FB
VCC21 VCCHV2 C17 C12
P27 VCC22
N27 VCC23 VCCSM0 AM37Z1112 C369 0.1u JP18 QT1608RL060 Modify M30 in RB
M27 VCC24 VCCSM1 AH37Z1113 22nF_0603 0.1u_0603 CLOSE Modify M30 in RB
L27 VCC25 VCCSM2 AP29 Z1114 2 1
40mA B23 K27 AD28 +1.05V
VCC26 VCCSM3 C368 0.1u B52
J27 VCC27 VCCSM4 AD27
H27 VCC28 VCCSM5 AC27 +1.5V
QT1608RL060 K26 AP26 C67 C352
C318 C323 VCC29 VCCSM6 QT1608RL060
H26 VCC30 VCCSM7 AN26
K25 AM26 C371 0.1u 22nF 0.1u 24mA
4.7U_10V_0805_OP 0.1u VCC31 VCCSM8 C746 C745+
J25 VCC32 VCCSM9 AL26
K24 VCC33 VCCSM10 AK26
K23 AJ26 B5
VCC34 VCCSM11 QTVDAC_FB 10U_10V_1206_OP 220U_2V_POS_OP
K22 VCC35 VCCSM12 AH26
K21 AG26 C18 C13
40mA B3 VCC36 VCCSM13 QT1608RL060
W20 VCC37 VCCSM14 AF26
U20 AE26 22nF 0.1u
VCC38 VCCSM15
T20 AP25

POWER
QT1608RL060 C16 C11 VCC39 VCCSM16
K20 VCC40 VCCSM17 AN25
V19 VCC41 VCCSM18 AM25
4.7U_10V_0805_OP 0.1u U19 AL25
C VCC42 VCCSM19 70mA +2.5V_SYSTEM D4 C
K19 VCC43 VCCSM20 AK25
W18 AJ25 R14
VCC44 VCCSM21 Z1122
V18 VCC45 VCCSM22 AH25 C A +1.5V
T18 VCC46 VCCSM23 AG25
K18 AF25 C10 C306 C21 C9 C7 C308 1K_OP
45mA B24 VCC47 VCCSM24 BAT54_OP
K17 VCC48 VCCSM25 AE25
AE24 4.7U_10V_0805 0.1u 0.1u 0.01u 0.1u 4.7U_10V_0805 Modify M30 in RB
Z1123 VCCSM26
AC2 VCCH_MPLL1 VCCSM27 AE23
QT1608RL060 C342 C341 AC1 AE22
Z1101 VCCH_MPLL0 VCCSM28 +1.8V_MB
B23 VCCA_DPLLA VCCSM29 AE21
4.7U_10V_0805_OP 0.1u Z1102 C35 AE20
Z1103 VCCA_DPLLB VCCSM30
AA1 VCCA_HPLL VCCSM31 AE19
Z1104 AA2 AE18 Modify M30 in RB +1.8V_MB
VCCA_MPLL VCCSM32 C747 C748 C749 C750 C751 C752
VCCSM33 AE17
Z1106 F19 AE16 For 3A trace
VCCA_CRTDAC0 VCCSM34 B68 0_1206 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u_X7R
E19 VCCA_CRTDAC1 VCCSM35 AE15 +1.8V_DDR
45mA B26 Z1128 G19 AE14
VSSA_CRTDAC VCCSM36 C373 C372 C375 B69 0_1206
VCCSM37 AP13
AN13 C710
QT1608RL060 Z1124 VCCSM38 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805
H20 VCC_SYNC VCCSM39 AM13 22P Modify 9 in RB.
C345 C344 AL13
VCCSM40
K13 VTT0 VCCSM41 AK13
4.7U_10V_0805_OP 0.1u J13 AJ13
VTT1 VCCSM42
K12 VTT2 VCCSM43 AH13
W11 VTT3 VCCSM44 AG13
V11 VTT4 VCCSM45 AF13
U11 VTT5 VCCSM46 AE13
T11 VTT6 VCCSM47 AP12
+2.5V_SYSTEM Total 70mA +VGA_NB R11 AN12
D5 VTT7 VCCSM48
P11 VTT8 VCCSM49 AM12 Modify M30 in RB
N11 VTT9 VCCSM50 AL12
Z1105 C A M11 AK12
B R18 1K VTT10 VCCSM51 B
L11 VTT11 VCCSM52 AJ12
K11 AH12 Z1111 R15 QT1608RL060
VTT12 VCCSM53 +2.5V_SYSTEM
BAT54 W10 AG12
68mA B22 VTT13 VCCSM54 C376 0.1u C741 C742
V10 VTT14 VCCSM55 AF12 10mA
U10 AE12 JP19
VTT15 VCCSM56 22nF 0.1u CLOSE
T10 VTT16 VCCSM57 AD11
QT1608RL060 C315 C314 R10 AC11 B27 Z1127 2 1
JP20 VTT17 VCCSM58 C367 0.1u
P10 VTT18 VCCSM59 AB11 +1.5V
CLOSE 0.1u 22nF N10 AB10 QT1608RL060
VTT19 VCCSM60 C370 C374
2 1 M10 VTT20 VCCSM61 AB9
K10 AP8 Z1116 250mA
2mA B53 VTT21 VCCSM62 Z1117 C353 0.1u 0.1u 4.7U_10V_0805
J10 VTT22 VCCSM63 AM1
Y9 AE1 Z1118
VTT23 VCCSM64
W9 VTT24
QT1608RL060 C24 U9 B28
VTT25 VCCTX_LVDS0 +2.5V_SYSTEM
R9 VTT26 VCCTX_LVDS1 A28
Modify M30 in RB 0.1u P9 A27
VTT27 VCCTX_LVDS2 60mA for 1.5A trace B7
N9 VTT28
M9 VTT29 VCCA_SM0 AF20 +1.5V
L9 AP19 QT2012RL030HC_3A_0805
VTT30 VCCA_SM1 C42 C23 C32
J9 VTT31 VCCA_SM2 AF19
N8 AF18 Z1119
VTT32 VCCA_SM3 4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805
M8 VTT33
N7 Total 1500mA
VTT34 Z1120
M7 VTT35 VCC3G0 AE37
N6 W37 for 1.5A trace
C14 0.47u VTT36 VCC3G1 B8
M6 VTT37 VCC3G2 U37
Z1107 A6 R37 Z1121
VTT38 VCC3G3 +1.5V
N5 N37 QT2012RL030HC_3A_0805
VTT39 VCC3G4 C66 C62
M5 VTT40 VCC3G5 L37
N4 VTT41 VCC3G6 J37
C15 0.47u M4 0.1u 4.7U_10V_0805
A VTT42 A
N3 VTT43 VCCA_3GPLL0 Y29 Modify M30 in RB
M3 VTT44 VCCA_3GPLL1 Y28
N2 VTT45 VCCA_3GPLL2 Y27
+1.05V 640mA M2 B54
C48 0.22u_10V Z1108 VTT46 Z1125
B2 VTT47 VCCA_3GBG F37 +2.5V_SYSTEM
Z1109 V1 G37
VTT48 VSSA_3GBG C19 QT1608RL060
N1
M1
VTT49 JP21 0.15mA UNIWILL COMPUTER CORP.
Z1110 VTT50 0.1u CLOSE
G1 VTT51
C332 0.22u_10V Z1129 2 1 Title
C33 C38
ALVISO_90 MX0/M40/50EI0
4.7U_10V_X5R_0805 2.2U_0603 Size Document Number Rev
NB POWER-4/5 C
3017
Modify 4 in RB. Date: Tuesday, August 09, 2005 Sheet 11 of 35
5 4 3 2 1
 A
B
C
D
VCCSM_NCTF31 AB12
VCCSM_NCTF30 AC12

+1.8V_MB
AD12

U34F
VCCSM_NCTF29
AB13

9
VCCSM_NCTF28
VCCSM_NCTF27 AC13
VCCSM_NCTF26 AD13
VCCSM_NCTF25 AC14 VSS267 AL24
VCCSM_NCTF24 AD14 VSS266 AN24
VCCSM_NCTF23 AC15 Y1 VSS271 VSS265 A26

CFG7
VCCSM_NCTF22 AD15 D2 VSS270 VSS264 E26

CFG7
VCCSM_NCTF21 AC16 G2 VSS269 VSS263 G26
VCCSM_NCTF20 AD16 J2 VSS268 VSS262 J26

(CPU Strap)
VCCSM_NCTF19 AC17 L2 VSS260 VSS261 B27

0.1u
AD17 E27

C900
VCCSM_NCTF18 P2 VSS259 VSS129
VCCSM_NCTF17 AC18 T2 VSS258 VSS128 G27
AD18 W27

5
5

VCCSM_NCTF16 V2 VSS257 VSS127

+1.05V
VCCSM_NCTF15 AC19 AD2 VSS256 VSS126 AA27

0.1u
AD19 AB27

C901

640mA
VCCSM_NCTF14 AE2 VSS255 VSS125

Add M30 in R:B

VCCSM_NCTF13 AC20 AH2 VSS254 VSS124 AF27
VCCSM_NCTF12 AD20 AL2 VSS253 VSS123 AG27

R28
L12 VTT_NCTF17 VCCSM_NCTF11 AC21 AN2 VSS252 VSS122 AJ27

0.1u
M12 AD21 AL27

C902
VTT_NCTF16 VCCSM_NCTF10 A3 VSS251 VSS121

2.2K_OP
N12 VTT_NCTF15 VCCSM_NCTF9 AC22 C3 VSS250 VSS120 AN27
P12 VTT_NCTF14 VCCSM_NCTF8 AD22 AA3 VSS249 VSS119 E28
R12 VTT_NCTF13 VCCSM_NCTF7 AC23 AB3 VSS248 VSS118 W28

0.1u

High = Mobile CPU

T12 AD23 AA28

C903
VTT_NCTF12 VCCSM_NCTF6 AC3 VSS247 VSS117
U12 VTT_NCTF11 VCCSM_NCTF5 AC24 AJ3 VSS246 VSS116 AB28
V12 VTT_NCTF10 VCCSM_NCTF4 AD24 C4 VSS245 VSS115 AC28
W12 VTT_NCTF9 VCCSM_NCTF3 AC25 H4 VSS244 VSS114 A29

0.1u
L13 AD25 D29

C904
VTT_NCTF8 VCCSM_NCTF2 L4 VSS243 VSS113
M13 VTT_NCTF7 VCCSM_NCTF1 AC26 P4 VSS242 VSS112 E29
N13 AD26 F29

Low = DT/Transportable CPU

VTT_NCTF6 VCCSM_NCTF0 U4 VSS241 VSS111
P13 VTT_NCTF5 Y4 VSS240 VSS110 G29

0.1u
R13 L17 H29

C905
VTT_NCTF4 VCC_NCTF78 AF4 VSS239 VSS109
T13 VTT_NCTF3 VCC_NCTF77 M17 AN4 VSS238 VSS108 L29
U13 VTT_NCTF2 VCC_NCTF76 N17 E5 VSS237 VSS107 P29
V13 VTT_NCTF1 VCC_NCTF75 P17 W5 VSS236 VSS106 U29

0.1u
W13 T17 V29
C906
VTT_NCTF0 VCC_NCTF74 AL5 VSS235 VSS105
VCC_NCTF73 U17 AP5 VSS234 VSS104 W29
VCC_NCTF72 V17 B6 VSS233 VSS103 AA29
VCC_NCTF71 W17 J6 VSS232 VSS102 AD29
0.1u

L18 AG29
C907

CFG18
VCC_NCTF70 L6 VSS231 VSS101
M18 AJ29

9
VCC_NCTF69 P6 VSS230 VSS100
Y12 VSS_NCTF68 VCC_NCTF68 N18 T6 VSS229 VSS99 AM29
P18 C30

(VCC Select)
AA12VSS_NCTF67 VCC_NCTF67 AA6 VSS228 VSS98
0.1u

R18 Y30
C908

Y13 VSS_NCTF66 VCC_NCTF66 AC6 VSS227 VSS97

AA13VSS_NCTF65 VCC_NCTF65 Y18 AE6 VSS226 VSS96 AA30
L14 VSS_NCTF64 VCC_NCTF64 L19 AJ6 VSS225 VSS95 AB30
M14 VSS_NCTF63 VCC_NCTF63 M19 G7 VSS224 VSS94 AC30
0.1u

N19 AE30

CFG18
C909

N14 VSS_NCTF62 VCC_NCTF62 V7 VSS223 VSS93

P14 VSS_NCTF61 VCC_NCTF61 P19 AA7 VSS222 VSS92 AP30

4
4

R14 VSS_NCTF60 VCC_NCTF60 R19 AG7 VSS221 VSS91 D31

T14 VSS_NCTF59 VCC_NCTF59 Y19 AK7 VSS220 VSS90 E31
U14 VSS_NCTF58 VCC_NCTF58 L20 AN7 VSS219 VSS89 F31

High = 1.5V
Low = 1.05V
M20 G31
+VGA_NB

V14 VSS_NCTF57 VCC_NCTF57 C8 VSS218 VSS88

W14 VSS_NCTF56 VCC_NCTF56 N20 E8 VSS217 VSS87 H31
Y14 VSS_NCTF55 VCC_NCTF55 P20 L8 VSS216 VSS86 J31
AA14VSS_NCTF54 VCC_NCTF54 R20 P8 VSS215 VSS85 K31
AB14VSS_NCTF53 VCC_NCTF53 Y20 Y8 VSS214 VSS84 L31
L15 VSS_NCTF52 VCC_NCTF52 L21 AL8 VSS213 VSS83 M31
M21 N31
M15 VSS_NCTF51
N15 VSS_NCTF50 NCTF VCC_NCTF51
VCC_NCTF50 N21
A9 VSS212
H9 VSS211
VSS82
VSS81 P31

R25
P21 R31

+2.5V_SYSTEM
P15 VSS_NCTF49 VCC_NCTF49 K9 VSS210 VSS80

1K_OP
R15 VSS_NCTF48 VCC_NCTF48 T21 T9 VSS209 VSS79 T31
T15 VSS_NCTF47 VCC_NCTF47 U21 V9 VSS208 VSS78 U31
U15 VSS_NCTF46 VCC_NCTF46 V21 AA9 VSS207 VSS77 V31
V15 VSS_NCTF45 VCC_NCTF45 W21 AC9 VSS206 VSS76 W31
W15 VSS_NCTF44 VCC_NCTF44 L22 AE9 VSS205 VSS75 AD31
Y15 VSS_NCTF43 VCC_NCTF43 M22 AH9 VSS204 VSS74 AG31
AA15VSS_NCTF42 VCC_NCTF42 N22 AN9 VSS203 VSS73 AL31
C49

0.1u

P22 A32

CFG16
AB15VSS_NCTF41 VCC_NCTF41 D10 VSS202 VSS72
L16 VSS_NCTF40 VCC_NCTF40 R22 L10 VSS201 VSS71 C32
M16 VSS_NCTF39 VCC_NCTF39 T22 Y10 VSS200 VSS70 Y32
N16 VSS_NCTF38 VCC_NCTF38 U22 AA10VSS199 VSS69 AA32
VSS

P16 VSS_NCTF37 VCC_NCTF37 V22 F11 VSS198 VSS68 AB32

C60

0.1u

R16 VSS_NCTF36 VCC_NCTF36 W22 H11 VSS197 VSS67 AC32

L23 AD32

9
T16 VSS_NCTF35 VCC_NCTF35 Y11 VSS196 VSS66
U16 VSS_NCTF34 VCC_NCTF34 M23 AA11VSS195 VSS65 AJ32
V16 VSS_NCTF33 VCC_NCTF33 N23 AF11 VSS194 VSS64 AN32
C61

0.1u

W16 VSS_NCTF32 VCC_NCTF32 P23 AG11VSS193 VSS63 D33

Y16 VSS_NCTF31 VCC_NCTF31 R23 AJ11 VSS192 VSS62 E33
AA16VSS_NCTF30 VCC_NCTF30 T23 AL11 VSS191 VSS61 F33
AB16VSS_NCTF29 VCC_NCTF29 U23 AN11VSS190 VSS60 G33
V23 H33
CFG16
R17 VSS_NCTF28 VCC_NCTF28 B12 VSS189 VSS59
W23 J33
+VGA_NB

Y17 VSS_NCTF27 VCC_NCTF27 D12 VSS188 VSS58

AA17VSS_NCTF26 VCC_NCTF26 L24 J12 VSS187 VSS57 K33
M24 L33

3
3

AB17VSS_NCTF25 VCC_NCTF25 A14 VSS186 VSS56

AA18VSS_NCTF24 VCC_NCTF24 N24 B14 VSS185 VSS55 M33
AB18VSS_NCTF23 VCC_NCTF23 P24 F14 VSS184 VSS54 N33
AA19VSS_NCTF22 VCC_NCTF22 R24 J14 VSS183 VSS53 P33
AB19VSS_NCTF21 VCC_NCTF21 T24 K14 VSS182 VSS52 R33
AA20VSS_NCTF20 VCC_NCTF20 U24 AG14VSS181 VSS51 T33
AB20VSS_NCTF19 VCC_NCTF19 V24 AJ14 VSS180 VSS50 U33
R21 VSS_NCTF18 VCC_NCTF18 W24 AL14 VSS179 VSS49 V33
Y21 VSS_NCTF17 VCC_NCTF17 L25 AN14VSS178 VSS48 W33
AA21VSS_NCTF16 VCC_NCTF16 M25 C15 VSS177 VSS47 AD33
N25 AF33

(FSB Dynamic ODT) High = Dynamic ODT Enabled

Low = Dynamic ODT Disabled
AB21VSS_NCTF15 VCC_NCTF15 K15 VSS176 VSS46
R39

Y22 VSS_NCTF14 VCC_NCTF14 P25 A16 VSS175 VSS45 AL33

AA22VSS_NCTF13 VCC_NCTF13 R25 D16 VSS174 VSS44 C34
2.2K_OP

AB22VSS_NCTF12 VCC_NCTF12 T25 H16 VSS173 VSS43 AA34

Y23 VSS_NCTF11 VCC_NCTF11 U25 K16 VSS172 VSS42 AB34
AA23VSS_NCTF10 VCC_NCTF10 V25 AL16 VSS171 VSS41 AC34
AB23VSS_NCTF9 VCC_NCTF9 W25 C17 VSS170 VSS40 AD34
Y24 VSS_NCTF8 VCC_NCTF8 L26 G17 VSS169 VSS39 AH34
AA24VSS_NCTF7 VCC_NCTF7 M26 AF17 VSS168 VSS38 AN34
AB24VSS_NCTF6 VCC_NCTF6 N26 AJ17 VSS167 VSS37 B35
Y25 VSS_NCTF5 VCC_NCTF5 P26 AN17VSS166 VSS36 D35
AA25VSS_NCTF4 VCC_NCTF4 R26 A18 VSS165 VSS35 E35
T26 F35
CFG19

AB25VSS_NCTF3 VCC_NCTF3 B18 VSS164 VSS34

U26 G35
9

Y26 VSS_NCTF2 VCC_NCTF2 U18 VSS163 VSS33

AA26VSS_NCTF1 VCC_NCTF1 V26 AL18 VSS162 VSS32 H35
W26 J35
(VTT Select)

AB26VSS_NCTF0 VCC_NCTF0 C19 VSS161 VSS31

H19 VSS160 VSS30 K35
+VGA_NB

J19 VSS159 VSS29 L35

T19 VSS158 VSS28 M35
N35
U34H

W19 VSS157 VSS27

P35
CFG19

AG19VSS156 VSS26
AN19VSS155 VSS25 R35
ALVISO_90

A20 VSS154 VSS24 T35

D20 VSS153 VSS23 U35
E20 VSS152 VSS22 V35
High = 1.2V
Low = 1.05V

F20 VSS151 VSS21 W35

2
2

G20 VSS150 VSS20 Y35

V20 VSS149 VSS19 AE35
C36
9

AK20VSS148 VSS18
C21 VSS147 VSS17 AA36
F21 VSS146 VSS16 AB36
CFG5

AC36
R24
+2.5V_SYSTEM

AF21 VSS145 VSS15

AN21VSS144 VSS14 AD36
1K_OP

A22 VSS143 VSS13 AE36

D22 VSS142 VSS12 AF36
CFG5

E22 VSS141 VSS11 AJ36

J22 VSS140 VSS10 AL36
AH22VSS139 VSS9 AN36
AL22 VSS138 VSS8 E37
H23 VSS137 VSS7 H37
AF23 VSS136 VSS6 K37
CFG6

B24 VSS135 VSS5 M37

Low = DMI*2

P37
High = DMI*4

D24 VSS134 VSS4

F24 VSS133 VSS3 T37
J24 VSS132 VSS2 V37
R31

Title

Size

Y37
Date:

AG24VSS131 VSS1
AJ24 VSS130 VSS0 AG37
2.2K_OP

3017
CFG6

High = DDR-I
Low = DDR-II
Lane
CFG9
ALVISO_90

Document Number
9

Tuesday, August 09, 2005

R29
PCIE Graphics

2.2K_OP

1
1

CFG9

Sheet
NB VSS_NCTF-5/5
operation

12
CFG[17:3] have internal pullup ressistors.
High = Normal

CFG[19:18] have internal pulldown resistors.

MX0/M40/50EI0

of
UNIWILL COMPUTER CORP.
Low = Reverse Lane
R30
2.2K

35
Rev
C
A
B
C
D
 5 4 3 2 1

+3.3V
MBA_A[13:0]
10,14 MBA_A[13:0]
+3.3V
10,14 MAA_A[13:0]

MBA_A10
MBA_A11

MBA_A13
MBA_A12
C137

MBA_A0
MBA_A1

MBA_A3

MBA_A5
MBA_A6

MBA_A8
MBA_A2

MBA_A4

MBA_A7

MBA_A9
MAA_A11

MAA_A13
+1.8V_DDR

MAA_A10

MAA_A12
MAA_A1

MAA_A3
MAA_A4

MAA_A6

MAA_A8
MAA_A9
MAA_A0

MAA_A2

MAA_A5

MAA_A7
C403 +1.8V_DDR 0.1u_OP

0.1u_OP

102
101
100

105

116

199

103
104
111
112
117
118
CON15

99
98
97
94
92
93
91

90
89

86
84

81
82
87
88
95
96
102
101
100

105

116

199

103
104
111
112
117
118
CON4

99
98
97
94
92
93
91

90
89

86
84

81
82
87
88
95
96
MA_DQ[63:0] 10 MB_DQ[63:0] 10

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A11
A12
NC/A13
NC/A14
NC/A15

VDDSPD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A10/AP
6 MB_DQ3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A11
A12
NC/A13
NC/A14
NC/A15

VDDSPD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A10/AP
MA_DQ1 +3.3V DQ5 MB_DQ5
DQ5 6 DQ0 5
D 7 MA_DQ5 R353 163 17 MB_DQ7 D
DQ1 MA_DQ2 NC/TEST DQ2 MB_DQ6
163 NC/TEST DQ3 19 50 NC DQ3 19
50 16 MA_DQ3 10K 69 16 MB_DQ0
R345 R344 NC DQ7 MA_DQ0 R352 NC DQ7 MB_DQ2
69 NC DQ4 4 83 NC DQ6 14
83 5 MA_DQ4 120 7 MB_DQ4
10K 10K NC DQ0 MA_DQ6 10K NC DQ1 MB_DQ1
120 NC DQ6 14 DQ4 4
17 MA_DQ7 Z1303 198 23 MB_DQ12
Z1301 DQ2 MA_DQ12 Z1304 SA0 DQ8 MB_DQ13
198 SA0 DQ12 20 200 SA1 DQ9 25
Z1302 200 22 MA_DQ8 35 MB_DQ10
SA1 DQ13 MA_DQ10 DQ10 MB_DQ15
DQ14 36 7,16,17 SB_SMB_DATA 195 SDA DQ11 37
195 37 MA_DQ14 197 20 MB_DQ8
7,16,17 SB_SMB_DATA SDA DQ11 MA_DQ13 7,16,17 SB_SMB_CLK SCL DQ12 MB_DQ9
7,16,17 SB_SMB_CLK 197 SCL DQ9 25 10,14 MB_BA[2:0] DQ13 22
23 MA_DQ9 MB_BA0 107 36 MB_DQ11
10,14 MA_BA[2:0] MA_BA0 DQ8 MA_DQ15 MB_BA1 BA0 DQ14 MB_DQ14
107 BA0 DQ10 35 106 BA1 DQ15 38
MA_BA1 106 38 MA_DQ11 MB_BA2 85 46 MB_DQ18
MA_BA2 BA1 DQ15 MA_DQ20 BA2 DQ21 MB_DQ16
85 BA2 DQ17 45 DQ17 45
43 MA_DQ16 MB_CS#2 110 44 MB_DQ21
MA_CS#0 DQ16 MA_DQ18 9,14 MB_CS#2 MB_CS#3 S0# DQ20 MB_DQ19
9,14 MA_CS#0 110 S0# DQ18 55 9,14 MB_CS#3 115 NC/S1# DQ19 57
MA_CS#1 115 57 MA_DQ23 55 MB_DQ20
9,14 MA_CS#1 NC/S1# DQ19 MA_DQ21 10 MB_DM[7:0] MB_DM0 DQ18 MB_DQ17
10 MA_DM[7:0] DQ20 44 10 DM0 DQ16 43
MA_DM0 10 46 MA_DQ17 MB_DM1 26 56 MB_DQ22
MA_DM1 DM0 DQ21 MA_DQ19 MB_DM2 DM1 DQ22 MB_DQ23
26 DM1 DQ22 56 52 DM2 DQ23 58
MA_DM2 52 58 MA_DQ22 MB_DM3 67 61 MB_DQ28
MA_DM3 DM2 DQ23 MA_DQ24 MB_DM4 DM3 DQ24 MB_DQ29
67 DM3 DQ24 61 130 DM4 DQ25 63
MA_DM4 130 63 MA_DQ25 MB_DM5 147 75 MB_DQ26
MA_DM5 DM4 DQ25 MA_DQ28 MB_DM6 DM5 DQ27 MB_DQ30
147 DM5 DQ28 62 170 DM6 DQ30 74
MA_DM6 170 75 MA_DQ27 MB_DM7 185 62 MB_DQ25
MA_DM7 DM6 DQ27 MA_DQ31 DM7 DQ28 MB_DQ24
185 DM7 DQ30 74 DQ29 64
64 MA_DQ26 73 MB_DQ27
DQ29 MA_DQ29 MB_WE# DQ26 MB_DQ31
DQ26 73 10,14 MB_WE# 109 WE# DQ31 76
MA_WE# 109 76 MA_DQ30 MB_CAS# 113 126 MB_DQ32
10,14 MA_WE# MA_CAS# WE# DQ31 MA_DQ38 10,14 MB_CAS# MB_RAS# CAS# DQ37 MB_DQ34
10,14 MA_CAS# 113 CAS# DQ32 123 10,14 MB_RAS# 108 RAS# DQ36 124
C MA_RAS# 108 125 MA_DQ33 136 MB_DQ35 C
10,14 MA_RAS# RAS# DQ33 MA_DQ39 DQ39 MB_DQ37
DQ34 135 DQ38 134
137 MA_DQ34 MB_CKE2 79 125 MB_DQ36
MA_CKE0 DQ35 MA_DQ37 9,14 MB_CKE2 MB_CKE3 CKE0 DQ33 MB_DQ33
9,14 MA_CKE0 79 CKE0 DQ36 124 9,14 MB_CKE3 80 NC/CKE1 DQ32 123
MA_CKE1 80 126 MA_DQ36 137 MB_DQ39
9,14 MA_CKE1 NC/CKE1 DQ37 MA_DQ32 MB_CK3 DQ35 MB_DQ38
DQ38 134 9 MB_CK3 30 CK0 DQ34 135
MA_CK0 30 136 MA_DQ35 MB_CK4 164 141 MB_DQ45
9 MA_CK0 MA_CK1 CK0 DQ39 MA_DQ44 9 MB_CK4 MB_CK#3 CK1 DQ40 MB_DQ44
9 MA_CK1 164 CK1 DQ40 141 9 MB_CK#3 32 CK#0 DQ41 143
MA_CK#0 32 140 MA_DQ45 MB_CK#4 166 151 MB_DQ41
9 MA_CK#0 MA_CK#1 CK#0 DQ44 MA_DQ43 9 MB_CK#4 CK#1 DQ42 MB_DQ40
9 MA_CK#1 166 CK#1 DQ42 151 10 MB_DQS[7:0] DQ43 153
153 MA_DQ47 MB_DQS0 13 142 MB_DQ42
10 MA_DQS[7:0] MA_DQS0 DQ43 MA_DQ41 MB_DQS1 DQS0 DQ45 MB_DQ46
13 DQS0 DQ45 142 31 DQS1 DQ44 140
MA_DQS1 31 143 MA_DQ40 MB_DQS2 51 152 MB_DQ43
MA_DQS2 DQS1 DQ41 MA_DQ46 MB_DQS3 DQS2 DQ46 MB_DQ47
51 DQS2 DQ46 152 70 DQS3 DQ47 154
MA_DQS3 70 154 MA_DQ42 MB_DQS4 131 174 MB_DQ54
MA_DQS4 DQS3 DQ47 MA_DQ52 MB_DQS5 DQS4 DQ54 MB_DQ51
131 DQS4 DQ48 157 148 DQS5 DQ55 176
MA_DQS5 148 159 MA_DQ49 MB_DQS6 169 173 MB_DQ55
MA_DQS6 DQS5 DQ49 MA_DQ55 MB_DQS7 DQS6 DQ50 MB_DQ52
169 DQS6 DQ50 173 10 MB_DQS#[7:0] 188 DQS7 DQ52 158
MA_DQS7 188 175 MA_DQ51 MB_DQS#0 11 160 MB_DQ49
10 MA_DQS#[7:0] MA_DQS#0 DQS7 DQ51 MA_DQ53 MB_DQS#1 DQS#0 DQ53 MB_DQ48
11 DQS#0 DQ52 158 29 DQS#1 DQ49 159
MA_DQS#1 29 160 MA_DQ48 MB_DQS#2 49 157 MB_DQ53
MA_DQS#2 DQS#1 DQ53 MA_DQ50 MB_DQS#3 DQS#2 DQ48 MB_DQ50
49 DQS#2 DQ54 174 68 DQS#3 DQ51 175
MA_DQS#3 68 176 MA_DQ54 MB_DQS#4 129 179 MB_DQ62
MA_DQS#4 DQS#3 DQ55 MA_DQ56 MB_DQS#5 DQS#4 DQ56 MB_DQ56
129 DQS#4 DQ56 179 146 DQS#5 DQ57 181
MA_DQS#5 146 181 MA_DQ62 MB_DQS#6 167 192 MB_DQ57
MA_DQS#6 DQS#5 DQ57 MA_DQ61 MB_DQS#7 DQS#6 DQ62 MB_DQ58
167 DQS#6 DQ58 189 186 DQS#7 DQ63 194
MA_DQS#7 186 191 MA_DQ60 180 MB_DQ61
DQS#7 DQ59 MA_DQ63 MB_ODT2 DQ60 MB_DQ60
DQ60 180 9,14 MB_ODT2 114 ODT0 DQ61 182
MA_ODT0 114 182 MA_DQ58 MB_ODT3 119 191 MB_DQ59
9,14 MA_ODT0 MA_ODT1 ODT0 DQ61 MA_DQ57 9,14 MB_ODT3 NC/ODT1 DQ59 MB_DQ63
9,14 MA_ODT1 119 NC/ODT1 DQ62 192 DQ58 189
194 MA_DQ59 DDR_VREF_2 1 NC3
DDR_VREF_1 DQ63 VREF VSS
1 VREF VSS 201 VSS NC4 Modify 1 in
B C405 B
VSS 202 Modify 1 in 184 VSS VSS 145
R:A.
C399 184 145 187 149
187
VSS VSS
149
R:A. 0.1u 190
VSS VSS
150
0.1u VSS VSS VSS VSS
190 VSS VSS 150 193 VSS VSS 155
193 VSS VSS 155 196 VSS VSS 156
196 VSS VSS 156 171 VSS VSS 161
171 VSS VSS 161 172 VSS VSS 162
172 VSS VSS 162 177 VSS VSS 165
177 VSS VSS 165 178 VSS VSS 168
178 168 183

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS
183
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
DDR CONN2

121
122
127
128
132
133
138
139
144
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
DDR CONN1
121
122
127
128
132
133
138
139
144

2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
2
3
8
9

+1.8V_DDR +1.8V_DDR Change in RC 6/29

Thermistor Place to SO-DIMM +1.8VS to GND
DDR_VREF_1 DDR_VREF_2
R336 C377 C400 R340

0.1u 0.1u_OP 150_1_OP +3.3V C132 1000p

+1.8V_DDR
150_1 R341 0

RT2 C131 1000p

+1.8V_DDR
R337 C378 C379 C406 R349
10K_T
150_1 0.1u 1000p 0.1u_OP 150_1_OP
A C408 1000p A
24 DDR2_TEMP +1.8V_DDR
If DRAM need to adjust voltage.
R333
C409 1000p
+1.8V_DDR
1.5K_1
+1.8V_DDR
UNIWILL COMPUTER CORP.
C135 C144 C401 C138 C398 C129 C134 C133 C410 C407 C69 C70 C68 C71
Title
4.7U_10V_0805 4.7U_10V_0805 2.2U_0603 2.2U_0603 2.2U_0603 2.2U_0603 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
MX0/M40/50EI0
Size Document Number Rev
DDR2 CHANNELA,B SODIMM0,1 C
3017
Date: Tuesday, August 09, 2005 Sheet 13 of 35
5 4 3 2 1
 5 4 3 2 1

10,13 MBA_A[13:0]

10,13 MAA_A[13:0] SMART POWER

10,13 MB_BA[2:0]
+0.9V_DDR R710 0_OP
10,13 MA_BA[2:0]
Q23
S D CPU_VID4
6 H_VID4
RP3 56X4_0402 RP13 56X4_0402 2N7002
MB_CKE3 8 1 MB_BA2 8 1 VID5 VID4 VID3 VID2 VID1 VID0 VCORE +_mV
9,13 MB_CKE3
MA_BA2 7 2 MA_CKE1 7 2 R115
9,13 MA_CKE1

G
MBA_A11 6 3 MBA_A12 6 3 0 1 1 0 1 1 1.276
D D
MBA_A7 5 4 MBA_A9 5 4 1K_OP
RP15 56X4_0402 RP12 56X4_0402 R371 1K 0 1 1 1 0 0 1.260
MBA_A6 8 1 MBA_A8 8 1 R109 0_OP Z1401
24 SMP1_EN# +3.3V
MAA_A12 7 2 MAA_A6 7 2 0 1 1 1 1 0 1.228
MAA_A9 6 3 MAA_A7 6 3
MAA_A8 5 4 MAA_A11 5 4 R711 0_OP 1 0 0 0 0 0 1.196
RP4 56X4_0402 RP11 56X4_0402
MBA_A4 8 1 MBA_A5 8 1 Q27 1 0 0 0 1 0 1.164
MBA_A2 7 2 MBA_A3 7 2 S D CPU_VID3
6 H_VID3
MBA_A0 6 3 MBA_A1 6 3 2N7002 1 0 0 1 0 1 1.116
MAA_A5 5 4 MAA_A4 5 4
RP5 56X4_0402 RP8 56X4_0402 R374 1K 1 0 0 1 1 0 1.100

G
MAA_A3 8 1 MAA_A2 8 1 R118 R111 0_OP Z1405
+3.3V
MAA_A1 7 2 MBA_A10 7 2 1 0 1 0 1 0 1.036
MB_BA1 6 3 MB_BA0 6 3 1K_OP
MB_CS#2 5 4 MB_WE# 5 4 R712 0_OP 1 0 1 0 1 1 1.020
9,13 MB_CS#2 10,13 MB_WE#
RP2 56X4_0402 RP9 56X4_0402
MB_RAS# 8 1 MA_CS#0 8 1 Q26 1 0 1 1 0 0 1.004
10,13 MB_RAS# 9,13 MA_CS#0 CPU_VID2
MAA_A10 7 2 MA_RAS# 7 2 S D
10,13 MA_RAS# 6 H_VID2
MA_BA0 6 3 MAA_A13 6 3 2N7002 1 0 1 1 0 1 0.988
MA_WE# 5 4 MA_ODT0 5 4
10,13 MA_WE# 9,13 MA_ODT0
RP6 56X4_0402 RP10 56X4_0402 1 0 1 1 1 0 0.972

G
MB_ODT2 8 1 MA_BA1 8 1 R114 R107 0 Z1412 R372 1K
9,13 MB_ODT2 +3.3V
MBA_A13 7 2 MAA_A0 7 2 R110 0_OP 1 0 1 1 1 1 0.956
10,13 MBA_A13
MA_CAS# 6 3 MB_CAS# 6 3 1K
10,13 MA_CAS# 10,13 MB_CAS#
MA_CS#1 5 4 MB_CS#3 5 4 1 1 0 1 1 0 0.844
9,13 MA_CS#1 9,13 MB_CS#3
R713 0_OP
MB_ODT3 R342 56 1 1 1 1 1 1 0.716
9,13 MB_ODT3
MB_CKE2 R343 56 Q30
9,13 MB_CKE2 CPU_VID1
C MA_ODT1 R88 56 S D C
9,13 MA_ODT1 6 H_VID1
MA_CKE0 R87 56 2N7002
9,13 MA_CKE0
Z1402

G
R112 0 Z1413 R376 1K
+3.3V
Z1403

R714 0_OP
+0.9V_DDR
Q33
S D CPU_VID0
6 H_VID0
2N7002
C158 C156 C391 C154 C153 C387 C157 C386 C385 C384 C382 C381
0.1u

G
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u R117 0 Z1414 R125 1K_OP
+3.3V

C
B Q25
C159 C162 C160 C163 C161 C380 C155 C383 C152 C390 C389 C388 2N3904
0.1u

E
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
Z1404

D
Q24 VID5 VID4 VID3 VID2 VID1 VID0 VCORE +_mV
R113
+3.3V Z1406 G 0 0 0 0 0 0 1.708 -0mV
2N7002

S
10K 0 0 0 0 1 0 1.676 -32mV

D
Q22
B B
Layout note: Place one cap close to every 2 pullup resistors terminated to DDR_VREF 0 0 0 1 0 0 1.644 -64mV
24 SMP1_EN# G
2N7002 0 0 1 0 0 0 1.580 -128mV

S
0 1 0 0 0 0 1.452 -256mV
0 0 1 0 1 0 1.548
0 0 1 0 1 1 1.532
+1.05V
+5V 0 0 1 1 0 0 1.516
Add M30 in R:B 0 0 1 1 1 0 1.484
C150 0 1 0 0 0 1 1.436
8
7
6
5

0.1u R96
RP1 +3.3V +1.05V 0 1 0 0 1 0 1.420
24

U10
10KX4_0805 10K 0 1 0 1 0 0 1.388
VCC

R373 R807
0 1 0 1 1
1
2
3
4

0 1.356
CPU_VID4 3 2 SMP2_EN#
CPU_VID3 1A1 1B1 PM_VID4 25 4.7K
4 1A2 1B2 5 PM_VID3 25 0 1 1 0 0 1 1.308
CPU_VID2 7 6 4.7K_OP

G
CPU_VID1 1A3 1B3 PM_VID2 25 Q31
8 1A4 1B4 9 PM_VID1 25 0 1 1 0 1 0 1.292
CPU_VID0 11 10 2N7002
1A5 1B5 PM_VID0 25 H_VID5
6 H_VID5 S D PM_VID5 25
R108 200 Z1408 14 15
24 EC_VID4 Z1409 17 2A1 2B1
R103 200 16 TO PWM CONTROLLER
24 EC_VID3 Z1410 18 2A2 2B2
A R102 200 19 Q32 Q28 A
24 EC_VID2 Z1411 21 2A3 2B3
R99 200 20 ( CPU V_CORE PWM)
24 EC_VID1 2A4 2B4 Z1407
22 2A5 2B5 23 S D S D
R119
SMP2_EN 1 Modify 2 in
+5V 1OE#
SMP2_EN# 13 2N7002_OP 2N7002_OP
2OE# R:A. UNIWILL COMPUTER CORP.
G

4.7K
D

Q29
GND

SMP2_EN Title
24 CELERON_VO_DET
G
24 SMP2_EN#
2N7002 SN74CBT3384A MX0/M40/50EI0
12
S

Size Document Number Rev

DDR Terminate / Smart Power C
3017
Date: Tuesday, August 09, 2005 Sheet 14 of 35
5 4 3 2 1
 5 4 3 2 1

D18 +3.3VA_RTC

A C Z1501 R184 470

+3.3VA

1
C234
D D
BAT54 JP7
Modify 3 in R:A. OPEN_1A_OP 1u_6.3V Modify M30
in RB

2
D50
R830 470_OP C204
Z1506 Z1509 A C Z1508 R186 180K

BAT54_OP
R831 C241 C240 15p
R619 Modify 6 in RB. 0.1u Y1 R130
470 0.1u_OP 32.768KHz_DIP 10M
470_OP PIN 3=GND POWER
CON102 Z1510 R185 C201
U19D
SUBBAT+ RTC_X1 Y1 P2
1 RTC_X2 RTCX1 LAD[0] LPC_AD0 24
R158 1M Y2 N3
2 RTCX2 LAD[1]/FB[1] LPC_AD1 24
15p N5

RTC

LPC
RTC_RST# LAD[2]/FB[2] LPC_AD2 24
BAT_CONN_OP 470 AA2 N4
RTCRST# LAD[3]/FB[3] LPC_AD3 24
Z1502 SM_INTRUDER# AA3 N6
INTRUDER# LDRQ[0]# +1.05V
AA5 INTVRMEN LDRQ[1]#/GPI[41] P4
1

BT1 Disable VccSus1.5 VRM Mode

LFRAME# P3 LPC_FRAME# 24
MAXELL-ML1220 D12 EE_CS R609 10K
B12 EE_SHCLK +3.3V
Modify 5 in RB. R365
2

D11 EE_DOUT A20GATE AF22 H_A20GATE 24

LAN
F13 EE_DIN A20M# AF23 H_A20M# 5
C R814 FCM1005M-060T00 F12 AE27 C
23 ACZ_BITCLK LAN_CLK CPUSLP# H_CPUSLP# 5,8
56
B11 LAN_RSTSYNC DPRSTP#/TP[4] AE24 H_DPRSTP# 5
Thermistor C921 AD27 H_DPSLP#

CPU
+3.3V DPSLP#/TP[2] H_DPSLP# 5
E12 LANRXD[0]
22p_OP E11 AF24 H_FERR_R R366 56
LANRXD[1] FERR# H_FERR# 5
C13 LANRXD[2]
+3.3V AG25
CPUPWRGD/GPO[49] H_PWRGD 5
C12 LANTXD[0]
R217 C11 AG26
LANTXD[1] IGNNE# H_IGNNE# 5
E13 LANTXD[2] INT3_3V# AE22
RT1 AF27
INT# H_INIT# 5
1K_OP Z1507 C10 AG24
ACZ_BIT_CLK INTR H_INTR 5 +1.05V
10K_T B9
23 ACZ_SYNC ACZ_SYNC

AC-97/AZALIA
RCIN# AD23 H_RCIN# 17,24
24 SB_TEMP 23 ACZ_RST# A10 ACZ_RST#
AF25 R364
NMI H_NMI 5
23 ACZ_SDATAIN0 F11 ACZ_SDIN[0] SMI# AG27 H_SMI# 5
R149 F10
23 ACZ_SDATAIN1 Z1503 ACZ_SDIN[1]
B10 AE26 75_1_OP
TP61 ACZ_SDIN[2] STPCLK# H_STPCLK# 5
1.5K_1
C9 AE23 H_THERMTRIP_R R363 56
23 ACZ_SDATAOUT ACZ_SDO THRMTRIP# PM_THRMTRIP# 5,9

20 SATA_LED# AC19 SATALED# DA[0] AC16 SDA0 20

DA[1] AB17 SDA1 20
SATA_RXN0_C AE3 AC17
SATA_RXP0_C SATA[0]RXN DA[2] SDA2 20
AD3 SATA[0]RXP
SATA_TXN0_C AG2 AD16
SATA_TXP0_C SATA[0]TXN DCS1# SDCS1# 20
B
AF2 SATA[0]TXP DCS3# AE17 SDCS3# 20 B

AD7 AD14 SDD0

SATA[2]RXN DD[0] SDD1 SDD[0..15] 20
AC7 SATA[2]RXP DD[1] AF15

SATA
SATA_TXN2_C AF6 AF14 SDD2

IDE
SATA_TXP2_C SATA[2]TXN DD[2] SDD3
AG6 SATA[2]TXP DD[3] AD12
AE14 SDD4
DD[4] SDD5
7 CLK_SATA# AC2 SATA_CLKN DD[5] AC11
AC1 AD11 SDD6
7 CLK_SATA SATA_CLKP DD[6] SDD7
DD[7] AB11
Z1505 AG11 AE13 SDD8
SATARBIAS# DD[8] SDD9
AF11 SATARBIAS DD[9] AF13
AB12 SDD10
R379 DD[10] SDD11
Placement note DD[11] AB13
AC13 SDD12
24.9_1 DD[12] SDD13
Distance between the ICH-6 M and cap on the'P' signal 20 SDIORDY AF16 IORDY DD[13] AE15
AB16 AG15 SDD14
should be identical distance between the ICH-6 M and 20 SDIRQ15 IDEIRQ DD[14] SDD15
20 SDDACK# AB15 DDACK# DD[15] AD13
"N" signal for same pair. AC14
20 SDIOW# DIOW#
20 SDIOR# AE16 DIOR# DDREQ AB14 SDDREQ 20
ICH-6_M

SATA_RXN0 C246 3900p SATA_RXN0_C

20 SATA_RXN0
NPO
SATA_RXP0 C251 3900p SATA_RXP0_C
20 SATA_RXP0
NPO Modify M30 in RB.
Close to IC
Close to IC
A SATA_TXN0 C191 3900p SATA_TXN0_C A
20 SATA_TXN0
NPO
SATA_TXP0 C186 3900p SATA_TXP0_C SATA_RXP0_C R645 0_OP SATA_RXP0_C_HDD
20 SATA_TXP0 SATA_RXN0_C R646
NPO 0_OP SATA_RXN0_C_HDD
Close to S/B
SATA_TXN0 R647 0_OP SATA_TXN0_HDD UNIWILL COMPUTER CORP.
SATA_RXN0_C_HDD SATA_TXP0 SATA_TXN0_HDD 20
SATA_RXN0_HDD C214 3900p_OP R648 0_OP SATA_TXP0_HDD
20 SATA_RXN0_HDD SATA_TXP0_HDD 20
NPO Title
SATA_RXP0_HDD C211 3900p_OP SATA_RXP0_C_HDD
20 SATA_RXP0_HDD
NPO MX0/M40/50EI0
Size Document Number Rev
Close to HDD SB ICH-6M-1/3 C
3017
Date: Tuesday, August 09, 2005 Sheet 15 of 35
5 4 3 2 1
 5 4 3 2 1

+3.3V

U19B
18,21,22,23 PCI_AD[31:0] PCI_AD0 E2 L5 U19C
PCI_AD1 AD[0] REQ[0]# PCI_REQ#0 17,22 PCIE_RXN0
E5 C1 T2 H25
PCI_AD2
PCI_AD3
C2
AD[1]
AD[2]
PCI GNT[0]#
REQ[1]# B5
PCI_GNT#0 22
PCI_REQ#1 17,18
17,18,23 PM_RI#
SATA0_GP
RI# HSIN[0]
HSIP[0] H24 PCIE_RXP0
PCIE_TXN0
PCIE_RXN0 18
PCIE_RXP0 18
F5 B6 R375 10K AF17 G27
PCI_AD4 AD[3] GNT[1]# PCI_GNT#1 18 SATA[0]GP/GPIO[26] HSON[0] PCIE_TXP0 PCIE_TXN0 18
F3 M5 AE18 G26

PCI-EXPRESS
PCI_AD5 AD[4] REQ[2]# PCI_REQ#2 17,21 19 LCDSEL1# SATA[1]GP/GPIO[29] HSOP[0] PCIE_TXP0 18
E9 AD[5] GNT[2]# F1 PCI_GNT#2 21 19 LCDSEL2# AF18 SATA[2]GP/GPIO[30]
PCI_AD6 F2 B8 AG18 K25 PCIE_RXN1
PCI_AD7 AD[6] REQ[3]# PCI_REQ#3 17,23 19 LCDSEL0# SATA[3]GP/GPIO[31] HSIN[1] PCIE_RXP1 PCIE_RXN1
D
D6 AD[7] GNT[3]# C8 PCI_GNT#3 23 HSIP[1] K24 PCIE_RXP1 D
PCI_AD8 E6 F7 SMBCLK Y4 J27 PCIE_TXN1
PCI_AD9 AD[8] REQ[4]#/GPI[40] PCI_REQ#4 17 SMBDATA SMBCLK HSON[1] PCIE_TXP1 PCIE_TXN1
D3 AD[9] GNT[4]#/GPO[48] E7 PCI_GNT#4 W5 SMBDATA HSOP[1] J26 PCIE_TXP1
PCI_AD10 A2 E8 +3.3VS LINK_ALERT# Y5

GPIO
PCI_AD11 AD[10] REQ[5]#/GPI[1] Z1615 PCI_REQ#5 17 LINKALERT# PCIE_RXN2
D2 AD[11] GNT[5]#/GPO[17] F6 TP62 Boot BIOS SEL 17 SMLINK0 W4 SMLINK[0] HSIN[2] M25 PCIE_RXN2
PCI_AD12 D5 B7 U6 M24 PCIE_RXP2
PCI_AD13 AD[12] REQ[6]#/GPI[0] GNT#6/GPO16 PCI_REQ#6 17 17 SMLINK1 MCH_SYNC# SMLINK[1] HSIP[2] PCIE_TXN2 PCIE_RXP2
H3 AD[13] GNT[6]#/GPO[16] D8 AG21 MCH_SYNC# HSON[2] L27 PCIE_TXN2
PCI_AD14 B4 R139 ACZ_SPKR F8 L26 PCIE_TXP2
PCI_AD15 AD[14] 23 ACZ_SPKR SPKR HSOP[2] PCIE_TXP2
J5 AD[15] C/BE[0]# J6 PCI_C/BE#0 18,21,22,23
PCI_AD16 K2 H6 W3 P24 PCIE_RXN3
PCI_AD17 AD[16] C/BE[1]# PCI_C/BE#1 18,21,22,23 SUS_STAT#/LPCPD# HSIN[3] PCIE_RXP3 PCIE_RXN3
K5 G4 10K P23
PCI_AD18 AD[17] C/BE[2]# PCI_C/BE#2 18,21,22,23 SYS_RST# HSIP[3] PCIE_TXN3 PCIE_RXP3
D4 AD[18] C/BE[3]# G2 PCI_C/BE#3 18,21,22,23 U2 SYS_RESET# HSON[3] N27 PCIE_TXN3
PCI_AD19 L6 N26 PCIE_TXP3
PCI_AD20 AD[19] HSOP[3] PCIE_TXP3
G3 AD[20] IRDY# A3 PCI_IRDY# 17,18,21,22,23 9 BM_BUSY# AD19 BM_BUSY#/GPI[6]
PCI_AD21 H4 E1 +3.3V T25
AD[21] PAR PCI_PAR 17,18,21,22,23 DMI[0]RXN DMI_RXN0 9

Direct Media Interface

PCI_AD22 H2 R2 GPI7 AE19 T24
PCI_AD23 AD[22] PCIRST# PCI_RST# 17,18,21,22,23,24 GP[7] DMI[0]RXP DMI_RXP0 9
H5 AD[23] DEVSEL# C3 PCI_DEVSEL# 17,18,21,22,23 24 EC_EXTSMI# R1 GP[8] DMI[0]TXN R27 DMI_TXN0 9
PCI_AD24 B3 E3 R26
PCI_AD25 AD[24] PERR# PCI_PERR# 17,18,21,22,23 DMI[0]TXP DMI_TXP0 9
M6 AD[25] PLOCK# C5 PCI_LOCK# 17 17 SMB_ALERT# W6 SMBALERT#/GPI[11]
PCI_AD26 B2 G5 R377 R388 V25
PCI_AD27 AD[26] SERR# PCI_SERR# 17,21,22,23 GPI12 DMI[1]RXN DMI_RXN1 9
K6 AD[27] STOP# J1 PCI_STOP# 17,18,21,22,23 M2 GPI[12] DMI[1]RXP V24 DMI_RXP1 9
PCI_AD28 K3 J2 GPI13 R6 U27
PCI_AD29 AD[28] TPDY# PCI_TRDY# 17,18,21,22,23 GPI[13] DMI[1]TXN DMI_TXN1 9
A5 10K_OP 10K_OP U26
PCI_AD30 AD[29] DMI[1]TXP DMI_TXP1 9
L1 AD[30] PLTRST# R5 PLT_RST# 9,17,20,24 7 PM_STPPCI# AC21 STP_PCI#/GPO[18]
PCI_AD31 K4 G6 Y25
AD[31] PCICLK CLK_PCI 7 Z1610 DMI[2]RXN DMI_RXN2 9
PME# P6 PCI_PME# 18,21,22,23 TP69 AB21 GPO[19] DMI[2]RXP Y24 DMI_RXP2 9
17,18,21,22,23 PCI_FRAME# J3 FRAME# DMI[2]TXN W27 DMI_TXN2 9
7,25 PM_STPCPU# AD22 STP_CPU#/GPO[20] DMI[2]TXP W26 DMI_TXP2 9
Interrupt I/ F
N2 D9 Z1616 AD20 AB24
17,18 INT_PIRQA# PIRQ[A]# PIRQ[E]#/GPI[2] INT_PIRQE# 17,18 TP82 Z1611 GPO[21] DMI[3]RXN DMI_RXN3 9
C L2 C7 AD21 AB23 +1.5V C
17,23 INT_PIRQB# PIRQ[B]# PIRQ[F]#/GPI[3] INT_PIRQF# 17,23 TP73 GPO[23] DMI[3]RXP DMI_RXP3 9
17,22 INT_PIRQC# M1 PIRQ[C]# PIRQ[G]#/GPI[4] C6 INT_PIRQG# 17 DMI[3]TXN AA27 DMI_TXN3 9
L3 M3 GPIO24 V3 AA26
17,21 INT_PIRQD# PIRQ[D]# PIRQ[H]#/GPI[5] INT_PIRQH# 17 GPIO[24] DMI[3]TXP DMI_TXP3 9
R415
RESERVED GPIO25 P5 AD25
Z1601 Z1606 GPIO27 GPIO[25] DMI_CLKN CLK_PCIE_ICH# 7
AC5 AD9 TP64 R3 AC25
TP63 Z1602 RSVD[1] RSVD[6] Z1607 GPIO28 GPIO[27] DMI_CLKP CLK_PCIE_ICH 7
AD5 AF8 TP66 T3 24.9_1
TP65 Z1603 RSVD[2] RSVD[7] Z1608 GPIO[28]
AF4 AG8 TP68 AF19 F24 +3.3VS
TP67 Z1604 RSVD[3] RSVD[8] Z1609 17,21,22,23 PM_CLKRUN# CLKRUN#/GPIO[32] DMI_ZCOMP
AG4 U3 TP71 +3.3V AF20
TP70 RSVD[4] RSVD[9] SB_ALERT#1 GPIO[33] Z1613
Z1605 AC9 AC18 F23
TP72 RSVD[5] SB_ALERT#2 GPIO[34] DMI_IRCOMP
ICH-6_M Modify M30 in U5 C23 USB_OC#4 RP14 1 8 8P4RX8.2K
17,18 PCIE_WAKE# WAKE# OC[4]#/GPI[9] USB_OC#5
R384 D23 2 7
RB. AB20
OC[5]#/GPI[10]
C25 USB_OC#6 3 6
17,18,24 INT_SERIRQ SERIRQ OC[6]#/GPI[14] USB_OC#7
10K Close to S/B. C24 4 5
OC[7]#/GPI[15]
17,24 PM_THROTTING# AC20 THRM#
C27 USB_OC#0 RP7 4 8 8P4RX8.2K
OC[0]# USB_OC#1
9 DELAY_VR_PWRGOOD AF21 VRMPWRGD OC[1]# B27 2 7
+3.3VS B26 USB_OC#2 1 6
OC[2]# USB_OC#3
E10 C26 3 5

CLOCKS
GPIO24 7 CLK_ICH14 CLK14 OC[3]#
R398 10K R378 C711
7 CLK_USB48 A27 CLK48 USUP[0]N C21 USB_P0- 19 Test by M30
+3.3V R145 10K GPIO27 0 0.1u_OP D21
SUS_CLK V6
USUP[0]P
A20
USB_P0+ 19 R:A
GPI12 GPIO28 17 SUS_CLK SUSCK USUP[1]N USB_P1- 23
R150 10K R403 10K B20
25 VR_PWRGD PM_SLP_S3# USUP[1]P USB_P1+ 23
17,20,21,24 PM_SLP_S3# T4 SLP_S3# USUP[2]N D19 USB_P2- 19
R383 10K SB_ALERT#1 R142 10K EC_EXTSMI# PM_SLP_S4# T5 C19

POWER MGT
17,24 PM_SLP_S4# Z1612 SLP_S4# USUP[2]P USB_P2+ 19
TP74 T6 SLP_S5# USUP[3]N A18 USB_P3- 18
R389 10K SB_ALERT#2 R404 10K GPI13 B18
USUP[3]P USB_P3+ 18

USB
B 17,24 PWROK AA1 PWROK USUP[4]N E17 USB_P4- 19 B
R385 10K MCH_SYNC# R134 10K SMBCLK D17
USUP[4]P USB_P4+ 19
25 PM_DPRSLPVR AE20 DPRSLPVR/TP[1] USUP[5]N B16 USB_P5- 23
R381 10K GPI7 R133 10K SMBDATA A16
USUP[5]P USB_P5+ 23
17 PM_BATLOW# V2 BATLOW#/TP[0] USUP[6]N C15 MB_USB6- 23
USUP[6]P D15 MB_USB6+ 23
24 PWRBTN# U1 PWRBTN# USUP[7]N A14 USB_P7- 18
USUP[7]P B14 USB_P7+ 18
PLT_RST# V5 LAN_RST#
USBRBIAS# A22
R138 100 PM_RSMRST#_R Y3 B22 USB_RBIAS_PN R216 22.6_1
17,24 PM_RSMRST# RSMRST# USBRBIAS
ICH-6_M

ICH6 STRAPING

R430 1K_OP GNT#6/GPO16 Audio BD --> USB_P1,USB_P5

+3.3V
GPIO25
IO BD --> USB_P2,USB_P4
R410 1K_OP
CRT BD --> USB_P6
Disable VccSus2.5 VRM Mode USB BD --> USB_P0
R135
New Card --> USB_P3
4.7K Buletooh Card--> USB_P7
Z1614
+3.3VS

G
A Q36 A
2N7002
Reserved LINK_ALERT# R392 4.7K SMBCLK D S SB_SMB_CLK 7,13,17

SMBDATA D S SB_SMB_DATA 7,13,17 UNIWILL COMPUTER CORP.

+3.3V Q35
2N7002 Title
G

1:Normal
0:No Reboot Mode
ACZ_SPKR R420 4.7K_OP MX0/M40/50EI0
Size Document Number Rev
SB ICH-6M-2/3 C
3017
Date: Tuesday, August 09, 2005 Sheet 16 of 35
5 4 3 2 1
 5 4 3 2 1

U19E
B30
Z1701 AA22 F9
+1.5V VCC1_5[1] VCC1_5[98] +1.5V
AA23 VCC1_5[2] VCC1_5[97] U17
QT1608RL060 C445 C437 C440 C443 C439 AA24 U16 C426 C433 C432 C427 C425 C421 C446
VCC1_5[3] VCC1_5[96]
AA25 VCC1_5[4] VCC1_5[95] U14

4.7U_10V_0805

4.7U_10V_0805
0.1u 0.1u 0.1u AB25 U12 0.1u 0.1u 0.1u 0.1u 0.1u 4.7U_10V_0805 4.7U_10V_0805
VCC1_5[5] VCC1_5[94]
AB26 VCC1_5[6] VCC1_5[93] U11
AB27 VCC1_5[7] VCC1_5[92] T17
F25 VCC1_5[8] VCC1_5[91] T11
F26 P17
+5VREF +3.3V VCC1_5[9] VCC1_5[90] ICH6 PULLUPS

CORE
F27 VCC1_5[10] VCC1_5[89] P11
G22 VCC1_5[11] VCC1_5[88] M17
G23 VCC1_5[12] VCC1_5[87] M11
G24 L17
A
D R237 VCC1_5[13] VCC1_5[86] +3.3VS D
G25 VCC1_5[14] VCC1_5[85] L16
D21 H21 L14
VCC1_5[15] VCC1_5[84] R143 10K
H22 VCC1_5[16] VCC1_5[83] L12 16,18,23 PM_RI#
J21 L11 R394 10K
VCC1_5[17] VCC1_5[82] 16 SMB_ALERT#
10 BAT54 J22 AA21 R397 10K
VCC1_5[18] VCC1_5[81] 16 SMLINK0
C

K21 AA20 R407 10K

VCC1_5[19] VCC1_5[80] 16 SMLINK1
VCC5REF K22 AA19
VCC1_5[20] VCC1_5[79]
L21 VCC1_5[21]
L22 VCC1_5[22] VCC3_3[21] AA10 +3.3V
C459 C428 M21 AG19 +3.3V
VCC1_5[23] VCC3_3[20] C245 C450
M22 VCC1_5[24] VCC3_3[19] AG16
1u_6.3V 0.1u N21 AG13 R414 8.2K
VCC1_5[25] VCC3_3[18] 16,18,21,22,23 PCI_FRAME#
N22 AD17 0.1u 0.1u R232 8.2K
VCC1_5[26] VCC3_3[17] 16,18,21,22,23 PCI_IRDY#

PCIE

IDE
N23 AC15 R157 8.2K
VCC1_5[27] VCC3_3[16] 16,18,21,22,23 PCI_TRDY#
N24 AA17 R163 8.2K
VCC1_5[28] VCC3_3[15] 16,18,21,22,23 PCI_STOP#
N25 AA15 R418 8.2K
VCC1_5[29] VCC3_3[14] 16,21,22,23 PCI_SERR#
P21 AA14 R220 8.2K
VCC1_5[30] VCC3_3[13] 16,18,21,22,23 PCI_DEVSEL#
P25 AA12 R191 8.2K
+5VS +3.3VS VCC1_5[31] VCC3_3[12] 16,18,21,22,23 PCI_PERR#
P26 R436 8.2K
VCC1_5[32] Z1708 16 PCI_LOCK#
P27 P1 B56 R413 8.2K
VCC1_5[33] VCC3_3[11] +3.3V 16,22 PCI_REQ#0
R21 M7 QT1608RL060 R219 8.2K
VCC1_5[34] VCC3_3[10] 16,18 PCI_REQ#1
R22 L7 C447 C431 C430 R412 8.2K
VCC1_5[35] VCC3_3[9] 16,21 PCI_REQ#2
T21 L4 Modify in RB R218 8.2K
A

VCC1_5[36] VCC3_3[8] 16,23 PCI_REQ#3

T22 J7 0.1u 0.1u 0.1u R423 8.2K
VCC1_5[37] VCC3_3[7] 16 PCI_REQ#4

PCI
R188 D19 U21 H7 R426 8.2K
VCC1_5[38] VCC3_3[6] 16 PCI_REQ#5
U22 H1 R231 8.2K
VCC1_5[39] VCC3_3[5] 16 PCI_REQ#6
V21 E4 R144 8.2K
VCC1_5[40] VCC3_3[4] +1.5VS 16,18 INT_PIRQA#
10 BAT54 V22 B1 R153 8.2K
VCC1_5[41] VCC3_3[3] 16,23 INT_PIRQB#
C

W21 A6 R148 8.2K

V5REF_SUS VCC1_5[42] VCC3_3[2] 16,22 INT_PIRQC#
W22 R154 8.2K
+1.5V VCC1_5[43] 16,21 INT_PIRQD#
Y21 U7 R437 8.2K
VCC1_5[44] VCCSUS1_5[3] 16,18 INT_PIRQE#
Y22 R7 R431 8.2K
C VCC1_5[45] VCCSUS1_5[2] 16,23 INT_PIRQF# C
C456 C238 C435 C438 C436 R441 8.2K
16 INT_PIRQG#
AA6 R411 8.2K
VCC1_5[46] 16 INT_PIRQH#
1u_6.3V 0.1u 0.1u 0.1u 0.1u R382 8.2K

USB
AB4 VCC1_5[47] VCCSUS1_5[1] G19 16,21,22,23 PM_CLKRUN#
C448 C449 AB5 R187 8.2K
VCC1_5[48] 16,18,21,22,23 PCI_PAR
AB6 G20 R395 10K
VCC1_5[49] VCC1_5[78] +1.5V 16,18,24 INT_SERIRQ
0.1u 0.1u_OP AC4 F20 C458 C455 R419 8.2K
VCC1_5[50] VCC1_5[77] 16,24 PM_THROTTING#

USB CORE
AD4 E24 R390 10K
VCC1_5[51] VCC1_5[76] 15,24 H_RCIN#
AE4 E23 0.1u 0.1u R137 10K
VCC1_5[52] VCC1_5[75] 7,13,16 SB_SMB_CLK
AE5 E22 R136 10K
VCC1_5[53] VCC1_5[74] 7,13,16 SB_SMB_DATA
AF5 VCC1_5[54] VCC1_5[73] E21
+1.5V +1.5V AG5 E20
B9 VCC1_5[55] VCC1_5[72]
VCC1_5[71] D27
AA7 D26 +3.3VS
QT1608RL060 VCC1_5[56] VCC1_5[70]
AA8 VCC1_5[57] VCC1_5[69] D25
C172 C179 C452 AA9 D24
VCC1_5[58] VCC1_5[68] R406 8.2K
AB8 VCC1_5[59] 16,18,21,22,23,24 PCI_RST#
SATA
4.7U_10V_0805 0.01u 0.1u AC8 G8 R400 8.2K
VCC1_5[60] VCC1_5[67] +1.5V 9,16,20,24 PLT_RST#
AD8 R399 10K
VCC1_5[61] 16 SUS_CLK
AE8 AB18 R425 0 R405 680
VCC1_5[62] VCC2_5[4] +2.5V_SYSTEM +1.5V 16,18 PCIE_WAKE#
C441 R141 10K
PCI/IDE
AE9 VCC1_5[63] VCC2_5[2] P7 16 PM_BATLOW#
AF9 C457 R402 4.7K
VCC1_5[64] 16,20,21,24 PM_SLP_S3#
0.1u R408 4.7K
REF

AG9 VCC1_5[65] 16,24 PM_SLP_S4#

+3.3V AA18 0.1u
Z1702 V5REF[2] VCC5REF
AC27 VCCDMIPLL V5REF[1] A8
E26 VCC3_3[1]
F21 V5REF_SUS
R126 0 Z1703 V5REF_SUS
+1.5V AE1 VCCSATAPLL
C444 AG10 A25 Z1704
C194 VCC3_3[22] VCCUSBPLL
VCCSUS3_3[20] A24 +3.3VS PM_CLKRUN# need to test
0.1u A13 C260 by VER:A.
0.1u_OP VCCLAN3_3/VCCSUS3_3[1]
F14 VCCLAN3_3/VCCSUS3_3[2] VCCRTC AB3
G13 +1.5V 0.1u
B VCCLAN3_3/VCCSUS3_3[3] B
G14 VCCLAN3_3/VCCSUS3_3[4]
+3.3V G11 PM_CLKRUN# R468 10K_OP
VCCLAN1_5/VCCSUS1_5[2] C451 R140 10K
A11 VCCSUS3_3[1]VCCLAN1_5/VCCSUS1_5[1] G10 16,24 PM_RSMRST#
U4 R387 10K
VCCSUS3_3[2] +1.05V 16,24 PWROK
V1 AG23 0.1u
VCCSUS3_3[3] V_CPU_IO[3] +3.3VA_RTC
C453 Modify M30 in RB. V7 AD26
VCCSUS3_3[4] V_CPU_IO[2] C196 C198
W2 VCCSUS3_3[5] V_CPU_IO[1] AB22
0.1u Y7 C424
B57 Z1705 VCCSUS3_3[6] 0.1u 0.1u
+3.3V VCCSUS3_3[19] G16
QT1608RL060 A17 G15 0.1u
C222 C429 VCCSUS3_3[7] VCCSUS3_3[18]
B17 VCCSUS3_3[8] VCCSUS3_3[17] F16
C17 VCCSUS3_3[9] VCCSUS3_3[16] F15
0.1u 0.1u F18 E16
VCCSUS3_3[10] VCCSUS3_3[15]
G17 VCCSUS3_3[11] VCCSUS3_3[14] D16
G18 VCCSUS3_3[12] VCCSUS3_3[13] C16

ICH-6_M
+3.3VS
+3.3VS

C454 C434 C261

0.1u 0.1u 0.1u

AG22
AG20
AG17
AG14
AG12

AD24

AD18
AD15
AD10

AC26
AC24
AC23
AC22
AC12
AC10
AE25
AE21

AE12
AE11
AE10

AB19
AB10

AA16
AA13
AA11
AF26
AF12
AF10
AG7
AG3

AG1

AD6

AD2

AD1
AC6
AC3
AE7
AE6

AE2

AB9
AB7
AB2

AB1
AA4
D22
D20
D18
D14
D13
D10

C22
C20
C18
C14

AF7
AF3

AF1
E25
E19
E18
E15
E14

B25
B24
B23
B21
B19
B15
B13

A26
A23
A21
A19
A15
A12
F22
F19
F17

D7

D1
C4

A9
A7
A4

A1
F4

A U19A A
VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]
VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]

ICH-6_M

VSS
VSS[172]
VSS[171]
VSS[170]
VSS[169]
VSS[168]
VSS[167]
VSS[166]
VSS[165]
VSS[164]
VSS[163]
VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[157]
VSS[156]
VSS[155]
VSS[154]
VSS[153]
VSS[152]
VSS[151]
VSS[150]
VSS[149]
VSS[148]
VSS[147]
VSS[146]
VSS[145]
VSS[144]
VSS[143]
VSS[142]
VSS[141]
VSS[140]
VSS[139]
VSS[138]
VSS[137]
VSS[136]
VSS[135]
VSS[134]
VSS[133]
VSS[132]
VSS[131]
VSS[130]
VSS[129]
VSS[128]
VSS[127]
VSS[126]
VSS[125]
VSS[124]
VSS[123]
VSS[122]
VSS[121]
VSS[120]
VSS[119]
VSS[118]
VSS[117]
VSS[116]
VSS[115]
VSS[114]
VSS[113]
VSS[112]
VSS[111]
VSS[110]
VSS[109]
VSS[108]
VSS[107]
VSS[106]
VSS[105]
VSS[104]
VSS[103]
VSS[102]
VSS[101]
VSS[100]
VSS[99]
VSS[98]
VSS[97]
VSS[96]
VSS[95]
VSS[94]
VSS[93]
VSS[92]
VSS[91]
VSS[90]
VSS[89]
VSS[88]
VSS[87]

UNIWILL COMPUTER CORP.

Title
W25
W24
W23

M27
M26
M23
M16
M15
M14
M13
M12

G21
G12
U25
U24
U23
U15
U13

R25
R24
R23
R17
R16
R15
R14
R13
R12
R11

N17
N16
N15
N14
N13
N12
N11

H27
H26
H23
E27

Y27
Y26
Y23

V27
V26
V23

P22
P16
P15
P14
P13
P12

K27
K26
K23
T27
T26
T23
T16
T15
T14
T13
T12

L25
L24
L23
L15
L13

J25
J24
J23

MX0/M40/50EI0
W7

W1

M4

G9
G7

G1
R4

N7

N1
Y6

V4

K7

K1
T7

T1

J4

Size Document Number Rev

SB ICH-6M-3/3 C
3017
Date: Tuesday, August 09, 2005 Sheet 17 of 35
5 4 3 2 1
 5 4 3 2 1

MIC CON
CON18
INTMIC CON100
1 INTMIC 23 16,21,22,23 PCI_AD[0..31] CLKRUN# Pull-Low in PCMCIA Board. CON101
INTMIC_GND PCI_AD21 1
2 INTMIC_GND 23 1
PCI_AD20 2 1
2 16,17,21,22,23 PCI_TRDY# 1
MIC_CONN PCI_AD19 3 2
3 16,17,21,22,23 PCI_STOP# 2
PCI_AD18 4 3
4 16,17,21,22,23 PCI_PAR 3
PCI_AD17 5 4
5 16,17,21,22,23 PCI_PERR# 4
PCI_AD16 6 5
BLUETOOH CONN PCI_AD15 7
6
7
16,17 PCI_REQ#1
16 PCI_GNT#1 6
5
6
PCI_AD14 8 7
8 16,17,21,22,23,24 PCI_RST# 7
PCI_AD13 9 8
D +5V 9 16,21,22,23 PCI_PME# 8 D
PCI_AD12 10 9
10 23 CARD_SPK 9
PCI_AD11 11 10
11 16,17,23 PM_RI# 10
PCI_AD10 12 11
12 16,17,24 INT_SERIRQ 11
R245 0_0603_OP PCI_AD9 13 R489 0_OP Z1808 12
USB_7- 23 13 16,17 INT_PIRQA# 12
PCI_AD8 14 R490 0_OP PCI_AD31 13
14 16,17 INT_PIRQE# 13
CON20 R246 0_0603_OP PCI_AD7 15 PCI_AD30 14
USB_7+ 23 15 14
PCI_AD6 16 PCI_AD29 15
1 PCI_AD5 16 PCI_AD28 15
2 USB_P7- 16 17 17 16 16
PCI_AD4 18 PCI_AD27 17
3 USB_P7+ 16 18 17
PCI_AD3 19 PCI_AD26 18
4 PCI_AD2 19 PCI_AD25 18
5 BLUETOOTH_OFF# 23,24 20 20 19 19
PCI_AD1 21 PCI_AD24 20
BLUETOOH_CONN_OP PCI_AD0 21 PCI_AD23 20
16,21,22,23 PCI_C/BE#[0..3] 22 22 21 21
PCI_C/BE#3 23 PCI_AD22 22
PCI_C/BE#2 23 22
24 24 16,21,22,23 PCI_AD[0..31] 23 23
PCI_C/BE#1 25 24
PCI_C/BE#0 25 24
26 26 +3.3V 25 25
27 27 26 26
28 27
DC IN 16,17,21,22,23 PCI_DEVSEL#
16,17,21,22,23 PCI_FRAME# 29
28
29
C283
+5V 28
27
28
16,17,21,22,23 PCI_IRDY# 30 30 +12VS 29 29
31 GND1 0.1u_OP 30
MB_DC_IN VIN 31 GND1 C282 C281 30
7 PCICLK_PCM 32 32 GND2 GND2 31 31 GND1 GND1
32 32 GND2 GND2
CON1 D2 SK34A_SMA CARD BUS-1_OP 0.1u_OP 0.1u_OP
A C CARD BUS-2_OP
1
2 Modify M30 in R:B
3 Modify M30 in R:B
D1 SK34A_SMA
4
C
5 A C C

6
DC CONN B1 D27
Z1809 A C CHG_VCC NEW CARD
QT2012RL030HC_3A_0805 +3.3VS_PCIE
SK34A_SMA

+3.3VA
R708
+3.3V_PCIE +3.3VS_PCIE +1.5V_PCIE +1.5V
D

+1.5V_PCIE +3.3VS +3.3VS_PCIE +3.3V +3.3V_PCIE 100k

R67 Q10
Z1801 G 2N7002 C800 C801 C802
MB_DC_IN
CPPE# R700 0 Z1802
S

100K 0.1u 0.1u 0.1u R701 0 R702 0 R703 0

ADAP_IN 24,27 CPUSB# R704 0

R68 R69

100K 100K

CON200
B B
CPU FAN CONTROL +5V U35B Z1813 1
3
2
4 USB_P3- 16
5 CPUSB#
16 USB_P3+ 5 6
7 7 8
6 9 10
Modify 1 in RC.
R66
11 12 +1.5V_PCIE
16,17 PCIE_WAKE# 13 14 +3.3VS_PCIE
10K LM358 R811 0 PREST#
24 EC_PREST# 15 16 +3.3V_PCIE
Q73 A1797 CON10
0~5VZ1807 +3.3V_PCIE 17 18
E C 24 CPPE# CPPE#
+5V Z1810 3 19 20 Z1814 CLK_PCIE_NEW_CARD# 7
2 7 CLK_PCIE_NEW_CARD 21 22
+5V 1 16 PCIE_RXN0 23 24 PCIE_RXP0 16
R319 C327 C72 Modify 1 in RC. 25 26 PCIE_TXN0 16
B

R317 CPU FAN_CON 16 PCIE_TXP0

4.7U_10V_0805 0.1u_OP PIN NC1~2=GND POWER 27 28
1K Z1803 29 30
NEWCARD_FPC_CON
C337 5.11K_1
R618 10K
R320 0.1u U35A
+3.3V
8

LM358
1k 3 Z1805 B103 B104
FAN_SPD# 24
Z1804 1
D

QT1608RL600 QT1608RL600
2
R318 Q102
G 2N7002
10K_1 Modify M30 in R:B
4

C350

A 0.1u A

R321
Modify M30 in R:B
Z1806 FAN_CTRL0
FAN_CTRL0 24
0~3.3V
100K
R322
UNIWILL COMPUTER CORP.
Title
100K MX0/M40/50EI0
Size Document Number Rev
DC IN / CARD BUS / FAN / MIC / BLUETOOH C

Date: Tuesday, August 09, 2005 Sheet 18 of 35

5 4 3 2 1
 5 4 3 2 1

S3

16 USB_P2-
CON16
1 2
Z1909
POLY SW_1206

+5V
CON14
LCD LCDVCC +3.3V

16 USB_P2+ 3 4 21 TRL0+ 1 2 Modify 4 in

CON12
5 6 21 TRL0- 3 4 R:C.
9 TV_DAC_B 7 8 5 6 1 2
9 TV_DAC_C 9 10 TPA0+ 22 21 TRL1+ 7 8 TRL3+ 21 3 4 LB_DATA2- 9
11 12 TPA0- 22 21 TRL1- 9 10 TRL2+ 21 9 LB_CLK- 5 6 LB_DATA2+ 9
Z1910 R631 0
16 USB_P4- 13 14 9 LB_CLK+ 7 8 +3.3V
LAN CONN
16 USB_P4+ 15 16 TPB0+ 22 PIN NC3~4=GND POWER 9 10 LA_DATA1- 9
17 18 TPB0- 22 9 LA_DATA0- 11 12 LA_DATA1+ 9
9 LA_DATA0+ 13 14 LCDSEL0# R16 47K
D 15 16 LA_DATA2- 9 D
IO BD CONN LCDSEL1# R13 47K
PIN NC3~4=GND POWER 9 LA_CLK- 17 18 LA_DATA2+ 9
Modify 4 in R:A. LCDSEL2# R19 47K
9 LA_CLK+ 19 20
21 22 LB_DATA0- 9
9 LB_DATA1- 23 24 LB_DATA0+ 9
13" IO BD:USB , TV , 1394 Modify 2 in R:C. 9 LB_DATA1+ 25 26 LCDSEL2# 16
14" IO BD:USB*2 , TV , 1394 16 LCDSEL1# EDID_CLK 27 28 EDID_DATA LCDSEL0# 16
S5 0_1206 R675 0_0603 29 30
+5V
LCD_CON C920 Modify 4 in
Q78 0.1U R:C.
SI2301DS_OP
S2 Z1907 S D
+5VA
POLY SW_1206_OP Modify 5 in R:C.
Modify M30 in
PANNEL SELECT

G
Modify 4 in R393 100K_OP R:B. +3.3V
Z1903 LCDSEL2# LCDSEL1# LCDSEL0#
R:A. +2.5V_SYSTEM +3.3V
CON17
L L L 1024X768

D
USB_POWER R602
Q34 1
2 L L H 1400X1050
G 4.7K
24 USB5VA_ON 3
2N7002_OP L H L 1280X800
4

S
USB0- R606 R607 Z1908 R603 R604
USB0+ 5
6 L H H 1280X768
10K 10K 10K 10K

G
7 Q79
C
8 H L L reserved C
C412 2N7002
S D EDID_CLK H L H 1680X1050
9 LDDC_CLK
R129 R128 0.1U USB BD CONN
Modify 3 in R:C. H H L 1920X1200
S D EDID_DATA
9 LDDC_DATA
0 0 H H H 1440X900
U15 +5V Q80
2N7002

G
USB_P0_ON# 1 8
USB_P0- BE1# VCC
16 USB_P0- 2 A1 BE2# 7 USB_P0_ON# USB_P0_ON# 24
USB0- 3 6 USB0+
B1 B2
4 GND A2 5 USB_P0+ USB_P0+ 16
C202

0.1U
SN74CBT3306PWR_OP
VIN_LCD

INVERTER CON13
1 2
D9
Modify 6 in R:C.

R54 100 R60 100 A2 BLTADJ C41 0.1U

Z1901 3 4 Z1902 BL_ON
24 BLTADJ 5 6 +3.3V C
Q9
B6 7 8 BL_ON C47 0.1U
9 10 A1
S D VCC3_LCD
B +3.3V LCDVCC B
QT2012RL030HC_3A_0805 INV CONN BAT54C_OP

R62 SI2301DS R51 C36 C712

G

47K 1K 0.1u 220P_OP

Z1905
D

Q76 +3.3V
R61 300K Z1906 G
9 EN_LCD
2N7002
S

C65
R272
0.1u
D33 BAS16 10K

C A BL_ON
24 LCD_SW

D34 BAS16

9 EN_BL C A

D
Q66
R273 100K_OP
Z1904 G 2N7002_OP
+3.3V

S
A A
B25

D
Q67
VIN VIN_LCD
QT2012RL030HC_3A_0805 C343 C349 G 2N7002_OP
UNIWILL COMPUTER CORP.

S
0.1u_25V_0603_OP 0.01u_25V_0603
R266
Title
100K_OP
Size Document Number
MX0/M40/50EI0 Rev
Modify M30 in R:B. LCD/INVERTOR/CRT/TV C
3017
Date: Tuesday, August 09, 2005 Sheet 19 of 35
5 4 3 2 1
 5 4 3 2 1

V_SATA3V V_HDD V_DVD V_DVD

CON32 CON11
CDAUDIOL CDAUDIOR
SATA_TXP0_HDD S1 CDAGND 1 2
15 SATA_TXP0_HDD SATA_TXN0_HDD S2 DVD_RST# 3 4
R432 0 SDD8
15 SATA_TXN0_HDD S3 9,16,17,24 PLT_RST# SDD7 5 6 SDD9
SATA_RXN0_HDD S4 SDD6 7 8 SDD10
15 SATA_RXN0_HDD SATA_RXP0_HDD S5 SDD5 9 10 SDD11
15 SATA_RXP0_HDD S6 SDD4 11 12 SDD12
S7 SDD3 13 14 SDD13
SDD2 15 16 SDD14
P1 SDD1 17 18 SDD15
D D
P2 SDD0 19 20 SDDREQ
P3 21 22 SDIOR# SDDREQ 15
P4 SDIOW# 23 24 SDIOR# 15
P5 15 SDIOW# SDIORDY 25 26 SDDACK#
C604
P6 15 SDIORDY SDIRQ15 27 28 SDDACK# 15
P7 15 SDIRQ15 SDA1 29 30 DVD_PDIAG
1U
P8 15 SDA1 SDA0 31 32 SDA2
P9 15 SDA0 SDCS1# 33 34 SDCS3# SDA2 15
P10 15 SDCS1# DVD_ACT# 35 36 SDCS3# 15
P11 37 38 R23
Modify 7 in R:C. P12 39 40
P13 41 42
P14 43 44 10K
P15 45 46

GND1
GND2
R50 470 CSEL2
47 48
GND1 C22 49 50 C31
GND2
SATA_CON 4.7U_10V_080 5 DVD_CON 10U_16V_1206

R209 10K for Marvell

B32 0_0805
R209 2.2K for Acard ARC770
+3.3V CSEL : Master = 0 / Slave = 1
Marvell V_SATA3V +3.3V
B31 0_0805
T0=OPEN(INT PD) R380 4.7K SDIORDY
T1=OPEN(INT PD) V_HDD +5V
T2=OPEN(INT PD) SDD[0..15] 15
B18 0_0805
C T3=1 R193 4.7K DRDY C
T4=OPEN(INT PD) V_DVD
+1.8V_SYSTEM T5=0 R451
R224 10K for Marvell T6=OPEN(INT PD) R396 10K SDIRQ15 CDAUDIOR CD_R
+3.3V_SATA CD_R 23
R224 2.2L for Acard ARC770
CONFIG0=OPEN(INT PD) CONFIG0=OPEN(INT PD) 0
CONFIG1=0 CONFIG1=0
R224 CONFIG2=OPEN(INT PD) CONFIG2=OPEN(INT PD) R455 C461

+3.3V +3.3V_SATA +3.3V 22K_1_OP 100P_OP

10K The following system configuration is assumed: CNF 2 1 0
B59 1. SSC is disabled (T2=0) R467
TP75TP76
T6

T2
T1

2. 25MHz reference clock (T[4:3]=01b)

Defult 0 0 0 100MB/s CDAGND CD_GND
3. No fixed UDMA mode (T5=0) CD_GND 23
DCS0#
DCS1#

QT1608RL060 4. Disable power management (T6=0) 0 0 1 133MB/s 0

C703 R7
Z2003
Z2004

Z2005

0 1 0 150MB/s
0.1u R462 C462
Device UDMA 150 0_OP
22K_1_OP 100P_OP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

U21
R458
CS0n
CS1n
PDIAGn

PHYRDY/T7
PMEN/T6
FXDMA/T5
CLKSEL1/T4
CLKSEL0/T3
SSCEN/T2
DASPn/T1
MSSEL/T0
UAI
DGND
UAO
VCCO

VCCK

AGND and DGND connect in IC internal design. CONFIG2 R657 10K_OP CDAUDIOL CD_L
+3.3V CD_L 23
SATA_RXP0 R658 5.6K_OP 0
SATA_RXN0 R659 5.6K_OP
DSA2 49 32 SATA_RXP0 +5V
DSA0 DA2 TX_P SATA_RXN0 SATA_RXP0 15
50 31 SATA_RXN0 15
R252 R249
DSA1 H_DA0 TX_M SATA_AGND A0 5.6K-S 5.6K-S
51 30
DA1 AGND AVDDL_SATA A3 OPEN OPEN
52 29
DIRQ SPn AVDDL/VAA3.3V SATA_TXN0
53 28 SATA_TXN0 15 R213
B DACK# INTRQ RX_M SATA_TXP0 B
54
DMACKn RX_P 27 SATA_TXP0 15 Modify M30 in RB. Q54
DRDY 55 26 I_SET R427 12.1K R660 10K_OP 10K
IORDY REXT +3.3V
56 25 SATA_AGND D25 BAS16
+1.8V_SYSTEM VCCK AGND AVDDH_SATA 2N7002
57
DGND AVDDH/VAA3.3V 24 Modify 8 in RC.
DIOR# CLKO
DIOW#
58
59
DIORn 88SA8040 XTALO/ISET 23
22 CLKI PRST# C743 0.1u
DVD_ACT# C A Z2001 S D MB_IDE_ACT# 23
DDRQ DIOWn XTALI/OSCI
60 21 D22 BAS16_OP
DD15 DMARQ ATAIOEN CONFIG2
61 20
DD0 DD15 MODE2 CONFIG1 HDD_ACT#
62 19

G
DD0 MODE1 HDD_ACT# C A
DD14 63 18 CONFIG0 R610 10K_OP
DD1 DD14 MODE0 PRST# PLT_RST# +3.3V T1 PM_SLP_S3# 16,17,21,24
64 17 R662 0_OP R663 10K_OP
DD1 PORn PLT_RST# 9,16,17,24 +3.3V
R661 0
T2 R664 0_OP
PRST# 24 T6 R666 2.2K_OP
RESETn

CSEL1 R667 10K_OP Modify M30 in RB. +3.3V

+3.3V
DGND
VCCO

VCCK

HDD_PDIAG R668 10K_OP

DD13

DD12

DD11

DD10
DD2

DD3

DD4

DD5
DD9
DD6
DD8
DD7

+1.8V_SYSTEM DD7 R669 10K_OP

88SA8040 R197 330 for Marvell R809 R810

10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9

R197 0 for Acard ARC770

C244 R672 10K_OP CONFIG0 D60 BAS16 0_OP 10K Q110
DRST#

C705 C706 CLKO R197 330_OP Z2006

DD13

DD12

DD11

DD10

R421 0_OP CONFIG1 Z2007

DD2

DD3

DD4

DD5
DD9
DD6
DD8
DD7

15 SATA_LED# C A S D MB_IDE_ACT# 23
0.1u 0.1u 15p_OP For Acard
CL=12
Y3 R189 2N7002

G
AVDDH_SATA R221 QT1608RL060
+3.3V
1M_OP
PM_SLP_S3# 16,17,21,24
+3.3V_SATA 25MHz_SMT_OP C262 R709
+1.8V_SYSTEM C237
CLKI SATA_AGND 0.1u
A A
0
15p_OP
The following system configuration is assumed: CL=12 AVDDL_SATA B72 QT1608RL060_OP
+1.8V_SYSTEM
1. Spread Spectrum Clocking is disabled-->(T2=0) C744
R178 0_OP SATA_25MHZ
2. 25MHz reference clock (T[4:3]=01b) SATA_25MHZ 21
0.1u UNIWILL COMPUTER CORP.
NEAR CRYSTAL
3. No fixed UDMA mode (T5=0) Title

4. Disable power management (T6=0) MX0/M40/50EI0

DRST# R671 0_OP PLT_RST# R670 0_OP Size Document Number Rev
SATA HDD/CD-ROM C
For Acard 3017
Date: Tuesday, August 09, 2005 Sheet 20 of 35
5 4 3 2 1
 A B C D E

AVDD33_AV25_GLAN
+3.3V
VCC2.5_LAN
+2.5V_SYSTEM
+2.5V_SYSTEM
C188
C209 C230 C228 C187 C213 C233
0.1u
0.1u 0.1u 0.1u 0.1u 0.1u 4.7U_10V_0805_OP

107
12

32
54
78
99

20

26
41
56
71
84
94
3
7
U18

AVDD25/NC

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

AVDD33/AVDD25
AVDD33/AVDD25
AVDD33/AVDD25

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
PCI_AD31 33
4 16,18,22,23 PCI_AD[0:31] AD31 4
PCI_AD30 34 Differential Impedance:near 100 ohm.
PCI_AD29 AD30
36 AD29
B10 PCI_AD28 37
AVDD33_AV25_GLAN PCI_AD27 AD28 TP_TX+
+3.3V 39 AD27 TXD+/MDI[0]+ 1
PCI_AD26 40 2 TP_TX-
QT1608RL060 PCI_AD25 AD26 TXD-/MDI[0]-
42 AD25
C190 C189 PCI_AD24 43 5 TP_RX+
PCI_AD23 AD24 RXIN+/MDI[1]+ TP_RX-
47 AD23 RXIN-/MDI[1]- 6
0.1u 0.1u PCI_AD22 49
PCI_AD21 AD22
50 AD21
PCI_AD20 53
PCI_AD19 AD20
55 AD19
PCI_AD18 57
PCI_AD17 AD18 SEECS
58 AD17 EESEL 106
PCI_AD16 59 111 SEECLK
PCI_AD15 AD16 EECK SEEDI
79 AD15 AUX_EEDI 109
PCI_AD14 82 108 SEEDO
PCI_AD13 AD14 EEDO
83 AD13
PCI_AD12 85 31
AD12 PMEN PCI_PME# 16,18,22,23
PCI_AD11 86 75
Near RTL8100CL PCI_AD10 87
AD11 SERRN
30
PCI_SERR# 16,17,22,23
AD10 REQN INT_PIRQD# PCI_REQ#2 16,17
B11 PCI_AD9 89 25
VCC2.5_LAN AD9 INTAN INT_PIRQD# 16,17
PCI_AD8 90 29
+2.5V_SYSTEM AD8 GNTN PCI_GNT#2 16
QT1608RL060 PCI_AD7 93 AD7
C232 C231 C229 C206 C193 PCI_AD6 95 AD6 ISOLATEB# 23 ISOLATEB R120 1K
PM_SLP_S3# 16,17,20,24
PCI_AD5 96 105
1u_6.3V 0.1u 0.1u 0.1u 0.1u PCI_AD4 AD5 LWAKE
97 AD4
PCI_AD3 98 117
PCI_AD2 AD3 LED0
102 AD2 LED1 115
3 PCI_AD1 103 114 3
PCI_AD0 AD1 LED2
104 AD0
NC1/VSS 9
PCI_C/BE#0 92 10
16,18,22,23 PCI_C/BE#[0:3] CBEN0 NC2/AVDD33
PCI_C/BE#1 77 11
PCI_C/BE#2 CBEN1 NC3
60 CBEN2 NC4/VSS 13
PCI_C/BE#3 44 14
CBEN3 NC5/MDI[2]+
NC6/MDI[2]- 15
7 PCICLK_LAN 28 PCICLK NC7/AVDD25 16
16,17,18,22,23,24 PCI_RST# 27 RSTN NC8/MDI[3]+ 18
NC9/MDI3]- 19
+3.3V 22
PCI_AD28 R132 100 Z2101 46 NC10/GND
IDSEL NC11/VDD18 24
16,17,18,22,23 PCI_PERR# 70 PERRN NC12/VDD18 45
16,17,18,22,23 PCI_PAR 76 PAR NC13/GND 48
16,17,18,22,23 PCI_STOP# 69 STOPN NC14 62
16,17,18,22,23 PCI_TRDY# 67 TRDYN NC15/VDD18 64
R409
EEPROM 16,17,18,22,23 PCI_FRAME#
16,17,18,22,23 PCI_DEVSEL#
61
68
FRAMEN NC16 72
73
10K +3.3V DEVSELN NC17/GND
16,17,18,22,23 PCI_IRDY# 63 IRDYN NC18 74
U17 88
SEECS NC19/M66EN
1 CS VCC 8 NC20/VDD18 110
SEECLK 2 7 C199 112
SEEDI SK NC NC21/GND
3 DI NC 6 NC22/LED3 113
SEEDO 4 5 0.1u R127 5.62K_1 Z2102 127 116
DO GND RTSET NC23/VDD18
NC24/GND 118
93C46 8 120
CTRL25 NC25/AVDD33
NC26/CTRL18 125
16,17,22,23 PM_CLKRUN# 65 CLKRUN NC27/VDD18 126
2 2

121 LAN_X1
X1

122 LAN_X2 R131 1M

X2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y2

RTL8100CL_LQFP

100
101
119
123
124
128
17
21
35
38
51
52
66
80
81
91
C200 25MHz_SMT C205

4
Near Transformer Modify M30 in R:B1.
22P 22P
C183
Z2103 As short as possible.
PT1 TRL0+
TRL0- TRL0+ 19
0.1u
TRL0- 19
R124 R123 1 16
TX+ TD+ TRL1+ 19 +3.3V
2 TX- TD- 15 TRL1- 19
49.9_1 49.9_1 Z2105 3 14 TRL_CT0 TRL2+
CT CT TRL3+ TRL2+ 19
TRL3+ 19
All close to LAN, and test to
C195
TP_TX+ Z2106 6 11 TRL_CT1 replacement SATA to PATA IC
TP_TX- CT CT
7 RX+ RD+ 10 crystal. 0.1u
8 RX- RD- 9

5
TP_RX+ U13
TP_RX- R75 R72 R74 R73 R116 22
NS681690 Z2108 4 2
20 SATA_25MHZ
1 75 75 75 75 1

R122 R121 C117 C116 Z2107 C185 74AHC14_1G

3
49.9_1 49.9_1 0.1u 0.1u C88 10P
C184
Z2104 150P_3KV_1808
Uniwill International Corp.
0.1u Title

Near IC MX0/M40/50EI0
Size Document Number Rev
LAN 10/100 C
3017
Date: Tuesday, August 09, 2005 Sheet 21 of 35
A B C D E
 5 4 3 2 1

B12 B17
1394_PVCC3 1394_AVCC3
+3.3V +3.3V +3.3V
QT1608RL060 C254 QT1608RL060 C287 C272 C295 C296 C253 C266 C294 C252 C288

B13 0.1u B14 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
1394_PGND 1394_AGND
D D
QT1608RL060 QT1608RL060

Close to Pin 59,62,64,65

+3.3V

1394_AVCC3

1394_PVCC3 C250 22P

100

120
108
107
88
72
59
51
39
27
15

78
62
48
35
20

2
1

7
U24 Y5

VDDP
VDDP
VDDP
VDDP
VDDP
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD

AVDD
AVDD
AVDD
AVDD
AVDD

PLLVDD
24.576MHz_SMT
5 1394_XIN
XI C249 22P
6 1394_XOUT
16,18,21,23 PCI_AD[0..31] XO
PCI_AD0 84 PCI_AD0
PCI_AD1 82 PCI_AD1 R1 119 Z2203
PCI_AD2 81 R475 6.34K_1 Close to pin
PCI_AD2
PCI_AD3 80 PCI_AD3 R0 118 Z2204
PCI_AD4 79
PCI_AD5 PCI_AD4 Z2205
77 3
PCI_AD6 76
PCI_AD5 TSB43AB22A FILTER0 C285
PCI_AD7 PCI_AD6 C255 1394_AGND
74 PCI_AD7
PCI_AD8 71
PCI_AD9 PCI_AD8 0.1U 1u_6.3V
C 70 PCI_AD9
C
PCI_AD10 69 4 Z2206 R249 R254
PCI_AD11 PCI_AD10 FILTER1
67 PCI_AD11
PCI_AD12 66 56.2_1 56.2_1
PCI_AD13 PCI_AD12 TPBIAS0
65 PCI_AD13 TPBIAS0 116
PCI_AD14 63 115 TPA0+
PCI_AD14 TPA0+ TPA0- TPA0+ 19
PCI_AD15 61 114
PCI_AD15 TPA0- TPB0+ TPA0- 19
PCI_AD16 46 113
PCI_AD16 TPB0+ TPB0- TPB0+ 19
PCI_AD17 45 112
PCI_AD17 TPB0- TPB0- 19
PCI_AD18 43 PCI_AD18 TPBIAS1 125 Z2207 C269 0.1U
PCI_AD19 42 124
PCI_AD20 PCI_AD19 TPA1+
41 PCI_AD20 TPA1- 123
PCI_AD21 40 PCI_AD21 TPB1+ 122 Z2208 R466 1K R265 R269
PCI_AD22 38 PCI_AD22 TPB1- 121 Z2209 R473 1K
PCI_AD23 37 56.2_1 56.2_1
PCI_AD24 PCI_AD23
32 PCI_AD24 PC0 99
PCI_AD25 31 98 Z2210
PCI_AD26 PCI_AD25 PC1
29 PCI_AD26 PC2 97
PCI_AD27 28
PCI_AD28 PCI_AD27
26 PCI_AD28 TEST0 105
PCI_AD29 25 104 C286 R267
PCI_AD30 PCI_AD29 TEST1
24 PCI_AD30 TEST2 102
PCI_AD31 22 101 220P 5.11K_1
PCI_AD31 TEST3
16,18,21,23 PCI_C/BE#[0..3] TEST8 95
PCI_C/BE#0 73 94 1394_AGND
PCI_C/BE#1 PCI_CBE0# TEST9
60 PCI_CBE1#
PCI_C/BE#2 47
PCI_C/BE#3 PCI_CBE2#
34 PCI_CBE3#

B 16,17,18,21,23 PCI_PAR 58 PCI_PAR CPS 106 Z2211 R482 390K 1394_AVCC3

B
16,17,18,21,23 PCI_FRAME# 49 PCI_FRAME#
50 87 Z2212 R277 4.7K
16,17,18,21,23 PCI_IRDY# PCI_IRDY# CYCLEIN Z2213 +3.3V
16,17,18,21,23 PCI_TRDY# 52 PCI_TRDY# CYCLEOUT 86
16,17,18,21,23 PCI_DEVSEL# 53 PCI_DEVSEL#
54 11 Z2214 R463 10K +3.3V +3.3V
16,17,18,21,23 PCI_STOP# PCI_STOP# TEST16
PCI_AD26 R243 100 Z2201 36 10 Z2215 R459 10K
PCI_IDSEL TEST17
19 96 Z2216 8 1
16,17 PCI_REQ#0 PCI_REQ# CNA
18 7 2 R487 R488
16 PCI_GNT#0 PCI_GNT# Z2217
16,17,18,21,23 PCI_PERR# 56 PCI_PERR# GPIO3 89 6 3
57 90 Z2218 5 4 10K 10K U26
16,17,21,23 PCI_SERR# PCI_SERR# GPIO2 RP16 10KX4_0805
16 92 Z2219 5 4
7 PCICLK_1394 PCI_CLK SDA Z2220 SDATA GND
16,17,21,23 PM_CLKRUN# 12 PCI_CLKRUN# SCL 91 6 SCLK A2 3
Z2221 7 2
Z2222 WP A1
14 G_RST# REG18 30 Modify M30 in +3.3V 8 VCC A0 1
85 93 Z2223
16,17,18,21,23,24 PCI_RST#
21
PCI_RST# REG18 R:B1. R486
16,18,21,23 PCI_PME# PCI_PME#
13 9 AT24C02
16,17 INT_PIRQC# PCI_INTA# REG_EN C619 C618 300
PLLGND

0.1U 0.1U
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND

AGND
AGND
AGND
AGND
ANGD
AGND
AGND
103

109
110
111
117
126
127
128
17
23
33
44
55
64
68
75
83

1394_PGND

A 1394_AGND A

Uniwill International Corp.

Title

MX0/M40/50EI0
Size Document Number Rev
1394 C
3017
Date: Tuesday, August 09, 2005 Sheet 22 of 35
5 4 3 2 1
 5 4 3 2 1

PCI_AD[0..31] +5V +3.3V +3.3V_MINI

MINI PCI CON +3.3V_MINI +3.3V_MINI

PCI_C/BE#[0..3]
PCI_AD[0..31]

PCI_C/BE#[0..3]
16,18,21,22

16,18,21,22
B60
QT1608RL060
CON21 C275 C290 C291 C468 C257 C292 C293 C467
1 2
TIP RING 1u_6.3V 1u_6.3V 0.1u 1u_6.3V 0.1u 0.1u 0.1u 0.1u
3 LAN REV LAN REV
4 Modify M30
5 6
7
LAN REV LAN REV
8
in RB.
LAN REV LAN REV
9 10
LAN REV LAN REV
11 12
LAN REV LAN_REV
24 RF_PWR_OFF# 13 14
LAN REV LAN_REV
15 16
CHGGND LAN_REV
17 18
D
16,17 INT_PIRQB#

18 USB_7-
19
21
INTB#
VCC3
REV
VCC5
INTA#
REV
20
22
+5V
INT_PIRQF# 16,17
USB_7+ 18
AUDIO CONN 24 CHG_R#
R820
R821
180_OP
220_OP
AD_CHG_R#
AD_SCROLL#
CON6

40
D

23 GND 24 +3.3V_MINI 24 EC_SCROLL#

+3.3VAUX PCI_RST# R822 180_OP AD_CHG_G# 39
7 PCICLK_MINIPCI 25 CLK 26 PCI_RST# 16,17,18,21,22,24 24 CHG_G#
RST# 38
27 GND 28 24 LID#
VCC3 R823 220_OP AD_NUM# 37
16,17 PCI_REQ#3 29 REQ# 30 PCI_GNT#3 16 24 EC_NUM#
GNT# R824 220_OP AD_SILENT_LED# 36
31 VCC3 GND
32 Modify 8 in RA.24 EC_SILENT_LED# 35
PCI_AD31 33 34 PCI_PME# R825 220_OP AD_CAPS#
AD31 PME# PCI_PME# 16,18,21,22 24 EC_CAPS# AD_RFLED_ON# 34
PCI_AD29 35 36 R826 220_OP
AD29 REV PCI_AD30 24 EC_RFLED_ON# AD_PWR_LED# 33
37 38 R827 220_OP
GND AD30 24 EC_PWR_LED# 32
PCI_AD27 39 40
AD27 VCC3 PCI_AD28 24 AMP_MUTE# AD_IDE_ACT# 31
PCI_AD25 41 42 R828 220_OP
AD25 AD28 PCI_AD26 20 MB_IDE_ACT# 30
43 44 24 RF_OFF#
PCI_C/BE#3 REV AD26 PCI_AD24 29
45 46 20 CD_R
PCI_AD23 C/BE3# AD24 Z2301 R275 100 PCI_AD19 28
47 48 20 CD_GND
AD23 IDSEL 27
49 50 20 CD_L
PCI_AD21 GND GND PCI_AD22 26
51 52 15 ACZ_SDATAIN1
PCI_AD19 AD21 AD22 PCI_AD20 25
53 54 15 ACZ_SDATAIN0
AD19 AD20 PCI_PAR 24
55 56 PCI_PAR 16,17,18,21,22 15 ACZ_SDATAOUT
PCI_AD17 GND PAR PCI_AD18 23
57 58 15 ACZ_RST#
PCI_C/BE#2 AD17 AD18 PCI_AD16 R815 22
59 60 15 ACZ_SYNC
PCI_IRDY# C/BE2# AD16 Z2309 21
16,17,18,21,22 PCI_IRDY# 61 62 15 ACZ_BITCLK
IRDY# GND PCI_FRAME# Del Pin19 CODEC_14MHZ for EMI 6/29 20
63 64 PCI_FRAME# 16,17,18,21,22
PM_CLKRUN# VCC3 FRAME# PCI_TRDY# FCM1005M-220T00 19
16,17,21,22 PM_CLKRUN# 65 66 PCI_TRDY# 16,17,18,21,22 +12VS
PCI_SERR# CLKRUN# TRDY# PCI_STOP# B61 18
16,17,21,22 PCI_SERR# 67
SERR# STOP#
68 PCI_STOP# 16,17,18,21,22 Modify 12 in RC. 18 INTMIC 17
69 70 Z2308
PCI_PERR# GND VCC3 PCI_DEVSEL# 18 INTMIC_GND 16
71 72 QT1608RL060
16,17,18,21,22 PCI_PERR# PERR# DEVSEL# PCI_DEVSEL# 16,17,18,21,22 +5V_AUX_P 15
PCI_C/BE#1 73 74
PCI_AD14 C/BE1# GND PCI_AD15 14
75 76
AD14 AD15 PCI_AD13 PC_BEEP 13
77 78
PCI_AD12 GND AD13 PCI_AD11 12
79 80 +3.3V
C PCI_AD10 AD12 AD11 11 C
81 82
AD10 GND PCI_AD9 10
83 84 16 USB_P1+
PCI_AD8 GND AD09 PCI_C/BE#0 9
85
AD08 C/BE0#
86 Modify 5 in R:A. 16 USB_P1- 8
PCI_AD7 87 88
AD07 VCC3 PCI_AD6 7
89 90 +5V
PCI_AD5 VCC3 AD06 PCI_AD4 R800 10K 6
91 92 18 CARD_SPK
AD05 AD04 PCI_AD2 BAS16 5
18,24 BLUETOOTH_OFF# 93 94
PCI_AD3 REV AD02 PCI_AD0 4
95 96
AD03 AD00 R801 10K Z2303 PC_BEEP 3
+5V 97 98 24 BTL_BEEP A C 16 USB_P5+
PCI_AD1 VCC5 REV 2
99 100 16 USB_P5-
AD01 REV D53 1
101 102
GND GND Z2302 R274 10K R802 10K R480 C464
103 104 16 ACZ_SPKR
AC_SYNC M66EN C714 C715 C716 FPC_LED_CONN
105 106
AC_SDATA_IN1 AC_SDATA_OUT 10K 0.1u_OP
107 108
AC_BIT_CLK AC_CODEC_ID0 0.1U 0.1U 0.1U Modify 3 in R:B
109 110
AC_CODEC_ID1 AC_RESET#
111 112
MOD_AUDIO_MON REV
113 114
AUDIO_GND GND
115 116
SYS_AUDIO_OUT SYS_AUDIO_IN
117
SYS_AUDIO_OUT GND SYS_AUDIO_IN GND
118 Modify 13 in RC.
119 120
AUDIO_GND AUDIO_GND
16,17,18 PM_RI# 121 122
NC MCPIACT#
+5V 123
+5VA
MINI-PCI
+3.3VAUX
124 +3.3V_MINI
SWITCH CONN
PIN 129~130=GND POWER +3.3V +3.3VA

C29 0.1u CON2

C28 0.1u 1
1
2
R226 47K VL 2
3
B CRT CON +3.3VA
24 EC_INSTANT_ON#
24 EC_ADAP_I MB_PWRON# 4
5
3
4
5
B

24 EC_SILNET_ON# 6
R271 220 SW_RFLED_ON# 6
24 PWR_SW_ON 24 EC_RFLED_ON# 7
+3.3V +5V R239 R214 220 SW_IDE_ACT# 7
20 MB_IDE_ACT# 8
R270 220 SW_SILENT_LED# 8
Modify 9 in RC. 10K 24 EC_SILENT_LED# 9
9
R238 47K R276 180 SW_CHG_R# 10

D
24 CHG_R# SW_CHG_G# 10
Q51 R260 180 11
A

VL 24 CHG_G# SW_PWR_LED# 11
Modify 11 in RC. R257 220 12
+3.3V MB_PWRON# 24 EC_PWR_LED# SW_CAPS# 12
BAT54 Modify 9 in RC. G R268 220 13
27 1632_OFF# 24 EC_CAPS# SW_NUM# 13
D8 R263 220 14
24 EC_NUM# SW_SCROLL# 14

S
2N7002 R233 220 15

D
24 EC_SCROLL# 15
U100 Q50 16
16
5
C

TC7SH08FU R 17
Z2304 Z2305 G 17
+2.5V_SYSTEM 9 CRT_VSYNC 1 G 18
VSYNC B 18
4 19
19

S
2 2N7002 20

D
Design guind is U101 Q48 20
21
21
5

R47 R44 Q8 R46 R45 TC7SH08FU HS 22

2.2K ohm. VS 22
3.01K_1 3.01K_1
3

1 G 23
G

9 CRT_HSYNC 23
4.7K 4.7K 4 HSYNC 24
24

S
2 2N7002 25
DDC_DATA 16 MB_USB6+ 25
9 CRT_DATA S D Modify M30 in R:B. 16 MB_USB6- 26
26
C26 0.1u 27

D
2N7002 Q55 27
3

+5V 28
DDC_CLK 28
9 CRT_CLK S D 29
SW_BTLED_ON # 29
G Z2306 R225 47K_OP
+3.3VA 24 BT_LED_ON#
R605 30
Q7 D_DATA 30
31 GND1
D_CLK 31 GND1
2N7002 S 2N7002 R808 0
FPWRON 24 Modify 8 in RA. 220_OP 32 GND2
32 GND2
G

Modify 9 in CRT CONN

A Modify 11 in RC. RA. Modify 5 in R:B A
Modify 10 in RC.

MB_CRT_R C938 10P Modify 7 in

DDC_DATA B110 QT1608RL120 D_DATA
MB_CRT_G C939 10P RA. DDC_CLK B111 QT1608RL120 D_CLK
UNIWILL COMPUTER CORP.
+3.3V MB_CRT_B C940 10P Modify in
HSYNC B70 QT1608RL120 HS Title
RB. VSYNC B71 QT1608RL120 VS
9 MB_CRT_R
MB_CRT_R B62 QT1608RL120 R MX0/M40/50EI0
MB_CRT_G B63 QT1608RL120 G Size Document Number Rev
9 MB_CRT_G MB_CRT_B B
B64 QT1608RL120 MINI PCI / AUDIO CON / CRT CONN C
9 MB_CRT_B
3017
Date: Tuesday, August 09, 2005 Sheet 23 of 35
5 4 3 2 1
 5 4 3 2 1

+3.3VA
K/B CONTROLLER +3.3V +3.3VA +3.3VA +3.3VA +3.3V +3.3V
B16 BAT_SMBCLK R223 4.7K
Z2404 BAT_SMBDAT R222 4.7K
QT1608RL060 EC_INSTANT_ON# R442 100K
C280 C277 C278 R208
C224 C279 C221 C259 C271
0.1u 0.1u 0.1u 4.7K R230 R240 Modify 11 in +5VA
0.1u 1u_6.3V 1u_6.3V 0.1u 0.1u
Z2410 10K 10K R:A. IR_CLK R195 4.7K_OP
IR_DATA R194 4.7K_OP

G
123
136
157
166

161
U41

16

34
45

95
Q49 Modify 10 in +5V
BAT2_SMBCLK D S 2N7002

VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY

VBAT
VCC

AVCC
D 15 LPC_AD[0..3] SMBCLK_EC 5,7 R:A. TP_CLK R205 4.7K D
LPC_AD3 10 TP_DATA R204 4.7K
LPC_AD2 LAD3 ROMA0 BAT2_SMBDAT

System & LPC Bus

13 LAD2 FA0 124 D S SMBDAT_EC 5,7
LPC_AD1 14 125 ROMA1 Modify in R:C.
LPC_AD0 LAD1 FA1 ROMA2 Q56
15 LAD0
Power Supply BADDR1/FA2 126
127 ROMA3 2N7002
BADDR0/FA3

G
7 128 ROMA4 +3.3V
16,17,18 INT_SERIRQ SERIRQ FA4
LPC_FRAME# 9 131 ROMA5
15 LPC_FRAME# LFRAME SHBM/FA5 +3.3V
18 132 ROMA6 LID# R416 4.7K
7 CLK_PCI_LPC LPCCLK FA6 A20GATE
LRST1# 19 133 ROMA7 Modify M30 in R256 4.7K_OP
WRST FA7 ROMA8 RCIN# R255 4.7K_OP
FA8 143 R:B.
23 142 ROMA9 EC_EXTSMI# R422 4.7K
16 EC_EXTSMI# PWUREQ FA9 RF_OFF#
22 135 ROMA10 R613 R251 100K
D35 BAT54 ECSMI FA10 ROMA11 +3.3V BLUETOOTH_OFF#R247 100K
134

Flash Interface
FA11 ROMA12 10K EC_SILNET_ON# R634 100K
15 H_A20GATE A C 31 GPD3/ECSCI FA12 130
A20GATE 5 GPO 129 ROMA13
D36 BAT54 RCIN# GPB5/GA20 FA13 ROMA14 TP_BT C212 10P_0603_OP
6 GPB6/KBRST FA14 121
A C 120 ROMA15 R146
15,17 H_RCIN# FA15 7 CLK_BSEL0
113 ROMA16

D
KEYIN0 FA16 ROMA17 47K TP_DATA C415 10P_0603_OP
71 KSI0 FA17 112
KEYIN1 72 104 ROMA18 Q82
KEYIN2 KSI1 FA18 Z2405 EC_CPU_BSEL0#
Diode to 73 KSI2 FA19 103 TP77 G 2N7002
KEYIN3 74 TP_CLK C416 10P_0603_OP
prevent for KSI3

S
KEYIN4 77 138 ROMD0

C
KEYIN5 KSI4 FD0 ROMD1 00=PSB400(BSEL1=0)
EC leakage 78 139 Modify 12 in
KEYIN6 79
KSI5
IT8510E FD1
140 ROMD2 R95 47K Z2412 B Q19 01=PSB533(BSEL0=1) EC_ADAP_I R162 4.7K
KB Matrix Interface

voltage. KEYIN7 80
KSI6 FD2
141 ROMD3
5,7 CPU_BSEL0 R:A.
KSI7 FD3 ROMD4 2N3904
FD4 144

E
KEY_0 ROMD5 01=PSB400(BSEL0=1)
KEY_1
49
50
KSO0 Embedded FD5 145
146 ROMD6 00=PSB533(BSEL1=0)
KEY_2 KSO1 FD6 ROMD7 R261 10K
KEY_3
51
52
KSO2 Controller FD7 147 +5VA
C KEY_4 KSO3 ROMCS# R262 10K C
53 KSO4 FCS 173
KEY_5 56 150 ROMRD#
KEY_6 KSO5 FRD ROMWR#
57 KSO6 FWR 151 23 CHG_R#
KEY_7 58

D
KEY_8 KSO7 Q63
59
KEY_9 60
KSO8
KSO9 DA0 99 BLTADJ 19
TOCHPAD CONNECTOR
KEY_10 61 100 +5V CHGLED_R G
KSO10 OUT DA1 CHG_I 28
KEY_11 64 101 FAN_CTRL0 2N7002
KSO11 DA2 Z2417 FAN_CTRL0 18

S
KEY_12 65 102 Del in RC 7/20 CON5
KSO12 DA3 TP101
KEY_13 66
KEY_14 KSO13 Z2406 6
67 KSO14 ADC8/ANOTE 93 TP78 5 23 CHG_G#
KEY_15 68 GPI 94 Z2407 C700 C701

D
KSO15 ADC9/CATHODE TP79 4 Q62
0.1U_0603_OP 0.01u TP_DATA 3
ADC0 81 BATT_TEMP 28 2
110 82 EC_ADAP_I TP_CLK CHGLED_G G
23 RF_OFF# PS2CLK0/GPCF0 IN ADC1 EC_ADAP_I 23 1
111 83 2N7002
23 EC_SILNET_ON# PS2DAT0/GPCF1 ADC2 DDR2_TEMP 13

S
114 84 T/P_CONN
IR_CLK PS2CLK1/GPCF2 ADC3 SB_TEMP 15
IR_DATA 115 PS2DAT1/GPCF3 Modify M30 in R:B for
TP_CLK 116 GPIO 87 Z2408 R401 4.7K
TP_DATA 117
PS2CLK2/GPCF4 ADC4/GPE0
88 EC_CPU_BSEL0# ESD. Modify M30 in
PS2DAT2/GPCF5 GPI ADC5/GPE1 Z2419
Z2418 ROMA5 R476 4.7K
ADC6/GPE2 89 TP83 R:B. +3.3VA
Modify 8 in RA. EC_GPIO 118 90 Z2416

C
GPCF6/PS2CLK3 ADC7/GPE3 TP100
119 D63
23 EC_RFLED_ON# GPCF7/PS2DAT3
2 PWR_SW_ON
PWRSW/GPE4 PWR_SW_ON 23
148 44 LID# Modify M30 in R:B.
23 EC_SCROLL# GPI0 GPI WUI5/GPE5 LID# 23
149 24 BAT54
23
23
EC_CAPS#
EC_NUM# 152
GPI1
GPI2 GPIO
LPCPD/WUI6/GPE6
CLKRUN/WUI7/GPE7 25 PM_SLP_S3# EC_INSTANT_ON# 23
PM_SLP_S3# 16,17,20,21
KEYBOARD CONNECTOR

A
CHGLED_R 155 LRST1# R446 100K
GPI3 CON3 +3.3VA
CHGLED_G 156 26
GPI4 WUI0/GPD0 EC_REMOTE_ON ADAP_IN 18,27
168 GPIO 29 24 KEY_15 C460
23 EC_PWR_LED# GPI5 WUI1/GPD1 Z2411 24
174 GPO 30 R424 0_OP 23 KEY_14 D64 BAT54_OP
23 RF_PWR_OFF# GPI6 WUI4/GPD2 PCI_RST# 16,17,18,21,22,23 23
R428 0 22 KEY_13 0.1u A C
B PM_SLP_S4# PLT_RST# 9,16,17,20 22 B
48 41 21 KEY_12
26 +1.8V_DDR_ON GPH0 IOPD4 PM_SLP_S4# 16,17 21
+1.8V_ON 54 42 20 KEY_11
26,29 +1.8V_ON GPH1 GPIO GINT/IOPD5 PM_THROTTING# 16,17 20
55 62 19 KEY_10 Modify 13 in R:A.
30 +1.05VS_ON GPH2 TACH0/GPD6 FAN_SPD# 18 19
+3.3VS_ON 69 GPIO 63 BLUETOOTH_OFF# 18 KEY_9
29 +3.3VS_ON GPH3 TACH1/GPD7 BLUETOOTH_OFF# 18,23 18
+5V_ON 70 Modify in DDR2 17 KEY_8
27,29 +5V_ON GPH4 17
75 32 16 KEY_7
28
26
SET_V
+1.5VS_ON 76
GPH5
GPH6
GPA0/PWM0
GPA1/PWM1 33
BTL_BEEP 23
EC_VID1 14
16
15 15 KEY_6 FLASH ROM
105 36 14 KEY_5
25 VCORE_ON GPH7 GPO GPA2/PWM2 EC_VID2 14 14 ROMA18
37 R258 13 KEYIN0
CPPE# GPIO GPA3/PWM3 EC_VID3 14 EC_REMOTE_ON 13 +5VA
KEYIN1

32
18 CPPE# 3 GPG4 GPA4/PWM4 38 EC_VID4 14 +3.3VA 12 12

1
4 39 11 KEYIN2 U39
19 LCD_SW AMP_MUTE# GPG5 GPIO GPA5/PWM5 SMP1_EN# 14 11
27 40 47K_OP 10 KEYIN3

VPP

VCC
23 AMP_MUTE# GPG6/LPC80HL GPA6/PWM6 SMP2_EN# 14 10
28 43 9 KEY_4 ROMA0 12

D
9 EXTTS#0 GPG7/LPCGPG7 GPA7/PWM7 PWRBTN# 16 9 A0
Q64 8 KEY_3 ROMA1 11
8 KEYIN4 ROMA2 A1
14 CELERON_VO_DET 153 GPB0/URXD 7 7 10 A2
154 G 6 KEYIN5 ROMA3 9 13 ROMD0
18 EC_PREST# GPB1/UTXD REMOTE_ON# 6 A3 DQ0
162 GPO 47 5 KEYIN6 ROMA4 8 14 ROMD1
16,17 PM_RSMRST# GPB2 CLOCKOUT/GPC0 PWROK 16,17 5 A4 DQ1
169 BAT2_SMBCLK

S
163 GPIO 2N7002_OP 4 KEYIN7 ROMA5 7 15 ROMD2
28 BAT_SMBCLK SMCLK0/GPB3 GPC1/SMCLK1 BAT2_SMBCLK 4 A5 DQ2
28 BAT_SMBDAT 164 SMDAT0/GPB4 GPC2/SMDAT1 170 BAT2_SMBDAT BAT2_SMBDAT 3 3 KEY_2 ROMA6 6 A6 DQ3 17 ROMD3
171 2 KEY_1 ROMA7 5 18 ROMD4
GPC3 USB5VA_ON 19 2 A7 DQ4
165 GPIO 172 1 KEY_0 ROMA8 27 19 ROMD5
23 BT_LED_ON# GPB7 WUI2/GPC4 USB_P0_ON# 19 1 A8 DQ5
175 ROMA9 26 20 ROMD6
GPC5 FPWRON 23 A9 DQ6
Modify 8 in RA. 176 Modify 11 in R:A. ROMA10 23 21 ROMD7
32KI WUI3/GPC6 CHG_ON 28 A10 DQ7
158 1 KEYBOARD_CON ROMA11 25
CK32K CLKOUT/GPC7 EC_SILENT_LED# 23 A11
ROMA12 4 A12
LPCPROG

R229 ROMA13 28
32KO ROMA14 A13
160 CK32KE 29 A14
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7

+3.3VA ROMA15 3
ID A15
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

20M_OP (ID2) (ID1) (ID0) ROMA16 2

R244 ROMA17 A16
NUM# CAPS# SCROLL# MODEL 30 A17
IT8510E
122
159
167
137

106
107
108
109
17
35
46

96

11
12
20
21
85
86
91
92
97
98

0 0 0 0 223 ROMCS#
8

22 CE# GND 16
A Y6 R248 R253 R252 ROMRD# 24 A
Z2403 ROMWR# OE#
1 2 0 0 1 245 31 WE#
270K_OP 270K 270K
32.768KHz_DIP 0 1 0 255 28F020
PIN 3=GND POWER EC_SCROLL#
EC_CAPS# 0 1 1 259
C267 C274 EC_NUM#
1
UNIWILL COMPUTER CORP.
0 0 770
10p 10p
R715 0_OP R241 R264 1 0 1 XXX Title
PRST# 20
EC_GPIO Modify 14 in RC. 270K 270K_OP 1 1 0 M30EI0
Size Document Number
MX0/M40/50EI0 Rev
1 1 1 XXX C
3017 EC IT8510E / BIOS / TP & Keyboard CONN
Date: Tuesday, August 09, 2005 Sheet 24 of 35
5 4 3 2 1
 5 4 3 2 1

R360 +5V
JP5 CLOSE 10 Modify M30 in RB.
Z2518
2 1 A_GND
C165 C182 C177 B102

4.7U_10V_0805 4.7U_10V_0805 4.7U_10V_0805 QT2012RL500HC_3A_1206

B101
CPU_CORECPU_CORE QT2012RL500HC_3A_1206
B100

A
D13
D VIN_CPU D
HCB4516K-600T60_6A_1806_OP
R608 R356 BAT54
332_1_OP 332_1

C
R80
Z2501 Z2506 1 2 VIN
Modify M30 in
10mR/F/1W_2512_OP
R:B.

5
6
7
8

5
6
7
8
C146 R355 R105 C128 C119 C127 + C414
100K_1_OP Q77 Q12

D
6800p_0603 1 RSS090N03 RSS090N03 0.1u_25V_0603 4.7U_25V_1210_OP 4.7U_25V_1210 10U_25V_ELE_DIP
C180 C176 4 4
Z2519

G
0.22u_25V_0603 0.22u_25V_0603

17

28

3
U9

S
BST
CORE

V5_1
Z2507 CPU_CORE

3
2
1

3
2
1
21 VCCA TG 2
L4 R350
0.6uH_25A
9 1 Z2508 1 2 1 2
14 PM_VID5 VID5 DRN
10 1.5mR/F/2W_2512
14 PM_VID4 VID4

5
6
7
8

5
6
7
8
27 Z2509

C
BG Q11 Q16 R83

D
14 PM_VID3 11 VID3 SI4362 SI4362 D10 0
12 26 4 4 SK34A_SMA C181 + C118 C115 C114+ C359+ C360 + C361+ C347
14 PM_VID2 VID2 PGND Z2517

G
C126

220U_2V_POS

4.7U_10V_0805

220U_2V_POS

220U_2V_POS

220U_2V_POS_OP

220U_2V_POS_OP
C143 C140 4.7U_10V_0805_OP 0.1u

S
14 PM_VID1 13 VID1

A
2200P_OP 2200P_OP
Z2510 1000p

3
2
1

3
2
1
14 PM_VID0 14 VID0 CL 24

C C

16 VR_PWRGD 16 PWRGD
23 Z2511
CMP
Z2502 6 R370 931_1
PBOOT
Modify M30 in RB.
25 22 R369 619_1 Z2520
24 VCORE_ON ENPAD CLRF
Modify 7 in R:B.
Z2503 5 Z2512 R367 931_1
VDPR
Modify M30 in RB.
4 20 Z2513 R358 931_1
16 PM_DPRSLPVR DPRSL CMPRF

7 VTT_PWRGD# 7 CLK_ENABLE# R357 C168 C173 C151 C175

Z2504 8 18 Z2514
C609 R368 HYS DAC 330p 330p 330p 330p
Z2505 15 C147 825_1
0.1U 22K R359 R97 SS
GND

1000p Modify 7 in R:B.

38.3K_1 301K_1 C139
Cap. for EMI SC451 Modify M30 in RB.
19

0.022u_16V R354

51.1K_1
C166 R362

1000p 34.8K_1 +5V

Z2515

B B
R86
C169 R361

D
22K Q15
1000p 57.6K_1
Z2516 G 2N7002

S
D

Q14

G 2N7002
7,16 PM_STPCPU#
S

D Q13

PM_DPRSLPVR G 2N7002
S

H3 H4 H17 H21 H9 H22 H13 H8 H12 H19 H7 H25 H6 H5 H11 H10 H15 H14 H16 H20 H18 H1 H2 H24 H23
C315D174 C315D174 C237D107 C315D107-1 C315D107 C315D107 C315D107 C197D107 C100B210D60 C100B210D60 C100B210D60 C100B210D60 C100B210D60 C315D158 C315D158 C315D158 C315D158 C197D87 C197D87 C197D87 C197D87 C158D158 C158D158 C158D158 C158D158

A A

M26 M12 M5 M11 M8 M24 M7 M25 M6 M22 M18 M20 M13 M21 M3 M23 M4 M9 M19 M10 M27 M1 M17 M15 M16 M14 M28 M2
M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1
UNIWILL COMPUTER CORP.
Title

MX0/M40/50EI0
Size Document Number Rev
CPU_CORE C
3017
Date: Tuesday, August 09, 2005 Sheet 25 of 35
5 4 3 2 1
 5 4 3 2 1

R346 R347 JP12 JP13 JP14 JP15 BLOCK1

VIN
Modify 8 in R:B.
Modify 8 in R:B. DDR1(2.5V) 1K_1 1.82K_1 Open Open Short Open Non-OP
R324
R323 2.2_0603
+5VS DDR2(1.8V) 10K_1 10K_1 Open Short Open Short OP
2.2_0603

Z2601

C364 C365 C411

A
U38

A
C4 U3 1u_6.3V D29 ISL6227 1u_6.3V 1u_6.3V +1.8VS_DDR +1.8V_DDR

8
7
6
5
+1.5VS RSS090N03 D31
4.7U_25V_1210 BAT54 C125 Modify 10 in RB.

D
D D
1 GND VCC 28

5
6
7
8
C
4 BAT54 U5 4.7U_25V_1210
Z2602 27 Z2614

C
RSS090N03 B65 HCB4516K-600T60_6A_1806_O P

D
G
2 LGATE1 LGATE2
Modify 30 in R:B.

S
JP1 OPEN_5A 3 26 4
PGND1 PGND2

G
L3 Modify 30 in R:B. Modify 14 in R:C.

1
2
3
2 VOUT1 Z2603 25 Z2619 JP4 3A

S
1 4 PHASE1 PHASE2
4.7UH_6A JP12
Z2604 24 Z2620 Modify 30 in R:B. L1 4.7UH_6A OPEN_1A_OP

3
2
1
5 UGATE1 UGATE2 1 2

8
7
6
5
U4 1 2

C
Z2605 +2.5V_SYSTEM
D6 RSS090N03 0.1u_25V_X7R_0603 C363 6 23 Z2621 C396 0.1u_25V_X7R_0603

D
BOOT1 BOOT2

5
6
7
8
C6 U40 R850 U7 JP13
+ C335 Z2606 22 Z2622 RSS090N03 OPEN_1A_OP

D
4 7 AO4422_OP

C
1000p SK14A_SMA C20 R330 1.05K_1 ISEN1 ISEN2 R339 1.5K_1 D32 0 C394 + C417

G
8 1 1 2 +1.8V_SYSTEM
560U_4V_OSC_DIP_L

R326 8 21 Z2623 4 7 2

S
EN1 EN2

G
A

C354 6800P 1u_6.3V 560U_4V_OSC 6 3 +12VS

VOUT1 +1.8VS_DDR C418

S
1
2
3
9 VOUT1 VOUT2 20 5 S
1000p Modify 30 in R:B. C420 D
Z2608 19 Z2624

A
6.8K_1 1000p G

3
2
1
10 VSEN1 VSEN2 0.01U SK14A_SMA C404 R347
Z2609 18 Z2625 R91 R94

4
11 OCSET1 OCSET2 1000p 10K_1
Z2610 12 17 Z2626 Modify 30 in R:B. 100K 100K
SOFT1 SOFT2
Modify 30 in R:B.
13 16 Z2630 R351 22K_OP 1.8V_ON_HV
DDR PG2/REF C397 C392 R338
R325 C362 Z2611 14 15

D
VIN PG1 0.1u 0.068u 75K_1 Q18
10K_1 22p_OP C136
R329 C356 C393 R346 G +1.8V_ON#
0.1u_OP

D
24 +1.5VS_ON

S
0.01u C366 22p_OP 10K_1 2N7002 Q17
Modify 14 in 75K_1 Vo=0.9*(R1+R2)/R2
0.1u_25V_0603 G
R:A. Modify 30 in R:B.
+1.8V_ON 24,29

S
R236 1K 2N7002
C 24,29 +1.8V_ON C

R348 1K_OP
24 +1.8V_DDR_ON
1.8V_ON_HV 29
C395

0.1u_OP

DDR Termination Power

+3.3VS
+1.8V_DDR +3.3V
+5VS

U8
U32 1 5
C329 VIN VCNTL C130
1 VIN VCNTL 5 VCNTL 6
6 C149 7
C330 VCNTL 1u_6.3V R93 Z2628 VCNTL 1u_6.3V
VCNTL 7 3 REFEN VCNTL 8
R302 3 8 1u_6.3V
1u_6.3V REFEN VCNTL 100K_1
2.4K_1 2 4
GND OUTPUT +0.9V_DDR
2 GND OUTPUT 4 +2.5VS_SYSTEM
B Z2616 RT9173B B
RT9173B C402 C145
C325 C148 R92
C333 4.7U_10V_0805 4.7U_10V_0805
R301 4.7U_10V_0805 1u_6.3V 100K_1
1u_6.3V
7.5K_1

Modify 30 in R:B.

BLOCK1
+3.3V

+5V

U60
1 5 C602
VIN VCNTL
VCNTL 6
C600 7 1u_6.3V
R600 VCNTL
3 REFEN VCNTL 8
1u_6.3V
6.25K_1
2 GND OUTPUT 4 +1.8V_SYSTEM
A Z2627 A
RT9173B
C603
C601
R601 4.7U_10V_0805
1u_6.3V
7.5K_1

UNIWILL COMPUTER CORP.

Title
Modify 30 in R:B.
MX0/M40/50EI0
Size Document Number Rev
1.05V/1.5V/1.8V/2.5V/0.9V C
3017
Date: Tuesday, August 09, 2005 Sheet 26 of 35
5 4 3 2 1
 A B C D E

JP11 OPEN_3A
1 2 MAX1632 shutdown current : 4~10uA ( SHDN# pin = low )
THERMAL SOLUTION 1:
MAX1632 standby power : 2.5mW ~ 4mW USE CPUHOT# TO IMPLEMENT H/W THROTTLING AND SHUT DOWN.
B29 QT4532KL080HC_8A_1812_OP
+3.3VA EC READ TEMPRATURE AND CONTROL FAN.
VIN
C442 C728 C729 C730 Modify M30 in R:B. THERMAL SOLUTION 2:
1

JP6 1000p 4.7U_25V_X5R_1206 4.7U_25V_X5R_1206 4.7U_25V_X5R_1206 USE 1617 TO READ TEMPRATURE AND EC CONTROL FAN, THROTTLING AND SHUT DOWN.
CPU SHUT DOWN PIN IS FOR H/W PROTECT
R98
OPEN_5A_20X197R U16 U20
8mR/F/1W_2512_OP L5 RSS090N03 L6
2

4 RSS090N03 4
Z2701 1 2 Z2702 1 8 Z2703 8 1 2 1
L2* L1*
2 7 7 2
4.7UH_8A D14 3 6 C210 6 3

C
SK34A_SMA S 5 0.1u_25V_0603 C207 5 S 3 4
C

C
D15 D16 R803 D R101 R100 D D20 Z2714 L1 L2
C203 + C419 8mR/0.5W_1206 G 0.1u_25V_0603 G 10uH_1_2
1 2 220K_1 22_0603 +5VA
SK14A_SMA_OP

BAT54 1u_6.3V 560U_4V_OSC_DIP_L SK34A_SMA

4
Z2704 Z2715

A
R804
Z2705
A

A
8mR/0.5W_1206_OP R106 100
1 2
C167 Z2710

2
BAT54

BAT54
Modify M30 in R:B. JP8

C
Modify 15 in C171 R104 0.1u_25V_0603
23 1632_OFF#
R:A. 4.7U_16V_1206 330K C142 C164 U23 OPEN_5A_20X197R

5
6
7
8
D11

D12
C170 R250

1
D
1 2

A
0.22u_25V_0603 0.22u_25V_0603 4.7U_25V_1206 RSS090N03
4 8mR/F/1W_2512_OP

8
7
6
5
Z2706

G
Modify in R:B

C
U12 Z2711 R805 D23 D24

S
D
RSS090N03 VL 6mR/0.5W_1206 + C465 C265
Z2708 Z2712

3
2
1
4 1 2
Z2709 Z2713 390U_6.3V_DIP_L BAT54 SK14A_SMA_OP 1u_6.3V

G
C174 AUX_OFF# C264 R806

S
5 AUX_OFF#

A
R89 10K Modify M30 8mR/0.5W_1206_OP
4700P 2200P
1
2
3 in R:B. 1 2

28
27
26
25
24
23
22
21
20
19
18
17
16
15
3 C910 C178 3
U6 D17 Modify 15 in

#SHDN
V+

PGND
RUN/ON3
DH3
LX3
BST3
DL3

VL

DL5
BST5
LX5
DH5
SEQ
2.2U_X5R_0603

4.7U_10V_0805
Modify M30 BAS16
C A
R:A.
in R:B.

C121

4.7U_25V_1210

TIME/ON5
JP3

REF2.5V

#RESET
OPEN_1A Modify 6 in R:A.

12OUT

#SKIP
SYNC
CSH3

CSH5
CSL3

CSL5
1 2

GND
VDD
+12VA

FB3

FB5
SC1404

10
11
12
13
14
C141

1
2
3
4
5
6
7
8
9
4.7U_16V_1206 Z2716 Z2719
+3.3VA

Z2720 +5V_AUX_P
Z2717
R181
Z2718 ADAP_IN 18,24
Z2721 100_0603

C124 Z2707 Z2730

R81

D
100p C120 C123 C122 Q44
R82 100K +5V
2 2
1000p 1u_6.3V 100p VA_OFF G
100K 2N7002
VL

S
VL R212

MAX1632 SC1404 100_0603

R190
MAX1902
100K Z2722

D
C124 0 100pF
Q47 +5VA
VCC_OFF G
R82 100K_OP 100K 2N7002 VL

S
Q45 R227
C122 0 100pF 24,29 +5V_ON G Modify 11 in R:B.
2N7002 R228 100_0603

S
R98,R250 15mR,15mR 8mR,8mR 100K Z2731

D
Q52

Add in RC 7/12. VA_OFF G

2N7002

S
Q53
+12VS
+1.5VS +2.5V_SYSTEM +1.05V +1.8V_DDR +3.3VS +3.3V +5VS G
5 AUX_OFF#
2N7002 Modify 11 in R:B.

S
R851
1 R174 R182 R173 R155 R169 R199 R170 1
100_0603
100_0603 100_0603 100_0603 100_0603 100_0603 100_0603 100_0603
Z2725
Z2725 Z2726 Z2729 Z2734 Z2732 Z2724 Z2723
D

UNIWILL COMPUTER CORP.

D
D

D
Q200 Q38 Q40
VCC_OFF G Q43 Q42 Q41 Q46 Q39
2N7002 VCC_OFF G VCC_OFF G VCC_OFF G VCC_OFF G VCC_OFF G VCC_OFF G VCC_OFF G Title
2N7002
S

2N7002 2N7002 2N7002 2N7002 2N7002 2N7002

MX0/M40/50EI0

S
S

S
Size Document Number Rev
Modify 11 in Modify 11 in Modify 11 in C
R:B. 3017
+3.3VA/+5VA/+12VA
R:B. R:B. Date: Tuesday, August 09, 2005 Sheet 27 of 35
A B C D E
 5 4 3 2 1

Modify M30 in R:B.

MB_DC_IN
F1
Modify M30 in R:B. 1206/3A/32V
594_VCC_5V CHG_VCC_FUSE
CHG_VCC
C322
DTC R291 100K C299
R6 R4 R3 + C297

D
Q68 C309 4.7K 4.7K 10K
D D
0.1u_25V_X7R_0603 CON9

12

C
G 1u_6.3V U30 100U_25V_ELE_DIP
24 CHG_ON 1
2N7002 R292 B U28

VCC
2

3
2
1
S
100K_1 Q1 SI4835 0.1u_25V_X7R_0603 VBAT
Z2807 2N3904 Z2810 BAT_SMBCLK R280 100 BAT1C 3

S
14 REF C1 8 24 BAT_SMBCLK 4

E E
Z2801 1 Modify M30 in R:B. BAT_SMBDAT R281 100 BAT1D

G
1IN+ E1 9 4 24 BAT_SMBDAT 5
Z2802 2 11 VCHG
Z2816 Z2803 1IN- C2 6
E2 10 7
C319 0.01u R290 10K

D
3 FB B 8
Z2817 4 DTC Q2 BAT_TEMP
DTC 24 BATT_TEMP 9
C307 0.01u R287 10K Z2808 2N2907 L2 4.7UH_8A_PCMC063T Modify M30 in R:B.

5
6
7
8
16 2IN+ CT 5 10
Z2811

C
R293 Z2804 15 6 Z2809
2IN- RT GND1

OUT-CTRL
300K_1 C5

C
+ C298 GND2
SET_V :
R294 C321 4 Battery_CON

GND
"H"=12.71V
Z2805 10K_1 1000p D26 100U_25V_ELE_DIP 0.1u_25V_X7R_0603
D

"L"=16.84V Q37 TL594 SK34A_SMA R10

13

A
7
1 2
24 SET_V G
R286 40mR/F/1W_2512
S

2N7002 Z2806

C303 576_1 4

470P R8
220K_1 U29
Z2812
AO4422
C 8 1 C
R282 39K 7 2
24 CHG_I
6 3
CHG_I : R9 5 S
R283 16.2K_1 D
3.2V = 2.0A 1K_1 C304 G
0.1u
1.6V = 1.0A

4
0.4V = 0.1A
R285
100K_1

4 R289 200K
Z2813
VIN

D
R288
Q71
G 2N7002 560K
24 CHG_ON

S
Modify M30 in R:B.
B Modify for EMI B

B2 JP22 OPEN_3A
VBAT BAT1C C301 220P
1 2
QT4532KL080HC_8A_1812
BAT1D C302 220P

U1 SI4835_OP +3.3VA
VIN D3 C A SK34A_SMA Z2814 1 8 BAT_TEMP C300 220P
VCHG
2 7
U2 SI4835 3 6 R160
1 8 S 5
2 7 D
3 6 G
S 5 R279 100K
D
4

G BAT_TEMP
100K_1_OP
4

Z2815 R161
MB_DC_IN R284 330 Z2819
220K_1
D

Q70
R278 G CHG_ON 24
20K_1
S

2N7002_OP

A A

UNIWILL COMPUTER CORP.

Title

MX0/M40/50EI0
Size Document Number Rev
BATT IN / Charger C
3017
Date: Tuesday, August 09, 2005 Sheet 28 of 35
5 4 3 2 1
 5 4 3 2 1

@Modify resister for power on sequence.

+5VA +5V +12VS Q20 +12VA
U25 3LP01C
AO4422
8 1 +12VS D S
7 2
6 3
5 S R485 R483 R85

G
D Z2910
G 100K 100K
100K
Z2905 R484 0 5V_ON_HV

4
R84
D 5V_ON# D

D
C289 Q69 100K
Modify M30 in R:B. 0.1u_25V_X7R_0603
G Z2911
Modify M30 in R:B. 2N7002

D
+2.5VS_SYSTEM

S
Q65 Q21
Q72
SI2301DS JP14 G +5V_ON 24,27 G Z2912 R90 0
+3.3VS_ON 24
OPEN_1A 2N7002 2N7002
D Z2901

S
S 1 2 +2.5V_SYSTEM

R651
G

Q60
100K +5VA SI2301DS +5VS
Z2915
S D
D

Q106 +12VS
R654 0_OP +5VS Q59 +5VREF
Z2902 R303 +3.3VS_ON 24
G 22K 1.8V_ON_HV R653 SI2301DS
1.8V_ON_HV 26

G
?? A
S

2N7002 S D
C334 100K
0.1u_25V_X7R_0603 Z2916 R479 R474
100K 100K Replace 3LP01C by

G
Modify M30 in R:B. Q108 VER:A test ??
R235
G Z2906 R259 0 3VS_ON_HV Z2913
C Z2907 C

D
S
2N7002 Q61 10K
C276

D
0.1u_25V_X7R_0603 G Q58

D
Z2914

S
2N7002 Q57 G R234 0
+1.8V_ON 24,26
2N7002

S
G +3.3VS_ON 24
Modify M30 in R:B. C270

S
2N7002 0.1u_25V_X7R_0603_OP

Modify M30 in R:B.

+1.5VS U36 +1.5V
AO4422 +1.5V
8 1 JP31 OPEN_4A +3.3VA +3.3V
7 2 U14
6 3 1 2 +VGA_NB AO4422
5 S + C753 8 1
D 7 2
G 220U_2V_POS_OP 6 3
5 S Modify 15 in R:C.
Z2903 R331 22K 1.8V_ON_HV D
4

G
C357 BAT54 D70

4
0.1u_25V_X7R_0603_OP A C +12VS
Modify M30 in R:B.
B B
Z2908 R391 10K 5V_ON_HV

C197
0.1u_25V_X7R_0603

Modify M30 in R:B.

+1.05VS U31 +1.05V

For EMI Test
AO4422 +3.3VS
8 1 +3.3VA
7 2 R674 0_0805 U11 C610 0.1u
6 3 +1.05V AO4422 +3.3V +3.3VS
5 S 8 1
D Modify in R:B 7 2
G 6 3 C611 0.1u
JP30 OPEN_4A 5 S Modify 15 in R:C. +5V +3.3V
D
4

1 2 G
+VGA_NB
BAT54 D71 C612 0.1u
4

+3.3V
A C +12VS
Z2904 R296 22K 1.8V_ON_HV C613 0.1u

Z2909 R386 3VS_ON_HV +5V

C326 56K
A A
0.1u_25V_X7R_0603
C192
Modify M30 in R:B. 0.1u_25V_X7R_0603

Modify M30 in R:B.

UNIWILL COMPUTER CORP.
Title
M30EI0
Size Document Number Rev
CustomMX0/M40/50EI0 VCC SW/+1.05VS/+1.5VS C
3017
Date: Tuesday, August 09, 2005 Sheet 29 of 35
5 4 3 2 1
 5 4 3 2 1

+5VS

R635
100K

D 824_ON D

D
R636 Q103
+1.05VS_ON_DELAY 825K Z3001 G 2N7002

S
C731

1U

AGND

D
+5VS
AGND Q104
FBVDD_PG G 2N7002

S
R621
AGND
100K

AGND

NVDD_PG
VIN +5VS

33
U62

GNDA
29 28
AGND CS2N CS2P
R638 30 27
C R637 SLEW2 PWRGD2 C
1K 31 26 VIN
SKIP2 LX2
22_0603 32 25
VSET2 HDR2
AGND 1 24
ON2 BST2 +5VS
Z3002 3 23 C732 C718
VIN GNDP2
VREF 4 22
VREF LDR2 0.1u_25V_X7R_0603 4.7U_25V_X5R_1210
5 20 D51

A
GNDA VDDP1 BAT54
Z3003 6 19 Z3010 C720
VDDA LDR1

2
1
824_ON 7 18 1u_25V_X7R_0603 Q105A
CE GNDP1
+1.05VS

C
R649 0 +1.05VS_ON_DELAY 8 17 Z3006 0_0603
24 +1.05VS_ON ON1 BST1 R626 Z3011 8
Z3004 9 16 Z3007 SP8K10S_FD5
C740 VSET1 HDR1 C721
Z3008 1u_25V_0805 L7 JP17 OPEN_5A

7
10 SKIP1 LX1 15
0.1u_OP
Z3005 11 14 Z3012 1 2
SLEW1 PWRGD1 4.7uH_IHLP2525CZ
VDDP2
12 13 R628
CS1N CS1P

5
6
AGND C735 C733 C734 C726
NC
Q105B R639
R650

C
1U 1U 0.047U OZ824_QFN 0 C723 + C722 D54
21

10NF R640 131K_1 R630 227K_1 51_1

2

3
CS1P Z3009 1000p

560U_4V_OSC_DIP
B B
C736 15K BAT54
AGND AGND AGND AGND AGND C724

A
CS1N SP8K10S_FD5 C725 4.7NF

3
2200P_OP 1000P
CS1P
R641

74K_1 CS1N
FBVDD_PG
+5VS
C737
R642 100K C738

C739 1NF
R644 22P

47NF 53K_1 AGND AGND

AGND AGND
R643 0_0603

AGND

A A

UNIWILL COMPUTER CORP.

Title

MX0/M40/50EI0
Size Document Number Rev
1.05V/1.5V/1.8V/2.5V/0.9V C
3017
Date: Tuesday, August 09, 2005 Sheet 30 of 35
5 4 3 2 1
 5 4 3 2 1

USB BD
D D
M_5VA
MCN2

1
2
3
M_USB_P5- 4
M_USB_P5+ 5
6 MB1
7 M_USB_PWR
8 M_5VA
MC2
MUSB_CONN HCB2012K-301T07_1A_0805
0.1U MC5
Modify 12 MC3 150P_3KV_1808
0.1u MDC_CHASIS_GND
in RB.

GND2
MDC_GND MDC_GND MODEM_TX+
4 MCN4 MCN3 MCN1
M_USB5- 3 MRV1
M_USB5+ USB1_CON 1 1
2 2 2
1 DSSAP3100SBRP
MDC CON-1 MODEM_RX+ MDC C0N-2

GND1
PIN GND1=MDC_GND
PIN GND2=MDC_GND1

MDC_GND
MDC_GND MC4 150P_3KV_1808
C C
MDC_GND1 MDC_GND

Modify 13 in
RB.
ML1
M_USB_P5- 8 1 M_USB5-
M_USB_P5+ R2O R2I M_USB5+
7 R1O R1I 2
6 L2O L2I 3
5 L1O L1I 4

FRC1394_SMALL

MR2 0_OP
MR1 0_OP

B B

MH2 MH1
C217D87 C217D87

MDC_GND MDC_GND1

A A

UNIWILL COMPUTER CORP.

Title
M50EA0
Size Document Number Rev
M30EI0 C
3017 MDC BD
Date: Tuesday, August 09, 2005 Sheet 31 of 35
5 4 3 2 1
 5 4 3 2 1

SCN1

2
DC_IN_B DC_IN
DC_JACK
SF1 SL1
6125T/5A QT2012KL120HC_5A_0805 SCN2
D DC_IN+ D
1 1 2 6
SC1 SR1 5
SC2 SR2 SR3 SC3 25mR/F/2W_2512A_5A 4
22p 3
1U_25V_0805 12.1K_0603 12.1K_0603 0.01u 2

3
1

DC CONN
GND_P

GND_P

TOTAL POWER
C C
GND_P
SR4
Rsense=25m ohm
SSW1 65 Watt 20V/3.25A , 25mV/A X 7 = 175 mV/A ,
PWRON#
5

1 2 175mV/A X 6 = 1.05 V/A , 1.05 V/A / 5.99 = 175.3

1K mV/A
3 4
6

S_5VA SR5 1M_1

1%
POWER BUTTOM S_3.3VS

GND_S
0.1u_OP SC4 0.1u_OP SCN3
SC5 32 SU1A SU1B
32

4
GND_S 31 LM358
GND_S ADAP_I 31 SR6 127K_1 LM358
30 30 DC_IN 2
GND_P PWRON# 29 1 5 1.05 V/A
INTERNET_ON# 29 SR7 127K_1
for M30 SILENT_ON#
28
27
28 DC_IN_B 3
175mV/A 6
7
common 3 BTLLED_ON# 26
27
26 SR8

8
3 IDE_ACT# 25 25
24 1M_1 SR9 SR10
3 SILENT_LED# 24
GND_S 3 CHGLED_R# 23 23
SSW2 SR11 DC_IN_B 4.99K_1
3 CHGLED_G# 22 22
SILENT_ON# 21 14K_1_0603
5

1 2 3 PWR_LED# 21
B 3 CAPS# 20 20
175.3 mV/A B
1K 19 GND_S ADAP_I
3 4 3 NUM# 19
6

3 SCROLL# 18
17
18 FOR EC
SILENT BUTTOM 17 SR12 SC6
2 CRT_R 16 16
15 SR13
2 CRT_G 15
14 1K_1 1000P_0603
FOR M30EI 2 CRT_B 14
13 SR39 0_0603_OP 2K_1
2 CRT_RGB# 13
12 12
2 HSYNC 11 11
VSYNC 10
2 VSYNC 10
GND_S 9 9 GND_S GND_P GND_S GND_S
2 USB_P6+ 8 8
2 USB_P6- 7 7
6 6
5 SR14 0_0603_OP
S_5V 5
4 4
3 RFLED_ON# 3 3
DDC_DATA 2
SR15 2 DDC_DATA 2
GND_S SSW3 DDC_CLK 1 GND_S GND_P
2 DDC_CLK 1
INTERNET_ON#
5

1 2 CRT CONN
1K PIN GND1~2=GND_S
3 4
6

SC33 SC7
A GND_S S_5V A
RF_BUTTOM 0.1u_OP 0.1u

GND_S GND_S
SC31 UNIWILL COMPUTER CORP.
0.1u Title
PWRSW BOARD(M40/MX0/M50)
GND_S GND_S Size Document Number Rev
C
3017 AC_IN/SWITCH/CONN
Date: Tuesday, August 09, 2005 Sheet 32 of 35
5 4 3 2 1
 5 4 3 2 1

SDN1C
IMN10_OP

3
SDN3C SDN4A SDN4B SDN4C S_5V
FOR EMI ISSUE

3
IMN10_OP IMN10_OP IMN10_OP SDN2B
IMN10_OP SDN1A SDN1B SDN2A IMN10_OP SDN2C

4
IMN10_OP IMN10_OP
IMN10_OP IMN10_OP SB2

4
QT1608RL060
S_5V GND_S S_5V GND_S
SC11
D D
HSYNC SR16 39 S_5V GND_S S_5V GND_S GND_S
1 HSYNC
S_5V GND_S SCN4
VSYNC SR17 39
1 VSYNC move to MB 0.1u
17

CRT_R SB1 0_0603 1

1 CRT_R
9
CRT_G SB3 0_0603 2
1 CRT_G
10
CRT_B SB4 0_0603 3
1 CRT_B
11
CRT_DOCK_DET 4
DDC_DATA SB5 QT1608RL060 12
1 DDC_DATA
5
SB6 QT1608RL060 13
CRT_USB-_IO 6
SB7 QT1608RL060 14
CRT_USB+_IO 7
SB8 QT1608RL060 15
1 DDC_CLK
8

SC14 SC15 SC16 SC17 SC18 SC19 SC20 16

10P 10P 10P 10P 10P 10P 10P CRT_CONN

6

SR18 SR19 SC12 SR20 SC13

SDN5A SDN5B SDN3A SDN3B SC23
IMN10_OP IMN10_OP IMN10_OP IMN10_OP 150_1 150_1 10P 150_1 10P
10P
1

GND_S
C C

GND_S
S_5V GND_S S_5V GND_S SD9 BAT54
S_5V C A
S_5V S_5V SR34
4

SR35 SR36 SR21 300K CRT_GND_ON

SDN5C 150_1
IMN10_OP SR37 SR38 150_1 150_1 SC28
S_5V S_5V
3

10K 10K 0.1u

D
SR22

D
SQ4
G SQ5 SQ6 SD10BAT54 GND_S SU3 SU4
2N7002

5
G G 100K A C 74AHC14_1G 74AHC14_1G
2N7002 2N7002

S
D

S
SR23 1M SR24 300K 2 4 2 4 CRT_USB_ON#
SQ7

D
1 CRT_RGB# G
GND_S GND_S SQ1 SC30
S

CRT_DOCK_DET

1
GND_S GND_S G 2N7002
2N7002 0.1u

S
GND_S GND_S GND_S GND_S
GND_S
FOR M30EI
B
DOCK_DET is Pulled High at Docking Side B

Close to CRT CRT_USB-_IO CRT_USB+_IO

D
SU2 SL2 SQ2 SQ3
2 3 CRT_USB+_OUT CRT_USB+_OUT 4 3 CRT_USB+_IO CRT_GND_ON G CRT_GND_ON G
1 USB_P6+ A1 B1 R1I R1O 2N7002 2N7002
5 6 CRT_USB-_OUT CRT_USB-_OUT 1 2 CRT_USB-_IO
1 USB_P6- A2 B2 R2I R2O

S
CRT_USB_ON# 1
CRT_USB_ON# BE1# FRC1394_SMALL(4 PIN)
7 BE2#
4 GND VCC 8 S_5V
GND_S GND_S
SC29
SN74CBT3306PWR
0.1u SR27 0_0402_OP

SR29 0_0402_OP Keep the USB Stub to the MOSFET.Drain as Short as Possible
GND_SCLOSE TO CN2 GND_S

Pin 2.PIN 5 --> Input SH3 SH1 SH2 SM1 SM2 SM3 SM4 SM5 SM6
holec256d91holec177b276d91
C276D91 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1
A Pin 3.PIN 6 --> Output A

Common Mode Chock For EMI

GND_S GND_S GND_P
Title
Unwill International Corp.
PWRSW BOARD(M40/MX0/M50)
Size Document Number Rev
CRT 2/3 C
3017
Date: Tuesday, August 09, 2005 Sheet 33 of 35
5 4 3 2 1
 5 4 3 2 1

D
LED D

S_5VA
1
1
BTLLED_ON#
SILENT_LED#
SCN5
1
3
2
4
IDE_ACT# 1
CHGLED_R# 1
S_3.3VS
LAN
1 CHGLED_G# 5 6 PWR_LED# 1
1 CAPS# 7 8 NUM# 1
1 SCROLL# 9 10 RFLED_ON# 1
11 12
13 14
15 16 SCN6
TRL3+
SC21 LED BD CONN TRL2+ 1
SC22 2
GND_S GND_S 3
0.1u TRL1-
0.1u TRL1+ 4
5
C GND_S GND_S C
TRL0- 6
TRL0+ 7
8

GND_S LAN CONN

RJ45
FRC1394_SMALL(8 PIN)
TRL0+ 5 4 TRL0_+
TRL0- L1O L1I TRL0_-
6 L2O L2I 3
TRL1+ 7 2 TRL1_+
TRL1- R1O R1I TRL1_-
8 R2O R2I 1
SCN7
RJ45 SL3

TRL0_+ 1 SRP1
B
TRL0_- TX+ B
2 TX- GND GND1 8 1
TRL1_+ 3 7 2
TRL2+ RX+
4 RJ-4 6 3
5 RJ-5 5 4
TRL1_- 6
TRL3+ RX- 0X4_0402_OP
7 RJ-7 GND GND2
8 RJ-8

GND_S

A A

Title
Unwill International Corp.
PWRSW BOARD(M40/MX0/M50)
Size Document Number Rev
LAN/LED 3/3 C
3017
Date: Tuesday, August 09, 2005 Sheet 34 of 35
5 4 3 2 1
 5 4 3 2 1

M30 to M40/50 R:A Change Note: M40/50 R:B to R:C Change Note:
Page 18->1. Del. R812 and R813 for unnecessary parts.
Page 13->1.DDR SODIMM fixed pin connect to GND by EMI solution.
Page 19->2. Change R675 to 0 ohm 1206 size for M50EA0 mutual design.
Page 14->2.No smart power 2 function so del. Q28 and Q32.
Page 19->3. Add C417(0.1uf) for EMI proposed.
Page 15->3.Del. R619,D50 and add R158,BT1 for ME assembling.
Page 19->4. Add R631(0 ohm) and C920(0.1uf) for EDID function.
D
Page 19->4.Del. USB always have power design for new customer. D
Page 19->5. Change power source to control MOS.
Page 23->5.Modify system beep sound circuit for wrong design.
Page 19->6. Add C41 and C47 for EMI proposed.
Page 27->6.Add R910 to improvent AUX_OFF# signal.
Page 20->7. Add C604(1uf) to improve SATA HDD power.
Page 23->7.Add B70 and B71 for EMI solution.
Page 20->8. Add C743(0.1uf) for EMI proposed.
Page 23->8.Change signal name for right control.
Page 23->9. Add circuit for signal dirving ability.
Page 23->9.Change DDC_CLK/DDC_DATA to 31 and 32 pin.
Page 23->10. Add C938~C940(0.1uf) for EMI proposed.
Page 24->10.Del touch pad pull high resister(R204/R205).
Page 23->11. Change power source to control MOS.
Page 24->11.No IR function so del pull high resister(R194/R195).
Page 23->12. Change R815 to 220 ohm bead for EMI proposed.
Page 24->12.Add Q82 and R613 for selecting CPU function.
Page 23->13. Add C714~C716(0.1uf) for EMI proposed.
Page 24->13.Add R446 and D63 to prevent EC leakage currect issue.
Page 26->14. Add R815(0 ohm) for EMI test.
Page 26->14.Adjust R329 value for 1.5V over current protect.
C C
Page 28->15. Add D70 and D71 for power shut down sequence.
Page 27->15.Change R803 and R805 value for 3V and 5V over currect protect.

M40/50 R:A to R:B Change Note:

Page 13->1.DDR SODIMM fixed pin connect to GND by EMI solution.
Page 7->2. Change R452,R196 and R435 to 0603 size.
Page 7->3. Del. R176 and add R829(0 ohm) for EMI proposed.
Page 11->4. Change X5R capacity to improve 1.05V power.
Page 15->5. Change R814 to 60 ohm bead for EMI proposed.
Page 15->6. Add R830 and R831 for safety test.
Page 25->7. Change R357(825 ohm) and R369(619 ohm) to adjust core voltage slope.

B Page 26->8. Change R323 and R324to 0603 size. B

Page 11->9. Change R68 and R69 to 0 ohm 1206 size.

Page 26->10. Change R65 to 0 ohm 1206 size.
Page 27->11. Add for power shut down.
Page 31->12. Change Conn. type.
Page 31->13. Change common choke for EMI proposed.

A A

Uniwill International Corp.

Title

M40/50EI0
Size Document Number Rev
Chang Note C
3017
Date: Tuesday, August 09, 2005 Sheet 35 of 35
5 4 3 2 1