S.D.M.

Jain matt Trust®

A.G.M RURAL COLLEGE OF ENGINEERING AND TECHNOLOGY,
VARUR, HUBLI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NOTES
Subject with code: Electronic Principles and Circuits (BEC303)

Module 2

Prepared By

Prof. ASIF IQBAL MULLA

Department of Electronics and Communication
Syllabus :

MOSFET
Biasing in MOS amplifier circuits:
Fixing VGS, Fixing VG, Drain to Gate feedback resistor.

Small signal operation and modelling:

The DC bias point, signal current in drain, voltage gain, small signal equivalent circuit
models, transconductance, The T equivalent circuit model.

MOSFET Amplifier configuration:

Basic configurations, characterizing amplifiers, CS amplifier with and without source
resistance, The Common Gate Amplifier, Source follower.
 Biasing in MOS Amplifier Circuits

An essential step in the design of a MOSFET amplifier circuit is the establishment of

an appropriate dc operating point for the transistor. This is the step known as biasing or bias
design. An appropriate dc operating point or bias point is characterized by a stable and
predictable dc drain current ID and by a dc drain-to-source voltage VDS.

Biasing by Fixing VGS

The most straight forward approach to biasing a MOSFET is to fix its gate-to-source
voltage VGS to the value required to provide the desired ID. This voltage value can be
derived from the power-supply voltage VDD through the use of an appropriate voltage
divider. Alternatively, it can be derived from another suitable reference voltage that might be
available in the system. This is not a good approach to biasing a MOSFET. To understand the
reason for this statement, recall that ID is

and note that the values of the threshold voltage Vt, the oxide-capacitance Cox, and (to a
lesser extent) the transistor aspect ratio vary widely among devices of supposedly the same
size and type. The spread is also large in integrated circuits, especially among devices
fabricated on different wafers and certainly between different batches of wafers. Furthermore,
both Vt and μn depend on temperature, with the result that if we fix the value of VGS, the
drain current ID becomes very much temperature dependent. As shown in the Fig. 5.51 two
iD–vGS characteristic curves representing extreme values in a batch of MOSFETs of the same
type having different current ID for the fixed value of VGS.

Biasing by Fixing VG and Connecting a Resistance in the Source

An excellent biasing technique for discrete MOSFET circuits consists of fixing the dc
voltage at the gate, VG, and connecting a resistance in the source lead, as shown in Fig.
5.52(a).For this circuit we can write

Here the resistor RS provides negative feedback, which acts to stabilize the value of
the bias current ID. To see how this comes about, consider what happens when ID increases
for whatever reason. Equation (5.93) indicates that since VG is constant, VGS will have to
decrease. This in turn results in a decrease in ID, a change that is opposite to that initially
assumed. Thus the action of RS works to keep ID as constant as possible. This negative
feedback action of RS gives it the name degeneration resistance.
Figure 5.52(b) provides a graphical illustration of the effectiveness of this biasing
scheme. Here too we show the iD–vGS characteristics for two devices that represent the
extremes of a batch of MOSFETs. Observe that compared to the case of fixed VGS, here the
variability obtained in ID is much smaller. Also, note that the variability decreases as VG and
RS are made larger (thus providing a bias line that is less steep).
Two possible practical discrete implementations of this bias scheme are shown in Fig.
5.52(c) and (e). The circuit in Fig. 5.52(c) utilizes one power-supply VDD and derives VG
through a voltage divider (RG1, RG2). As shown in Fig. 5.52(d) capacitor CC1 blocks dc and
thus allows us to couple the signal vsig to the amplifier input without disturbing the MOSFET
dc bias point. Finally, note that in. When two power supplies are available, as is often the
case, the somewhat simpler bias arrangement of Fig. 5.52(e) can be utilized.

Biasing Using a Drain-to-Gate Feedback Resistor

A simple and effective discrete-circuit biasing arrangement utilizing a feedback resistor
connected between the drain and the gate is shown in Fig. 5.54. Here the large feedback
resistance RG forces the dc voltage at the gate to be equal to that at the drain (because IG =
0). Thus we can write

which is identical in form to Eq. (5.93), which describes the operation of the bias scheme
discussed above [that in Fig. 5.52(a)]. Thus, here too, if ID for some reason changes, say
increases, then Eq. (5.96) indicates that VGS must decrease. The decrease in VGS in turn
causes a decrease in ID, a change that is opposite in direction to the one originally assumed.
Thus the negative feedback or degeneration provided by RG works to keep the value of ID as
constant as possible.

Small-Signal Operation and Models

For small signal operation we utilize the conceptual amplifier circuit shown in Fig.
5.34. Here the MOS transistor is biased by applying a dc voltage VGS, and the input signal to
be amplified, vgs, is superimposed on the dc bias voltage VGS. The output voltage is
taken at the drain.

The DC Bias Point

The dc bias current ID can be found by setting the signal vgs to zero; thus,
Here VOV = VGS – Vt is the overdrive voltage at which the MOSFET is biased to operate.
The dc voltage at the drain, VDS, will be

The Signal Current in the Drain Terminal

The Voltage Gain

The minus sign in Eq. (5.51) indicates that the output signal vds is 180° out of phase
with respect to the input signal vgs. This is illustrated in Fig. 5.36, which shows vGS and vDS.
The input signal is assumed to have a triangular waveform with an amplitude much smaller
than2(VGS – Vt), the small-signal condition in Eq. (5.44), to ensure linear operation.
For operation in the saturation region at all times, the minimum value of vDS should
not fall below the corresponding value of vGS by more than Vt. Also, the maximum value of
vDS should be smaller than VDD; otherwise the FET will enter the cut off region and the
peaks of the output signal waveform will be clipped off.
 Small-Signal Equivalent-Circuit Models

From a signal point of view, the FET behaves as a voltage-controlled current source.
It accepts a signal vgs between gate and source and provides a current gmvgs at the drain
terminal. The input resistance of this controlled source is very high—ideally, infinite. The
output resistance that is, the resistance looking into the drain also is high, and we have
assumed it to be infinite thus far. Putting all of this together, we arrive at the circuit in Fig.
5.37(a), which represents the small-signal operation of the MOSFET and is thus a small-
signal model or a small-signal equivalent circuit.

The most serious shortcoming of the small-signal model of Fig. 5.37(a) is that it
assumes the drain current in saturation to be independent of the drain voltage. But the drain
current does in fact depend on vDS in a linear manner. Such dependence was modeled by a
finite resistance ro between drain and source, whose value was given by
The Transconductance gm

We shall now take a closer look at the MOSFET transconductance given by Eq.
(5.47), which we rewrite with Kn = Kn’ (W/L) as follows:

This relationship indicates that gm is proportional to the process gm parameter and to

the W/ L ratio of the MOS transistor; hence to obtain relatively large gm the device must be
short and wide.

This expression shows two things:

1. For a given MOSFET, gm is proportional to the square root of the dc bias current.
2. At a given bias current, gm is proportional to √W/L.

The T Equivalent-Circuit Model

Through a simple circuit transformation it is possible to develop an alternative equivalent-

circuit model for the MOSFET. The development of such a model, known as the T model, is
illustrated in Fig. 5.40. Figure 5.40(a) shows the equivalent circuit studied
 Basic MOSFET Amplifier Configurations

The Three Basic Configurations:

 1. Common Source Amplifier (CS)

2. Common Gate Amplifier (CG)

The common-gate (CG) or grounded-gate amplifier is shown in Fig. 5.43(b). It is

obtained by connecting the gate to ground, applying the input vi between the source and
ground, and taking the output vo across the resistance RD connected between the drain and
ground.

3. Common Drain (CD)

Characterizing Amplifiers
The Common-Source (CS) Amplifier without source resistance (Rs)

Usually RD much lower than ro (RD << ro) , thus voltage gain is

With RD << ro
Thus overall voltage gain Gv is given by
Gv = vo / vsig = vo / vi = Av

The Common-Source (CS) Amplifier with source resistance (Rs)

It is often beneficial to insert a resistance Rs in the source lead of the common-source

amplifier as shown in Fig. 5.47(a). The corresponding small-signal equivalent circuit is
shown in Fig. 5.47(b), where we note that the MOSFET has been replaced with its T
equivalent-circuit model.
The output resistance Ro which can be found by inspection to be

The Common-Gate (CG) Amplifier

Alternatively, Av can be obtained by simply replacing RD in Eq. (5.85) by (RD || RL) thus,

Overall voltage gain Gv:

The low input resistance of the CG amplifier can cause the input signal to be severely
attenuated. Hence Vsig is not equal to vin which is given by

Thus overall voltage gain Gv is given by

Gv = vo / vsig =( vo / vi )( vi / vsig )

The Common-Drain Amplifier or Source Follower

It is most convenient to use the T model, as shown in Fig. 5.50(b). Note that we have
included , ro simply because it is very easy to do so. From the circuit of figure 5.50(a) we can
write input resistance as

By looking at figure 5.50(c) vi = i(1/gm + RL ) and vo = i(1/gm ) Therefore the Av is