Error-Detection and - Correction Techniques
Error-Detection and - Correction Techniques
SCIENTIFIC RESEARCH
AL-MUSTAQBAL UNIVERSITY COLLEGE
COMPUTER ENGINEERING DEPARTMENT
Let’s now examine three techniques for detecting errors in the transmitted data: parity
checks (to illustrate the basic ideas behind error detection and correction), checksumming
methods (which are more typically used in the transport layer), and cyclic redundancy
checks (which are more typically used in the link layer in an adapter).
1.1 Parity Checks
Perhaps the simplest form of error detection is the use of a single parity bit. Suppose that
the information to be sent, D in Figure 2, has d bits. In an even parity scheme, the sender
simply includes one additional bit and chooses its value such that the total number of 1s in
the d + 1 bits (the original information plus a parity bit) is even. For odd parity schemes,
the parity bit value is chosen such that there is an odd number of 1s. Figure 2 illustrates an
even parity scheme, with the single parity bit being stored in a separate field.
Receiver operation is also simple with a single parity bit. The receiver need only count the
number of 1s in the received d + 1 bits. If an odd number of 1-valued bits are found with an
even parity scheme, the receiver knows that at least one bit error has occurred. More
precisely, it knows that some odd number of bit errors have occurred. But what happens if
an even number of bit errors occur? You should convince yourself that this would result in
an undetected error.
Let’s consider a simple generalization of one-bit parity that will provide us with insight into
error-correction techniques. Figure 3 shows a two-dimensional generalization of the single-
bit parity scheme. Here, the d bits in D are divided into i rows and j columns. A parity
value is computed for each row and for each column. The resulting i + j + 1 parity bits
comprise the link-layer frame’s error-detection bits.
Suppose now that a single bit error occurs in the original d bits of information. With this
two-dimensional parity scheme, the parity of both the column and the row containing the
flipped bit will be in error. The receiver can thus not only detect the fact that a single bit
error has occurred, but can use the column and row indices of the column and row with
parity errors to actually identify the bit that was corrupted and correct that error! Figure 3
shows an example in which the 1-valued bit in position (2,2) is corrupted and switched to a
0—an error that is both detectable and correctable at the receiver. Although our discussion
has focused on the original d bits of information, a single error in the parity bits themselves
is also detectable and correctable.
Figure 3: Two-dimensional even parity
10110011
10101011
01011110
1
01011111
01011010
10111001
11010101
10001110
1
Sum:10001111
Checksum:01110000
Receiver:
10110011
10101011
01011110
1
01011111
01011010
10111001
11010101
10001110
1
10001111
01110000
Sum:11111111
No error
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Proc. 1970 Fall Jt Com- puter Conf, AFIPS Press, Arlington, Va., pp 281-285.
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(March 1964), 1-9.