2422 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO.

10, OCTOBER 2012

Memristor Emulator for Memristor

Circuit Applications
Hyongsuk Kim, Member, IEEE, Maheshwar Pd. Sah, Changju Yang, Seongik Cho, and
Leon O. Chua, Life Fellow, IEEE

Abstract—A memristor emulator which imitates the behavior of Due to such unusual features of the memristor, many scien-
a TiO memristor is presented. Our emulator is built from off-the- tists had started to exploit the memristor for analog [6], [7] and
shelf solid state components. To develop real world memristor cir- digital information processing [8], [9] applications. Others have
cuit applications, the emulator can be used for breadboard exper-
iments in real time. Two or more memristor emulators can be con-
applied memristive devices as resistive switching devices for
nected in serial, in parallel, or in hybrid (serial and parallel com- memory and logic applications [10]–[12]. Also, the potential for
bined) with identical or opposite polarities. With a simple change exploiting memristors for neuromorphic applications had been
of connection, each memristor emulator can be switched between proposed by many scientists [3], [4], [7], and [20]–[22]. The
a decremental configuration or an incremental configuration. The analog signal storing capability of the memristor is very impor-
hardware and spice simulation of the proposed emulator showed tant in neuromorphic applications.
promising results that provides an alternative solution of TiO
memristor model in real circuit.
Recently, Jo et al. [7] and Kund et al. [13] had built memris-
tors using Ag and Si in a sandwiched layer and reported their
Index Terms—Decremental configuration, emulator, incre- performances as analog memories. Also, Snider had presented
mental configuration, memristor, off-the-shelf devices.
a memristor-based self-organized network employing dedicated
memristor connections for inhibitory (negative) weighting [4].
I. INTRODUCTION Despite such immense interest among scientists on the mem-
ristor, commercially available memristors are not expected to

A MEMRISTOR is a circuit element developed recently,

which exhibits excellent features of both memory and
neuromorphic applications. For memory applications, it is non-
appear in the near future due to the cost and technical difficul-
ties in fabricating nano-scale devices. Therefore, some circuit
replacements which behave like memristors are needed to build
volatile and has an extremely small size of a few nanometers. real-world application circuits which exploit memristor’s po-
For neuromorphic applications, it has features of pulse-based tentials. Indeed, several research groups presented spice macro
operation and adjustable resistance, which are ideal for tuning models [14]–[17], which are useful for simulating memristor.
the synaptic weights of neuromorphic cells. However, macro models are not hardware, and they cannot be
The memristor was first postulated by Chua in 1971 as the used to build physically implementable memristor application
fourth basic element of electrical circuits [1] and later the con- circuits. Therefore, emulators which act like the real memris-
cept was generalized to a class of dynamical systems called tors are needed. Some important features which should be in-
memristive a device [2]. Recently, the Stanley Williams group cluded in any memristor emulator are 1) the memristance (re-
[3] from hp has built a nano-scale TiO device which is non- sistance of memristor) should be programmable 2) the mem-
volatile and exhibits synaptic characteristics [3], [4]. A common ristance should be nonvolatile, and 3) it can be connected di-
fingerprint of both the memristor, and the memristive device, is rectly to other memristor circuit elements. Only a few research
the pinched hysteresis loop in the current versus voltage plane, groups had made contributions in the area of memristor emula-
under sinusoidal excitations. Due to these phenomena, the re- tors. Pershin et al. had built a memristor model [18] using digital
sistance of the device depends upon the past history of the input and analog mixed circuits. Since the signals in their circuit are
current or voltage, and hence can function as synapses of neural converted between analog and digital to perform the memristor
networks. operation, instant interoperability with other analog circuit ele-
ment is limited. On the other hand, Mutlu et al. had presented
Manuscript received September 08, 2011; revised December 13, 2011; ac- a memristor emulating circuit via pure analog technology [19],
cepted January 09, 2012. Date of publication April 13, 2012; date of current where the features of the TiO memristors are well emulated.
version September 25, 2012. This work was supported in part by the National Though, it is pedagogically useful, the serial, parallel, hybrid
Research Foundation of Korea (NRF) under Grant 2010-0006871 and in part
by the U.S. Air Force under Grant FA9550-10-1-0290. Corresponding author is expandable, and the connectivity with other circuit elements are
M. P. Sah. This paper was recommended by Associate Editor J. Lu. difficult in their design. Also, the memristance does not remain
H. Kim, M. P. Sah, C. Yang, and S. Cho are with the Division of Electronics constant for a long enough time sufficient for application study,
and Information Engineering, Chonbuk National University, Jeonju 561-756,
Korea (e-mail: hskim@jbnu.ac.kr; maheshwarsah@hotmail.com). thereby reduces and limits the usefulness of their work.
L. O. Chua is with the Department of Electrical Engineering and Com- In this paper, we propose a memristor emulating circuit
puter Sciences, University of California, Berkeley, CA 94720 USA (e-mail: which is built with off-the-shelf solid state devices. Our pro-
chua@eecs.berkeley.edu).
Color versions of one or more of the figures in this paper are available online
posed memristor emulator includes the features of the TiO
at http://ieeexplore.ieee.org. memristor faithfully; its memristance does not vary over a
Digital Object Identifier 10.1109/TCSI.2012.2188957 relatively long period of time, and it is compatible with other

1549-8328/$31.00 © 2012 IEEE

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KIM et al.: MEMRISTOR EMULATOR FOR MEMRISTOR CIRCUIT APPLICATIONS 2423

circuit devices. Various features of our proposed memristor

emulator are demonstrated via experiments and simulations.
The concept of the memristor is briefly reviewed in Section II,
and the design principle of our memristor emulator circuit is
described in Section III. For application studies, an expandable
model of our memristor emulator is proposed in Section IV. Var-
ious features of our memristor-emulator hardware were tested to
verify its performance in Section V. A short conclusion is given
in Section VI.

II. PRINCIPLE OF THE MEMRISTOR

Fig. 1. (a) Structure of the TiO memristor TiO and TiO layers are sand-
In the memristor, the current and voltage relationship can be wiched between two platinum electrodes. When a voltage/current is applied,
defined by its memristance (resistance of the memristor in Ohms)/ memductance (conduc-
tance of the memristor) in siemens) is altered. (b) Symbol of the memristor.

(1) where is defined as the state variable. In the TiO mem-

ristor [3], the rate of change of the state variable is defined as a
function of current ; namely,
where and denote the flux and charge, respectively,
at time . Thus, the resistance can be interpreted as the slope at
the operating point at time on the memristor (4)
curve. If the curve is nonlinear; the resistance will vary
with the operating point. Without external voltage or current, where is the dopant mobility. This model is called a linear
the operating point does not change and hence the resistance drift model since the velocity of the width is linearly propor-
remains constant. Thus, the signal is memorized as the value of tional to the current.
the memristor’s resistance, namely, the memristance . The relationship between the flux and the charge of the
Since the flux is defined by , the mem- memristor is given by [3]; see equation (5) at the bottom of the
ristance (resistance of memristor) can be controlled by ap- page.
plying a voltage or current signal across the memristor, where From (2) and (5), we obtain

(2)

Fig. 1(a) shows the structure of the TiO memristor [3].

In the TiO memristor, a thin titanium dioxide TiO layer and
a thin oxygen-poor titanium dioxide TiO layer are sand- (6)
wiched between two platinum electrodes. The TiO layer and
the TiO layer are referred to as undoped, and doped layers, Observe that the memristance in (6) is a linear function of the
respectively. When a voltage or current is applied to the device, charge . Fig. 1(b) shows the symbol of the memristor with
the dividing line between the TiO and TiO layers shifts as the polarity indicated by a black bar at one end. It follows from
a function of the applied voltage or current. As a result, the re- (6) that the memristance decreases when current flows from
sistance between the two electrodes is altered. the left side toward the right (black bar) side.
Let and denote the thickness of the sandwiched area and
III. BASIC MEMRISTOR EMULATING CIRCUIT
the doped area (oxygen deficient area) in the TiO memristor,
respectively, and let and denote the resistances at Our memristor emulating circuit is designed in a way of com-
high and low dopant concentration areas, respectively. posing the input resistance as a function of applied voltage or
Then, the relation between the voltage and the current is given current. The circuit in Fig. 2(a) gives the idea on how to imple-
by ment features of the memristor using an op amp circuit.
In the figure, a voltage equation at the input terminal of
Fig. 2(a) is
(3)
(7)

(5)

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2424 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

a voltage multiplier. The output voltage of the voltage mul-

tiplier is given by

(9)

where is the resistance in Fig. 3(a). Therefore, the input

voltage is
Fig. 2. Concept for implementing the proposed memristor emulator. (a) Input
resistance as a function of voltage . (b) Equivalent circuit. (10)

and the input resistance of Fig. 3 is .

When a positive pulse is applied at the input terminal, the resis-
tance increases proportional to the time integral of input cur-
rent with offset . We call this the incremental memristor
configuration.
Observe that the memristance in (10) is composed of a fixed
part and a variable part . Let the voltages cor-
responding to the fixed part and the variable part of memristance
be and , respectively, namely,

(11)

In the hp TiO memristor, the fixed part of the memristance

Fig. 3. Basic configuration of the incremental memristor. (a) Simplified circuit.
(b) Symbol of the incremental memristor.
is normally much smaller than that of the variable part. Fig. 3(a)
shows the simplified circuit of the incremental memristor.
In memristor, if a positive voltage is applied to the opposite
polarity of the incremental memristor, the memristance is de-
creased. We call this the decremental memristor configuration.
By adding a voltage inverter after the voltage multiplier, the
decremental memristor configuration can be implemented. The
input voltage in this case is

(12)

The resultant input resistance of the decremental memristor

configuration is

(13)
Fig. 4. Basic configuration of the decremental memristor. (a) Simplified cir-
cuit. (b) Symbol of the decremental memristor.
Here, the input resistance is equal to the subtraction of the vari-
able part from the fixed part of the memris-
where the input is current, is a resistance at the inverting tance. Fig. 4(a) shows the simplified circuit of the decremental
input terminal and is the voltage applied to the positive ter- memristor and Fig. 4(b) is its symbol. Observe that (13) is the
minal of the op amp. same expression of the memristance in (6), which implies that
Assume that the voltage is proportional to input current circuit in Fig. 4(a) acts as memristor.
, then A full schematic of a basic incremental memristor configura-
tion is shown in Fig. 5. The schematic of a decremental mem-
(8) ristor is the same as that of incremental memristor except for an
analog inverter inserted at the end of the multiplier. In practice,
where is a proportionality coefficient and . Equa- the resistance is chosen to be small (around 5 k ) for the
tion (8) implies that the input resistance of the circuit is . incremental memristor and large (around 16 k ) for the decre-
If we can control so that it is time integral of the input current mental memristor configurations.
, then, the circuit in Fig. 2 acts as a memristor. To emulate When an input voltage is applied at a memristor emulator, it is
in (8), three devices (a capacitor, a resistor, and a voltage mul- converted into an input current with a resistor and op amp
tiplier) are utilized, in which the voltage from the capacitor and U0 via the virtual ground constraint. Since the current is used
that from the resistor are multiplied using a voltage multiplier at several places shown in Figs. 3(a) and 4(a), its replicas are
as in Fig. 3 [see the right side of Figs. 3(a) and 4(a)]. generated using current mirrors. Observe that a current mirror
In the figure, the capacitor produces a voltage by inte- copies single directional currents only. For bidirectional (posi-
grating the current , and the resistor produces a voltage pro- tive and negative) currents, must be separated into a positive
portional to the current . These two voltages are multiplied by part and a negative part, and processed separately at different

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KIM et al.: MEMRISTOR EMULATOR FOR MEMRISTOR CIRCUIT APPLICATIONS 2425

Fig. 5. Schematic of a basic incremental memristor configuration.

parts of the circuit. In the circuit of Fig. 5, the positive part of

the current, duplicated by a current mirror MN0 and MN2 is fed
into a resistor and a capacitor C by current mirror MP3 and
MP4 with couple of MP1 respectively. On the other hand, MP0
and MP2 acts as the negative part of current mirror that flows
out from resistor and capacitor C by current mirror MN3
and MN4 with MN1 couple transistor, respectively.
One of the distinguished features of a memristor is the capa-
bility of keeping the programmed information for a long time
until new programming inputs are presented. The charge stored
at capacitor C is the programmed information in our memristor
Fig. 6. Expandable memristor configurations. (a) Incremental configuration.
emulator. To avoid discharging during the period when an input (b) Decremental configuration.
signal does not exist, the path to the output terminal is connected
to the gate of a MOS type buffer U1. analog Adder as shown at the bottom of Fig. 6(a) and (b), where
the terminal indicated as is for the voltage of the next
IV. EXPANDABLE MODEL OF MEMRISTOR EMULATOR memristor.
The expandable structure of an incremental memristor is
A. Serial Connection
shown in Fig. 6(a). Since the memristance of the decremental
One of the important function of the memristor emulator memristor configuration is reduced by subtracting the variable
is for the development of memristor application circuits. In part from the fixed part of the memristance as in (13), its
such applications, the compatibility with other devices is very slightly different expandable structure is shown in Fig. 6(b).
important. The full schematic including the expandable structure is shown
When a voltage is applied at serially connected memristors, in the Appendix.
the input voltage is distributed to every memristor according Fig. 7 illustrates an example of two serially connected mem-
to the voltage law so that the sum of each memristor voltage ristors with opposite polarities, where Fig. 7(a) is a symbol con-
is equal to the input voltage like in ordinary resistors. Also, a nection and Fig. 7(b) is its simplified circuits. In serially con-
voltage measured in front of the memristor is the sum of nected devices, the currents at each device should be common.
voltages from the memristor to the last memristor. Let such To implement this constraint, the input current of the first mem-
voltage measured in front of the memristor be . Then, ristor is replicated and fed to every memristor individually to
is produce its voltage in the memristor emulator. The dependant
current source shown at the beginning of the second memristor
in Fig. 7(b) is to implement this common current constraint.

(14) B. Parallel Connection

where and are the voltages corresponding to the fixed In the case of parallel connection, the same input voltage
part and the variable part of the memristor as in (11). Also, must be applied at both input terminals of the parallel devices.
is the sum of the voltages from the memristor Fig. 8 illustrates an example of a parallel connection of two
to the last memristor. memristors with opposite polarities, where Fig. 8(a) is a symbol
Equation (14) can be rearranged as connection and Fig. 8(b) is its simplified circuits. For two mem-
ristor with opposite polarities, the connection diagram is shown
(15) in Fig. 8. The two component memristor currents are
From (15), each memristor requires three parts of voltage ad-
dition. The addition between the fixed voltage and the vari-
able voltage are performed with an op amp.
However, the addition in is implemented by an (16)

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2426 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

Fig. 8. Parallel connection of two memristors with opposite polarities.

(a) Symbol connection. (b) Connection diagram of the simplified circuits.

C. Hybrid Connection
Fig. 7. Two serially connected memristors with opposite polarities. (a) Symbol
connection. (b) Connection diagram of the simplified circuits. More complicate circuit is with hybrid model composited
with serial and parallel circuits. There could be many dif-
where the first one is the equation for a decremental memristor ferent combinations in hybrid model. One of them is a circuit
and the second one is that for an incremental memristor. Rear- consisting of three memristors in which one memristor is
ranging the equations in (16), we obtain connected serially to two parallel memristors as illustrated
in Fig. 9. Fig. 9(a) is its symbol connections and Fig. 9(b)
is the corresponding circuit which is built with the proposed
expandable memristor emulating circuit shown in Fig. 6. The
(17) composite memristor circuit acts as a single memristor is given
by
The total input current is
(20)

(18) V. EXPERIMENTS AND SIMULATIONS

We have built a memristor emulator circuit which works like a
Therefore, the total memristance M is TiO memristor [3] and is expandable via serial, parallel and hy-
brid connections. It has been tested with hardware experiments
(19) and simulations. The supplied power is 5 V and 5 V and it
was designed for both current controlled and voltage controlled
It follows that Fig. 8(a) acts as a parallel connection of the memristor models.
memristors and and Fig. 8(b) represents its connection The first experiment is to show our memristor emulator can
symbol. be implemented with ordinary circuit devices. The decremental

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KIM et al.: MEMRISTOR EMULATOR FOR MEMRISTOR CIRCUIT APPLICATIONS 2427

Fig. 11. Voltage waveforms measured at several nodes of the hardware circuit
in Appendix A for the experiment of Fig. 10.

Fig. 9. A hybrid circuit in which one memristor is connected serially to two

memristors in parallel. (a) Symbol connections. (b) Simplified circuit.

Fig. 12. Oscilloscope tracings of the pinched hysteresis loops recorded from
our memristor emulator for input signals with various frequencies.

Fig. 13. Oscilloscope trace showing the memristance change measured from
Fig. 10. Oscilloscope trace of the pinched hysteresis loop of our memristor the memristor emulator circuit when identical positive rectangular pulses (0.1 V,
emulator at 100 Hz. 2.5-ms duration, 10-s period) are applied repeatedly. During inter-pulse period,
the memristance is nonvolatile. Note that the decrement step size is bigger as
more pulses are applied since the memristance is reduced proportional to the
memristor in Appendix A was built on a breadboard with the integration of applied voltage.
devices listed in Appendix B. Experiments were conducted to
confirm the pinched hysteresis loop fingerprint of the mem- Note the frequency dependence of the pinched hysteresis loop
ristor. The input signal was a 100-Hz sinusoidal voltage with is another unique feature of the memristor.
2 Vp-p. Fig. 10 shows an oscilloscope display of a pinched Another unique feature of the memristor is the nonvolatility
hysteresis loop measured from the memristor emulator. The of its memristance during the idling periods when no input sig-
pinched loop shows that the memristance varies according to nals are applied. Since most memristor application circuits are
the input voltage/current, where the inverses of slope at various expected to operate with pulsed input signals, such nonvolatility
points of the loop are the memristances. Voltage waveforms feature is very important. Fig. 13 shows the memristance change
measured at several nodes are shown in Fig. 11. measured from our implemented memristor emulator circuit,
The variations of the pinched hysteresis loop for various fre- when a rectangular pulse train (0.1 V, 2.5 ms duration, 10-s pe-
quencies at 100, 200, 400, and 800 Hz are also shown in Fig. 12. riod) is applied across a decremental memristor once every 10 s.

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2428 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

Fig. 16. Voltage-current curve of two-memristor circuit connected in series, or

in parallel with opposite polarities. When two memristors with opposite polar-
ities are connected in series, the total change of memristance is negligible due
to the complementary action between two memristors.

Fig. 14. (a) Pinched hysteresis loops of memristors in single, serial, and par-
allel connections when sinusoidal voltage signals (2 V p-p, 100 Hz) are applied,
where K , F, and k . The slope of the pinched
hysteresis loop of the serial connection is a half and a quarter of the single and
the parallel memristor connections, respectively. (b) Variations of the memris-
tances along the time for these three cases.

Fig. 15. Variation of memristance when voltage input pulses (0.1-V amplitude,
5-ms width) are applied successively to the single memristor, serial and parallel
connected memristors at every 10 s.

Observe that the memristance is nonvolatile during non-pulse

period. Whenever, rectangular pulses are presented, the graph Fig. 17. Simulation results of a hybrid circuit in which a memristor is con-
nected serially to two parallel memristors as in Fig. 9. (a) Pinched hysteresis
changes abruptly. The rate of the memristance change (step size) loops when sinusoidal voltage input signals (2 V p-p, 300 Hz) are applied.
increases as more voltage pulses are applied since the memris- (b) Memristance variations when voltage input pulses (0.1-V amplitude, 2-ms
tance decreases as input voltage pulses are applied. width) are applied successively at every 10 s.
To utilize the memristor emulator for developing memristor
circuit application, the memristors should be connectable in se- and parallel, when sinusoidal voltage signals (2 V p-p, 100 Hz)
ries, in parallel or in hybrid (series-parallel) with other devices. are applied where K , F, and K
PSPICE simulations with memristor emulator circuits of same The slope of the pinched hysteresis loop of the serial connection
polarities and connected in series, in parallel have been con- is a half and a quarter of the single and the parallel memristor
ducted to demonstrate our memristor emulator circuit. Fig. 14(a) connections, respectively. Fig. 14(b) shows the variations of the
shows pinched hysteresis loops of memristors in single, serial, memristances along the time for these three cases.

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KIM et al.: MEMRISTOR EMULATOR FOR MEMRISTOR CIRCUIT APPLICATIONS 2429

Simulations with pulse inputs have also been made for these the small amount of current flow through the individual mem-
three configurations. Fig. 15 shows the memristances for a ristor in a parallel memristor circuit. The composite memris-
single memristor, and for the series and parallel connected tance, , which is the total memristance among ,
memristors when five positive and five negative voltage pulses , and reveals the biggest among all as we expected.
(0.1-V amplitude, 5-ms width) are applied successively at Fig. 17(b) shows the memristance variation of each memristor
every 10 s. The slope of the memristance variation in the serial while a sequence of pulse train is applied as indicated at the
connection case is two times and four times steeper than those bottom. Observe that the memristances of and vary in
of the single and the parallel circuit cases, respectively. opposite way since they are with opposite polarities.
In contrast to the above cases, the connections of two mem-
ristors in opposite polarities as shown in Figs. 7 and 8 have VI. CONCLUSION
been conducted, where memristances are K , Memristor emulator which acts as a real memristor device
K , respectively, and the input is a sinusoidal voltage signal is useful for developing memristor application circuits as well
(2 V p-p, 300 Hz). When two memristors with opposite polari- as for the memristor circuit demonstrations for educational
ties are connected in series, the total change of memristance is purpose.
negligible and its V-I curve is linear due to the complementary In this study, a memristor emulator has been designed and
action between two memristors as in Fig. 16. When two memris- built with off-the-shelf solid state devices. Various features of
tors with opposite polarities are connected in parallel, the com- this memristor emulator are tested via both circuit measure-
posite memristance shows still pinched hysteresis phenomenon ments and SPICE simulations. Experimental measurements
as shown in Fig. 16. are very similar to the real TiO memristor [3]. We have
Simulations for a hybrid circuit in which memristors are con- also confirmed experimentally that our memristor emulator is
nected serially to two parallel memristors as in Fig. 9 have nonvolatile over the time period of our experiments.
also been conducted. Memristances for these simulation were Our memristor emulator is also designed to be expandable.
K , where and are decre- This feature has been proved via simulations; our memristor
mental and is incremental. The input is a sinusoidal voltage emulator can be connected in serial, in parallel, or in hybrid (se-
signal (2 V p-p, 300 Hz). Observe in Fig. 17(a) that the graphs of rial and parallel combined) with other memristors with identical
and are shrunk pinched hysteresis loops (almost linear or opposite polarities. Also, it is switchable between the incre-
in the graph) which implies that the memristance variation of mental and the decremental configuration by a simple change of
and are much smaller than that of M1. This is due to the connections.

APPENDIX A

A Full schematics of the decremental memristor emulator with expandable non-volatile architecture.

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2430 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

APPENDIX B
PART LIST OF THE MEMRISTOR EMULATOR IN APPENDIX A

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[7] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, [22] M. P. Sah, C. Yang, H. Kim, and L. O. Chua, “Memristor circuit for
“Nanoscale memristor device as synapse in neuromorphic systems,” artificial synaptic weighting,” in Proc. IEEE Int. Symp. Circuit Syst.
Amer. Chem. Soc., Nano Lett., vol. 10, no. 4, pp. 1297–1301, Mar. (ISCAS), 2012, to be published.
2010.
[8] Q. Xia et al., “Memristor-CMOS hybrid integrated circuits for recon-
figurable logic,” Amer. Chem. Soc., Nano Lett., vol. 9, no. 10, pp.
3640–3645, Sep. 2009.
[9] J. Borghettil, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and Hyongsuk Kim (M’09) received the Ph.D. degree
R. S. Williams, “Memristive switches enable stateful logic operations in electrical engineering from the University of Mis-
via material implication,” Nature Lett., vol. 464, no. 8, pp. 873–876, souri, Columbia, in 1992.
Apr. 2010. Since 1993, he has been a Professor with the Divi-
[10] M. Aono and T. Hasegawa, “The atomic switch,” Proc. IEEE, vol. 98, sion of Electronics Engineering, Chonbuk National
no. 12, pp. 2228–2236, Dec. 2010. University, Jeonju, Korea. From 2000 to 2002 and
[11] M. N. Kozicki, C. Gopalan, M. Balakrishnan, and M. Mitkova, “A again from 2009 to 2010, he was with the Nonlinear
low-power nonvolatile switching element based on copper-tungsten Electronics Laboratory, Electrical Engineering
oxide solid electrolyte,” IEEE Trans. Nanotechnol., vol. 5, no. 5, pp. and Computer Science Department, University of
535–544, Sep. 2006. California, Berkeley, as a Visiting Scholar. His
[12] R. Waser and M. Aono, “Nanoionics-based resistive switching memo- current research interests include memristors and its
ries,” Nature Mater., vol. 6, pp. 833–840, Nov. 2007. application to cellular neural/nonlinear networks.
[13] M. Kund, G. Beitel, C. U. Pinnow, T. Röhr, R. Schumann, R.
Symanczyk, K. D. Ufert, and G. Müller, “Conductive bridging RAM
(CBRAM): an emerging non-volatile memory technology scalable to
sub 20 nm,” IEDM Tech. Dig., pp. 754–757, 2005. Maheshwar Pd. Sah received the B.E. degree from
[14] A. Rak and G. Cserey, “Macromodelling of the memristor in SPICE,” Nepal Engineering College, Changunarayan, Nepal,
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. in 2005 and the M.E. degree from Chonbuk National
4, pp. 632–636, Apr. 2010. University, Jeonju, Korea, in 2010, where he is cur-
[15] Z. Biolek, D. Biolek, and V. Biolková, “SPICE model of memristor rently working toward the Ph.D. degree in electronics
with nonlinear dopant drift,” Radio Eng., vol. 18, no. 2, pp. 210–214, and information engineering.
Jun. 2009. His main research interests include circuit design,
[16] D. Batas and H. Fiedler, “A memristor SPICE implementation and cellular neural networks, analog Viterbi decoders,
a new approach for magnetic flux-controlled memristor modeling,” analysis of memristors, and memristive systems.
IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 250–255, Mar. 2011.

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KIM et al.: MEMRISTOR EMULATOR FOR MEMRISTOR CIRCUIT APPLICATIONS 2431

Changju Yang received the B.S and M.S. degrees Leon O. Chua (LF’02) received the M.S. degree
in electronics and information engineering from from the Massachusetts Institute of Technology,
Chonbuk National University, Jeonju, Korea, in Cambridge, in 1961 and the Ph.D. degree from the
2008 and 2010, respectively, where he is currently University of Illinois at Champaign-Urbana in 1964.
working toward the Ph.D. degree in electronics and He became an Assistant Professor of Electrical
information engineering. Engineering at Purdue University, West Lafayette,
His main research interests include circuit design, IN, in 1964, and was promoted to Associate
analog Viterbi decoders, analysis of memristors, and Professor in 1967. He joined the University of Cali-
memristive systems. fornia, Berkeley in 1970, and has been a Professor of
Electrical Engineering and Computer Sciences. His
research interests are in memristors, chaos, cellular
automata and cellular neural networks.
Dr. Chua is the first recipient of the 2005 Gustav Kirchhoff Award, the highest
IEEE Technical Field Award for outstanding contributions to the fundamentals
Seongik Cho received the B.S., M.S., and the Ph.D. of any aspect of electronic circuits and systems that has a long-term significance
degrees in electrical engineering from Chonbuk Na- or impact. He was also awarded the prestigious IEEE Neural Networks Pioneer
tional University, Jeonju, Korea, in 1987, 1989, and Award in 2000 for his contributions in neural networks, the Guggenheim Fellow
1994, respectively. award in 2010 and a Leverhulme Trust Visiting Professorship in 2011.
From 1996 to 2004, he was with the System
IC R&D Center and Memory R&D Center, Hynix
Semiconductor, Inc., Korea, where he worked on
high-speed graphic DRAM, data converters, and
analog circuits. Since March 2004, he has been with
the Department of Electronic Engineering, Chonbuk
National University, where he is an Associate
Professor. His current research includes low-voltage low-power high-speed
analog circuits, high-speed I/O interfaces, DLL/PLLs, data converters, and
power management ICs.

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