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Mutator for transferring a memristor emulator into meminductive and memcapacitive circuits

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2014 Chinese Phys. B 23 070702

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 Chin. Phys. B Vol. 23, No. 7 (2014) 070702

Mutator for transferring a memristor emulator into

meminductive and memcapacitive circuits∗
Yu Dong-Sheng(于东升)a)† , Liang Yan (梁 燕)a) , Herbert H. C. Iub) , and Hu Yi-Hua (胡义华)c)
a) School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou 221116, China
b) School of Electrical, Electronic and Computer Engineering, The University of Western Australia, Perth, Australia
c) School of Electronic and Electrical Engineering, University of Strathclyde, Glasgow, UK

(Received 24 December 2013; revised manuscript received 12 January 2014; published online 15 May 2014)

In this paper, a concise but effective interface circuit for transforming a memristor into meminductive and memcapac-
itive systems is designed. This newly proposed interface circuit, constructed by only two current conveyors, is equipped
with three available ports, which can provide six connecting combinations in terms of one resistor, one capacitor, and one
memristor. For the sake of confirming the design effectiveness, theoretical and simulation discussions are hence introduced
and all the experimental waveforms provide conclusive evidence to validate the correctness of these new mutators. The
most attractive features of this new interface circuit are the floating terminals and convenient practical implementation.

Keywords: memristor, meminductive, memcapacitive, self-excited oscillator

PACS: 07.50.Ek, 84.30.Ng, 85.25.Hv DOI: 10.1088/1674-1056/23/7/070702

1. Introduction replacing a plate of a parallel-plate capacitor with a strained

The memristor was originally envisioned by Chua as the elastic membrane, a bistable non-volatile memcapacitor was
fourth non-linear passive two-terminal fundamental circuit el- realized in Ref. [19] and then the chaotic behavior existing
ement in 1971. [1] In 2009, by taking an extra step, Chua et in this memcapacitive circuit was discussed. Biolek and his
al. generalized the concept of memory devices to the capaci- team have established several behavioral models of memin-
tor and the inductor, and brought forward two other dynamic ductive and memcapacitive systems in accordance with the
elements called the memcapacitor and the meminductor. [2] To- constitutive relations, and they also proposed mutators for sim-
gether with the memristor, the memcapacitor and the memin- ulating a meminductor and a memcapacitor by a grounded
ductor constitute an important class of two terminal circuit memristor. [20–24]
mem-elements, which can retain memory of their past states. By making use of the microprocessor based memristive
The memory features of these elements are related to the cor- emulator proposed in Ref. [10], memcapacitive and memin-
responding internal states and can also be influenced by the ex- ductive systems inherently connected in a series with a re-
ternally imposed control parameters. These elements, as func- sistor were proposed by Pershin and Di Ventra. [25] Refer-
tionally combined in integrated circuits, will certainly play im- ences [24] and [26] pointed out the limitation of the trans-
portant roles in future applications, in the area of non-volatile forming mutators proposed in Ref. [25] and designed a more
memory, low-power and remote sensing, oscillators, neuro- exact memcapacitive emulator without the parasitic resistor. A
morphic and biological systems, quantum computing, etc. [2–5] grounded memcapacitive emulator was experimentally intro-
Currently, since all these three mem-elements are not duced in Ref. [27], of which the memcapacitance can hardly be
commercially available, a lot of emulating methods have been obtained with high precision in consideration of the nonlinear
brought forward to analyze their equivalent dynamical char- response of the light-dependent resistor. Mutators for transfer-
acteristics beforehand. The memristor has attracted relatively ring a memristor into floating memcapacitive and meminduc-
more extensive research attention after the announcement of tive systems were conceptually proposed in Ref. [28]. Interest-
the successful fabrication of a solid memristive system by the ingly, by pointing out that most of the preceding memcapacitor
HP Lab. [5–17] emulators had an identical character of being designed neces-
Note that, in addition to information, memcapacitors and sarily based on the memristor, a new memristor-less memca-
meminductors are capable of storing energy, and therefore, pacitor emulator was contrived in Ref. [29]. Recently, based
could explore new orientations in the technologically impor- on the memristor proposed in Ref. [14], a novel meminductor
tant area of energy storage and circuit operation. [18] As two emulator was designed and experimentally tested in Ref. [30].
newly emerged elements, only a few articles relating to the These emulators have assisted researchers commendably in
meminductor and the memcapacitor have been published. Via discovering the dynamic behaviors and potential applications
∗ Projectsupported by the National Natural Science Foundation of China (Grant No. 51307174), the Fundamental Research Funds for the Central Universities
of Ministry of Education of China (Grant No. 2013QNB28), and the China Postdoctoral Science Foundation (Grant No. 2013M531423).
† Corresponding author. E-mail: dongsiee@163.com

© 2014 Chinese Physical Society and IOP Publishing Ltd http://iopscience.iop.org/cpb http://cpb.iphy.ac.cn

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 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
of these memory elements in circuit design. where ϕAB is defined as the integral of terminal voltage vAB .
These memory elements are of very general interest in Equation (1) apparently shows that the control function of
science and engineering and are potentially useful not just in memductance is of linearity with respect to flux ϕAB . This
information storage, but also apparently in other areas of re- control function can be varied by adding a computing circuit
search. However, since these elements are currently unavail- to the input terminal y1 of the multiplier chip. For example, by
able as commercial off-the-shelf components, this paper fo- adding one more multiplier chip, equation (1) can be modified
cuses on designing a concise interface circuit which can trans- into a quadratic equation in terms of flux ϕAB . In consideration
fer the previously proposed memristive emulator into memin- of simplicity, only the linear flux-controlled memritor emula-
ductive and memcapacitive circuits. tor is considered in this paper. By taking advantage of Ohm’s
law, equation (1) can be rewritten as
2. Floating memristor emulator dϕAB
i = W (ϕAB ) . (2)
Inspired by Ref. [28], a practical memcapacitor emulator dt
without the parasitic resistor and grounded restriction had been
Hence, the current going through the memristor emulator can
formulated and experimentally tested in Ref. [31], by making
be computed by solving Eq. (2), which implies that the inter-
use of the relation between the terminal voltage and the current
nal state of the memristor emulator is dynamically varying in
of a floating memristive circuit. Subsequently, a meminductive
accordance with the integral of the terminal voltage.
circuit inherently parasitized with dissipative elements, resis-
Assuming that a voltage vAB (t) of a square wave with
tor and memristor, was put forward in Ref. [32], also with the
period T is imposed upon the memristor terminals A and B,
assistance of a floating memristor emulator. Clearly, the float-
namely
ing memristive circuit is essential in these two designs. How-
1

ever, the memristive circuit earlier introduced in Ref. [31] has  Am ,
 0≤t < ,
evident insufficiency that the emulator itself cannot guarantee vAB (t) = 2f (3)
1 1
the equality between the input and output currents of its two  −Am ,
 ≤t < ,
2f f
terminals. The memristor emulator used in Ref. [32] has up-
graded the performance by the utilization of two current con- where f is the frequency of the square wave. This square wave
veyors and hence can ensure the current equality. By referring can be represented by means of a Fourier series
to Ref. [32], the memristive circuit of Ref. [31] can be easily  
4Am 1
improved to achieve the current equality by two current con- vFAB (t) = sin(2π f t) + sin(6π f t) + · · ·
π 3
veyors as well, as shown in Fig. 1.
4Am ∞ 1
= ∑ 2n + 1 sin[(4n + 2)π f t]. (4)
π n=0
w(ϕAB) A B
Since flux ϕAB is actually the integral of vAB (t), by carrying
i R2 R4 R7
A out an integral operation on both sides of Eq. (4), it hence can
AD633
R1 i2 be calculated that
νAB R6 x1
R3 C1 x2 v2
i1

y1 w
2Am 1
vϕ ϕAB (t) = − 2 cos(2π f t) + cos(6π f t)
TL084 y2 π f 9
TL084 z 
R5 1
i4 + cos(10π f t) + · · ·
i3 25
x y 2Am ∞ 1
AD844 i =− 2 ∑ cos[(4n + 2)π f t]. (5)
5
z U1 π f n=0 (2n + 1)2
U2 z
i6 x y AD844
B It is worth noting that since the amplitude of the high fre-
quency item is relative small, here, only the first two items
are adopted to represent ϕAB approximately
 
2Am 1
Fig. 1. The circuit diagram of memristor emualtor. ϕAB (t) = − 2 cos(2π f t) + cos(6π f t) . (6)
π f 9

Therefore, a mathematical description of the flux- The memductance hence can be calculated as
controlled memductance can be directly introduced by refer- 1

Am
ring to Ref. [31] W ( f ,t) = 1−
R1 5R6C1 π 2 f
   
1 1 1
W (ϕAB ) = 1+ ϕAB , (1) × cos(2π f t) + cos(6π f t) . (7)
R1 10R6C1 9
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 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
Note that, it can be calculated that possible values of the two 3. Design of meminductive and memcapacitive
cosine items enclosed by the inside bracket in Eq. (7) are lo- circuits
cated in an interval of [−1.11, 1.11]. Therefore, in order to
Since prospective designs of the solid-state meminductor
guarantee positive memductance, the parameter configuration
and memcapacitor have not been started, it is of significant
of the forced voltage is supposed to satisfy the following con-
importance to design effective circuits currently to investigate
dition:
their dynamic behaviors. It has been stressed in Ref. [26]
f 0.22 that, from the view point of circuit response, memcapacitive
> . (8)
Am R6C1 π 2 and meminductive operation models can be realized by the
Based on Eqs. (7) and (8), all the possible values of memduc- appropriate utilization of a memristor emulator. As shown
tance satisfy in Ref. [2], a canonical lossless flux-controlled meminductive
2 and charge-controlled memcapacitive systems can be defined
0<W < . (9)
R1 by the following equations, respectively
The result of Eq. (9) is identical with that obtained in Ref. [31].
Z t 
−1
Actually, for other periodical forcing voltages with different ix (t) = Lm ϕx (τ)dτ ϕx (t), (12a)
−∞
waveforms, etc., triangular wave or sawtooth wave, as long as Z t 
−1
the amplitude of the DC component is equivalent to zero, val- vx (t) = Cm qx (τ)dτ qx (t), (12b)
−∞
ues of memductance satisfy the boundary condition of Eq. (9).
For the sake of simplicity, a sinusoidal forcing voltage is where ϕx (t) is the flux of the inductor, ix (t) is the internal cur-
a more appropriate candidate for approaching the characters of rent, Lm represents the meminductance, vx (t) is the terminal
the memristor with the memductance of Eq. (1). On the basis voltage, qx (t) is the integration of current ix (t), and Cm repre-
of vAB = Am cos(2π f t), the time-points tmax and tmin , corre- sents the memcapacitance.
sponding to the maximal and minimal values of memductance,
3.1. Design of meminductive circuit
respectively, can be computed as
To obtain a circuit with meminductive characteristics,
4m + 1 4m + 3
tmax = , tmin = , (10) there are various amplifier-RC methods, as summarized in
4f 4f
Ref. [33]. In this subsection, a brief meminductive circuit con-
where, m is a natural number. Equation (10) also implies that sisting of one memristor, one capacitor, one resistor and two
the varying period of memductance is identical to the period current conveyors, is newly designed and analyzed. The key
of the forcing voltage. In accordance with Eq. (2), the current part of this circuit is the utilization of the previously proposed
i can then be calculated by floating memristor emulator to achieve nonlinear controllable
Am A2m meminductance, as shown in Fig. 2(a).
i= cos(2π f t) + sin(4π f t)
R1 40πR1 R6C1 f
= i1f + i2f , (11) ix
D

which apparently implies that current i includes two frequency

W(ϕDB)
components, i1f and i2f . The i1f is proportional to imposed
AD844
voltage vAB in terms of coefficient R1 , while i2f possesses the B ix vx
x y
frequency twice as big as vAB and the variable amplitude of AD844
U1 z iz
Cx x U2
frequency-dependence. This frequency character of i2f indi-
ix Rx y z
cates that the curve of i versus vAB is not a straight line but a
ix
Lissajous-like loop, which can be correspondingly shrunk as E
the frequency of the imposed voltage increases. (a)
In the following section, by taking advantage of this im-
proved memristor emulator, an interface circuit using two cur- D B
rent conveyors for transferring a floating memristor into mem- W(ϕDB)
Rm
capacitive and meminductive circuits are discussed. The mem- Rx
capacitive circuit proposed in this paper is different from that B'
using four current conveyors as depicted in Ref. [31]. Al-
though the meminductive circuit addressed in Ref. [32] also Lm

has three ports, reference [32] only pays attention to one con- E
necting combination of meminductive character and more im- (b)
portantly, no experimental results as applied in practical cir-
cuits are presented in Ref. [32]. Fig. 2. Meminductive circuit (a) schematic diagram (b) equivalent circuit.

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 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
The two current conveyor chips, AD844, are labeled as ix
qx1 = −Cx vDB = −Cx , (20)
U1 and U2, respectively. According to their inherent proper- W (ϕDB )
ties, we can obtain qx = qx2 + qx1 . (21)

Combining Eqs. (19)–(21), we can get the following equation

vx = vD , ix1 = iz , (13)
to describe this meminductive circuit:
 
where vD is the voltage of terminal D. The U2 is used to Cx Rx 1
ϕDE = ix + qx Rx + . (22)
change the flowing direction of current iz , which can guaran- W (ϕDB ) W (0.5ϕDB )
tee the relation of ix1 = iz . Based on Ohm’s Law, the following On the basis of Eq. (22), the nonlinear controllable meminduc-
two equations hold: tance hence can be identified as
(−vDB + vDE ) Cx Rx
ix = vDBW (ϕDB ), ix2 = , (14) Lm = . (23)
Rx W (ϕDB )

where, vDE is the voltage source imposed on the two terminals Apparently, comparing Eq. (22) with Eq. (17), the mathe-
of the meminductive circuit and vDB is the voltage across the matical expression of the second item enclosed in the square
memristor emulator, and vB and vE are the voltages of node B bracket is different owing to the coefficient 0.5, which implies
and terminal E, respectively. For capacitor Cx , since vx = vD , that it is incorrect to derive the equivalent memristance directly
the current passing through its two terminals can be calculated from Eq. (22). It can be seen from Eq. (23) that the meminduc-
by tance is controlled by the terminal flux of the equivalent serial
memristor, not by the meminductor itself. Here, the flux of the
dvDB equivalent meminductor can be exhibited in terms of current
ix1 = −Cx . (15)
dt ix or the voltage across the memristor, namely
According to Kirchhoff’s current law, the current flowing into ix
ϕL = Cx Rx = Cx Rx vDB . (24)
a meminductive circuit can be computed as W (ϕDB )

ix = ix2 + ix1 . (16) Since the circuit depicted in Fig. 2(a) includes only one
energy-storage component Cx , equations (17) and (22) actually
By combining Eqs. (14)–(16), we can obtain present a first-order system. Note that, as shown in Fig. 2(b),
  although the voltage of node B can be directly measured from
Cx Rx dix 1
vDE = + ix Rx + . (17) Fig. 1(a), while the voltage of equivalent node B0 can only be
W (ϕDB ) dt W (ϕDB )
indirectly gained by calculation.
Equation (17) indicates that the circuit depicted in Fig. 2(a)
3.2. Design of memcapacitive circuit
can be simplified equivalently as one resistor, one memris-
tor, and one meminductor connected in a series, as shown in By exchanging capacitor Cx and memristor emulator W , a
Fig. 2(b), where the memristor connected in the series with new circuit with the memcapacitive property can be obtained.
the resistor is denoted by Rm . According to Ohm’s law, the As shown in Fig. 3(a), ϕDB is proportional to the integration
equivalent memristance can be identified as of the charge going through capacitor Cx , by defining that σx
is the integral of charge qx , we can obtain
1
Rm = + Rx . (18) Z t
W (ϕDB ) Cx ϕDB = qx dτ = σx . (25)
−∞
Note that, inductance is defined as a parameter to present the
In this case, the flux-controlled memristor can be converted
constitutive relationship between the flux and the current, and
into the σx -controlled memristor emulator. The memductance
since W (ϕAB ) is not constant but flux-dependent, it is im-
hence can be rewritten as
proper to derive the equivalent meminductance directly from  
Eq. (17) in terms of the voltage and the derivative of the cur- 1 σx
W (σx ) = 1+ . (26)
rent. R1 10R6C1Cx
By applying an integral operation to Eqs. (14)–(16), the Referring to the state equations induced in the preceding anal-
following four equalities hold: ysis, we can get
dvDB
  
1 1
Z
qx = vDB 1+ ϕDB dt = ϕDBW (0.5ϕDB ), ix = Cx , (27)
R1 10R6C1 dt
vBE
(−ϕDB + ϕDE ) ix1 = W (σx ) vBD , ix2 = . (28)
qx2 = , (19) Rx
Rx
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 Chin. Phys. B Vol. 23, No. 7 (2014) 070702

ix It is worth noting that since there is no such node corre-

D
sponding to the equivalent node B0 of Fig. 2(b), the terminal
Cx voltages of the equivalent memcapacitor and resistor Rm are
AD844 also incapable of being measured directly.
ix vx
x y AD844
ix B iz 3.3. Transferring interface circuit
W(ϕDB) U1 z x U2
Rx y z Preceding analysis shows that different circuit properties
ix
E can be interestingly obtained by changing the connecting po-
(a) sition of memristor W and capacitor Cx . Here, referring to
D Figs. 2 and 3, a transferring circuit is designed as depicted in
Fig. 4, of which three interface ports are defined by T1 (1, 2), T2
Cm
(3, 4), and T3 (5, 6), respectively. Besides the two previously
B' discussed meminductive and memcapacitive circuits, there are
other four possible connection combinations of memristor W ,
Rm
capacitor Cx , and resistor Rx in terms of the three interface
E ports. The six possible combinations, and corresponding cir-
(b) cuit properties are depicted in Table 1, of which two memin-
Fig. 3. Memcapacitive circuit (a) schematic diagram (b) equivalent circuit. ductive and four memcapacitive circuits can be obtained.

Combining Eqs. (27) and (28), the following set of state ix

D
equations can be used to describe this memcapacitive circuit
dqx qx
vDE = Rx + [RxW (σx ) + 1], (29) 1
dt Cx T
2 AD844
3 4 ix
which demonstrates that the circuit presented in Fig. 3(a) is x y
T AD844
equivalent to a memcapacitor connected in serial with a linear 5 U1 z iz
T x U2
resistor Rx , as redrawn in Fig. 3(b). The nonlinear controllable 6
ix y z
memcapacicitance and Rm hence can be identified as E
ix

Cx
Cm = , Rm = Rx . (30) Fig. 4. Interface circuit.
RxW (σx ) + 1

Table 1. Circuit properties and equivalent parameters according to six combinations.

Connecting combinations
Circuit properties Equivalent parameters
T1 (1,2) T2 (3,4) T3 (5,6)
W Cx Rx meminductive Lm = RxCx /W (ϕDB ), Rm = Rx + 1/W (ϕDB )
Cx W Rx memcapacitive Cm = Cx /(RxW (ϕDB ) + 1), Rm = Rx
W Rx Cx memcapacitive Cm = RxCx /(Rx + 1/W (0.5ϕDB )), Rm = 1/W (ϕDB )
Rx W Cx memcapacitive Cm = Cx /(RxW (0.5ϕDB ) + 1), Rm = Rx
Cx Rx W memcapacitive Cm = RxCx /(Rx + 1/W (ϕBE )), Rm = 1/W (ϕBE )
Rx Cx W meminductive Lm = RxCx /W (0.5ϕBE ), Rm = Rx + 1/W (ϕBE )

4. Simulation analysis figured as: R1 = 33 kΩ, R2 = R3 = R4 = R5 = R7 = 1000 kΩ,

R6 = 51 kΩ, C1 = 100 nF. First, the forcing voltage is con-
SPICE is adopted in this section to verify the correctness
figured to be a square waveform with amplitude Am = 2.8 V
and effectiveness of the newly designed memristive, memin-
and frequency f = 40 Hz. Since i is proportional to vA with
ductive, and memcapacitive circuit.
coefficient R1 , vA can be used to characterize current i. [31] The
Lissajous curve of vAB versus vA is drawn in Fig. 5(a) using
4.1. Improved memristor emulator
a dashed line. This curve looks like fan blades and is simi-
The memristor emulator is connected with an ac voltage lar to Fig. 8, as discussed in Ref. [13]. The most important
source in parallel for the test. The circuit parameters are con- character of a memristor is the frequency-dependence of the
070702-5
 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
pinched hysteresis loops. [34] As is also presented in Fig. 5(a), where the bigger value associates with the rising region of vAB
the pinched hysteresis loop of f = 80 Hz is obviously shrunk in the time domain. Note that, all the three curves are symmet-
compared with the dashed curve of f = 40 Hz. This simu- ric in terms of the coordinate point (0, 0.0303) on the voltage
lated result is evidently consistent with the preceding theoret- versus the memductance plane and the maximal and minimal
ical analysis of Eq. (7). values of the memductance both emerge at vAB = 0 V; these
simulation results show great agreement with the theoretical
analysis. Based on Eq. (1) and the given system parameters,
4
80 Hz varying intervals of the emulator memductance can be calcu-
3 40 Hz lated within one excitation voltage period, namely, (0.0161,
2 0.0445), (0.0232, 0.0374), and (0.0300, 0.0359) mS.
1
vA /V

0 0.045 20 Hz
40 Hz
-1 1 kHz
0.040
-2
0.035
-3

W/mS
(a) 0.030
-4
-3 -2 -1 0 1 2 3 0.025
vAB /V
0.020
4
20 Hz 0.015
40 HZ
1 kHz -4 -3 -2 -1 0 1 2 3 4
2
vAB /V

Fig. 6. (color online) Calculated curve of memductance.

vA /V

4.2. Meminductive and memcapacitive emulators

-2
From Eq. (24) we can clearly see that the flux of the
(b) equivalent meminductance in Fig. 2(b) is actually proportional
-4 to the voltage across the memristor, namely vDB . By setting
-3 -2 -1 0 1 2 3 Rx = 10 kΩ, Cx = 1 µF, vDE = 4.56 sin(2π f t), this circuit is
vAB /V
tested using SPICE and the curves of testing results are plot-
Fig. 5. (color online) Simulated results (a) vA versus vAB with the forc-
ing voltage of the square wave, (b) vA versus vAB with the forcing volt- ted in Fig. 7. As discussed in Ref. [32], ix is proportional
age of the sinusoidal wave. to vD with coefficient R1 and since flux ϕL is in proportion
to vDB , vD and vDB are collected instead here to represent ix
Then, a forcing voltage of vAB = 3 cos(2π f t) is used to and ϕL , respectively. To probe the time domain behaviors of
further test this memristor emulator. Figure 5(b) displays the the equivalent meminductor, vD , vDB , and vDE are measured
Lissajous curves of vA versus vAB at f = 20 Hz, f = 40 Hz, at f = 24.1 Hz and the Lissajous curves at f = 24.1 Hz and
and f = 1 kHz, respectively, while the memductance in terms f = 11.6 Hz are correspondingly drawn, as shown in Fig. 5.
of vAB is displayed in Fig. 6. Figure 5(b) clearly shows that Figure 5(b) distinctly displays that the pinched hysteresis loop
the Lissajous curves in the voltage–current plane appear in behaves also as an inclined number “8”.
a pinched hysteresis loop as an inclined “8”. By comparing Equation (12) reveals that the current is zero whenever the
these three curves, as the frequency increases, the pinched flux is zero. Figure 5(b) also shows a pinched hysteretic loop
hysteresis loop gradually degenerates to a straight line passing exactly passing through the origin and there may be at most
through the origin, of which the slope depends on the ampli- two values of the flux for a given current (using vD instead). It
tude and shape of the excited voltage signal. In other words, at has been discussed in Ref. [2] that the frequency-dependence
a very high frequency, there is not enough time for any kind of of the pinched hysteresis loop is also an important property of
memristance change during a period of the control parameter, the meminductor. This property can also be easily unfolded
so that this emulator operates as a linear resistor. This simu- by comparing the two Lissajous curves given in Fig. 5(b). The
lated result is in good agreement with the theoretical analysis area of each lobe of the pinched hysteresis loop shrinks as the
of Eq. (11). frequency of the forcing signal increases. Actually, the rel-
Figure 6 demonstrates that for a given value of forcing ative decrements of current ix and terminal voltage of mem-
voltage vAB , there are two possible values of memductance, ristor (vDB ), as shown in Fig. 7(b), indirectly reflect that the
070702-6
 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
impedance of the equivalent meminductor is increased by the between current ix and vcm is always π/2. These circuit char-
higher forcing frequency. This characteristic is consistent with acteristics clearly indicate that our newly proposed circuit has
the regular resistive and inductive circuit. the resistive and nonlinear capacitive property. The waveform
shapes of current ix and voltage vcm are noticeably nonstan-
dard sinusoidal, which can partially reflect the nonlinearity of
4 the σx controlled memcapacitance.
vDE
vD
vD&vDB&vDE /V

2
4 0.4
vDE
vcm
0
vD
2 0.2

vDB&vDE&vcm /V
-2
vDB

ix/mA
0 0
-4
(a)

0.50 0.52 0.54 0.56 0.58 0.60 0.62 -2 -0.2

ix
t/s
vDB
-4 (a) -0.4
4
11.6 Hz 0.50 0.55 0.60 0.65 0.70
24.1 Hz
t/s
2
4
8.1 Hz
12.1 Hz
vD /V

0
2
vcm /V

-2 0

(b)
-4 -2
-3 -2 -1 0 1 2 3
vDB /V
(b)
Fig. 7. (color online) Simulation results of the meminductive circuit (a) -4
-3 -2 -1 0 1 2 3
time domain waveforms of vD , vDE , and vDB . (b) Lissajous curves.
vDB /V
Fig. 8. (color online) Simulation results of the equivalent memcapac-
From the equivalent circuit in Fig. 2(b), we can see that
itive circuit (a) time domain waveforms of ix , vDE , vcm , and vDB . (b)
one linear resistor and one memristor are unavoidably con- Lissajous curves.
nected in a series with the equivalent meminductor. Hence,
there must be a phase difference between the terminal voltage The Lissajous curves in the voltage–charge plane cor-
and the internal current and the value of the phase difference responding to different forcing frequencies, as revealed in
can be adjusted by the forcing frequency and the resistor con- Fig. 8(b), reflects that the memcapacitance is also nonlinear
nected in the serial circuit. To show the phase difference, the frequency dependent and the terminal voltage of the serial
time domain waveforms of terminal voltage vDB and internal memcapacitor is reduced as the frequency increases, which
current (using vD instead) are presented in Fig. 7(a). Evidently, also displays the inherent resistive and capacitive property of
the current lags behind the voltage and the phase difference this circuit.
confirms clearly that this proposed circuit possesses the me- As a matter of fact, when the forcing frequency increases
minductive property. towards infinity, both the equivalent meminductor and memca-
To test the memcapacitive behaviors, the forcing voltage, pacitor will act as linear inductor and capacitor, respectively.
vDE = 3.78 sin(2π f t), is introduced to energize the circuit of
Fig. 3(a). Although the voltage across memcapacitor vcm is di-
rectly immeasurable, it can be calculated by (vDE –Rx ix ) based
5. Experimental results
on simulation data. The simulation results in the time-domain Previously, meminductive and memcapacitive circuits are
are displayed in Fig. 8(a) as f = 12.1 Hz, from which it can achieved based on the floating memristive emulator. From this
be seen that forcing voltage vDE is lagging behind current ix point of view, the performance of the memristive emulator can
but ahead of vcm in terms of phase, and the phase difference be reflected by the experimental quality of meminductive and
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 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
memcapacitive circuits. Therefore, for the sake of simplicity, 4
only meminductive and memcapacitive circuits are put into ex-
3 11.6 Hz
perimental confirmation of correctness and practicability.
2

1
5.1. Fundamental characteristics

vD /V
0

Since current ix is hard to measure precisely, differing -1

from the simulated curves in Fig. 8(a), the terminal voltage -2

of the equivalent memcapacitor is calculated by -3 24.1 Hz (a)
-4
  -3 -2 -1 0 1 2 3
Rx vDB /V
vcm = vDE − vrx = vDE − vBE − vD , (31)
R1
4

where vrx is the voltage across the equivalent serial resistor in 3

Fig. 3(b). 2

Based on the same parameters as in the simulation, the 1 8.1 Hz

vcm /V
pinched hysteresis loops for meminductive and memcapacitive 0
circuits are presented in Fig. 9. These experimental pinched -1 12.1 Hz
hysteresis loops, which are of high similarity with the simu-
-2
lation results, behave as inclined number “8” passing through
-3 (b)
the origin and also can be shrunk as the forcing frequency in-
-4
creases. Via zooming in experimental loops, it can be noticed -3 -2 -1 0 1 2 3
that there are slight differences of amplitudes in comparison vDB /V

with the simulated loops of Figs. 7(b) and 8(b). These small Fig. 9. (color online) Pinched hysteresis loops (a) meminductive loops
(b) memcapacitive loops.
differences are of the highest possibility caused by the inaccu-
racy of practical components. In order to compare the exper-
Table 2. Comparison of amplitude as forcing frequency f = 24.1 Hz.
imental results with simulated results more precisely, by tak-
ing Fig. 9(a) for demonstration, amplitude spectrums of vari- f /Hz
vD /V vDB /V

ables vD and vDB are captured by taking advantage of FFT. Experiment Simulation Error Experiment Simulation Error
0 0.025 0.015 0.010 0.010 0.003 0.007
In accordance with the forcing frequency of 24 Hz, the am-
24.1 2.221 2.247 −0.026 2.255 2.276 −0.021
plitudes of Fourier components at f = 0 Hz, f = 24.1 Hz,
48.2 0.313 0.299 0.014 0.054 0.043 0.011
f = 48.2 Hz, f = 72.3 Hz, and f = 96.4 Hz are extracted and
72.3 0.023 0.021 0.002 0.017 0.014 0.003
exhibited in Table 2, respectively. By comparing the compo- 96.4 0.010 0.013 0.003 0.008 0.009 0.001
nent amplitudes in Table 2, it can be numerically revealed that
the difference between the experiment and simulation results Table 3. Comparison of amplitude as forcing frequency f = 11.6 Hz.
is extremely small. Additionally, the amplitude differences
vD /V vDB /V
corresponding to forcing frequency f = 11.6 Hz, as listed in f /Hz
Experiment Simulation Error Experiment Simulation Error
Table 3, are also quite small but comparatively greater than 0 0.217 0.203 0.014 0.101 0.060 0.041
those shown in Table 2. This result demonstrates that these ex- 11.6 2.652 2.808 −0.156 2.934 3.094 −0.160
perimental errors can be lessened by means of increasing the 23.2 1.203 1.150 0.053 0.255 0.203 0.052
forcing frequency. Since these errors are very small, it can be 34.8 0.131 0.119 0.012 0.024 0.015 0.009

concluded that the experimental results are in good agreement 46.4 0.007 0.010 −0.003 0.001 0.001 0.000

with the theoretical analysis and simulation results.

Note that, both experimental and simulated variables of 5.2. Behaviors of meminductive circuit connected with ca-
vD and vDB have a relative small DC component, which can pacitor
be attributed to the non-ideality raised in experimental imple- To test the dynamical characteristics of the meminductive
mentation. circuit, here a canonical capacitor Cr is adopted for serial con-
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 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
nection with the meminductive circuit, which is denoted as the frame, maintains the internal dynamical features of the induc-
Rm LmCr circuit for simplicity, as shown in Fig. 10. tive property. The nonstandard sinusoidal shapes of vD and
The set of state equations for describing this Rm LmC cir- vDE exactly illustrate the nonlinear characteristics of the me-
cuit can be expressed as minductive circuit. These experimental results provide us with
    comprehensive confirmation that the newly proposed memin-
dqxc W (ϕDB ) 1


 = ϕPE − ϕPD − q xc Rx + , ductive circuit can be used to construct a dynamic circuit with
 dt Cx Rx W (0.5ϕDB )
the meminductive characteristic.


 dϕ 1
PD
= qxc , (32)

 dt Cr

 dϕDB ixc CH2:vPD
CH1:vPE
= .


dt W (ϕDB )


ixc
P D
Cr

W CH3:vD MATH:vDE
meminductive circuit

B
Fig. 11. (color online) Waveforms of vPE , vPD , vD , and vDE at f =
10.72 Hz. The horizontal coordinate scale is 25 ms/division and the
Rx vertical coordinate scale is 1 V/division.

Lm
MATH:vDE
CH2:vPD

Fig. 10. Meminductive circuit connected with capacitor.

CH3:vD
Despite the complexity of solving analytically, this CH1:vPE
second-order set of equations can be numerically computed.
Here, we only focus on the dynamical characteristics of the Fig. 12. (color online) Waveforms of vPE , vPD , vD , and vDE at f =
20.42 Hz. The horizontal coordinate scale is 10 ms/division and the
meminductive circuit from the viewpoint of the experiment. vertical coordinate scale is 1 V/division.
A sinusoidal voltage vPE = 2.3 sin(2π f t) is then imposed
on the terminals of this Rm LmC circuit for testing. Under
the configuration of f = 10.72 Hz and Cr = 0.22 µF, voltage 5.3. Behaviors of memcapacitive circuit as connected in
waveforms of vPE , vPD , vD , and vDE are painted by sampled Wien-bridge oscillator
data, as given in Fig. 11, of which vDE is obtained by vPE – The capacitive property of the memcapacitive circuit can
vPD using computational function of the oscilloscope MATH also be confirmed by analyzing the phase relationships among
button. Note that, based on the preceding analysis, the volt- waveforms of voltage and current in the time domain. By re-
age of node D is proportional to the current ixc going through configuring the forcing voltage as vDE = 3.78 sin(24.2πt), the
this series circuit, therefore, vD is employed here to display voltage waveforms of vDE , vDB , vcm , and vrx are described in
current ixc . Figure 11 shows that system current ixc is ahead Fig. 13, where vrx and vcm are obtained by calculating Eq. (31)
of terminal voltage vPE with regard to phase, which reflects based on the sampled data. The vDB is in proportion to the
that, at f = 10.72 Hz, this serial system is apparently of a ca- charge passing through the equivalent memcapacitor. The vDB
pacitive property. By rearranging the forcing frequency into and vcm are synchronously crossing the horizontal coordinate,
f = 20.42 Hz, the corresponding experimental waveforms are which evidently accords with the simulated Lisssjous curves
depicted in Fig. 12. Interestingly, in this case, current ixc lags in Fig. 9(b). Since vrx is proportional to the current going
behind terminal voltage vPE with regard to phase, which indi- through terminals D and E, vrx is adopted here to represent
cates that this serial system can show dynamic behaviors of an the current waveform and clearly, there is a phase-difference
inductive circuit under the forcing frequency of f = 20.42 Hz. between forcing voltage vDE and vrx , and circuit current ix is
It worth noting that vDE maintains the phase ahead of cur- leading ahead of forcing voltage vDE with regard to phase. The
rent ixc even at different forcing frequencies, which means phase difference among these waveforms reveals the resistive
that the meminductive circuit, enclosed by the dashed-line and capacitive property of this memcapacitive circuit.
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 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
vDE vDB The resonant frequency can be altered by changing the
values of R10 (R11 ) and C2 (C3 ). One attractive part of this os-
cillator is that changing frequency causes no influence on the
amplitude and phase angle of the output sinusoidal waveform.
It is worth noting that, there is another necessary condition for
achieving self-excited oscillation of this oscillator, namely, the
vrx
serial bridge arm must be of a capacitive circuit.
vcm
In order to test the dynamical property of the memcapac-
itive circuit in Fig. 3, by switching S to node h, the serial RC
Fig. 13. (color online) Waveforms of vDE , vDB , vrx , and vcm at f =
12.1 Hz. The horizontal coordinate scale is 25 ms/division and the ver-
bridge arm is replaced by the memcapacitive circuit. In order
tical coordinate scale is 1 V/division. to configure this oscillator properly, the resistance of Rx can
be easily installed as the same value of R10 . In accordance
In the next step, this memcapacitive circuit is applied with the preceding analysis, the memcapacitance of Cm is in-
into a typical self-excited oscillating circuit for the valida- constant and defined by the amplitude and frequency of the
tion of practicability. The Wien-bridge oscillator has been
voltage imposed on nodes h and a. Therefore, due to the influ-
widely used to produce sinusoidal voltage signals. As shown
ence from the nonlinear equivalent memcapacitor, the output
in Fig. 14, by connecting switch S to node g, a typical Wien-
waveform will be no longer standard sinusoidal, but include
bridge oscillator can be achieved. An adjustable negative-
feedback loop is constructed by R8 , R9 , and potentiometer Rp . rich sub-harmonic components. However, as long as the value
The two diodes are introduced to stabilize the amplitude of the of feedback gain Af is big enough, this circuit is capable of
output voltage. In order to achieve optimal output uo of sinu- self-excited oscillating.
soidal voltage, the system parameters are usually configured The parameters utilized for experimental validation are
as configured as: R8 = 6.8 kΩ, R9 = 10 kΩ, R10 = 100 kΩ,
Rp1 + R9 + R8 //RD C2 = 1 µF; RP is a potentiometer with a maximum resistance
C2 = C3 , R10 = R11 , Af = ≥ 2, (33) of 10 kΩ, while RP1 and RP2 are initialized as 0 kΩ and 10 kΩ,
Rp2
respectively. The parameters employed here to implement the
where Af is the feedback gain of the op amp; RD is the on-
memcapacitive circuit are identical with those used for the pre-
state resistance of the diode; node b is the non-inverting input
ceding simulation analysis. Two diodes connected in the neg-
terminal of the operational amplifier, and Rp1 is the resistance
ative feedback loop are 1N4118 with a 0.45 V forward voltage
between resistor R9 and node b, while Rp2 is the resistance be-
tween the ground and node b. The resonant frequency of this drop. The quad operational amplifier chip TL084 is adopted
oscillator can be calculated by here to achieve the self-oscillation, due to its advantages of low
cost, low distortion, low noise, and low drift with wide band-
1 1
fres = √ = . (34) width. By increasing the value of RP1 (decreasing RP2 ), the
2π R10 R11C2C3 2πR10C2
output voltage will start to oscillate with a relative small ampli-
tude and then evolve into a periodically alternating waveform.
S
By adjusting RP2 into 185 Ω, the oscillating waveforms of out-
g h put voltage uo and uf are obtained and shown in Fig. 15. The
amplitude and period of these two oscillating waveforms are
memcapacitive circuit

Cm steady, but clearly in nonstandard sinusoidal shape. Similar to

C 1N4118
a typical Wien-bridge oscillator, uo and uf also simultaneously
R
passes through zero. However, in each period, the negatively
R
R Rx oscillating duration T1 (13.6 ms), as marked in Fig. 15, is much
1N4118
less than the duration of positive voltage, T2 . The distortion
a
of output voltage, as compared to the typical Wien-bridge os-
b cillator, can be attributed to the nonlinearity and time-variant
uf Rp uo
C R
TL084 capacitance of the equivalent memcapacitor. The fundamen-
tal frequency of this oscillating voltage signal is measured at
about 32.2 Hz, which discloses the equivalent average mem-
Fig. 14. Wien bridge oscillator. capacitance approximately equaling to 24.76 nF.
070702-10
 Chin. Phys. B Vol. 23, No. 7 (2014) 070702
circuits is presented. The unavoidable serial resistor and float-
ing terminals explore the main specific features of these me-
CH1:uo
minductive and memcapacitive circuits. The Pspice based
simulation and experimental results manifest that these newly
proposed meminductive and memcapacitive circuits are capa-
ble of providing reliable operational performance. The most
CH2:uf attractive feature of these new meminductive and memcapac-
itive circuits are their convenient experimental implementa-
T1 T2 tions and potential practical applications in electronic circuits.
All the circuit components used in this design are common
Fig. 15. (color online) Waveforms of uo and uf . The horizontal coordi- purchasable devices and there is no requirement for any spe-
nate scale is 10 ms/division and the vertical coordinate scales are CH1: cial or expensive components.
5 V/division, CH2: 200 mV/division.

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