Ev12aq600 PDS

EV12AQ600
Quad 12bit 1.5 Gsps ADC with embedded

cross-point switch, Digitizing up to 6 GSps
Datasheet 1203
OVERVIEW At -8 dBFS output level:

- Fin = 2980 MHz (NZ4): ENOB: 8.3 bit / SFDR:
EV12AQ600 is a quad channel 12-bit 1.5 GSps ADC. 66 dBFS (EFPBW)
The built-in Cross-Point-Switch (CPS) allows multi- - Fin = 3730 MHz (NZ5): ENOB: 8.2 bit / SFDR:
mode operation with the capability to interleave the 67 dBFS (EFPBW)
four independent cores in order to reach higher - Fin = 5300 MHz (NZ5): ENOB: 8.1 bit / SFDR:
sampling rates. In 4-channel operating mode, the four 64 dBFS (EFPBW)
cores can sample, in phase, four independent inputs
at 1.5 GSps. In 2-channel operating mode, the cores SFDR@-8dBFS is better than 60 dBFS up to the 8th
are interleaved by 2 in order to reach 3 GSps Nyquist and ENOB is better than 7.9 bit.
sampling rate on each of two inputs. In 1-channel
operating mode, a single input is propagated to each Broadband performance at -14dB loading factor:
of the four cores which are interleaved by 4 in order to 4 channel mode at 1.5 GSps over 600MHz bandwidth
reach a sampling rate of 6 GSps. This high flexibility - NPR = 44 dB in 1st Nyquist (NFPBW)
enables digitization of IF and RF signals with up to 3 - NPR = 43.5 dB in 2nd Nyquist (NFPBW)
GHz of instantaneous bandwidth. - NPR = 43 dB in 3rd Nyquist (EFPBW)
With an extended input bandwidth above 6 GHz - NPR = 42.5 dB in 4th Nyquist (EFPBW)
(EFPBW) the EV12AQ600 allows sampling of signals 1 channel mode at 6 GSps over 2400MHz bandwidth
directly in the C-band (4-8 GHz) without the need to - NPR = 42 dB in 1st Nyquist (NFPBW)
translate the signal to baseband through a down- - NPR = 40 dB in 2nd Nyquist (EFPBW)
conversion stage.
SFDR in 4 channel mode without H2 and H3
The ADC includes a multiple ADC chained
harmonics is better than 70 dBFS at -1 dBFS up to
synchronization feature to enable design of multi-
5980MHz.
channel systems found in phased-array or MIMO
applications. The 0.5 dB Gain Flatness in extended bandwidth is
typically 4GHz.
The EV12AQ600 enables the qualification of a single
component which is capable of meeting a wide variety FEATURES
of application needs from single to multi-channel, from
baseband to more than 6 GHz of input bandwidth. 1 Vpp 100Ω differential DC/AC coupled input voltage
The latency is 126 system clock cycles. 100Ω Differential input AC coupled clock
Cross-point switch enabling 1, 2 or 4 channel mode at
The device is built in a non-hermetic flip-chip package 6 GSps/3 GSps/1.5 GSps
using HiTCE glass ceramic material in order to reach
optimized RF performance and higher pin density. 4.5/6GHz selectable analog input bandwidth (-3dB)
This circuit is designed, manufactured and will be Low Latency ESIstream serial link at 12 Gbps
qualified to be compliant with ESCC (European Space
Components Coordination) and QML-Y space Power supply: 3.3V (analog), 2.5V (I/O), 1.2V (digital),
requirements. optional 1.8V (SPI)
Power consumption: 6.6W
PERFORMANCE
SPI digital interface (gain, offset, sampling delay
Single core performance
adjust, test modes)
4 channel mode at 1.5Gsps at -1dBFS output level:
- Fin = 748 MHz (NZ1): ENOB: 8.7 bit / SFDR: One time programmable anti-fuses for calibration
71 dBFS using normal bandwidth (NFPBW) settings
- Fin = 1480 MHz (NZ2): ENOB: 8.4 bit / SFDR:
63 dBFS (NFPBW) ADC Gain, Offset, Sampling delay adjustment
- Fin = 1900 MHz (NZ3): ENOB: 8.1 bit / SFDR: Package: CBGA323 (HiTCE) 16x16mm pitch 0.80mm
64 dBFS (NFPBW)
Clock and SYNC chaining
Extended temperature range: Tc -55°C / Tj +125°C
Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the
consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS
accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices
in accordance with information contained herein.
Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 Saint-Egrève, FranceHolding Company: Teledyne e2v Semiconductors SAS
Telephone: +33 (0)4 76 58 30 00
Contact Teledyne e2v by e-mail: hotline-bdc@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations centres.
1203B-BDC-04/18 page 1 Teledyne e2v Semiconductors SAS 2018

EV12AQ600
INTRODUCTION
This document is the Preliminary Datasheet of 12-bit 4x1.5GSps ADC with embedded Cross Point Switch (P/N
EV12AQ600)
Teledyne e2v Semiconductors SAS 2018 Document subject to disclaimer on page 1 1203B-BDC-04/18
page 2
EV12AQ600
1 DESCRIPTION
Figure 1 - Quad 12-bit ADC with 12Gbps serial link
EV12AQ600 is a quad 12 bit 1.5Gbps ADC featuring a built in cross-point switch (controlled thru the SPI) allowing
1, 2 or 4 channel digitizing at respectively 6 GSps, 3 GSps or 1.5 GSps data rate.
The four ADC cores can operate in phase or interleaved (option controlled thru the SPI). External clock must be
provided at four times the individual sampling rate.
The architecture uses four high sampling rate single cores (up to 1.5GSps) without interleaving thus providing high
level of spectral purity.
Data is output on a short latency serial link at up to 12 Gbps, using ESIstream protocol.
ADC synchronization is possible through SYNC pin and multiple ADC synchronization is simplified thanks to ability
of SYNC chaining through SYNCO.
Digital CMOS inputs levels can be configured in 1.8V, 2.5V or 3.3V logic compatibility.
Tuning and functionality are controlled thru a Serial Peripheral Interface (SPI):
Functionalities controlled thru the SPI are:

 Test mode activation and selection (ramp, PRBS, …)
 Clocking modes: 4 ADC cores sampling simultaneously, 2 ADC cores sampling simultaneously in
opposition with 2 others, 4 ADC cores interleaved.
 Clocking features: enable/disable CLKOUT, SSO and SYNCO outputs (in order to save power if these
features are not needed).
 Inputs selection: 4 ADC cores interleaved and driven by the same input IN0 (or IN3), 2 ADC cores driven
simultaneously by IN0 (and IN3), 4 ADCs core driven simultaneously by IN0, IN1, IN2 and IN3.
 Analog input bandwidth: 4.5GHz (nominal) or 6GHz (extended)
 Sampling Delay Adjust enabled (for fine tuning of aperture delay) or disabled (recommended for clock Jitter
Reduction)
 Calibration selections: factory with OTP(recommended) or custom with SPI registers
 Selection of bit functionality: In range, Parity Bit, timestamp or Trigger bit.
 Trigger mode or SYNC select (in trigger mode the input on SYNCTRIG is propagated with the same delay
as the Analog input, in SYNC mode the input on SYNCTRIG is used to reinitialize internal clock dividers of

EV12AQ600
the ADC, SYNCO is a synchronized copy of SYNCTRIG, for the serial link version PRBS are reset by a
SYNC pulse).
 Swing Adjust: Output swing of both serial links and timer CML or LVDS buffers is reduced by 30% for power
dissipation reduction purpose.
 Output buffer impedance adjust (trim by a range of 20%) to improve transmission
 12 Gbps Serial link polarity can be inverted
The ADC features internal DACs controlled thru the SPI for tuning:
 Sampling Delay Adjust 12 bit with 120ps tuning range :
o 2 bit for coarse step (~ 30ps/step)
o 10 bit for fine step (~ 30fs/step)
 Gain Adjust: 4096 steps (12 bit DAC), ± 214 LSB (±0.9 dB) full scale variation, step of ~0.43 LSB.
 Offset Adjust: 512 steps (9 bit DAC), ± 27 LSB offset variation, step of ~ 0.11 LSB.
 Phase Adjust: 512 steps (9 bit DAC), ± 0.9 ps phase variation, step of ~3.5fs
 Analog Input impedance termination trimming (5 bit DAC, 2.5Ω step) common to all analog inputs
 Input common mode trimming (5 bit DAC) common to all analog inputs, step of 5mV
 CML output impedance termination trimming (2 bit DAC) by lane, 14 Ω step.
page 4
EV12AQ600
2 SPECIFICATIONS
2.1 Absolute Maximum Ratings
Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other
parameters are within specified operating conditions. Exposure above those conditions may cause permanent
damage. Long exposure to maximum ratings may affect device reliability
Table 1. Absolute Maximum ratings

Value
Parameter Unit
Min Max
Analog supply voltage 3.3V VCCA AGND – 0.3 3.8 (TBC) V
Output supply voltage 2.5V VCCO GNDO – 0.3 TBD V
Digital supply voltage 1.2V VCCD DGND – 0.3 TBD V
SPI supply voltage 1.8V, 2.5V or 3.3V VCC_SPI DGND – 0.3 TBD V
VSPI_SEL supply voltage VSPI_SEL TBD TBD V
INxN or INxP
Analog input peak voltage AGND – 0.3 VCCA + 0.3 V
(x=0,1, 2 or 3)
Maximum difference between VIN and VINN
| INxP – InxN |
(AC signal) in BIASED and Non BIASED 4.8 (TBC) Vppdiff
(x=0,1, 2 or 3)
mode
Clock input voltage VCLKP or VCLKN AGND – 0.3 VCCA+ 0.3 V
Maximum difference between VCLK and VCLKN |VCLKP - VCLKN| 4 Vppdiff
SYNC input peak voltage VSYNCP or VSYNCN AGND – 0.3 VCCA+ 0.3 V
Maximum difference between VSYNC and
|VSYNCP – VSYNCN| 4 Vppdiff
VSYNCN
CSN, SCLK, RSTN,
SPI input voltage& STBY DGND - 0.3 VCC0 + 0.3 V
MOSI, STBY
Max Junction Temperature TJ 150 °C
Storage Temperature Tstg -65 150 °C
VDIODEA input voltage to prevent leakage
VDIODEA -0.3 0.30 V
(VDIODEC=GND)
Maximum input current on DIODE IDIODEA 1 mA
All integrated circuits have to be handled with appropriate care to avoid damages due to ESD. Damage caused by
inappropriate handling or storage could range from performance degradation to complete failure.
Input buffers and associated ESD protection have been designed to allow for “cold sparing”.
VCCA
OUTN OUTP
500mVpp 500mVpp
DC blocking
50Ω Line
VINP
DC blocking ESD
50Ω Line ESD
VINN
AGND
Figure 2 – Analog input scheme regarding max ratings

EV12AQ600
2.2 Qualification requirements

This circuit is designed and manufactured and will be qualified to be compliant with space requirement (ESCC and QML
specifications).
Parameter Symbol Value Unit

Die operating life at Tj =degC HTOL TBD Years
ESD protection (HBM) HBM 1000 V
Latch up (JEDEC 78A) LU +/- 100 mA
2.3 Recommended conditions of use

Table 2. Recommended conditions of use
Parameter Symbol Comments Recommended Value Unit
Analog supply voltage VCCA Analog Part 3.3V V
Output supply voltage VCCO Output buffers 2.5V V
Digital supply voltage VCCD Digital buffers 1.2V V
1.8V if VD = 1.8V
SPI supply voltage VCC_SPI 2.5V if VD = 2.5V V
3.3V if VD = 3.3V
Differential analog input voltage 1 Vpp
VIN -VINN
(Full Scale) 1 dBm
Clock input power level PCLK PCLKN 1 dBm
VIL 0
Digital CMOS input VD V
VIH 3.3 or 2.5 or 1.8 (1)
External Clock frequency Fc ≤6 GHz
Operating Temperature Range TC; TJ -55°C <TC ; TJ< 125°C °C
Note 1: To be configured depending on configuration of pin VSPI_SEL. Refer to section 5.1.
page 6
EV12AQ600
2.4 Electrical Characteristics for supplies, Inputs and Outputs

Unless otherwise specified:
Typical values are given for typical supplies VCCA= 3.3V, VCCD = 1.2V, VCCO = 2.5V at ambient temperature with
Fclk=6GHz and with nominal mode of the SPI (SDA, CLKOUT and SYNCO disabled).
Minimum and Maximum values are given over temperature and power supplies.
Table 3. Electrical characteristics for Supplies, Inputs and Outputs

Parameter Symbol Min Typ Max Unit Note
RESOLUTION 12 bit
POWER REQUIREMENTS
Power Supply voltage
VCCA 3.15 3.3 3.45 V
- Analog
VCCO 2.35 2.5 2.65 V
- Output
VCCD 1.1 1.2 1.3 V
- Digital (1)
VCC_SPI See note 1 See note 1 See note 1 V
- SPI
Power Supply current
- Analog ICCA 1675 mA
- Output
full swing ICCO 365 mA (2)
reduced swing ICCO 330 mA
- Digital ICCD 195 mA
- SPI ICC_SPI 0.2 mA
Power Supply current standby mode
- Analog ICCA 660 mA
- Output ICCO 19 mA
- Digital ICCD 20 mA
- SPI ICC_SPI 0.2 mA
Power dissipation
Full power mode W
full swing PD 6.76 W (2)
reduced swing 6.65 W
standby mode 2.2 W
Maximum number of power-up NbPWRup 1E6 (3)
ANALOG INPUTS
Common mode compatibility for analog inputs AC or DC (4)
Input Common Mode VICM 1.6 V
Full Scale Input Voltage range on each single mVpp
ended input VIN-pp 1000 Diff
Analog Input power Level PIN +1 dBm

(in 100 differential termination)
Input leakage current IIN 40 µA
Input Resistance (differential)
- before digital trimming through SPI RIN 100 

(5)
- After digital trimming through SPI at given 100
temperature
Cross-talk between inputs @ Fin=2.4GHz 70 dB
CLOCK INPUTS
Source Type Low Phase noise Differential Sinewave
Clock input common mode voltage VCM 2.4 2.6 2.8 V
Clock input power level in 100 PCLK, CLKN TBD +1 +7 dBm
VCLK or
Clock input voltage on each single ended input TBD ±250 ±500 mV
VCLKN
Clock input voltage into 100 differential clock | VCLK -
TBD 1 2 Vpp
input VCLKN |
Clock input minimum slew rate
SRCLK 8 12 GV/s
(square or sinewave clock)
Clock input capacitance (die + package) CCLK 1 pF
Clock input resistance (differential) RCLK TBD 105 TBD  (5)
Clock Jitter (max. allowed on clock source) (6)
Jitter 70 fsrms
For 6 GHz sinewave analog input
Clock Duty Cycle Duty Cycle TBD 50 TBD %

EV12AQ600
CLOCK output (CLKOUT)

Logic Compatibility CML
Output levels (swing adjust off = full swing)
50 transmission lines,
100 (2 x50differential termination
VOL VccA – 0.31 V
Logic low VOH VccA-0.14 V
Logic high VOH- VOL 175 mVp
Differential output VOCM VccA - 0.22 V
Common mode
Output levels (swing adjust on = reduced swing)
100 (2 x50differential termination VOL VccA – 0.17 V
Logic low VOH VccA-0.09 V
Differential output VOCM VccA - 0.13 V
Common mode
SYNC, SYNCN Signal
Input Voltages to be applied
Swing VIH- VIL 100 350 450 mV
Common Mode VICM 1.125 1.25 1.375 V
SYNCTRIGP, SYNCTRIGN input capacitance CSYNC 1 pF
SYNCTRIGP, SYNCTRIGN input resistance RSYNC 118 
Input digital signals (CSN, SCLK, RSTN, MOSI)
Low level threshold of Schmitt trigger
- Vcc_spi = 2.5V Vtminusc 0.35 * VCCSPI V
- Vcc_spi = 1.8V or 3.3V 0.8
High level threshold of Schmitt trigger
- Vcc_spi = 2.5V Vtplusc 0.65 * VCCSPI V
- Vcc_spi = 1.8V or 3.3V 1.70
CMOS Schmitt trigger hysteresis Vhystc 0.10 * VCCO V
CMOS low level input current (Vinc=0 V) lilc 300 nA
CMOS high level input current (Vinc=VCCD
lihc 1000 nA
max)
CMOS low level output voltage (lolc = 3 mA) Volc 0.20 * VCCSPI V
CMOS high level output voltage (lohc = 3 mA) Vohc 0.8 * VCCSPI V
LVDS OUTPUTS (SSO, SYNCO)
Logic Compatibility LVDS
Output levels (full swing)
50 transmission lines, 100 (2 x 50
differential termination
VOL 1.450 V
Logic low
VOH 1.2 V
Logic high
VOH- VOL 240 310 375 mV
Differential output
VOCM 1.05 1.30 1.55 V
Common mode
Output levels (reduced swing)
Differential output VOH- VOL 100 210 275 mV
Common mode VOCM 1.1 1.6 V
SERIAL LINK OUTPUTS (ASLx,BSLx,CSLx,DSLx) with x=0 or 1
Logic Compatibility CML
Output levels (swing adjust off)
100 (2 x 50differential termination
VOL VccO – 0.65 V
Logic low
VOH VccO – 0.324 V
Logic high
VOH- VOL 325 mVp
Differential output VOCM VccO - 0.45 V
Common mode
Output levels (swing adjust on)
100 (2 x50differential termination VOL VccO–0.45 V
Logic low VOH VccO - 0.22 V
Differential output VOCM VccO -0.35 V
Common mode
page 8
EV12AQ600
Notes:
1. VCC_SPI supply value is chosen according to the chosen SPI input signals level. Refer to section 5.1.
2. Enabling either SDA or other features (CLKOUT, SSO, SYNCO) increases power consumption by 170mW (51mA on
VCCA). Maximum power consumption is estimated at 125°C, maximum supplies value and all features enabled.
3. Maximum number of power-up is limited by the maximum number of OTP reading
4. The DC analog common mode voltage is provided by the ADC.
5. For optimal performance in term of VSWR, Board input impedance must be 50± 5% and analog input impedance
must be digitally trimmed to cope with process deviation.
6. Jitter calculation integrated up to 6GHz
2.5 Converter Characteristics

 Typical values are given for typical supplies VCCA= 3.3V, VCCD = 1.2V, VCCO = 2.5V at ambient temperature
with Fclk=6GHz and with nominal mode of the SPI (SDA, CLKOUT and SYNCO disabled).
 Minimum and Maximum values are given over temperature and power supplies.
 ADC output level -1 dBFS
 Clock input differentially driven @ +7dBm at ADC input
 Non interleaved ADC
 Input common mode is trimmed using 2 different register values (see Table 36): 1B for 1st, 2nd and 3rd
Nyquist and default value for higher frequencies.
 Nominal bandwidth is selected for 1st and 2nd Nyquist and extended one is applied for other frequencies.
Table 4. Low frequency characteristics

DC ACCURACY
Gain central value Go -2.5 -1 0,5 dBFS /dBm (1)
Gain variation versus temperature G(T) TBD TBD dB
DC offset OFFSET -0.25 0 +0.25 LSB (2)
Fsampling = 1.5 GSps per core, Fin = 100 MHz, -1 dBFS
DNLrms DNLrms TBD 0.27 TBD LSB
Differential non linearity DNL TBD -0.7/+1.1 TBD LSB
INLrms INLrms TBD 1 (TBC) TBD LSB
Integral non linearity INL TBD +/-4 (TBC) TBD LSB
Notes:
1. After DC offset calibration

EV12AQ600
Table 5. Dynamic Characteristics

AC ANALOG INPUTS
Full Power Input Bandwidth:
Nominal bandwidth (selected by SPI) NFPBW 4.5 GHz
Extended bandwidth (selected by SPI) EFPBW >6 GHz
Gain Flatness (+/- 0.5 dB)
Nominal bandwidth (selected by SPI) NGF 1 (TBC) GHz
Extended bandwidth (selected by SPI) EGF 4 (TBC) GHz
Input Voltage Standing Wave Ratio
TBD
up to 2.4 GHz VSWR
TBD
up to 5 GHz
DYNAMIC PERFORMANCES
Spurious Free Dynamic Range (SFDR)
Single tone
At -1 dBFS output level
Fin=100 MHz 76
Fin=738 MHz 71
Fin=1480 MHz 63
Fin=1900 MHz 64

Fin=100 MHz 69
Fin=738 MHz 74
Fin=1480 MHz 68
Fin= 1900MHz 69
Fin= 2980 MHz 64
Fin=3730 MHz 58

Fin=100 MHz 74
Fin=738 MHz 73
Fin=1480 MHz |SFDR| 69 dBFS (2)(3)
Fin=1900 MHz 69
Fin=2980 MHz 66
Fin=3730 MHz 67
Fin=5300 MHz 64

Fin=100 MHz 71
Fin=738 MHz 71
Fin=1480 MHz 72
Fin=1900 MHz 71
Fin=2980 MHz 71
Fin=3730 MHz 73
Fin=5300 MHz 73
Dual tone
Fin=1480 MHz ∆Fin=15MHz
Pou1=Pout2= -9dBFs TBD
Over 50MHz band TBD
Over 200MHz band
page 10
EV12AQ600

THD
Single tone
Fin=100 MHz 69
Fin=738 MHz 66
Fin=1480 MHz 62
Fin=1900 MHz 62

Fin=100 MHz 65
Fin=738 MHz 68
Fin=1480 MHz 64
Fin=1900MHz 65
Fin=2980 MHz 63
Fin=3730 MHz 57
At -8 dBFS output level THD

dBFS
Fin=100 MHz 68
Fin=738 MHz 67
Fin=1480 MHz 65
Fin=1900 MHz 65
Fin=2980 MHz 63
Fin=3730 MHz 64
Fin=5300 MHz 62

Fin=100 MHz 66
Fin=738 MHz 66
Fin=1480 MHz 67
Fin=1900 MHz 66
Fin=2980 MHz 66
Fin=3730 MHz 67
Fin=5300 MHz 67
SNR
Fin=100 MHz 54.1
Fin=738 MHz 53.7
Fin=1480 MHz 52.9
Fin=1900 MHz 51.1
At -8 dBFS output level SNR

dBFS
Fin=100 MHz 54.3
Fin=738 MHz 54.2
Fin=1480 MHz 54.0
Fin=1900 MHz 52.4
Fin=2980 MHz 52.0
Fin=3730 MHz 51.6
Fin=5300 MHz 50.7
SINAD
Fin=100 MHz 53.9
Fin=738 MHz 53.4
Fin=1480 MHz 52.4
Fin=1900 MHz 50.8
Fin= 2980 MHz 48.9
SINAD
At -8 dBFS output level dBFS
Fin=100 MHz 54.1
Fin=738 MHz 54.0
Fin=1480 MHz 53.7
Fin=1900 MHz 52.2
Fin=2980 MHz 51.7
Fin=3730 MHz 51.4
Fin=5300 MHz 50.5

EV12AQ600

ENOB
Fin=100 MHz 8.7
Fin=738 MHz 8.6
Fin=1480 MHz 8.4
Fin=1900 MHz 8.1
At -8 dBFS output level ENOB

Bit_FS
Fin=100 MHz 8.7
Fin=738 MHz 8.7
Fin=1480 MHz 8.6
Fin=1900 MHz 8.4
Fin=2980 MHz 8.3
Fin=3730 MHz 8.2
Fin=5300 MHz 8.1
Noise Spectral Density
Four inputs mode Nominal Bandwidth
At -1 dBFS
st
1 Nyquist -143
2nd Nyquist -142
At -8 dBFS
1st Nyquist -143
nd NSD dBm/Hz
2 Nyquist -143
One input mode Extended Bandwidth
At -1 dBFS
rd
3 Nyquist TBD
At -8 dBFS
rd
3 Nyquist TBD
4th Nyquist TBD
Noise Power Ratio (NPR) @ -14 dB loading factor
Four inputs mode Nominal Bandwidth (600 MHz
noise pattern width, 5 MHz notch centred at Fs/4)
st
1 Nyquist 44.0
2nd Nyquist 43.5
rd
3 Nyquist NPR 43.0 dB
4th Nyquist 42.5
One input mode Extended Bandwidth (2400MHz
noise pattern width , 5 MHz notch centered at Fs/4)
st
1 Nyquist 42
2nd Nyquist 40
Notes:
1. Optimal bandwidth selection depends on signal characteristic. The bandwidth selection allows optimizing noise and
linearity trade-off. For signal below 1.5GHz, the bandwidth selection must be set to Nominal, for signal beyond this
frequency the bandwidth select must be set to Extended. The extended bandwidth degrades noise floor up to 1dB,
compensated at high frequency input signals by lower signal attenuation.
2. Linearity of high frequencies is dominated by H3 and H2, steppig back 3 or 6dB on input signals gives signifiant
improvement on SFDR figures. For narrow band operation (10MHz or 50MHz), a carefuly chosen frequency plan
allows rejection of these folded harmonics up to H8 beyond the band of interest.
3. SFDR without H3 harmonic is better than 60 dBFS at -1 dBFS. Removing H2 and H3 allows an SFDR performance
higher than 70 dBFS up to 5980MHz.
page 12
EV12AQ600
2.6 Transient and Switching Characteristics

 Typical values are given for typical supplies VCCA= 3.3V, VCCD = 1.2V, VCCO = 2.5V at ambient temperature
with Fclk=6GHz and with nominal mode of the SPI (SDA, CLKOUT and SYNCO disabled).
 Minimum and Maximum values are given over temperature ad power supplies.
 ADC output level -1 dBFS
 Clock input differentially driven @ +1dBm at ADC input
 Non interleaved ADC
Table 6. Transient characteristics

TRANSIENT PERFORMANCE
Conversion Error Rate at 1.5 GSps -14 Error/
CER 10E (TBC) (1)
Less than 128 LSB (TBC) sample
Error/
Serial link Bit Error Rate at 12 Gbps BER 10E-15(TBC)
sample
Overvoltage Recovery Time ORT 666 (TBC) ps
Notes:
1. Fs = 1.5 GSps, TJ = 110 C. For Tj=125°C, CER value is 10E-12
Table 7. Switching characteristics

SWITCHING PERFORMANCE AND CHARACTERISTICS (Any Output Mode)
External Clock frequency (performance) FCLK 800 6000 MHz
External Clock frequency (functionality) FCLK 6400 MHz
Sampling Clock frequency for performances 200 1500 MSps
Sampling Clock to CLKOUT delay Tclkout TBD ps
Max crosstalk from CLKOUT on clock input
XTALK_CKO2CK -40 (TBC) dB
signal@ 12Gbps
Aperture Delay (SDA Disabled) TA TBD ps
Sampling Delay Tuning Range (SDA Enabled) 0.03 120 ps
ADC Aperture uncertainty (SDA Disabled) JitterSDAOFF 135(TBC) fsrms (1)
ADC Aperture uncertainty (SDA enabled min) JitterSDAMIN 150(TBC) fsrms
ADC Aperture uncertainty (SDA enabled max) JitterSDAMAX 180 TBC) fsrms
CLKOUT jitter Jitterclkout 60 fsrms
Digital reset duration 10 µs
ADC settling time after power up TS TBD µs
External
Minimum SYNC pulse width TSYNC TBD Clock
cycles
SWITCHING PERFORMANCE AND CHARACTERISTIC (SSO, SYNCO)
Output rise time (20%-80%) TR 250 ps (2)
Output fall time (20%-80%) TF 250 ps (2)
External
SSO and SYNCO pipeline delay TPDSSO TBD Clock
cycles
SWITCHING PERFORMANCE AND CHARACTERISTIC (Serial output)
External
TPD TBD Clock
Output Data delay (pipeline + delay)
cycles
TOD TBD ps
Output rise time for DATA (20%-80%) TR 30 ps (3)
Output fall time for DATA (20%-80%) TF 30 ps (3)
Total jitter @ 12Gbps 2XT1 25 ps (3)
Minimum buffer amplitude time @ 12Gbps XT2 33.3 ps (3)
Maximum buffer amplitude @ 12Gbps YT1 260 mV (3)
Minimum buffer amplitude @ 12Gbps YT2 180 mV (3)
Skew between serial output signal P and N Tskew 0.6 (TBC) ps (3)
External
Conversion core latency 126 Clock (4)
cycles

EV12AQ600

crosstalk between xSL1 and xSL0@ 12Gbps
XTALK_SL2SL -40 (TBC) dB (3)
(x= A, B, C or D)
Max crosstalk between output serial link and
XTALK_SL2IN -80 (TBC) dB (3)
analog input signal @ 12Gbps
Notes:
1. See Definition of Terms.
2. 100 load + PCB line 17 cm
3. 100 load + PCB line 17 cm
4. The latency of the conversion core is fixed. The total latency of the ADC (including the serial interface) can take any
system external clock cycle between 126 and 141. ESIStream protocol wipes out the variable latency on the receivers
end due to its intrinsic synchronization protocol
Figure 3 - Serial link eye diagram
Table 8. SPI Timing characteristics

Test Value
Parameter Symbol Unit Note
Level Min Typ Max
RSTN pulse length TRSTN 10 µs
SCLK frequency FSCLK 10 MHz
CSN to SCLK delay TCSN-SCLK 0.5 TSCLK
MISO setup time Tsetup 3 ns
MISO hold time Thold 3 ns
MOSI output delay Tdelay TBD ns
Extended
CSN
TCSN ‐SCLK
SCLK
Tsetup Thold
MOSI
Tdelay
MISO
Figure 4 - SPI timing diagram
page 14
EV12AQ600
2.7 Digital Output Coding

Table 9. ADC Digital output coding table
Binary
Differential analog input Voltage level
MSB (bit 11)………LSB (bit 0) In-Range
> + 500.125 mV >Top end of full scale + ½ LSB 111111111111 0
+ 500.125 mV Top end of full scale + ½ LSB 111111111111 1
+ 500 mV Top end of full scale - ½ LSB 111111111110 1
+ 0.125 mV Mid scale + ½ LSB 100000000000 1
- 0.125 mV Mid scale - ½ LSB 011111111111 1
- 500 mV Bottom end of full scale + ½ LSB 000000000001 1
-500.125 mV Bottom end of full scale - ½ LSB 000000000000 1
< - 500.125 mV < Bottom end of full scale - ½ LSB 000000000000 0

EV12AQ600
2.8 Definition of Terms

Table 10. Definition of terms
Abbreviation Term Definition
(BER) Bit Error Rate percentage of bits with errors divided by the total number of bits that have been transmitted,
received or processed over a given time period
(CER) conversion Error Probability to exceed a specified error threshold for a sample at maximum specified
Rate sampling rate due to ADC quantization. An error code is a code that differs by more than +/-
128 LSB from the correct code.
(NFPBW) Nominal or Analog input frequency at which the fundamental component in the digitally reconstructed
(EFPBW) Extended Full output waveform has fallen by 3 dB with respect to its low frequency value (determined by
power input FFT analysis) for input at Full Scale –1 dB (- 1 dBFS).
bandwidth
(SINAD) Signal to noise and Ratio expressed in dB of the RMS signal amplitude to the RMS sum of all other spectral
distortion ratio components, including the harmonics except DC.
(SNR) Signal to noise Ratio expressed in dB of the RMS signal amplitude to the RMS sum of all other spectral
ratio components excluding the nine first harmonics.
(THD) Total harmonic Ratio expressed in dB of the RMS sum up to nth harmonic components, n to be specified, to
distortion the RMS input signal amplitude. It may be reported in dBFS (i.e, related to converter –1 dB
Full Scale), or in dBc (i.e, related to input signal level).
(SFDR) Spurious free Ratio expressed in dB of the RMS signal amplitude, to the RMS value of the highest
dynamic range spectral component (peak spurious spectral component). The peak spurious component
may or may not be a harmonic. It may be reported in dBFS (i.e., related to converter –1 dB
Full Scale), or in dBc (i.e, related to input signal level).
(ENOB) Effective Number Where A is the actual input
SINAD - 1.76 + 20 log (A / FS/2)
Of Bits ENOB = amplitude and FS is the full scale
range of the ADC under test
6.02
(DNL) Differential non The Differential Non Linearity for an output code i is the difference between the measured
linearity step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the
maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that
there are no missing output codes and that the transfer function is monotonic.
(INL) Integral non The Integral Non Linearity for an output code “I” is the difference between the measured
linearity input voltage at which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.
(TA) Aperture delay Delay between the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing
point), and the time at which analog input (INxP, INxN where X = 0, 1, 2 or 3) is sampled.
(JITTER) Aperture Sample to sample variation in aperture delay. The voltage error due to jitter depends on the
uncertainty slew rate of the signal at the sampling point.
(TS) Settling time Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale step
function is applied to the differential analog input.
(ORT) Overvoltage Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the
recovery time input is reduced to midscale.
(TOD) Digital data Output Delay from the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point)
delay to the next point of change in the differential output data (zero crossing) with specified load.
(TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated
output data being made available, (not taking in account the TOD).
(TR) Rise time Time delay for the output DATA signals to rise from 20% to 80% of delta between low level
and high level.
(TF) Fall time Time delay for the output DATA signals to fall from 20% to 80% of delta between low level
and high level.
(TSYNC) SYNC duration External SYNC pulse width needed for SYNC function
(IMD) InterModulation The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to
Distortion the worst third order intermodulation products.
(NPR) Noise Power Ratio The NPR is measured to characterize the ADC performance in response to broad
bandwidth signals. When applying a notch-filtered broadband white-noise signal as the
input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average
out-of-notch to the average in-notch power spectral density magnitudes for the FFT
spectrum of the ADC output sample test.
(NSD) Noise The NSD is the power spectral density magnitude of the ADC expressed in dBm/Hz
SpectralDensity
(VSWR) Voltage Standing The VSWR corresponds to the ADC input insertion loss due to input power reflection. For
Wave Ratio example a VSWR of 1.2 corresponds to a 20dB return loss (ie. 99% power transmitted and
1% reflected).
page 16
EV12AQ600
3 PACKAGE DESCRIPTION
3.1 Type /Outline
HiTCE Ceramic Ball Grid Array CBGA323

 High TCE Glass-Ceramic substrate
 Body size : 16.0x16.0 mm
 Lands Pitch : 0.80mm
 Number of balls : 323
 Conductor : cofired copper
 NiAu finish
Package interconnection
 18x18 BGA matrix (323 balls, A1 removed)
 0.80 mm ball pitch
 Ball type : Pb90Sn10
 MSL3 (non-hermetic)
Figure 5 – Package cross-section

EV12AQ600
Figure 6 – Package outline

page 18
EV12AQ600

3.2 Pinout top view
Figure 7 – Pinout
3.3 Thermal characteristics
Table 11. Thermal characteristics

Parameter Symbol Value Unit Note
Thermal resistance from junction to bottom of balls Rth Junction to Bottom of balls 4.0 °C/Watt (1)(2)
Thermal resistance from junction to board (JEDEC JESD51-8) Rth junction - board 5.5 °C/Watt (1)(2)
Thermal resistance from junction to top of lid Rth Junction – lid 2.05 °C/Watt (1)(2)
Thermal resistance from junction to ambient (JEDEC standard) Rth Junction – ambient 19.2 °C/Watt (1)(3)
Delta temperature Hot spot – temperature from diode +6.2 °C
Notes:
1. Rth are calculated from hot spot, not from average temperature of the die
These figures are thermal simulation results (finite elements method) with nominal cases.
2. Assumptions : no air, pure conduction, no radiation
3. Assumptions:
o Convection according to JEDEC
o Still air
o Horizontal 2s2p board
o Board size 114.3 x 76.2 mm, 1.6 mm thickness

EV12AQ600
3.4 Pinout Table

Table 12. Pinout Table
Pin Label Pin number Description Direction Simplified electrical schematics
Power supplies
A2,A3, A6,A9,A10,A13,A16,A17,
B3,B4,B5,B6,B7,B8,B9,B10,B11,
B12,B13,B14,B15,B16;
C5,C6,C7,C8,C9,C10,C11,C12,C15,
D6,D7,D8,D9,D10,D11,D12,D13,D14
E7,E8,E11,E12
F7,F8,F9,F10,F11,F12 Analog ground
G7,G12 All ground pins must be
H7,H8,H11,H12 connected to a one solid
J7,J9,J10,J12 ground plane on PCB
K7,K12 Common ground
L7,L9,L10,L12 (analog + digital)
AGND M7,M8,M11,M12 (Must be connected to
N4,N5,N6,N7,N8,N9,N10,N11,N12, same ground plane as
N13,N14,N15 GNDO, but a slit
P3,P4,P5,P6,P7,P8,P9,P10,P11, exceeding 5mm of
P12,P13,P14,P15,P16 package size should
R3,R4,R5,R6,R7,R8,R9,R10,R11, separate the 2 GND
R12,R13,R14,R15,R16 domains)
T1,T2,T3,T4,T5,T6,T7,T8,T9,T10,
T11,T12,T13,T14,T15,T16,T17,T18
U1,U2,U3,U6,U9,U10,U13,U16,
U17,U18
V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,
V11,V12,V13,V14,V15,V16,V17,V18
Digital ground
All ground pins must be
connected to a one solid
A18,
ground plane on PCB
B1,B2, B17,B18,
Common ground
C4, C16, C17
(analog + digital)
D15,
DGND (Must be connected to
E6,E13,
same ground plane as
F6,F13,
GNDO, but a slit
J6,J13,
exceeding 5mm of
L6,L13
package size should
separate the 2 GND
domains)
D1,D2, D17,D18
E1,E2,E3, E16,E17,E18
F3,F4, F15, F16 Ground for Output
G1,G2,G3,G4, G15,G16,G17,G18 buffers (Must be
H3, H16 connected to same
J1,J2,J3,J4,J5, J14,J15,J16,J17,J18 ground plane as AGND,
GNDO
K3, K16 but a slit exceeding
L1,L2,L3,L4,L5, 5mm of package size
L14,L15,L16,L17,L18 should separate the 2
M3,M16 GND domains)
N1,N2,N3, N16,N17,N18
P1,P2,P17,P18
E9;E10,G8,G9,G10,G11,H9,H10,J8,
J11,
V
K8,K9,K10,K11, Analog power supply
CCA
L8,L11,
M9,M10
SPI power supply
VCC_SPI F5
(1.8V, 2.5V or 3.3V)
F14
G6, G13,
VCCD H6,H13 Digital power supply
K6, K13
M6, M13
page 20
EV12AQ600

Output power supply.
H4, H5,H14,H15 The separation between
VCCO K4,K5, K14, K15 VCCO and VCCA must
M4,M5, M14,M15 be coincident with the
slit in GND plane.
Clock signal
VCCA
3.45K
CLKN
50
CLKP
In phase and Out of
CLKN A11,A12 I
phase input clock signal 5.25pF
50
CLKP
GN
13.45 K
AGND
VCCA
50  50 
CLKOUTP
CLKOUTP
CLKOUT In phase and Out of
A8,A7 O
N phase out clock signal
CLKOUTN
Analog signals
In phase analog input 0
IN0P I VCCA
U4, U5 Out of phase analog INxP
IN0N
input 0
IN1P 50 
U8, U7 Out of phase analog I
IN1N
input 1
IN2P I
U11, U12 Out of phase analog 400  CM
IN2N 40 pF
input 2
9000  a670 
GND
50  Iref
IN3P
U15, U14 Out of phase analog I INxN
IN3N
input 3
AGND

EV12AQ600

Output voltage VCCA
reference
In AC coupling
operation this output 200 
could be left floating (not
used)
In DC coupling
CMIREF operation, these pins O CM
R18
provides an output CMIREF
voltage which is the
common mode voltage
for the analog input 10k 
signal and should be
used to set the common
mode voltage of the AGND
input driving buffer.
Digital Output signals (CML)
ASL0P, Channel A output data
H1, H2 O
ASL0N serial link 0 VCCA
ASL1P, Channel A output data
F1, F2 O
ASL1N serial link 1
BSL0P, Channel B output data 50 
K1, K2 O OUTP
BSL0N serial link 0
BSL1P, Channel B output data
M1, M2 O
BSL1N serial link 1.
CSL0P, Channel C output data
K18, K17 O OUTN
CSL0N serial link 0.
CSL1P, Channel C output data
M18, M17 O
CSL1N serial link 1.
DSL0P, Channel D output data
H18, H17 O
DSL0N serial link 0.
DSL1P, Channel D output data
F18, F17 O
DSL1N serial link 1.
Digital output Signal (LVDS)
In phase and out of
SSOP, VCCA
C14, C13 phase Slow Synchro O
SSON
Output.Fsso=Fclk/32
SSOP/ SYNCOP
SYNCOP, In phase and out of

A5, A4 O SSON/SYNCON
SYNCON phase Sync Output.
Digital I/0 (CMOS)

used for logical level
VSPI_SEL C18 selection
page 22
EV12AQ600

SPI signal
Input SPI serial Clock
Serial data is shifted VCCD
into and out SPI
sclk D5 I
synchronously to this
signal on positive
transition of sclk
Internal pull-down
SPI signal
IN
Data SPI Input signal
(Master Out Slave In)
mosi C2 Serial data input is I 38 k
shifted into SPI while
sldn is active low
Internal pull-down
SPI signal
Input Chip Select signal
VCCO VCCD
(Active low)
D4 When this signal is
csn I
active low, sclk is used
to clock data present on 51 k
MOSI or MISO signal
Internal pull-up 11 k
SPI signal
Input Digital IN
asynchronous SPI reset
(Active low) 38 k
rstn C3 This signal allows to I
reset the internal value
of SPI to their default
value
Internal pull-up
VCCD
Pdriv
VCasc
SPI signal
Data output SPI signal
(Master In Slave Out)
miso C1 O MISO
Serial data output is VCCO
shifted out SPI while csn 80 ohms
4mA
is active low.
Ndriv
DIGITAL INPUT (LVDS)

EV12AQ600
VCCA
Differential Input
Synchronization signal
13 K
(LVDS)
SYNCTRIGN
Active high signal
SYNCTRI This signal is used to

GP synchronize internal
A14, A15 I
SYNCTRI ADC, if enabled
GN
Equivalent internal SYNCTRIGP
differential 100Ω input
resistor
Functionality SYNC or 7.5 K AGND
TRIG depends on SPI
selection
AGND
Miscellaneous
Junction Temperature
Monitoring diode Anode
Junction Temperature
DiodeA, Monitoring diode
R2, R1 I
DiodeC Cathode
Cathode must be
connected to ground
(AGND) externally
page 24
EV12AQ600
4 THEORY OF OPERATION
4.1 Overview
Table 13. Functional description

Name Function
VCCA Analog Power Supply
VCCD Digital Power Supply
VCCO Output buffer Power Supply
SPI Power Supply
VCC_SPI
(1.8V or VCCO or VCCA)
VSPI_SEL Selection of SPI logical levels
AGND Analog Ground
DGND Digital Ground
GNDO Ground for Output buffer
Differential Analog Input for ADC core
A, core B, core C or core D (depending
IN0P, IN0N
on cross point switch chosen
configuration)
IN1P, IN1N
B
IN2P, IN2N
C
IN3P, IN3N
A, core B, core C or core D
CLKP,CLKN Differential Clock Input
ASL0P, ASL0N Channel A output, serial link0 (CML)
ASL1P, ASL1N Channel A output, serial link1 (CML)
BSL0P, BSL0N Channel B output, serial link0 (CML)
BSL1P, BSL1N Channel B output, serial link1 (CML) mosi SPI input Data (Master Out Slave In)
CSL0P, CSL0N Channel C output, serial link0 (CML) miso SPI Output Data (Master In Slave Out)
CSL1P, CSL1N Channel C output, serial link1 (CML) CMIRef Input common Mode reference
DIODEA, Diode Anode and Cathode Inputs for die
DSL0P, DSL0N Channel D output, serial link0 (CML)
DIODEC junction temperature monitoring
CLKOUTP,
DSL1P, DSL1N Channel D output, serial link1 (CML) Differential output clock (copy of CLK)
CLKOUTN
csn SPI Chip Select Input (Active Low) SSOP, SSON Slow Synchro Output clock
LVDS input: Synchronization of Data
SPI Asynchronous Reset Input (Active SYNCTRIGP,
rstn Ready, or TRIGGER input depending on
Low) SYNCTRIGN
SPI selection
SYNCOP, Synchro output, resynchronized
sclk SPI Input Clock
SYNCON SYNCTRIG signal
The EV12AQ600 could be configured as follow:

 Both the analog inputs settings and the associated clocking mode (in phase or interleaved) of the 4 cores
can be selected thru the SPI.
 Test modes can be selected thru the SPI.
 Factory calibration or custom calibration can be loaded thru the SPI.
Refer to section 5.3 for registers description.

EV12AQ600
5 SERIAL PERIPHERAL INTERFACE (SPI)

The digital interface will be a standard SPI with:
 16 bits for the address A[15] to A[0] including a R/W bit (A[15] = R/W, being A[15] is the MSB);
 16 bits of data D[15] to D[0] with D[15] the MSB.
5 signals are required:

 RSTN for the SPI reset;
 SCLK for the SPI clock;
 CSN for the Chip Select;
 MISO for the Master In Slave Out SPI Output
 MOSI for the Master Out Slave In SPI Input.
The MOSI sequence should start with one R/W bit (A[15]):
 R/W = 0 is a read procedure
 R/W = 1 is a write procedure
5.1 SPI logic compatibility
Logical levels of SPI Digital CMOS levels can be configured in 1.8V, 2.5V or 3.3V logic compatibility. Table 14
depicts the SPI pins configuration depending on expected logic level. The selection of logic compatibility is done in
settings appropriate voltage levels to pins VCC_SPI and VSPI_SEL. Default logic compatibility is 1.8V.
Table 14. SPI pins configuration depending on logic voltage required
Logic Level VCC_SPI pin voltage VSPI_SEL pin voltage

1.8V 1.8V 0V (GND)
2.5V 2.5V 0V (GND)
3.3V 3.3V 3.3V
5.2 Timings
Register Write to a 16-bit register:

CSN
SCLK
MOSI RW A[14] A[13] A[3] A[2] A[1] A[0] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
MISO
Figure 8 - SPI writing
Register Read from a 16-bit register:

CSN
SCLK
MOSI RW A[14] A[13] A[3] A[2] A[1] A[0]
MISO D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Figure 9 - SPI reading
See section 2.6 for SPI timing characteristics (max clock frequency…)
page 26
EV12AQ600
5.3 Register map

Table 15. SPI register map
Default Refer to
Registers Names @ COMMENT
value Table
hex hex
The action of writing in this register causes the loading of
OTP_LOADING 0x0001 Table 28
OTP in secure SPI register
Additional protection against Single Event
0: major protection is available (default)
1: additional protection is available
_ All SPI registers can't be access, except this
EXTRA_SEE_PROTECT 0x0002 0 Table 31
register
_ SYNC is disabled
_ The presence of the CLOCK SPI refreshes
Triple Majority Redundancy registers
bit[0] = A OTP status
AB_OTP_STATUS 0x0003 Table 29
bit[1] = B OTP status
bit[0] = C OTP status
bit[1] = D OTP status
CD_OTP_STATUS 0x0004 Table 29
bit[2] = sup1 CD OTP status
bit[3] = sup2 CD OTP status
For all following bit :
0: reduced
SYNC_SSO_CLKOUT_FULL_
0x0005 0 1: full swing Table 24
SWING_EN
bit[1]= LVDS full swing on SSO and SYNCO
bit[0]= CML CLKOUT full swing
bit[0]=
AB_HSSL_FULL_SWING_EN 0x0006 0 0: HSSL output swing is reduced (default) Table 25
1: full HSSL output swing
bit[0]=
CD_HSSL_FULL_SWING_EN 0x0007 0 0: HSSL output swing is reduced (default) Table 25
bit[0]=
EXT_BW_DISABLE 0x0008 0 0: extended bandwidth (default) Table 19
1: nominal bandwidth
bit[0]= INL calibration set selection
0: set 0 selected
1: set 1 selected
CAL_SET_SEL 0x0009 0 Table 18
bit[2:1]= phase/gain/offset calibration set selection
00: set 0 selected
01: set 1 selected
bit[1:0]= clock control
11: clock A=B=C=D , all clocks are identical
CLK_MODE_SEL 0x000A 0 10: clock A=C, clock B=D Table 17
01: clock A=B, clock C=D
00: all clocks are interleaved (default)
1 channel mode
000 : input 0 to core A & B & C & D (default)
001 : input 3 to core A & B & C & D
2 channels mode
010 : input 0 to core A & B
input 3 to core C & D
CPS_CTRL 0x000B 0 011 : input 0 to core C & D Table 16
input 3 to core A & B
4 channels mode
100 : input 0 to core A
input 1 to core B
input 2 to core C
input 3 to core D
Bit[0] – sync_edge:Indicate system clock sampling edge
for SYNC
0 – Positive edge
1 – Negative edge
SYNC_CTRL 0x000C 0 Bit[2:1] – sync_shift : Add one(or more) system clock Table 22
period on SYNC internal path
00 – No system clock period added
01 – One system clock period added
10 – two system clock periods added
EV12AQ600
Default Refer to
value Table
hex hex
11 – three system clock periods added
Bit [0] – Indicate timing violation on SYNC

SYNC_FLAG 0x000D 0 Bit [0] = 0 – SYNC has been correctly recovered Table 20
Bit [0] = 1 –Timing violation on SYNC
SYNC_FLAG_RST 0x000E 0 Bit [0] = 0 – reset the flag Table 21
CHIP_ID 0x0011 Chip Identification number Table 30
bit[1:0]= DATA SELECTION FOR BIT[12]
00: IR selected (default)
01: TRIG selected (=> SYNC disabled)
10: TimeStamp selected
11: PARITY selected
bit[3:2]= DATA SELECTION FOR BIT[13]
AB_HSSL_CFG 0x0013 18 00: IR selected Table 27
10: TimeStamp selected (default)
11: PARITY selected
bit[4]= LSB first enable
0: MSB first
1: LSB first (default)
CD_HSSL_CFG 0x0014 18 Idem AB_HSSL_CFG Table 27
bit[0]= Pin N/P configuration of serial output buffer 0
CHANNEL A
CHANNEL A
AB_HSSL_POL 0x0015 06 Table 26
CHANNEL B
CHANNEL B
0: Pin N/P default
1: Pin N and P reversed
CHANNEL C
CHANNEL C
CD_HSSL_POL 0x0016 09 Table 26
CHANNEL D
CHANNEL D
0: Pin N/P default
0: disable
1: enable
TIMER_CTRL 0x0017 2 Table 23
bit[0]= CLKOUT enable (disable by default)
bit[1]= SSO enable (enable by default)
bit[2]= SYNCO enable (disable by default)
A_SET1_GAIN_CAL 0x0122 0800 A core Interleaving gain calibration Table 39
A_SET1_PHASE_CAL 0x0123 0100 A core Interleaving phase calibration Table 40
A_SET1_OFFSET_CAL 0x0124 0100 A core Interleaving offset calibration Table 41
A_SET2_GAIN_CAL 0x0125 0800 A core Interleaving gain calibration Table 39
A_SET2_PHASE_CAL 0x0126 0100 A core Interleaving phase calibration Table 40
A_SET2_OFFSET_CAL 0x0127 0100 A core Interleaving offset calibration Table 41
A core Sampling delay adjust (0 to 120 ps with a step of
30 fs)
A_SDA_CTRL 0x012F 1000 Table 33
bit[11:0] = sda value
[9:0]: fine delay, step 30fs
page 28
EV12AQ600
Default Refer to
value Table
hex hex
[11:10]: coarse delay, step 30ps
bit[12] = sda disable
0: enable
1: disable (default)
B_SET1_GAIN_CAL 0x0322 0800 B core Interleaving gain calibration Table 39

B_SET1_PHASE_CAL 0x0323 0100 B core Interleaving phase calibration Table 40
B_SET1_OFFSET_CAL 0x0324 0100 B core Interleaving offset calibration Table 41
B_SET2_GAIN_CAL 0x0325 0800 B core Interleaving gain calibration Table 39
B_SET2_PHASE_CAL 0x0326 0100 B core Interleaving phase calibration Table 40
B_SET2_OFFSET_CAL 0x0327 0100 B core Interleaving offset calibration Table 41
B core Sampling delay adjust (0 to 120 ps with a step of
30 fs)
B_SDA_CTRL 0x032F 1000 Table 33
0: enable
0x0500
C_SETx_INLy to Same principle as above registers for core C Table 33
0x0521
C_SET1_GAIN_CAL 0x0522 C core Interleaving gain calibration Table 39
C_SET1_PHASE_CAL 0x0523 C core Interleaving phase calibration Table 40
C_SET1_OFFSET_CAL 0x0524 C core Interleaving offset calibration Table 41
C_SET2_GAIN_CAL 0x0525 C core Interleaving gain calibration Table 39
C_SET2_PHASE_CAL 0x0526 C core Interleaving phase calibration Table 40
C_SET2_OFFSET_CAL 0x0527 C core Interleaving offset calibration Table 41
C core Sampling delay adjust (0 to 120 ps with a step of
30 fs)
C_SDA_CTRL 0x052F 1000 Table 33
0: enable
0x0700
D_SETx_INLy to Same principle as above registers for core D Table 33
0x0721
D_SET1_GAIN_CAL 0x0722 D core Interleaving gain calibration Table 39
D_SET1_PHASE_CAL 0x0723 D core Interleaving phase calibration Table 40
D_SET1_OFFSET_CAL 0x0724 D core Interleaving offset calibration Table 41
D_SET2_GAIN_CAL 0x0725 D core Interleaving gain calibration Table 39
D_SET2_PHASE_CAL 0x0726 D core Interleaving phase calibration Table 40
D_SET2_OFFSET_CAL 0x0727 D core Interleaving offset calibration Table 41
D core Sampling delay adjust (0 to 120 ps with a step of
30 fs)
D_SDA_CTRL 0x072F 1000 Table 33
0: enable
AB_CMIREF 0x0905 14 input common mode calibration for A & B cores Table 36
CD_CMIREF 0x0906 14 input common mode calibration for C &D cores Table 36
AB_RIN 0x0907 10 Input impedance calibration for A, B cores Table 37
CD_RIN 0x0908 10 Input impedance calibration for C, D cores Table 37
CALIBRATION R LOAD CML
AB_ROUT_HSSL 0x0909 55 Table 38
bit[1:0]= R_cml0 channel A (for link0)
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Default Refer to
value Table
hex hex
bit[5:4]= R_cml0 channel B (for link0)
bit[1:0]= R_cml0 channel C (for link0)
CD_ROUT_HSSL 0x090A 55 bit[3:2]= R_cml1 channel C (for link1) Table 38
bit[5:4]= R_cml0 channel D (for link0)
bit[0]= ramp mode

bit[1]= force VOH
bit[2]= force VOL
TEST_MODE 0x0B0A 0 Table 28
bit[3]= force decimation (/4)
0: disable
1: enable
A_CALC_OTP_CRC 0x0B0B CRC calculated after a OTP loading Table 29
B_CALC_OTP_CRC 0x0B0C idem Table 29
C_CALC_OTP_CRC 0x0B0E idem Table 29
D_CALC_OTP_CRC 0x0B0F idem Table 29
A_OTP_CRC 0x0B14 CRC OTP reading Table 29
B_OTP_CRC 0x0B15 CRC OTP reading Table 29
C_OTP_CRC 0x0B17 CRC OTP reading Table 29
D_OTP_CRC 0x0B18 CRC OTP reading Table 29
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5.4 Digital Reset and start up procedure

RSTN is an asynchronous active low global reset for the SPI and OTP (One Time Programmable registers). It is
mandatory to put RSTN at low level during a minimum of 10 µs at power-up of the device. It sets all SPI registers to
their default values. The SPI interface can be used or not; if it is not used, the OTP value and default SPI
configurations will be automatically loaded.
Figure 10 presents the reset and synchronization to realize after power-up when the SPI is used (see section Serial
Peripheral Interface (SPI) for more information on the SPI interface).
Figure 10 – Start-up sequence when using the SPI interface
1. It is mandatory to reset the device at power-up through RSTN. It is active low and the pulse must be at least 10 µs.
During the RSTN pulse, CSN must be held high and SCLK held low. The CLK must be provided before the RSTN
pulse. The CLK can start before or after the power-up;
2. The fuses need 1 ms to wake up;
3. The SPI instruction WRITE @0x0001 1 must be sent to the ADC. The OTP are loaded into the SPI registers at this
point. There must be at least 1 ms between the RSTN pulse and this SPI instruction;
4. The ADC is configured through the SPI interface;
5. A pulse is applied onto the SYNCTRIG input to reset the internal clocks (SYNC signal in Figure 10). At this stage, the
(trigger mode disabled);
6. The ADC can be configured in trigger mode enable and the EXTRA_SEE_PROTECT register can be activated – see
section 5.15;
7. Normal operation of the ADC.
5.5 ADC Synchronization Signal (SYNCTRIGP, SYNCTRIGN)

The SYNCTRIGP, SYNCTRIGN LVDS inputs deliver SYNC signal for synchronization or TRIGGER one for
triggering data. This section focused on using the SYNC signals.
Since SYNC is multiplexed with TRIGGER, to perform synchronization, the ADC must be configured in
synchronization mode. The SYNC function is enabled by default. Refer to AB_HSSL_CFG and CD_ HSSL_CFG
registers in section 0.
The SYNC signal is mandatory in order to have a deterministic timing for the 4 core synchronization (clock tree and
digital reset) and for multiple ADCs time alignment.
It is asynchronous regarding the external clock. It is active high and should be compliant with the timing shown in
the chronograms of Figure 10 and specified in Table 7 to work properly. It becomes effective on the rising edge of
SYNCTRIGP, SYNCTRIGN.

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5.6 Cross-point switch (CPS)

CPS functionality enables different input configurations by switching the signal to the dedicated core (A, B, C or D).
IN0 and IN3 can address any core. IN1and IN2 must be connected to core B and C if used, as described below:
IN0 IN1 IN2 IN3
A B C D
Figure 11 – CPS configurations
To interleave A to D cores, IN0 input can be used and register CPS_CTRL has to be set to 0. We have to choose
also the right clock distribution (see section 5.7).
Different CPS capabilities are described in register CPS_CTRL
.
Table 16. CPS_CTRL register description
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPS_CTRL
Default
Register Name @ Type Size Core Comment
Value
1 channel mode
000 : input 0 to core A & B & C & D (default)
001 : input 3 to core A & B & C & D
2 channels mode
010 : input 0 to core A & B
input 3 to core C & D
CPS_CTRL 0x000B RW 3 0b0 All
011 : input 0 to core C & D
input 3 to core A & B
4 channels mode
100 : input 0 to core A
input 1 to core B
input 2 to core C
input 3 to core D
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5.7 Clock interleaving

Core A to D could be addressed one to one or interleaved two by two or all four together to reach 6GSps. A
dedicated register (CLK_MODE_SEL) has to be used to provide the right clock behaviour to each core.
Table 17. CLK_MODE_SEL register description

CLK_MODE_
SEL
Default
Value
bit[1:0]= clock control
11: clock A=B=C=D , all clocks are identical
CLK_MODE_SEL 0x000A RW 2 0b00 All 10: clock A=C, clock B=D
01: clock A=B, clock C=D
00: all clocks are interleaved (default)
Detailed clocks chronograms for each configuration are given in Figure 12 to Figure 15.
ClockA
ClockB
ClockC
ClockD
External
Clock
Figure 12 - Clocks for four cores interleaved, CLK_MODE_SEL = 0
Above clocks mode configuration has to be associated with the case one Input IN0 (or IN3) of the CPS.
ClockA
ClockC
ClockB
ClockD
External
Clock
Figure 13 - Clocks for four cores aligned (averaging) or four channels, CLK_MODE_SEL = 3

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ClockA
ClockC
ClockB
ClockD
External
Clock
Figure 14 - Clocks for two cores interleaved – configuration 1, CLK_MODE_SEL = 1
For this configuration, IN0 and IN3 inputs are used: IN0 provides signal to two cores while IN3 provides the two
other cores input.
ClockA
ClockC
ClockB
ClockD
External
Clock
Figure 15 - Clocks for two cores interleaved – configuration 2, CLK_MODE_SEL = 2
5.8 Calibration selection

All cores could use different sets (set0 and set1) of calibrations on the on-chip OTP (predefined manufacturing
calibrations). One set is selected thanks to CAL_SET_SEL register.
Each calibration set addresses INL, gain, phase and offset tuning of each core.
Set 0 is dedicated to calibration at cold (exact temperature TBD)
Set 1 is dedicated to calibration at hot temperature (exact temperature TBD)
Table 18. CAL_SET_SEL register description

CAL_SET_SEL
Default
Value
bit[0]= INL calibration set selection
0: set 0 selected
1: set 1 selected
CAL_SET_SEL 0x0009 RW 3 0b000 All bit[2:1]= phase/gain/offset calibration set
selection
00: set 0 selected
01: set 1 selected
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5.9 Analog bandwidth

The ADC core Analog Bandwidth can be selected thanks to EXT_BW_DISABLE register (refer to dynamic
characteristic on Table 5).
Table 19. EXT_BW_DISABLE register description

Bit Bit Bit
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
9 8 7
EXT_BW_DISABLE
Default
Value
bit[0]=
EXT_BW_DISABLE 0x0008 W 1 0b0 All 0: extended bandwidth (default)
1: nominal bandwidth
5.10 SYNC, slow and fast output clocks (SSO, CLKOUT)
To use the SYNC signal internally, it should first be sampled by the internal clock. But, as the SYNC is
asynchronous, it may lead to metastability when the internal sampling clock edge is simultaneous with the SYNC
signal transition. To prevent this phenomenon, different SPI registers have to be used.
SYNC_FLAG indicates whether the SYNC has been correctly recovered by the system clock or not.
Table 20. SYNC_FLAG register description

Default
Value
Bit [0] – Indicate timing violation on SYNC
SYNC_FLAG 0x000D r 1 0b0 All Bit [0] = 0 – SYNC has been correctly recovered
Bit [0] = 1 –Timing violation on SYNC
The flag is reset by a reading of SYNC_FLAG_RST register:
Table 21. SYNC_FLAG_RST register description

Default
Value
SYNC_FLAG_RST 0x000E w 1 0b0 All Bit [0] = 0 – reset the flag
Two other SYNC_CTRL register’s bits are used to configure the ADC. The first one, described in Table 22, is the
sync_edge. It indicates to the ADC the system clock edge it should use to recover it. The other one is the
sync_shift, it adds one up to three system clock delay before resetting the ADC timing. Thanks to these registers,
the ADC timing can be reset and multiple ADCs can be synchronized.
Table 22. SYNC_CTRL register description

Default
Value
Bit[0] – sync_edge:Indicate system clock sampling edge
for SYNC
0 – Positive edge
1 – Negative edge
Bit[2:1] – sync_shift : Add one(or more) system clock
SYNC_CTRL 0x000C w 3 0b00 All
period on SYNC internal path
00 – No system clock period added
01 – One system clock period added
10 – two system clock periods added
11 – three system clock periods added

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The slow output clock SSO (used for synchronization, frequency generation and reference clock for serial link
receiver) is not affected by SYNCTRIGP, SYNCTRIGN (not interrupted). It is an LVDS output generated by a 32
times division of the input clock.
The SYNC signal also starts the synchronization sequence of the serial interface.
CLKOUT is an output clock signal provided by the circuit as a clock reference to other ADCs. It has the same
frequency as input clock CLKP, CLKN. The output signals SYNCOP, SYNCON result from the sampling of
SYNCTRIGP, SYNCTRIGN signals by the system clock.
In order to have deterministic resynchronization of several ADCs, it is recommended to chain the SYNC of ADC
part N on the SYNCO of ADC part N-1.In this way the delay between the different ADC will be deterministic. But
SYNC tree is still possible.
SYNCO, CLKOUT or SSO signals can be deactivated to save power when multiple ADC chaining is not used. The
deactivation is done thru TIMER_CTRL register:
Table 23. TIMER_CTRL register description

Default
Value
0: disable
1: enable
TIMER_CTRL @0x0017 w 3 0b010 All
bit[0]= CLKOUT enable (disable by
default)
bit[1]= SSO enable (enable by default)
bit[2]= SYNCO enable (disable by default)
These signals swing can be reduced to save power thru SYNC_SSO_CLKOUT_FULL_SWING_EN register:
Table 24. SYNC_SSO_CLKOUT_FULL_SWING_EN register description

Default
Value
0: reduced
1: full swing
SYNC_SSO_CLKOUT_FULL_SWING_EN @0x0005 w 2 0b00 All bit[1]= LVDS full swing on
SSO and SYNCO
bit[0]= CML CLKOUT full
swing
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5.11 Serial link output configuration
5.11.1 Serial link output swing and polarity configuration

IO‘s consumption represents a non-negligible part of dissipation. In case of short routing (in the range of 10 cm) or
lower receiver input swing capability, it is possible to reduce the output dynamic and so the consumption by using
“swing adjust”. IO’s consumption can be reduced by 1/3.
Note: CLKOUT, SSO, SYNCO and serial link buffers (HSSL links) have independent dynamic settings. Refer to
registers of Table 24 for CLKOUT, SSO and SYNCO swing setting.
The configuration is done via registers AB_HSSL_FULL_SWING_EN and CD_HSSL_FULL_SWING_EN.
Table 25. AB_HSSL_FULL_SWING_EN and CD_HSSL_FULL_SWING_EN registers description

Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
Bit 1 Bit 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2
AB_HSSL_FULL_SWING_EN
CD_HSSL_FULL_SWING_EN
Default
Value
bit[0]=
AB_HSSL_FULL_SWING_EN 0x0006 W 1 0b0 A, B 0: HSSL output swing is reduced (default)
bit[0]=
CD_HSSL_FULL_SWING_EN 0x0007 W 1 0b0 C, D 0: HSSL output swing is reduced (default)
It is also possible to invert the polarity of serial links outputs thanks to registers AB_HSSL_POL and
CD_HSSL_POL.
Table 26. AB_HSSL_POL and CD_HSSL_POL registers description

Bit Bit Bit Bit Bit Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
15 14 13 12 11 10
AB_HSSL_POL
CD_HSSL_POL
Default
Value
CHANNEL A
CHANNEL A
AB_HSSL_POL 0x0015 W 4 0b110 A, B
CHANNEL B
CHANNEL B
0: Pin N/P default
CHANNEL C
CHANNEL C
CD_HSSL_POL 0x0016 W 4 0b110 C, D
CHANNEL D
CHANNEL D
0: Pin N/P default

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5.11.2 Serial link In Range, Trigger, Timestamp, Parity and bit order configuration
It is possible to select the function of CB1 and CB2 (bit 12 and 13) of serial links among In Range, Trigger,
Timestamp or parity bit.(for more information on CB1 and CB2 see paragraph 7)
The converted data (bit[11:0]) can be set either MSB first or LSB first by means of bit[4] of this register.
Table 27. AB_HSSL_CFG and CD_HSSL_CFG registers description

AB_HSSL_CFG
CD_HSSL_CFG
Default
Value
bit[1:0]= DATA SELECTION FOR CB1
00: INRANGE selected (default)
10: TIMESTAMP selected
11: PARITY selected

AB_HSSL_CFG 0x0013 W 5 0b11000 A, B 00: INRANGE selected
10: TIMESTAMP selected (default)
11: PARITY selected

0: MSB first
00: INRANGE selected (default)
10: TIMESTAMP selected
11: PARITY selected

CD_HSSL_CFG 0x0014 W 5 0b11000 C, D 00: INRANGE selected
10: TIMESTAMP selected (default)
11: PARITY selected

0: MSB first
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5.11.3 Trigger mode

The SYNCTRIG input is an LVDS signal. It can be used in 2 different modes controlled through SPI: either in
SYNC mode (refer to section 5.5) or in TRIGGER mode. To set it in TRIGGER mode, at least one of the control bit
setting of register AB_HSSL_CFG and CD_HSSL_CFG must be set to TRIG (refer to section 0). The trigger bit is a
copy of the SYNCTRIG input with the same pipeline delay as the sampled data (refer to timing diagram in the
figure below).
CLOCK
X ANALOG INPUT
SYNCTRIG
Sampling sample N
ASL0 Sample N encoded / CBx = 0
Sampling sample N+4
ASL1 Sample N+4 encoded / CBx = 1
Sampling sample N+1
BSL0 Sample N+1 encoded / CBx = 1
Sampling sample N+5
BSL1 Sample N+5 encoded / CBx = 0
Sampling sample N+2
CSL0 Sample N+2 encoded / CBx = 1
CSL1 Sample N+6 encoded / CBx = 0
Sampling sample N+3
DSL0 Sample N+3 encoded / CBx = 1
DSL1 Sample N+7 encoded / CBx = 0
Figure 16 - Trigger mode timing diagram in serial interface
5.11.4 Parity bit

The parity of the 12 output bits of each data is calculated by performing an XOR combination between the 12 bits
of output data. It is outputted at the same time than the 12-bits data. It is multiplexed with the in range and trigger
bits. This function is selectable thru AB_HSSL_CFG and CD_HSSL_CFG registers (refer to Table 27). By default,
this function is not activated.
5.11.5 In-range bit

The “in-range” bit indicates whether the input signal is in the ADC dynamic range or not. When the ADC input
signal is over the ADC dynamic range, the “in-range” bit is low. It is multiplexed with the parity and trigger bits.
This function is selectable AB_HSSL_CFG and CD_HSSL_CFG registers (refer to Table 27). By default, this
function is activated.
5.11.6 TIMESTAMP
The timestamp control bit is a PRBS sequence that is updated with every frame. It is the same sequence for all
links and is reset upon receiving a SYNCTRIG pulse. The PRBS sequence is based on an LFSR of Galois
architecture with the polynomial X7+X6+1. It can be used to identify the samples order and/or check the
synchronization of the serial interface.
This function is selectable AB_HSSL_CFG and CD_HSSL_CFG registers (refer to Table 27). By default, this
function is activated.

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5.12 Test modes

Multiple test modes are available and can be generated by the ADC:
- PRBS : generates a pseudo-random binary sequence on the output
- Ramp : generates a ramp on the output
See below the registers used to enable or disable the different test modes:
Table 28. TEST_MODE & DATA_MODE_SEL registers description

Default
Value
For all following bits :
0: disable
TEST_MODE @0x0B0A w 4 0b0000 All 1: enable
bit[0]= ramp mode

bit[0] = PRBS enable
bit[1] = DATA enable (0 means DATA=0)
DATA_MODE_SEL
@0x0B07 w 3 0b111 All bit[2] = DC-Balance enable
0: disable
1: enable (default)
5.12.1 PRBS
Pseudo Random Bit Sequence can be generated for output. It can be:
 Deactivated
 Added to data (PRBS+data)
 Outputted without data
This pseudo-random test mode is encoded with ESIstream protocol (see section 7).
5.12.2 Ramp mode

In ramp mode, the data encoded corresponds to a 12 bit ramp value with only the even values on lane 1 and the
odd values on lane 2.
See below the chronogram of the ramp test mode. The data shown in the following figure only presents the 14bit
data from the ADC (12 bit sample values plus 2 control bits CB1 and CB2) and do not include the encoding of the
ESIstream protocol that is used on the serial interface, in order to understand the ramp test mode (for more
information on CB1 and CB2 see paragraph 7).
Figure 17 – Chronogram of the Ramp test mode
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5.12.3 DC balance
There are two main issues in serial transmission. First the transmission must be DC balanced to avoid voltage
imbalance issues while allowing AC coupling between transmitter and receiver. The second issue is brought by the
CDR in the receiver. This component uses the edges in the transmission to recover the clock. Thus if there are
long series of ‘1’ or ‘0’, the lock can be lost in the receiver.
To avoid these issues, a DC balance can be added using the 15th bit of the EsiStream protocol: if bit[15] is set to 1;
the bits parity is inverted. Otherwise, nothing is done.
5.13 CRC CHECKING

In order to prevent errors during the OTP (One Time Programmable) life time, a CRC check is added into the OTP.
The CRC reference value is stored in the OTP. During the operation of the ADC, the CRC value of the SPI register
can be calculated and compared to the one stored in the OTP, to check if the configuration has been corrupted. A
status equal to “1” means that CRC is OK. A status equal to “0” means the CRC is not OK.
Table 29. OTP and CRC registers description

Default
Value
bit[0] = to load fuses (OTP)
values into the SPI register.
OTP_LOADING @0x0001 w 1 NA All 0 or 1 : load OTP value into
SPI
This is a write only register
bit[0] = A OTP status
AB_OTP_STATUS @0x0003 r 4 N/A A, B
bit[1] = B OTP status
bit[0] = C OTP status
CD_OTP_STATUS @0x0004 r 4 N/A C, D
bit[1] = D OTP status
CRC calculated after a OTP
A_CALC_OTP_CRC @0x0B0B r 16 N/A A
loading
B_CALC_OTP_CRC @0x0B0C r 16 N/A B
loading
C_CALC_OTP_CRC @0x0B0E r 16 N/A C
loading
D_CALC_OTP_CRC @0x0B0F r 16 N/A D
loading
Default
Value
A_OTP_CRC @0x0B14 r 16 N/A A CRC OTP reading
B_OTP_CRC @0x0B15 r 16 N/A B CRC OTP reading
C_OTP_CRC @0x0B17 r 16 N/A C CRC OTP reading
D_OTP_CRC @0x0B18 r 16 N/A D CRC OTP reading

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5.14 CHIP ID
Chip_ID can be read thru dedicated register CHIP_ID described below:
Table 30. CHIP_ID register description

CHIP_ID
Default
Value
CHIP_ID 0x0011 R 16 0x914 - Chip id value is 0x914
5.15 Single event protection

All sensitive areas of the device have been protected to increase robustness. This includes but is not limited to
clock circuitry and SPI registers. To improve even more the robustness, an extra protection mode has been
implemented. It can be activated through the EXTRA_SEE_PROTECT register.
Table 31. EXTRA_SEE_PROTECT register description

_PROTECT
EXTRA_SEE
Default
Value
Additional protection against Single Event
0: major protection is available (default)
1: additional protection is available
_ All SPI registers can't be access, except this
EXTRA_SEE_PROTECT 0x0002 RW 1 0b0 All
register
_ SYNC is disabled
_ The presence of the CLOCK SPI refreshes
Triple Majority Redundancy registers
Enabling register EXTRA_SEE_PROTECT by writing ‘1’ disables the SYNCTRIG input when in SYNC mode and
thus prevents unwanted timing reset of the ADC (see section 5.5 for more information). It prevents as well any
modification on the SPI registers. The SPI clock (SCLK) can be provided from time to time to refresh the SPI (and
flush out any SE that would have impacted one branch of the TMR). When it is necessary to modify the
configuration of the device or synchronize the ADC, this register needs to be set back to ‘0’.
The consequences of extra SEE protection activation are described in Table 32.
Table 32. Consequences of extra SEE protection activation

PROTECTION OFF PROTECTION ON
SYNC mode SYNC possible SYNC deactivated
Trigger mode No SYNC possible, Trigger mode operating
Registers Registers can be modified by OTP or SPI Registers cannot be modified

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5.16 SDA operation
The effective sampling instant of each ADC core can be adjusted independently via registers A_SDA_CTRL (with
x=A, B, C or D) thanks to two built in fine and coarse internal clock shifters (fine: 1023 steps of 30fs, coarse:
addition of 0, 1, 2 or 3 delay of 30ps).
The total tuning range is 120ps. Delay is set only through SPI instructions. By default, SDA is disabled (by-passed).
Activating the SDA has an impact on the jitter performance of the device.
Table 33. A_SDA_CTRL, B_SDA_CTRL, C_SDA_CTRL and D_SDA_CTRL registers description

sda
sda value
disable
Default
Value
A core Sampling delay adjust (0 to 120 ps with a
step of 30 fs)

A_SDA_CTRL 0x012F W 13 0x1000 A

0: enable
B core Sampling delay adjust (0 to 120 ps with a
step of 30 fs)

B_SDA_CTRL 0x032F W 13 0x1000 B

0: enable
C core Sampling delay adjust (0 to 120 ps with a
step of 30 fs)
C_SDA_CTRL 0x052F W 13 0x1000 C [11:10]: coarse delay, step 30ps

0: enable
D core Sampling delay adjust (0 to 120 ps with a
step of 30 fs)
D_SDA_CTRL 0x072F W 13 0x1000 D [11:10]: coarse delay, step 30ps

0: enable

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6 DIE JUNCTION TEMPERATURE MONITORING DIODE

Two pins are provided so that the diode can be probed using standard temperature sensors. Maximum current
allowed on this pin is 1.2 mA.
The diode measures the junction temperature which is 7.5°C below the hot spot (but higher than die average
temperature)
INx
INx
Figure 18 – Junction temperature monitoring diode system
Note: If the diode function is not used, the diode pins can be left unconnected (open). If diode is used it is
mandatory to connect DiodeC to GND.
6.1 Functionalities Summary

Default mode is :
 ADC core calibrated through OTP values
 Serial buffer in reduced swing ( low power) mode
 Extended analog bandwidth selected
 Synchronization mode enabled
 In range signal outputted
 4 ADC Cores are interleaved.
Table 34. Functionalities summary

Functionality / mode Default mode description control
Serial 8 lanes ON Available SPI
data rate @4x Fsampling
(Max 12Gb/s)
Serial 4 lanes OFF Available SPI
data rate @4x Fsampling
(Max 12Gb/s)
Swing adjust ON ON (reduced swing) / OFF SPI
Input common Adjust Set by OTP Available OTP/SPI
Input impedance Adjust Set by OTP Available OTP/SPI
CML impedance Adjust Set by OTP Available OTP/SPI
Gain Adjust Set by OTP Available OTP/SPI
Offset Adjust Set by OTP Available: OTP/SPI
Phase adjust Set by OTP Available OTP/SPI
SDA Disabled Available OTP/SPI
Power ON Mode no standby Available SPI
InRange output Available Selected by SPI
SYNC mode /Trigger Mode SYNC MODE enable SYNC MODE enable Selected by SPI
SYNC mode disable,trigger mode enable
Test Mode Disabled Enable / Disabled Selected by SPI
Analog bandwidth extended Nominal or extended Selected by SPI
SE protection OFF OFF or ON Selected by SPI
Junction temperature monitoring Available Refer to section 6
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6.2 Calibrations summary

For details regarding calibration, see section 7.3.
Table 35. Calibrations summary

Calibration Description Set by OTP Set by SPI
Core gain adjust ADC gain adjust for interleaving operation Yes Yes
Core offset adjust ADC DC offset adjust for interleaving operation Yes Yes
Core phase adjust ADC sampling phase adjust for interleaving Yes Yes
operation
Core input impedance 100 ohm differential impedance calibration Yes Yes
CML output impedance 100 ohm differential impedance calibration Yes Yes
CMiref Input common mode calibration Yes Yes
6.2.1 Input common mode calibration

ADC analog input can operates in DC coupling or AC coupling mode. To cope with previous amplifier output stage,
ADC input common mode (CMIREF) can be trimmed via AB_CMIREF and CD_CMIREF registers described below.
Adjustment of input common mode can also be used to optimize ADC linearity.
Table 36. AB_CMIREF and CD_CMIREF registers description

AB_CMIREF
CD_CMIREF
Default
Value
AB_CMIREF 0x0905 R/W 5 0x14 A, B input common mode calibration for A & B cores
CD_CMIREF 0x0906 R/W 5 0x 14 C, D input common mode calibration for C &D cores
AB_CMIREF
CMIREF
CD_CMIREF
(V)
(hexa)
1F 1.525
10 1.6
0 1.675
excursion 0.15
step 5.10-3

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6.2.2 Input impedance calibration

ADC impedance matching is important to maximize power transmission. DC impedance can be trimmed digitally to
100 (Ω) with AB_RIN and CD_RIN registers to compensate process variation or optimized power transmission, with
2% accuracy.
Table 37. AB_RIN and CD_RIN registers description
AB_RIN
CD_RIN
Default
Value
AB_RIN 0x0907 R/W 5 0x10 A, B Input impedance calibration for A, B cores
CD_RIN 0x0908 R/W 5 0x10 C, D Input impedance calibration for C, D cores
AB_RIN
Rin
CD_RIN
(Ω)
(hexa)
0 142
10 90
3F 68
excursion 74
step 2.4
6.3 CML output impedance calibration

ADC impedance matching is important to maximize power transmission. DC impedance of CML output buffers can
be trimmed digitally to 100 (Ω) with AB_ROUT_HSSL (or CD_ROUT_HSSL) register on both cores A and B (C and
D respectively) to compensate process variation or to optimize power transmission, with 5% accuracy.
Note: CLKOUT CML output buffers impedance cannot be trimmed.
Table 38. AB_ROUT_HSSL and CD_ROUT_HSSL registers description
AB_ROUT_HSSL
CD_ROUT_HSSL
Default
Value
AB_ROUT_HSSL 0x909 R/W 8 0x55 A, B bit[3:2]= R_cml1 channel A (for link1)
bit[1:0]= R_cml0 channel C (for link0)
CD_ROUT_HSSL 0x90A R/W 8 0x55 C, D bit[3:2]= R_cml1 channel C (for link1)
AB_ROUT_HSSL
ROUT
CD_ROUT_HSSL
(Ω)
(hexa)
0 83
1 100
3 125
excursion 42
step 14
page 46
EV12AQ600
6.4 Interleaving functions

To improve interleaving performances, gain, phase and offset of each ADC core can be corrected thanks to
embedded DACs accessible via registers described in the following paragraphs. 2 factory calibration sets are also
available (recommended condition of use).
6.4.1 Gain Adjustment

The Gain of each ADC core is independently adjustable thanks to two built in 12 bit DACs controlled thru the SPI.
This feature is mandatory for interleaving mode.
Reminder: 2 sets of OTP fuses are available
Table 39. y_SETx_GAIN_CAL, registers description (x=1, 2 and y= A, B, C, D)

A_SET1_GAIN_CAL
B_SET1_GAIN_CAL
C_SET1_GAIN_CAL
D_SET1_GAIN_CAL
A_SET2_GAIN_CAL
B_SET2_GAIN_CAL
C_SET2_GAIN_CAL
D_SET2_GAIN_CAL
Default
Value
A_SET1_GAIN_CAL 0x0122 W 12 0x800 A
B_SET1_GAIN_CAL 0x0322 W 12 0x800 B
interleaving gain calibration
C_SET1_GAIN_CAL 0x0522 W 12 0x800 C
D_SET1_GAIN_CAL 0x0722 W 12 0x800 D
A_SET2_GAIN_CAL 0x0125 W 12 0x800 A
B_SET2_GAIN_CAL 0x0325 W 12 0x800 B
interleaving gain calibration
C_SET2_GAIN_CAL 0x0525 W 12 0x800 C
D_SET2_GAIN_CAL 0x0725 W 12 0x800 D
The tuning range is equivalent to a 427LSB variation of full scale (step of 0.47 LSB).
y_SETx_GAIN_CAL Fullscale variation

(hexa) (LSB)
0 -213,5
800 0
FFF 213,5
excursion 427
step 0.43

EV12AQ600
6.4.2 Phase adjustment

The phase of each ADC core is independently adjustable thanks to two built in 9 bit DACs controlled thru the SPI.
Table 40. y_SETx_PHASE_CAL registers description (x=1, 2 and y= A, B, C, D)

A_SET1_PHASE_CAL
B_SET1_PHASE_CAL
C_SET1_PHASE_CAL
D_SET1_PHASE_CAL
A_SET2_PHASE_CAL
B_SET2_PHASE_CAL
C_SET2_PHASE_CAL
D_SET2_PHASE_CAL
Default
Value
A_SET1_PHASE_CAL 0x0123 W 9 0x0100 A

B_SET1_PHASE_CAL 0x0323 W 9 0x0100 B interleaving phase calibration
C_SET1_PHASE_CAL 0x0523 W 9 0x0100 C
D_SET1_PHASE_CAL 0x0723 W 9 0x0100 D
A_SET2_PHASE_CAL 0x0126 W 9 0x0100 A
B_SET2_PHASE_CAL 0x0326 W 9 0x0100 B
interleaving phase calibration
C_SET2_PHASE_CAL 0x0526 W 9 0x0100 C
D_SET2_PHASE_CAL 0x0726 W 9 0x0100 D
The tuning range is equivalent to ± 0.9ps (step of 3.5 fs).

For wider range, SDA operation described hereafter could also be used.
y_SETx_PHASE_CAL phase variation

(hexa) (fs)
0 -900
080 0
FF 900
excursion 1800
step 3.5
page 48
EV12AQ600
6.4.3 Offset adjustment

The Offset of each ADC core is independently adjustable thanks to two built in 9 bit DACs controlled thru the SPI.
Table 41. y_SETx_OFFSET_CAL registers description (x=1, 2, 3, 4 and y= A, B, C, D)

A_SET1_OFFSET_CAL
B_SET1_OFFSET_CAL
C_SET1_OFFSET_CAL
D_SET1_OFFSET_CAL
A_SET2_OFFSET_CAL
B_SET2_OFFSET_CAL
C_SET2_OFFSET_CAL
D_SET2_OFFSET_CAL
Default
Value
A_SET1_OFFSET_CAL 0x0124 W 9 0x0100 A
B_SET1_OFFSET_CAL 0x0324 W 9 0x0100 B
Interleaving offset calibration
C_SET1_OFFSET_CAL 0x0524 W 9 0x0100 C
D_SET1_OFFSET_CAL 0x0724 W 9 0x0100 D
A_SET2_OFFSET_CAL 0x0127 W 9 0x0100 A
B_SET2_OFFSET_CAL 0x0327 W 9 0x0100 B
Interleaving offset calibration
C_SET2_OFFSET_CAL 0x0527 W 9 0x0100 C
D_SET2_OFFSET_CAL 0x0727 W 9 0x0100 D
The tuning range is equivalent to +/- 27.4 LSB (step of 0.11 LSB)
y_SETx_OFFSET_CAL offset variation

(hexa) (LSB)
0 -27.4
100 0
1FF 27.4
excursion 55
step 0.11

EV12AQ600
7 APPLICATION INFORMATION
7.1 Power supplies
7.1.1 Power supply ramp-up

Supplies settling time should be faster than 10ms. No specific power sequencing is required.
7.1.2 Bypassing, decoupling and grounding

Each power supply has to be bypassed as close as possible to its source or access by 100 nF in parallel to 22 μF
capacitors (value depending of DC/DC regulators).
All grounds pins have to be connected on PCB but locally under the component, a slit between AGND+DGND
(analog and digital ground) and GNDO (IO ground) has to be respected.
The minimum number of decoupling pairs of capacitors can be calculated as the minimum number of groups of
neighboring pins as described in Figure 19 and Table 42.
EV12AQ600
VCCA VCCO B
22 nF 100 nF
GND GNDO
X18 X4
VCCD
VCC_SPI B
100 nF
100 nF
GND
GND
x4
x1
Figure 19 - Power Supplies decoupling scheme

Table 42. List of recommended neighboring pins for VCCA decoupling
(VCCA, AGND)
Pins (E9-D9); (E10-D10) ; (G9-F9) ; (G10-F10) ; (G11-F11) ; (G8-F8)
(J8-H8); (J11-H11); (H9-J9); (H10-J10)
Pins (K8-K7); (K11-K12); (K9-L9); (K10-L10); (L8-M8); (L11-M11); (M9-N9); (M10-N10)
Table 43. List of recommended neighboring pins for VCCD decoupling

(VCCD, DGND)
Pins (G6-G7); (H6-J6); (K6-L6); (M6-N6)
Pins (G13-G12); (H13-J13); (K13-L13); (M13-N13) ; (F14-F13)
Table 44. List of recommended neighboring pins for VCCO decoupling

VCCO- GNDO
Pins (H4-J4); (M4-L4); (K4-K3); (H5-J5); (M5-L5)
Pins (H14-J14); (M14-L14); (K15-K16); (H15-J15); (M15-L15)
Table 45. List of recommended neighboring pins for VCC_SPI decoupling

VCC_SPI- DGND
Pins (F5-F6)
page 50
EV12AQ600
7.2 High Speed Serial Interface

More information on the ESIstream protocol can be found on www.esistream.com.
The ESIstream protocol is a 14b/16b encoding based on 14 scrambled bits along with 2 overhead bits: clock bit
and disparity bit. Applied onto the EV12AQ600, the 16 bits frames are as follows:
Figure 20 - ESIstream frame with EV12AQ600
DB being the disparity bit, CLK the clock bit, CB1 and CB2 the control bit of the ADC (Refer to Table 27) and bit 11
to 0 contains the ADC sample. Bit 13 to 0 are scrambled using an LSFR (Linear Feedback Shift Register) that
generate the PRBS (Pseudo-Random Binary Sequence). The frames are transmitted LSB first.
7.2.1 ESIstream protocol
7.2.1.1 Scrambling
Applying scrambling ensures a statistical DC balanced transmission. It also statistically ensures that there are
transitions in the transmission. It is necessary to comply with these constraints otherwise the CDR (Clock and Data
Recovery) may lose its lock and the data would be corrupted.
The scrambling technique used in ESIstream is an additive scrambling to avoid error propagation in case of a
single bit error. It is based on Fibonacci architecture using the following polynomial: X17+X3+1. It has a run length
of 217 - 1. Instead of using a shift of one bit per operation, it uses shifts of 14 bits per operation to adapt to the size
of the data being scrambled.
The equations to use to generate this PRBS are as follow:
0 14
1 15
2 16
3 0 xor 3
4 1 xor 4
5 2 xor 5
6 3 xor 6
7 4 xor 7
8 5 xor 8
9 6 xor 9
10 7 xor 10
11 8 xor 11
12 9 xor 12
13 10 xor 13
14 11 xor 14
15 12 xor 15
16 13 xor 16
The PRBS is applied to the data as follow; the 14 LSB of the PRBS are the bits used to scramble the data.
Figure 21 - LFSR operation

This particular LFSR was chosen because it reduces the number of necessary gates to be implemented.

EV12AQ600
7.2.1.2 Encoding
After scrambling, the 14 bits of data are encoded into a 16 bits frame. One of the added bits is the clk bit; it toggles
at every frame. The last bit encoding these 15 bits is the disparity bit. Its objective is to ensure deterministically the
advantages brought statistically by the scrambling process.
Figure 22 - Frame format after encoding
Even with scrambling, large running disparity can still occur with very low probability and could produce excessive
eye shifts. These eye shifts could be balanced by a more complicated equalization stage in the receiver if the
running disparity was still limited. However, a PRBS does not bind the running disparity deterministically, thus the
data could be corrupted on the reception end and it could eventually cause the CDR to lose its lock. To prevent
this, the disparity bit is implemented.
The running disparity of the transmission is constantly monitored by the transmitter on each link.
For each frame, its disparity is calculated, 2 cases can occur on the running disparity:
a. The running disparity of the transmission does not increase above +/- 15 (+15 and -15 included). In
this case, the disparity bit is set to ‘0’ and the 15 bits of data (scrambled data + clk bit) are transmitted
as such.
b. The running disparity of the transmission does increase above +/-15 (+15 and -15 excluded). In this
case, the 15 bits of data (scrambled data + clk bit) are inverted and the disparity bit is set to ‘1’.
The running disparity is updated with the disparity of the frame.
This disparity bit ensures that the longest possible series of ’1’ or ‘0’ transmitted is of 48 bits (the clk bit reduces this
value effectively to 32). It also ensures that the running disparity does not exceed +/- 15 (included) which satisfies
the DC balance condition.
In normal operating mode, the receiver will check the disparity bit first. If it is high then it will invert the received
data and descramble them. Otherwise it will directly descramble them.
7.2.1.3 Synchronization
The link must be synchronized to align the frames between the transmitter and the receiver and to synchronize the
reception scrambler with the transmission scrambler. The synchronization is controlled through the SYNC signal
sent by the receiver (FPGA/ASIC) to the transmitter (EV12AQ600).
The synchronization works in 2 steps and starts when the ADC receives a SYNCTRIG pulse in SYNC mode (refer
to section 5.5).
Figure 23 - Synchronization sequence
page 52
EV12AQ600
When the ADC sees the SYNCTRIG pulse, it will send an alignment pattern which is 32 frames alternating between
0xFF00 and 0x00FF. The sequence bypasses the scrambling and disparity processing (the sequence is DC
balanced). This alignment pattern should be used by the receiver to align its data on the transmitter output data.
After these 32 frames, the transmitter starts sending 32 additional frames containing the scrambling PRBS alone.
These frames contain 14 bits of the PRBS plus the clk bit and the disparity bit. They go through the disparity
processing, as the PRBS value will start to impact the running disparity of the transmission.
Figure 24 - Frame sent for PRBS initialization
The receiver will detect the transition from the alignment pattern to the PRBS alone (passive detection). It will
determine the initial value it has to start its PRBS with after receiving 2 frames of the PRBS. These 2 frames
contain 28 bits of the PRBS sequence; the receiver needs 17 bits to determine its initial value. The transmitter
(EV12AQ600) PRBS sequence is reset upon reception of a SYNCTRIG pulse in SYNC mode.
The PRBS used is based on the polynomial sequence X7 + X6 + 1.
After these 2 steps, the synchronization of the link is complete.
During normal operation, the synchronization of the serial links can be monitored through the clk bit. In case the
receiver does not detect that the clk bit is toggling properly, then it can state that the link is not synchronous or has
lost its synchronization and restart the synchronization process. Another option is to use the timestamp control bit
of the ADC to monitor the interface synchronization
7.3 Interleaving Calibration protocol

To reduce interleaving spur, phase, offset and gain can be adjusted through SPI. Refer to Table 39 to Table 41.
7.3.1 Offset interleaving calibration
To set offset, DC value should be extracted with high precision to quantify offset unbalance between cores. Offset
adjust 9 bits DAC should be set at the right value to decrease DC offset mismatch.
Protocol:
 Use single core output data with or without input signal
 Calculate output data average for each core DCcorex
 Apply DC correction equal to:
DCcorrectionx= (DCcorex-DCref)/LSBdccorex
With:
 DCcorrectionx= DAC code to compensate COREx DC offset

 DCcorex= DC offset at CORE X output
 DCref= reference value to align cores DC offset. It can be set to 2048 or to one core offset value
 LSBdccorex= core x DC offset DAC calibration LSB
Core x DC offset DAC calibration LSB is determined by measuring core x DC offset at maximum and minimum
correction.
LSBdccorex= (DCcorex@maxcode- DCcorex@mincode)/ (maxcode-mincode-1)
With:
 DCcorex@maxcode=core x DC offset at maximum DC offset correction code

 DCcorex@mincode=core x DC offset at minimum DC offset correction code
 Maxcode=511
EV12AQ600
 Mincode=0
7.3.2 Gain and phase interleaving calibration
By using FFT on each core output, gain and phase of each core can be estimated at input frequency Fin of interest.
Correction is calculated
GAINcorrectionx= (Gainx -Gainref)/LSBgaincorex
Phasecorrectionx= (Phasex - Phaseref)/LSBphasecorex/(360*Fin)
With :
Core x : core to be calibrated

Gainx :core x gain in dB
Gainref : core gain reference in dB
Phasex :core x phase in degree
Phaseref : core phase reference in degree
Fin: frequency of interest
Gain and phase measurement accuracy should be negligible regarding ADC LSB.
page 54
EV12AQ600
8 ORDERING INFORMATIONS
Table 1: Prototypes
Part Number Temperature Range Screening Level Comments
EVP12AQ600GH Ambient Prototype SnPb spheres
EVP12AQ600SH Ambient Prototype SAC spheres

EV12AQ600
9 REVISION HISTORY
Issue Date Comments
A 22/03/2018 Creation
B 27/04/2018 Main page: bring some clarification on performance in the different Nyquist
zones
Figure 1 modified for clarification
Table 3: clock output level is referenced to VCCA and not VCCO
Table 12: CLKOUT is an output and not an input
page 56
EV12AQ600
Table of contents
1 Description ........................................................................................................................................ 3
2 Specifications ................................................................................................................................... 5
2.1 Absolute Maximum Ratings ........................................................................................................................................................... 5
2.2 Qualification requirements ............................................................................................................................................................. 6
2.3 Recommended conditions of use ................................................................................................................................................... 6
2.4 Electrical Characteristics for supplies, Inputs and Outputs ............................................................................................................ 7
2.5 Converter Characteristics ............................................................................................................................................................... 9
2.6 Transient and Switching Characteristics ...................................................................................................................................... 13
2.7 Digital Output Coding ................................................................................................................................................................... 15
2.8 Definition of Terms ....................................................................................................................................................................... 16
3 Package Description ...................................................................................................................... 17
3.1 Type /Outline ................................................................................................................................................................................ 17
3.2 Pinout top view ............................................................................................................................................................................. 19
3.3 Thermal characteristics ................................................................................................................................................................ 19
3.4 Pinout Table ................................................................................................................................................................................. 20
4 Theory of Operation ....................................................................................................................... 25
4.1 Overview ...................................................................................................................................................................................... 25
5 Serial Peripheral Interface (SPI) .................................................................................................... 26
5.1 SPI logic compatibility .................................................................................................................................................................. 26
5.2 Timings ......................................................................................................................................................................................... 26
5.3 Register map ................................................................................................................................................................................ 27
5.4 Digital Reset and start up procedure ............................................................................................................................................ 31
5.5 ADC Synchronization Signal (SYNCTRIGP, SYNCTRIGN) ........................................................................................................ 31
5.6 Cross-point switch (CPS) ............................................................................................................................................................. 32
5.7 Clock interleaving ......................................................................................................................................................................... 33
5.8 Calibration selection ..................................................................................................................................................................... 34
5.9 Analog bandwidth ......................................................................................................................................................................... 35
5.10 SYNC, slow and fast output clocks (SSO, CLKOUT) ................................................................................................................... 35
5.11 Serial link output configuration ..................................................................................................................................................... 37
5.11.1 Serial link output swing and polarity configuration ....................................................................................................................... 37
5.11.2 Serial link In Range, Trigger, Timestamp, Parity and bit order configuration ............................................................................... 38
5.11.3 Trigger mode ................................................................................................................................................................................ 39
5.11.4 Parity bit ....................................................................................................................................................................................... 39
5.11.5 In-range bit ................................................................................................................................................................................... 39
5.11.6 TIMESTAMP ................................................................................................................................................................................ 39
5.12 Test modes .................................................................................................................................................................................. 40
5.12.1 PRBS............................................................................................................................................................................................ 40
5.12.2 Ramp mode .................................................................................................................................................................................. 40
5.12.3 DC balance .................................................................................................................................................................................. 41
5.13 CRC CHECKING ......................................................................................................................................................................... 41
5.14 CHIP ID ........................................................................................................................................................................................ 42
5.15 Single event protection ................................................................................................................................................................. 42
5.16 SDA operation .............................................................................................................................................................................. 43
6 Die junction temperature monitoring diode ................................................................................. 44
6.1 Functionalities Summary .............................................................................................................................................................. 44
6.2 Calibrations summary .................................................................................................................................................................. 45
6.2.1 Input common mode calibration ................................................................................................................................................... 45
6.2.2 Input impedance calibration ......................................................................................................................................................... 46
6.3 CML output impedance calibration ............................................................................................................................................... 46
6.4 Interleaving functions ................................................................................................................................................................... 47
6.4.1 Gain Adjustment ........................................................................................................................................................................... 47
6.4.2 Phase adjustment ........................................................................................................................................................................ 48
6.4.3 Offset adjustment ......................................................................................................................................................................... 49
7 Application information ................................................................................................................. 50
7.1 Power supplies ............................................................................................................................................................................. 50
7.1.1 Power supply ramp-up ................................................................................................................................................................. 50
7.1.2 Bypassing, decoupling and grounding ......................................................................................................................................... 50
7.2 High Speed Serial Interface ......................................................................................................................................................... 51
7.2.1 ESIstream protocol ....................................................................................................................................................................... 51
7.3 Interleaving Calibration protocol ................................................................................................................................................... 53
7.3.1 Offset interleaving calibration ....................................................................................................................................................... 53
7.3.2 Gain and phase interleaving calibration ....................................................................................................................................... 54
8 Ordering informations .................................................................................................................... 55
9 Revision history .............................................................................................................................. 56

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EV12AQ600

Quad 12bit 1.5 Gsps ADC with embedded

OVERVIEW At -8 dBFS output level:

1203B-BDC-04/18 page 1 Teledyne e2v Semiconductors SAS 2018

Figure 1 - Quad 12-bit ADC with 12Gbps serial link

Functionalities controlled thru the SPI are:

1203B-BDC-04/18 page 3 Teledyne e2v Semiconductors SAS 2018

Table 1. Absolute Maximum ratings

Figure 2 – Analog input scheme regarding max ratings

1203B-BDC-04/18 page 5 Teledyne e2v Semiconductors SAS 2018

2.2 Qualification requirements

Parameter Symbol Value Unit

2.3 Recommended conditions of use

Note 1: To be configured depending on configuration of pin VSPI_SEL. Refer to section 5.1.

2.4 Electrical Characteristics for supplies, Inputs and Outputs

Table 3. Electrical characteristics for Supplies, Inputs and Outputs

Analog Input power Level PIN +1 dBm

Clock input power level in 100 PCLK, CLKN TBD +1 +7 dBm

1203B-BDC-04/18 page 7 Teledyne e2v Semiconductors SAS 2018

Parameter Symbol Min Typ Max Unit Note

CLOCK output (CLKOUT)

2.5 Converter Characteristics

Table 4. Low frequency characteristics

1203B-BDC-04/18 page 9 Teledyne e2v Semiconductors SAS 2018

Table 5. Dynamic Characteristics

Parameter Symbol Min Typ Max Unit Note

At -3 dBFS output level

At -8 dBFS output level

At -12 dBFS output level

Parameter Symbol Min Typ Max Unit Note

At -3 dBFS output level

At -8 dBFS output level THD

At -12 dBFS output level

At -8 dBFS output level SNR

1203B-BDC-04/18 page 11 Teledyne e2v Semiconductors SAS 2018

Parameter Symbol Min Typ Max Unit Note

At -8 dBFS output level ENOB

2.6 Transient and Switching Characteristics

Table 6. Transient characteristics

Table 7. Switching characteristics

1203B-BDC-04/18 page 13 Teledyne e2v Semiconductors SAS 2018

Parameter Symbol Min Typ Max Unit Note

Figure 3 - Serial link eye diagram

Table 8. SPI Timing characteristics

Figure 4 - SPI timing diagram

2.7 Digital Output Coding

< - 500.125 mV < Bottom end of full scale - ½ LSB 000000000000 0

1203B-BDC-04/18 page 15 Teledyne e2v Semiconductors SAS 2018

2.8 Definition of Terms

HiTCE Ceramic Ball Grid Array CBGA323

Figure 5 – Package cross-section

1203B-BDC-04/18 page 17 Teledyne e2v Semiconductors SAS 2018

Figure 6 – Package outline

3.3 Thermal characteristics

Table 11. Thermal characteristics

Delta temperature Hot spot – temperature from diode +6.2 °C

1203B-BDC-04/18 page 19 Teledyne e2v Semiconductors SAS 2018

3.4 Pinout Table

Pin Label Pin number Description Direction Simplified electrical schematics