Full-Wave Rectifier Reference Design
Full-Wave Rectifier Reference Design
Full-Wave Rectifier Reference Design
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R1 R2
V+
V+
U2A
U2B R3 VOUT
+
+ -0.23V
-0.23V
VIN D1
V+
U3
+
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1 Design Summary
The design requirements are as follows:
Supply Voltage: 5 V
The goals of this design are to achieve accurate full-wave rectification of low-level signals at frequencies of
50 kHz and less. Figure 1 displays the measured input and output signals with a 1 kHz, 100 mVpp sine-
wave input. Channel 2 is the input voltage, Vin and Channel 1 is the output voltage, Vout
VIN
VOUT
Figure 1: Measured output transient waveform with 1 kHz, 100 mVpp input signal
2 Theory of Operation
A more complete schematic for the single supply full wave rectifier circuit is shown in Figure 2. This
topology was chosen to meet the design goals for signal levels as small as 5 mVpp. U2B is used to buffer
the input signal and prevents gain interactions between the feedback impedance of U 2A and the source
resistance of the signal source. With U2B in the circuit, the input impedance is set by R4, the source
termination resistor. U2B can be removed to allow bipolar input signals with a peak-to-peak voltage twice
as large as the supply voltage at the expense of decreased input impedance as described in Section 7.
This design differs from traditional single-supply rectifiers and allows for excellent linearity at low-level
signals by using the LM7705 negative bias generator. The LM7705 generates a -0.23 V output from the
+5V supply that is connected to negative supply pin of U2A and U2B. This allows a rail-to-rail input/output op
amp to accept signals and create outputs that are below the circuit ground (GND) potential of 0 V.
C1 4.7uF
U1 LM7705 C2
22uF
CFLY+ CFLY-
+5V VSS CRES -0.23V
SD VOUT
VDD VSS C8 C9 C10
C5 C6 C7 22uF 0.47uF 1000pF
10μF 0.1μF 100pF
R1 R2
1kΩ 1kΩ
C11
+5V
+5V
U2A
U2B R3 VOUT
+
+ -0.23V
-0.23V 1kΩ
VIN R4 D1 1N4148
C14
+5V
U3
+
R1 R2
1kΩ 1kΩ
+5V
+5V
U2A
U2B R3 VOUT
+
+ -0.23V
-0.23V 1kΩ
VIN R4 D1 1N4148
+5V
U3
+
VOUT R R
( 2 ) (1 2 )
v IN R1 R1 (1)
VOUT VIN
R3 should be sized such that the current flowing through it while U 3 is holding the non-inverting input of U2A
to GND is not significant to cause output errors of either U2B or U3 due to current draw.
R1 R2
1kΩ 1kΩ
+5V R1 R2
+5V
U2A VOUT
U2B R3 1kΩ 1kΩ
+ VIN +5V
+ -0.23V
-0.23V 1kΩ U2A
VIN R4 D1 1N4148 VOUT
+
-0.23V
+5V
U3
+
VOUT R
( 2 )
VIN R1
(2)
If R1 R2
VOUT VIN
3 Component Selection
3.2 Diode
Important specifications of the D1 diode are low forward voltage (VF), fast switching speed (TT), low diode
capacitance (CD), and low leakage current (IR). Schottky diodes usually have fast transition time but lager
leakage current. Standard diodes have low reverse current. The diode used in this design is fast switching
diode 1N4148 based on its performance and cost. Table 1 compares several diode candidates.
Table 1. Diode Selection Parameters
While they were not required for this version of the design with the OPA350, the compensation capacitors,
C18 and C19, should be selected as C0G/NP0 dielectrics with the proper voltage rating.
The tolerance of the other passive components in this circuit can be selected for 1% or above since the
components will not directly affect accuracy of this circuit.
4 Simulation
TM
The TINA-TI schematic shown in Figure 5 includes the circuit values obtained in the design process.
Since currently there is no macro model for LM7705, it is not included and has been replaced with a -0.23
V voltage source, Vee. DC analysis displays a dc offset voltage of -219.06 μV and dc quiescent current of
5.2 mA per OPA350 channel.
Vcc Vee
C4 100n
C3 10u
Vcc 5 V1 -230m
R1 1k R2 1k
Vee
Vee
-
C15 100n
C14 100p
VOUT -219.06uV
+
+
U1 OPA350
-
R3 1k Vcc
D1 1N4148
+
+ U3 OPA350
+
Vcc
R4 49.9
VIN -
Iq 5.2mA
C12 100p
C13 100n
+
+ U2 OPA350
Vcc
C17 100n
C16 100p
TM
Figure 5: TINA-TI simulation schematic showing dc output offset and quiescent current
T 400.00m
200.00m
Voltage (V)
0.00
-200.00m
Vin
Vout
-400.00m
1.00m 1.50m 2.00m 2.50m 3.00m
Time (s)
T 400.00m
200.00m
Voltage (V)
0.00
-200.00m
-400.00m
1.00m 1.50m 2.00m 2.50m 3.00m
Time (s)
of the diodes, as well as the slew rate and output current limits of U2B.
T 400.00m
0.00
-200.00m
Vin
Vout
-400.00m
500.00u 510.00u 520.00u 530.00u 540.00u
Time (s)
T 400.00m
200.00m
Voltage (V)
0.00
-200.00m
-400.00m
500.00u 510.00u 520.00u 530.00u 540.00u
Time (s)
The circuit performance with a low-level 5 mVpp, 1 kHz input signal is shown in Figure 8. Low-level input
signals have a limited useful bandwidth compared to larger amplitude signals because the distortion
dominates the output waveform easier at the low signal levels. Figure 9 shows how the distortion begins to
dominate the output with a low-level 5 mVpp input at just 5 kHz.
T 4.00m
2.00m
Voltage (V)
0.00
-2.00m
Vin
Vout
-4.00m
1.00m 1.50m 2.00m 2.50m 3.00m
Time (s)
T 4.00m
2.00m
Voltage (V)
0.00
-2.00m
Vin
Vout
-4.00m
1.00m 1.10m 1.20m 1.30m 1.40m
Time (s)
T 80.00m
60.00m
40.00m
20.00m
Voltage (V)
0.00
-20.00m
-40.00m
Vin
-60.00m Vout
-80.00m
2.499m 2.500m 2.500m 2.501m 2.501m
Time (s)
TM
Figure 10: TINA-TI simulated output step response at input of 50 mVpp
The simulated results show the design functions well at the maximum input signal level up to the maximum
frequency of 50 kHz with limited distortion. Full-wave rectification of low-level signals is possible at speeds less
than 1 kHz with limited distortion.
5 PCB Design
The PCB schematic and bill of materials can be found in the Appendix A.1 and A.2.
6.1 DC Measurements
DC measurements were made for the offset voltage and the quiescent current for five units. The average
values are reported in Table 2.
Table 2. Measured DC result summary
Measured Value
Output Offset Voltage (μV) 68.15
Quiescent Current (mA) 14.17
The transient response of the design with a 400 mVpp, 1 kHz sine-wave input signal is shown in Figure 12.
The design creates a very accurate full-wave rectified output with minimal distortion.
Figure 12: Measured output with 400 mVpp at 1 kHz sine-wave input
Figure 13 displays the measured transient response with a 50 kHz, 400 mVpp input. The output waveform
achieves good performance with only slight distortion, conforming to the design goals.
Figure 13: Measured output with 400 mVpp at 50 kHz sine-wave input
Figure 14 and Figure 15 display the performance with low-level 5 mVpp signals at 1 kHz and 5 kHz
respectively. The distortion is minimal at 1 kHz but increases quickly as the input frequency increases. The
output waveforms match simulation results shown in Figure 8 and Figure 9.
Figure 16: Measured output step response at input 50 mVpp and 1 kHz
Figure 17: FFT of output at 1 kHz with 400 mVpp sine-wave input
The measured transient results show the maximum frequency is approximately 50 kHz with a +/- 200 mV
input sine-wave before distortion begins to affect the signal integrity. The design also succeeds in achieving
a low distortion full-wave rectified output with a 5 mVpp low-level input signal at frequencies below 1 kHz
with minimal distortion.
7 Modifications
An absolute circuit can be implemented by many op amps provided they have the proper bandwidth and
slew rate for the input signals. However, as mentioned in the component selection section, this circuit will
work best with a low noise, low THD, wide bandwidth, high slew rate, and high AOL op amp. Other single
supply amplifiers suitable for this design are described as follows. OPA320 and OPA322 are other
precision amplifiers with modest bandwidths but better low frequency performance. The OPA353, OPA354,
and OPA356 are high speed op amps which have high bandwidth and slew rate; however, due to their
offset and to obtain a higher dynamic range, they should be applied in the design without input buffer and
LM7705. These op amps’ performance is summarized in Table 3.
Table 3. Alternate Single Supply Amplifiers
fin=10kHz
0.0005 at
OPA322 1 20 10 130 8.5 2 1.8 10 1.9
fin=10kHz
0.0006 at
OPA350 1 38 22 122 15 0.5 4 10 7.5
fin=1kHz
0.0006 at
OPA353 1 44 22 122 15 8 5 10 8
fin=1kHz
0.0178 at
OPA354 1 250 150 106 70 8 4 50 6
fin=1MHz
0.0891 at
OPA356 1 450 300 92 80 9 7 50 11
fin=1MHz
This circuit was designed to optimize the full-wave rectification performance of low-level signals below
200mVpp. As a result the input buffer, U2B, was included to prevent the source impedance of the input
signal from creating a gain error that leads to an unbalanced output for the positive and negative cycles.
With a -230 mV negative supply, the output stage of U2B limits the negative input signal magnitude to
roughly -200 mV before the output stage begins to saturate. Without the input buffer this topology can
accept inputs that are double the supply voltage. So a +5V single-ended supply can handle +/-5V inputs
as shown in Figure 18 below.
Figure 18: Output at 1 kHz with 4.95 Vp sine-wave input of the circuit without input buffer
Collin Wells is an applications engineer in the Precision Linear group at Texas Instruments where he
supports industrial products and applications. Collin received his BSEE from the University of Texas,
Dallas.
2. D. Jones and M. Stitt. (1997, Dec.). Precision Absolute Value Circuits. Available:
http://www.ti.com/lit/an/sboa068/sboa068.pdf
Appendix A.
Item # Quantity Designator Value Description Manufacturer Manufacturer Part Number Supplier Part Number
1 1 C1 4.7uF CAP, CERM, 4.7uF, 25V, +/-10%, X7R, 1206 TDK C3216X7R1E475K 445-1606-1-ND
2 2 C2, C8 22uF CAP, CERM, 22uF, 16V, +/-20%, X7R, 1210 TDK C3225X7R1C226M 445-3955-1-ND
3 1 C3 10uF CAP, TANT, 10uF, 50V, +/-10%, 0.4 ohm, 7343-43 SMD AVX TPSE106K050R0400 478-3361-1-ND
4 2 C4, C6 0.1uF CAP, CERM, 0.1uF, 50V, +/-10%, X7R, 0805 MuRata GRM21BR71H104KA01L 490-1666-1-ND
5 1 C5 10uF CAP, CERM, 10uF, 25V, +/-10%, X7R, 1206 MuRata GRM31CR71E106KA12L 81-GRM31CR71E106KA12
6 1 C7 100pF CAP, CERM, 100pF, 50V, +/-5%, C0G/NP0, 0805 MuRata GRM2165C1H101JA01D 490-1615-1-ND
7 1 C9 0.47uF CAP, CERM, 0.47uF, 16V, +/-10%, X7R, 0805 AVX 0805YC474KAT2A 478-1403-1-ND
8 1 C10 1000pF CAP, CERM, 1000pF, 100V, +/-5%, C0G/NP0, 0805 AVX 08051A102JAT2A 478-1290-1-ND
10 3 C12, C15, C17 100pF CAP, CERM, 100pF, 50V, +/-5%, C0G/NP0, 0603 Kemet C0603C101J5GACTU 399-1061-1-ND
11 3 C13, C16, C18 0.1uF CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603 MuRata GRM188R71E104KA01D 490-1524-1-ND
16 3 R1, R2, R3 1.00k RES, 1.00k ohm, 0.1%, 0.1W, 0603 Yageo America RT0603BRD071KL 603-RT0603BRD071KL
17 1 R4 49.9 RES 49.9 OHM 0.20W 0.1% 0805 Vishay Thin Film PAT0805E49R9BST1 PAT49.9BCT-ND
19 4 TP2, TP3, TP4, TP5 Test Point, TH, Miniature, Black Keystone 5001 5001K-ND
200.00m
Voltage (V)
0.00
-200.00m
Vin
Vout
-400.00m
500.00u 550.00u 600.00u 650.00u 700.00u
Time (s)
T 400.00m
200.00m
Voltage (V)
0.00
-200.00m
-400.00m
500.00u 550.00u 600.00u 650.00u 700.00u
Time (s)
Figure 21: Measured output with 400 mVpp at 10 kHz sine-wave input
Figure 23: FFT of output at 50 kHz with 400 mVpp sine-wave input
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