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CHAPTER 6 DIGITAL ELECTRONICS

INTRODUCTION
Our world is an analog world. Measurements that we make of the physical objects around us
are never in discrete units, but rather in a continuous range. We talk about physical constants
such as 2.718281828… or 3.141592…. To build analog devices that can process these values
accurately is next to impossible. Even building a simple analog radio requires very accurate
adjustments of frequencies, voltages, and currents at each part of the circuit.
To make things simpler, we work with a digital abstraction of our analog world. Instead of
working with an infinite continuous range of values, we use just two values! Yes, just two
values: 1 and 0, on and off, high and low, true and false, black and white, or whatever you want
to call it. It is certainly much easier to control and work with two values rather than an infinite
range. We call these two values a binary value for the reason that there are only two of them. A
single 0 or a single 1 is then a binary digit or bit. This sounds great, but we have to remember
that the underlining building block for our digital circuits is still based on an analog world.

This chapter discusses how digital circuits are implemented at the physical level. As you know,
transistors are the fundamental building blocks for all digital circuits. They are the actual
physical devices that implement the binary switch and, therefore, also for the logic gates. There
are many different transistor technologies for creating a digital circuit. Some of these
technologies are the diode-transistor logic (DTL), transistor-transistor logic (TTL), bipolar
logic, and complementary metal-oxide semiconductor (CMOS) logic. Among them, the most
widely used is the CMOS technology.

6.1 BASIC AND DERIVED LOGIC GATES

The three basic building blocks of digital circuits are the NOT, the OR, and the AND gates.
NOR, NAND, XOR, and XNOR gates are examples of derived logic gates. The operation of
these gates is explained in the upcoming sections.

a. NOT Gate (inverter)

The NOT gate simply inverts its input, so a 0 input will produce a 1 output, and a 1
becomes 0.
Logic symbol for NOT gate is shown in fig. 6.1.
x y

Figure 6.1 Logic symbol for NOT gate

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b. OR & NOR Gates

OR gate takes two or more inputs and produce an output of 1 if at least one of this
inputs is 1, and 0 if all are 0’s. NOR gate is derived by combining OR gate and Inverter
which does the opposite of OR gate. NOR gate give an output of 1 whenever all the
inputs are 0’s.

The logic symbol for two-input OR & NOR gates is depicted in fig. 6.2.

x x
F F
y y
(a) OR Gate Symbol (b) NOR Gate Symbo

Figure 6.2 Logic symbols for OR & NOR gates

Truth table for OR & NOR Gate is given in the table of figure 6.3.

x y F=x OR y F=x NOR y

1 1 1 0
1 0 1 0
0 1 1 0
0 0 0 1

Figure 6.3 Truth table for OR and NOR gates

c. AND & NAND Gates

AND gate takes two or more inputs and produces an output of 1 if and only if all the
inputs are 1, otherwise it gives 0 outputs. On the other hand, NAND gate produces an
output of 0 for only when all the inputs are 1.

The logic symbol for two-input AND & NAND gates is drawn in fig. 6.4.

x x
F F
y y

(a) AND Gate Symbol (b) NAND Gate Symbo

Figure 6.4 Logic symbols for OR & NOR gates

Truth table for AND & NAND Gate is shown in the table below

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x y F=x AND y F=x NAND y

1 1 1 0
1 0 0 1
0 1 0 1
0 0 0 1

Figure 6.5 Truth table for AND & NAND gate

d. XOR and XNOR Gates

XOR (exclusive OR) logic gate is a special class of derived logic gate that produce an
output of 1, only when one of the inputs is 1. XNOR does the opposite of XOR which
outputs 0 when one of the inputs is 1.

The logic symbol for XOR and XNOR gates is shown in figure 6.6.

X X
F F
Y Y

(a) XOR gate (b) XNOR gate

Figure 6.6 Logic symbol for XOR and XNOR gates

Truth table of XOR and XNOR gates for two inputs is given in the following table.

x y F=x XOR y F=x XNOR y

1 1 0 1
1 0 1 0
0 1 1 0
0 0 0 1

Figure 6.7 Truth table of two-input XOR and XNOR gates

6.2 REALIZATION OF DISCREET LOGIC GATES

Visualization of Gates with Binary switches

Two binary switches can be connected together either in series or in parallel to develop AND &
OR gate operations respectively.

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X
F F
X Y
Y
+ +5V +
- R - +5V R

(a) (b)
.
Figure 6.8 Switch realizations of gates

If two switches are connected in series as in figure 6.8 (a), then both switches have to be on in
order for the output F to be a 1. In other words, F = 1 if x = 1 and y = 1. If either x or y is off,
or both are off, then F = 0. This can be translated into the AND gate operation.

If we connect two switches in parallel as in figure 6.8 (b), then only one switch needs to be on
in order for the output F to be a 1. In other words, F = 1 if either x = 1, or y = 1, or both x and
y are 1’s. This means that F = 0 only if both x and y are 0’s. This is similar to the operation of
OR gate.

Realization of Gates with Digital Integrated Circuit

Physical circuits deal with physical properties, such as voltages and currents. Digital circuits
use the abstractions of 0 and 1 to represent the presence or absence of these physical properties.
In fact, a range of voltages is interpreted as the logic 0, and another, non-overlapping range is
interpreted as the logic 1. These ranges vary for different logic families. Traditionally, digital
circuits operate with a 5-volt power supply. In such a case, it is customary to interpret the
voltages in the range 0– 1.5 V as logic 0, while voltages in the range 3.5–5 V as logic 1. This
is shown in Figure 6.9. Voltages in the middle range (from 1.5–3.5 V) are undefined and should
not occur in the circuit except during transitions from one state to the other. However, they
may be interpreted as a “weak” logic 0 or a “weak” logic 1.

Figure 6.9 Voltage levels for logic 0 and 1.

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6.3 DIGITAL INTEGRATED CIRCUIT AND LOGIC FAMILIES

Logic families can be classified broadly according to the technologies they are built with. In
earlier days we had vast number of these technologies, as you can see in the list below.

• DL: Diode Logic.

• RTL: Resistor -Transistor Logic.
• DTL: Diode-Transistor Logic.
• TTL: Transistor-Transistor Logic.
• ECL: Emitter coupled logic.
• MOS: Metal Oxide Semiconductor Logic (PMOS and NMOS).
• CMOS: Complementary Metal Oxide Semiconductor Logic.

Among these, only CMOS logic is most widely used by chip designers; we will still try to
understand a few of the extinct / less used technologies, and more explanation of CMOS will be
covered in later section.

1. DIODE LOGIC

Simple digital logic gates can be made by combining diodes and resistors. Diode Logic makes
use of the fact that the electronic device known as a diode will conduct an electrical current in
one direction, but not in the other. In this manner, the diode acts as an electronic switch.

The OR Gate
Discrete OR gate may be realized by using diodes and a resistor as shown in Figure 6.10.
When at least one of the inputs X and Y are at +5V level, or Logic ‘1’, there will be an output
5v less 0.6V (diode forward voltage) which could be taken as logic ‘1’. On contrast, if both X
and Y becomes 0V, there will be no currents through the resistor and that will force the output
to be at the ground level.
D1
X F

Y
D2
R

Figure 6.10 Two-input diode discrete OR gate

The AND Gate:
Discrete AND gate may be realized by using diodes and resistor as shown in Figure 6.11.
When both X and Y are +5V (logic ‘1’), then two diodes are reverse biased to produce an
output of +5V (logic ‘1’). But, if either of X or Y is at 0V (logic ‘0’), one of these diodes is
forwarded pulling the output near to a ground (logic ‘0’).

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+5 V

X F

Figure 6.11 two-input diode-resistor AND gate

2. RESISTOR-TRANSISTOR LOGIC
One of the disadvantages of diode logic is that it is impossible to develop an inverter. Also DL
gates suffer from loading effect, which cause degradation of voltage from one stage to the next,
making it is difficult to connect many gates to a single gate. A correction to these problems is
to use bipolar transistor rather than diodes. In RTL (resistor transistor logic), all the logic are
implemented using resistors and transistors.

NOT Gate

Inverter can be realized by biasing NPN bipolar transistor to operate between cut-off and
saturation region. One basic thing about the NPN transistor is that HIGH input causes output
to be LOW. This bipolar inverter is the basic circuit from which most transistor logics are
developed.

+5V

R2

X
R1
X

Figure 6.12 transistor-resistors NOT gate

NOR Gate
Two-input Transistor-Resistor NAND gate is shown in fig. 6.13. The circuit will produce logic
‘1’, when only the two inputs are at 0V level causing the two transistors to operate in the cut-
off region. On the other hand, when either input X or Y is driven HIGH, the corresponding
transistor goes to saturation and output F is pulled to LOW.

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+5V

R R
X Y

Figure 6.13 Two-input transistor-resistor NOR gate

NAND Gate
For NAND gate operation two transistors can be connected in series as shown in fig. 6.14.
Here, the output is logic ‘1’, if either of the inputs is at logic ‘o’ level.

+5V

F
X

Figure 6.14 Two-input transistor-resistor NAND gate

3. DIODE-TRANSISTOR LOGIC GATES

Logic gates can also be constructed from the combination of Transistors and Diodes with fall in
the family of DTL, diode-transistor-logic. For example consider the following NAND gate
which is formed from diode-resistor AND gate and bipolar transistor Inverter.

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+5 V

X F

Figure 6.15 Two-input DTL NAND gate

4. TRANSISTOR-TRASISTOR (TTL) LOGIC

One of the problems with DTL circuits was that it takes as much room on the IC chip to
construct a diode as it does to construct a transistor. This necessitates the replacement of
diodes with transistors.TTL logic is directly evolved from DTL by replacing those input
diodes with one single NPN transistor with multiple emitter inputs as shown below for NAND
gate. When any input is driven low, the emitter base junction is forward biased and input
transistor conducts. This in turn drives the output transistor into cut-off, producing an output
of 1. But when both of the inputs are driven high, the emitter base junction become reveres
biased while the collector base diode completes the circuit between the supply and the base of
output transistor. The effect is to turn ON the output transistor pulling the output to the
ground.

+5 V

X
Y

Figure 6.16 Two input TTL NAND gate

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5. EMITTER-COUPLED LOGIC

The emitter-coupled logic (ECL) circuit is based on the differential amplifier circuit discussed
in chapter 2. For digital applications the diff-amp is driven into its nonlinear region. The
transistors are either in cut-off or in the active region. Saturation is avoided in order to
minimize switching time and propagation delay. Due to this ECL gates are used in application
where speed is very important. Basic ECL OR gate is shown in figure 6.17.

X Y
F
R

-VEE
Figure 6.17 Emitter Coupled OR gate

6. MOS Logic

MOS (metal oxide semiconductor) logic gates can be evolved from RTL logics by replacing
BJTs with their equivalent MOSFET and the output resistor with MOSFET based active
load. For example, the CMOS counter of RTL Inverter, NOR and NAND gates, are
developed using n-channel MOS transistor as in the figure 6.
+Vs +Vs

+Vs

F
F
X
F
X X Y
Y

Inverter NOR NAND

Figure 6.18 MOS logic gates

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7. CMOS Logic Gates

CMOS circuits are built using both the NMOS (n-channel MODFETs) and PMOS (p-channel
MOSFETs) transistors. Because of the inherent properties of the NMOS and PMOS
transistors, CMOS circuits are always built with two halves. One half will use one transistor
type while the other half will use the other type, and when combined together to form the
complete circuit, they will work in complement of each other.

The logic symbols and operations for the NMOS and PMOS transistors are shown in Figure
6.19 and Figure 6.20, respectively.

The operation of the NMOS transistor is shown in Figure 6.19(b). The biggest attraction
towards CMOS technology is due to the added opportunity of designing the logic circuit so
that there could not be unwanted power dissipation whenever there is no input. Consequently,
for proper operation of NMOS transistor, the input is connected to the gate terminal, one
terminal, say source, is grounded and the output is taken at the drain. For this configuration,
when the gate is 1, the NMOS transistor is turned on or enabled, thereby pulling the output to
the ground level. However, when the gate is a 0, the transistor is turned off, and the connection
between the source and the drain is disconnected. Thus, This NMOS configuration is inverter
of 1 and used to output the 0 half of the truth table.

Output

D Gate Status of Output

G
(input) Transistor
S
0 Open Circuited High impedance
1 Short Circuited 0

Figure 6.19 NMOS transistor: (a) logic symbol; (b) truth table.

The PMOS transistor works exactly the opposite of the NMOS transistor. For the PMOS
transistor, the source is the terminal with the higher voltage with respect to the drain. We can
intuitively think of the source as the terminal that is supplying the 1 value, while the drain
consumes the 1 value. The operation of the PMOS transistor is shown in Figure 6.20(b). When
the gate is a 0, the PMOS transistor is turned on or enabled, and the source input that is
supplying the 1 can pass through to the drain output through the connecting p-channel. On the
other hand, when the gate is a 1, the transistor is turned off, and the connection between the
source and the drain is disconnected. In this case, the drain will always have a high-impedance
value. Thus, this PMOS configuration is inverter of 0 and used to output the 1 half of the truth
table.

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+Vcc
Gate Status of Output
S (input) Transistor
G
0 Short Circuited 1
1 open Circuited High impedance
D
Output

Figure 6.20 PMOS transistor: (a) logic symbol; (b) truth table.

In CMOS technology a logic function f(x,y,…) is realized by two complementary circuits, one
pull-up circuit connected to the voltage source Vs, and a pull-down circuit connected to
ground, as shown in figure 6.21.
Vs

F(x,y,...)

X
Y
.
. Output
.

F’(x,y,…)

Figure 6.21 CMOS realization of digital circuits

When the inputs are such that the pull-up circuit is conducting (short) and the complementary
pull-down circuit is cutoff (open), the output is connected to the voltage source to output a high
voltage representing logic 1; however, when the input variables are such that the pull-up circuit
is cutoff (open) and the complementary pull-down circuit is conducting (short), the output is
connected to ground to output a low voltage representing logic.

CMOS Inverter

If we examine the truth table of inverter, half of the inverter truth table says that, given a 1, the
circuit needs to output a 0.Therefore, to realize this NMOS transistor is used. The
complementary half of the inverter circuit is to output a 1 when given a 0. Again, from looking
at the two transistor truth tables, we find that the PMOS transistor will do the job. To form
the complete inverter circuit, we simply combine these two complementary halves together, as
shown in Figure 6.22.

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+Vcc

input Output

Figure 6.22 CMOS inverter circuit:

For the above CMOS inverter circuit, when the gate input is a 1, the bottom NMOS transistor
is turned on while the top PMOS transistor is turned off. With this configuration, a 0 from
ground will pass through the bottom NMOS transistor to the output while the top PMOS
transistor will output a high-impedance value. Alternatively, when the gate input is a 0, the
bottom NMOS transistor is turned off while the top PMOS transistor is turned on. In this case,
a 1 from VCC will pass through the top PMOS transistor to the output while the bottom
NMOS transistor will output a high-impedance. The resulting output value is a 1. Since the
gate input can never be both a 0 and a 1 at the same time, therefore, the output can only have
either a 0 or a 1, and so, no short can result.

CMOS NAND Gate

The NAND Gate is operates as inverse of AND whose logic function for two inputs, X and Y,
could be given by
𝐹𝐹(𝑋𝑋, 𝑌𝑌) = (𝑋𝑋𝑋𝑋)′
Using the well known Demorgan’s law, this can, alternatively, be expressed as
𝐹𝐹(𝑋𝑋, 𝑌𝑌) = 𝑋𝑋 ′ + 𝑌𝑌 ′
Thus, the pull-up part of the NAND gate can be realized as the parallel connection of two
PMOS transistors.
The complement of NAND is simply AND gate which is expressed as
𝐹𝐹(𝑋𝑋, 𝑌𝑌) = 𝑋𝑋𝑋𝑋
This corresponds to the pull-down part of the NAND get which can be realized by the series
connection of two NMOS transistors. The complete CMOS NAND Gate is drawn in figure
6.23.

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+Vs
Pull-up circuit
X Y

Output
X
Pull-down circuit

Figure 6.23 CMOS NAND circuit:

CMOS AND Gate

We can proceed to derive this circuit in the same manner as we did for the NAND gate.
AND whose logic function for two inputs, X and Y, could be given by
𝐹𝐹(𝑋𝑋, 𝑌𝑌) = 𝑋𝑋𝑋𝑋
One half of the circuit is derived from the logic function itself with some modification as
𝐹𝐹(𝑋𝑋, 𝑌𝑌) = 𝑋𝑋𝑋𝑋 = (𝑋𝑋𝑋𝑋)′′ = (𝑋𝑋 ′ + 𝑌𝑌 ′ )′
This can be interpreted as the inverse of the parallel combination of the inverted inputs, which
is equivalent to the parallel connected two PMOS transistors with an NMOS transistor (see
figure 6.24(a)).
The other half circuit is developed from the inverse of the AND logic function as
𝐹𝐹(𝑋𝑋, 𝑌𝑌) = (𝑋𝑋𝑋𝑋)′
The direct translation of this is simply two series connected NMOS transistors with PMOS
inverter (see figure 6.24(b)). Note that in order to invert the output of NMOS we use PMOS
transistor and vice versa. The complete CMOS realization of AND gate is shown in figure
6.24(c).

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+Vs
+Vs
+Vs Output
X Y

X Y
Output
Output X X
+Vs

Y Y

Figure 6.24 CMOS AND circuit: (a) the 0 half using two PMOS transistors and an NMOS
transistor; (b) the 1 half

CMOS NOR and OR Gates

The CMOS NOR gate and OR gate circuits can be derived similarly to that of the NAND and
AND gate circuits. Like the NAND gate, the NOR gate circuit uses four transistors, whereas
the OR gate circuit uses six transistors.

6.4 COMPARISON OF COMMON LOGIC FAMILIES

Metrics for Logic Gate Comparison

Logic gates may be compared based on their areas of application, design cost, speed of
operation, etc. The following parameters are very important in selecting which family of logic
gate can be used for the particular application we are interested in.

a. Logic Level

Logic levels are the voltage levels for logic high and logic low.

• VOHmin : The minimum output voltage in HIGH state (logic '1'). VOHmin is 2.4 V for TTL
and 4.9 V for CMOS.
• VOLmax : The maximum output voltage in LOW state (logic '0'). VOLmax is 0.4 V for TTL
and 0.1 V for CMOS.
• VIHmin : The minimum input voltage guaranteed to be recognized as logic 1. VIHmin is 2 V
for TTL and 3.5 V for CMOS.
• VILmax : The maximum input voltage guaranteed to be recognized as logic 0. VILmax is 0.8
V for TTL and 1.5 V for CMOS.

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b. Noise margin
Gate circuits are constructed to sustain variations in input and output voltage levels. These
variations are usually resulting of several different factors such as

1. Batteries lose their full potential, causing the supply voltage to drop
2. High operating temperatures may cause a drift in transistor voltage and current
characteristics
3. Spurious pulses introduced on signal lines by normal surges of current in
neighbouring supply lines.

All these undesirable voltage variations that are superimposed on normal operating
voltage levels are called noise . All gates designed to tolerate a certain amount of noise
on their input and output ports. The maximum noise voltage level that is tolerated by a
gate is called a noise margin.

c. Fan-in and Fan-out

Fan-in is the number of inputs that a certain Gate has.The number of gates that each gate
can drive, while providing voltage levels in the guaranteed range is called the standard load
or fan-out. The fan-out really depends on the amount of electric current a gate can source or
sink while driving other gates. CMOS gates have the largest value of fan-out; typically up
to 50 loads can be driven by a single gate.

d. Power Dissipation

Each gate is connected to a power supply VCC (VDD in the case of CMOS). It draws a
certain amount of current during its operation. Since each gate can be in a High, Transition
or Low state, there are three different currents drawn from power supply.

• ICCH: Current drawn during HIGH state.

• ICCT: Current drawn during HIGH to LOW, LOW to HIGH transition.
• ICCL: Current drawn during LOW state.

For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If
we assume that ICCH and ICCL are equal then,

Average Power Dissipation = Vcc * (ICCH + ICCL)/2

For CMOS, ICCH and ICCL current are negligible, in comparison to ICCT. So the Average
power dissipation is calculated as below.

Average Power Dissipation = Vcc * ICCT.

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So for TTL like logics family, power dissipation does not depend on frequency of operation,
and for CMOS the power dissipation depends on the operation frequency.

Power Dissipation is an important metric for two reasons: One, as the amount of current
and power available in a battery is nearly constant, power dissipation of a circuit or system
defines battery life. i.e., the greater the power dissipation, the shorter the battery life.
Secondly, Power dissipation is proportional to the heat generated by the chip or system.
Excessive heat dissipation may increase operating temperature and cause gate circuitry to
drift out of its normal operating range and generate improper output values. Thus power
dissipation of any gate implementation must be kept as low as possible.

e. Propagation delay
Propagation delay defined as average time needed for an input change to propagate to the output.

Compared to TTL and CMOS logics, using discrete components such as Diodes, Resistors and
Transistors to make digital logic gates is not practical in commercially available logic IC's
because of the following reasons.

• These circuits suffer from propagation delay or gate delay due to the pull-up resistors,
• There is no "Fan-out" which is the ability of a single output to drive many inputs,
• They do not turn fully "OFF as Logic “0” produces an output voltage of 0.7v (diode
voltage drop).
• They dissipate large amount of power.

So, today most commonly used technologies are TTL and CMOS circuits. Standard
commercially available digital logic gates are available in two basic forms, TTL such as the
7400 series, and CMOS as the 4000 series of chips.

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