Serial Communications: Prof. Stephen A. Edwards Sedwards@cs - Columbia.edu

Serial Communications
Prof. Stephen A. Edwards

sedwards@cs.columbia.edu
Columbia University
Spring 2006
Serial Communications – p. 1/2

Early Serial Communication

Later Serial Communication
Data
Communications
Equipment
Data Terminal Equipment Serial Communications – p. 3/2
RS-232
Defined in early 1960s

Serial, Asynchronous, Full-duplex,
Voltage-based, point-to-point, 100 ft+ cables

+12V
SPACE = 0

+3V


−3V

MARK = 1

−12V

Idle Start LSB B1 B2 B3 B4 B5 B6 MSB Stop
Tx


RS-232 Signals
Signal DB-9 DTE ... Meaning

pin DCE
RxD 2 ← Data received by DTE
TxD 3 → Data sent by DTE
SG 5 — Ground
DSR 6 ← Data Set Ready (I’m alive)
DTR 4 → Data Terminal Ready (me, too)
DCD 1 ← Carrier Detect (hear a carrier)
RTS 7 → Request To Send (Yo?)
CTS 8 ← Clear To Send (Yo!)
RI 9 ← Ring Indicator

Receiving RS-232
Idle Start LSB B1 B2 B3 B4 B5 B6 MSB Stop
Rx

Rx

4×Clk

Start Sample Sample Sample
Most UARTs actually use 16× clocks

Variants
Parity bit: (Even = true when even number of 1s)
Idle Start LSB B1 B2 B3 B4 B5 B6 Parity Stop
Tx

Two stop bits:
Idle Start LSB B1 B2 B3 B4 B5 B6 MSB Stop Stop
Tx


Baud Rate
Baud: bits per second

Baud Application
110 ASR-33 Teletype
300 Early acoustic modems
1200 Direct-coupled modems c. 1980
2400 Modems c. 1990
9600 Serial terminals
19200
38400 Typical maximum

Physical Variants
Connectors: DB-25, DB-9, Mini DIN-8

RS-422: Differential signaling RS-485: Bus-like

OPB UART Lite
Serial port peripheral for the Microblaze

Full duplex operation
16-character transmit and receive FIFOs
Parameters that can be set at build time:
Parameter Value
Base Address 0xFEFF0100
High Address 0xFEFF01FF
Baud Rate 9600
Bits per frame 8
Parity None

OPB UART Lite Registers
Address Role
0xFEFF0100 Read characters from Receive FIFO
0xFEFF0104 Write characters to Receive FIFO
0xFEFF0108 Status register (read only)
0xFEFF010C Control register (write only)

Status and Control Registers
Bit Status Control

24 Parity Error -
25 Framing Error -
26 Overrun Error -
27 Interrupts Enabled Enable Interrupts
28 Tx buffer full -
29 Tx buffer empty -
30 Rx buffer full Clear Rx buffer
31 Rx buffer non-empty Clear Tx buffer
Non-empty Rx buffer or emptying of Tx buffer
generates an interrupt.

The I2C Bus
Philips invented the Inter-IC bus c. 1980 as a very

cheap way to communicate slowly among chips
ions E.g., good for setting control registers
100, 400, and 3400 kHz bitrates
SCL: Clock, generated by a single master

SDA: Data, controlled by either master or slaves

I2C Bus Transaction
Idle Start “0” “1” Ack Stop
SCL

SDA

Purchase of Philips I2C components conveys a license
under the Philips' patent to use the components in
the I2C system provided the system conforms to the
I2C specification defined by Philips.

USB: Universal Serial Bus
1.5 Mbps, 12 Mbps, and 480 Mbps (USB 2.0)

Point-to-point, differential, twisted pair
3–5m maximum cable length

USB Connectors

USB signaling
NRZI: 0 = toggle, 1 = no change

Bit stuffing: 0 automatically inserted after six
consecutive 1s
Each packet prefixed by a SYNC field: 3 0s

followed by two 1s
Low- vs. full-speed devices identified by different
pull-ups on D+/D- lines

USB Packets
Always start with SYNC

Then 4-bit type, 4-bit type complemented
2 bits distinguish Token, Data, Handshake, and
Special, other two bits select sub-types
Then data, depending on packet type
Data checked using a CRC
Addresses (1-128) assigned by bus master, each
with 16 possible endpoints

USB Bus Protocol
Polled bus: host initiates all transfers.

Most transactions involve three packets:
“Token” packet from host requesting data
Data packet from target
Acknowledge from host
Supports both streams of bytes and structured
messages (e.g., control changes).

USB Data Flow Types
Control
For configuration, etc.
Bulk Data
Arbitrary data stream: bursty
Interrupt Data
Timely, reliable delivery of data. Usually
events.
Isochronous Data
For streaming real-time transfer:
prenegotiated bandwidth and latency

Layered Architecture

USB: Flash Card Device
Bus 001 Device 002: ID 05e3:0760 Genesys Logic, Inc.
bcdUSB 2.00
bMaxPacketSize0 64
idVendor 0x05e3 Genesys Logic, Inc.
idProduct 0x0760
bcdDevice 1.14
iManufacturer 2 Genesys
iProduct 3 Flash Reader
iSerial 4 002364
Configuration Descriptor:
bNumInterfaces 1
MaxPower 300mA
Interface Descriptor:
bNumEndpoints 2
bInterfaceClass 8 Mass Storage
bInterfaceSubClass 6 SCSI
bInterfaceProtocol 80 Bulk (Zip)
Endpoint Descriptor:
bEndpointAddress 0x81 EP 1 IN
bmAttributes 2
Transfer Type Bulk
Synch Type none
wMaxPacketSize 64
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type none
wMaxPacketSize 64
Language IDs: (length=4)
0409 English(US)
USB: Mouse Device
Bus 002 Device 002: ID 04b4:0001 Cypress Semiconductor Mouse
Device Descriptor:
bcdUSB 1.00
idVendor 0x04b4 Cypress Semiconductor
idProduct 0x0001 Mouse
bcdDevice 4.90
iManufacturer 1 Adomax Sem.
iProduct 2 USB Mouse
iSerial 0
Configuration Descriptor:
bNumInterfaces 1
bmAttributes 0xa0
Remote Wakeup
MaxPower 100mA
Interface Descriptor:
bNumEndpoints 1
bInterfaceClass 3 Human Interface Devices
bInterfaceSubClass 1 Boot Interface Subclass
bInterfaceProtocol 2 Mouse
iInterface 5 EndPoint1 Interrupt Pipe
HID Device Descriptor:
bDescriptorType 34 Report
wDescriptorLength 52
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type none
wMaxPacketSize 4
bInterval 10
Language IDs: (length=4)
0409 English(US)

— Synchronous or Asynchronous interface
• Integrated phase-locked loop (PLL)
The CY7C68001 USB interface

• 3.3V operation, 5V tolerant I/Os
• 56-pin SSOP and QFN package
• Complies with most device class specifications
1.3 Block Diagram
WAKEUP*
RESET#
SCL
I2C Bus
Controller
(Master Only)
SDA
IFCLK*
24 MHz Read*, Write*, OE*, PKTEND*, CS#

PLL
XTAL
Interrupt#, Ready
SX2 Internal Logic
Flags (3/4)
Address (3)
Control
VCC
FIFO
1.5K
Data 8/16-Bit Data
Bus
DPLUS CY Smart USB 4 KB

USB 2.0 XCVR Data
DMINUS FS/HS Engine FIFO
Figure 1-1. Block Diagram
Document #: 38-08013 Rev. *B Page 7 of 50

The CY7C68001 USB interface
Operates as a peripheral (i.e., not a host)

Operates at 12 or 480 Mbps speeds
Control endpoint 0
Four other user-configurable endpoints
4 kB FIFO buffer
500 bytes of descriptor RAM (Vendor, Product)
I2 C bus interface for configuration from EEPROM
(Unused on the XSB board—processor must
configure)

CY7C68001 software interface
Five memory locations: one for each FIFO, one

for control registers
Internal registers written by first applying address
to control register, then reading or writing data to
control register.
33 different configuration registers, including
500-byte descriptor “register”

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Serial Communications

Prof. Stephen A. Edwards

Serial Communications – p. 1/2

Serial Communications – p. 2/2

Defined in early 1960s

Idle Start LSB B1 B2 B3 B4 B5 B6 MSB Stop

Serial Communications – p. 4/2

Signal DB-9 DTE ... Meaning

Serial Communications – p. 5/2

Idle Start LSB B1 B2 B3 B4 B5 B6 MSB Stop

Start Sample Sample Sample

Most UARTs actually use 16× clocks

Serial Communications – p. 6/2

Parity bit: (Even = true when even number of 1s)

Idle Start LSB B1 B2 B3 B4 B5 B6 Parity Stop

Two stop bits:

Idle Start LSB B1 B2 B3 B4 B5 B6 MSB Stop Stop

Serial Communications – p. 7/2

Baud: bits per second

Serial Communications – p. 8/2

Connectors: DB-25, DB-9, Mini DIN-8

Serial Communications – p. 9/2

Serial port peripheral for the Microblaze

Serial Communications – p. 10/2

Serial Communications – p. 11/2

Bit Status Control

Serial Communications – p. 12/2

Philips invented the Inter-IC bus c. 1980 as a very

SCL: Clock, generated by a single master

Serial Communications – p. 13/2

Idle Start “0” “1” Ack Stop

Serial Communications – p. 14/2

1.5 Mbps, 12 Mbps, and 480 Mbps (USB 2.0)

Serial Communications – p. 15/2

Serial Communications – p. 16/2

NRZI: 0 = toggle, 1 = no change

Each packet prefixed by a SYNC field: 3 0s

Serial Communications – p. 17/2

Always start with SYNC

Serial Communications – p. 18/2

Polled bus: host initiates all transfers.

Serial Communications – p. 19/2

Serial Communications – p. 20/2

Serial Communications – p. 21/2

Serial Communications – p. 23/2

The CY7C68001 USB interface

1.3 Block Diagram

24 MHz Read*, Write*, OE*, PKTEND*, CS#

SX2 Internal Logic

DPLUS CY Smart USB 4 KB

Figure 1-1. Block Diagram

Serial Communications – p. 24/2

Document #: 38-08013 Rev. *B Page 7 of 50

Operates as a peripheral (i.e., not a host)

Serial Communications – p. 25/2

Five memory locations: one for each FIFO, one

Serial Communications – p. 26/2

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24 MHz Read, Write, OE, PKTEND, CS#