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FPGA Lab 11

The document discusses finite state machines (FSM). It aims to understand FSM concepts, examine real-life examples like turnstiles and elevators, and distinguish between Moore and Mealy FSMs. FSMs can model computer programs and sequential logic. An FSM has a finite number of states, exists in one state at a time, and transitions between states based on external events. The document also shows how to model, design, and test an FSM using Verilog code.

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ihtisham ijaz mughal
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© © All Rights Reserved
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148 views

FPGA Lab 11

The document discusses finite state machines (FSM). It aims to understand FSM concepts, examine real-life examples like turnstiles and elevators, and distinguish between Moore and Mealy FSMs. FSMs can model computer programs and sequential logic. An FSM has a finite number of states, exists in one state at a time, and transitions between states based on external events. The document also shows how to model, design, and test an FSM using Verilog code.

Uploaded by

ihtisham ijaz mughal
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Objective:
The main objective of this lab is to:
 understand the concept of Finite State Machine.
 Overview of real-life examples of FSM.
 Difference between Moore and Mealy FSM.
 Model and design the FSM for a given state transition diagram.
 Design the state transition diagram and FSM for sequence detector.

Introduction:
A finite state machine (FSM) or simply a state machine is a mathematical model of
computation used to design both computer programs and sequential logic circuits. It is
conceived as an abstract machine that can be in one of a finite number of states. The machine
is in only one state at a time; the state it is in at any given time is called the  current state. It
can change from one state to another when initiated by an external triggering event or
condition; this is called a transition. A particular FSM is defined by a list of its states, its
initial state, and the triggering condition for each transition.

Examples of FSM:
There are numerous real life FSM examples and some of them are discussed below.
1. Coin operated turnstile:
A turnstile, used to control access to subways and amusement park rides, is a gate with three
rotating arms at waist height, one across the entryway. Initially the arms are locked, blocking
the entry, preventing patrons from passing through. Depositing a coin or token in a slot on the
turnstile unlocks the arms, allowing a single customer to push through. After the customer
passes through, the arms are locked again until another coin is inserted. Considered as a state
machine, the turnstile has two states: Locked and Unlocked. The state transition diagram and
table is shown below.

2. Elevator Lift for Building:

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The second example of finite state machine is the building elevator. Suppose elevator is
stationary and the floor requested is below the current floor, and then descend the elevator to
the floor requested. If elevator is stationary and the floor requested is above the current floor,
then ascend the elevator to the floor requested. The State transition diagram for this system is
shown below.

In Xilinx ISE, XST proposes a large set of templates to describe Finite State Machines
(FSMs). By default, XST tries to recognize FSMs from VHDL/Verilog code, and apply
several state encoding techniques (it can re-encode the user's initial encoding) to get better
performance or less area. However, you can disable FSM extraction using
a FSM_extract design constraint. Please note that XST can handle only synchronous state
machines.

The basic block diagram of an FSM is the same as that of a regular sequential circuit and is
shown in Figures shown below. It consists of a state register, next state logic and output
logic. An FSM is known as Moore machine if the output is only a function of state, and is
known as Mealy machine if the output is the function of both state and external input.

Fig. 1 Moore based FSM

Fig. 2 Mealy based FSM

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State Transformation Diagram

Verilog Code

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Test Bench

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Output Wave

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