MOS Field-Effect

Transistors (MOSFETs)

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 MOSFET ( Voltage Controlled Current Device)
• MOS Metal Oxide Semiconductor
Physical Structure

• FET Field Effect Transistor

The current controlled mechanism is based on an electric field established by the
voltage applied to the control terminal – GATE

• Uni-polar Current is conducted by only one carrier

• IGFET Insulated Gate FET

• 1930 was Known, 1960s Commercialized

1970s Most commonly used VLSI

• NMOSFET/PMOSFET n/p-channel enhancement mode MOSFET

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Figure 4.1 Physical structure of the enhancement-type NMOS
transistor:

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 Device Structure
• Types “n” channel enhancement MOSFET
“p” channel enhancement MOSFET

• “n” Channel MOSFET

– Fabricated on a p-type substance that provides physical support for
the device.

– Two heavily doped n-type region are created

• n+ Source (‘S’) n- for lightly doped ‘n’ type silicon
• n+ Drain (‘D’) n+ for heavily doped ‘n’ type silicon

– Area between source & Drain

• Thin Layer of Silicon dioxide (SiO2) is grown with thickness of tox
= 2-50 nanometers An excellent electrical insulator

• Metal is deposited on top of the oxide layer to form

the Gate electrode. Metal contact is made to
Source & Drain and the substrate (Body) 4
Figure 4.1 Physical structure of the enhancement-type NMOS
transistor

Cross-section. Typically L = 0.1 to 3 μm, W = 0.2 to 100 μm, and

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the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
 Device Structure
• Four terminals
– Source (S)
– Gate (G)
– Drain (D)
– Body (B)

•L Length of channel region

W Width of the substrate
tox Thickener of An oxide Layer
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 Device Structure
• Metal oxide semiconductor - name is derived
from its physical structure

• Insulted – Gate FET (IGFET) – gate is

electrically insulated from the device body
– Current in gate terminal is small (10-15 A)

• Substrate forms pn junctions with the source &

drain region & is kept reversed biased all the
time

• Drain will be at a positive voltage relative to the

source, two junctions are at cutoff.

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 Principle of operation
• Voltage applied to the Gate controls current flow
between Source & Drain with direction from Drain to
Source in channel region

• It is a symmetrical device thus Drain & Source can be

interchanged with no change in devices characteristics
•
• With no bias gate voltage, two back-to-back diodes exist
in series between drain and source.

• No current flows even if vDS is applied. In fact the path

between Source & Drain (1012Ω) has very high
resistance
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Figure 4.2 The enhancement-type NMOS transistor with a
positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate.

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Creating a Channel for Current Flow

• Source & Drain are grounded and a positive

voltage (vGS) is applied to the gate.

• Holes are repelled-leaving behind a carrier

depletion-region.

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 Channel for Current Flow
• Positive gate attracts electrons from the n+
source & drain region into the channel region.

• Due to electrons accumulated under the gate, an

‘n’ region is created & connects source & drain
region.

• Thus if voltage is applied between source &

drain, current flows due to mobile electrons
between drain & source.

• ‘n’ region forms a channel – ‘n’ channel MOSET

(NMOSFET) 11
 Channel for Current Flow
• An ‘n’ channel MOSFET is formed in a ‘p’ type
substrate. Known as “Inversion Layer”.

• The value of vGS that causes sufficient number of

mobile electrons to be accumulate in the channel
region to form conducting channel is called
threshold Voltage “Vt”.

• Vt for ‘n’ channel is positive & value is 0.5 to 1V

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 Channel for Current Flow
• Gate & channel region form a parallel plate capacitor,
with oxide layer as the capacitor dielectric.

• Positive charge is accumulated on gate electrode &

negative charge on channel electrode.

• An electric field thus develops in the vertical direction.

• Capacitor charge controls the current flow through the

channel when a voltage vDS is applied.
• Gate Channel

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Figure 4.3 An NMOS transistor with vGS > Vt and with a
small vDS applied.

The device acts as a resistance whose value is determined by vGS.

Specifically, the channel conductance is proportional to vGS – Vt’
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and thus iD is proportional to (vGS – Vt) vDS.
 Applying a Small vDS
• vDS is applied (vDS = 50mV) causes iD to flow through induced ‘n’
channel.
– Direction is opposite to that of the flow of negative charges.
– Magnitude of iD depends upon density of electrons and in term on vGS .

• vGS ≤ Vt
– Negligible current iD as the channel has been just induced.

• vGS > Vt
– iD current increases, increases conductance of the channel & is
proportional to Excess gate voltage (vGS - Vt )

– vGS - Vt is known as Excess gate Voltage , Effective Voltage

Overdrive Voltage (VOV)

– MOSFET operatrates as a linear resistance whose value is

controlled by vGS.

– vGS above Vt enhances the channel – named Enhanced Mode operation

& enhanced type MOSFET
iD = i S, i G = 0 15
Figure 4.4 The iD–vDS characteristics of the MOSFET

When the voltage applied between drain and source, vDS, is kept small.
The device operates as a linear resistor whose value is controlled by 16
v .
 Figure 4.5 Operation of the enhancement NMOS
transistor as vDS is increased. The induced channel
acquires a tapered shape, and its resistance increases as
vDS is increased. Here, vGS is kept constant at a value >
V t.

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 MOSFET

G
S D

n+ n+

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 MOSFET

S G D
+VDS

n+ n+

p substrate

If VGS = 0 V, ID = 0 because no channel exists for

current flow 19
 MOSFET
+VGS
S G D

+ + + + + +
- - - - - - - -
+VDS
n+ n+

p substrate

When positive voltage is applied to gate, it attracts the

electrons from channel and these electrons accumulate
near the gate.
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 MOSFET
+VGS
S G D
+VDS
+ + + + + +
- - - - - - - -
n+ n+
ID

p substrate

When VGS exceeds a certain voltage, called VT

(threshold voltage), sufficient electrons accumulate
near gate to form a channel and start the flow of
current. In this way a current channel is formed. 21
 MOSFET
+VGS
S G D
+VDS

n+ n+
ID

p substrate
• The depth of this channel depends on applied gate voltage.
• When VGS is increased, depth of channel increases.
• When VDS is small, the channel is of uniform depth.
• When VDS is increased, the channel changes to tapered
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shape.
 +3
S G D
+1
3 3 3 3

n+ n+
A B C D

0 0.25 0.5 1
VDS varying along the channel

p substrate
• Assume VDS = 1V and VGS = 3V
• Total voltage at A = VGS- VDS = 3 – 0 = 3 V
• Total voltage at B= VGS- VDS = 3 – 0.25 = 2.75 V
• Total voltage at C = VGS- VDS = 3 – 0.5 = 2.5 V
• Total voltage at D = VGS- VDS = 3 – 1 = 2 V
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• As channel depth depends on total voltage, so
channel shape will be tapered.
• If VDS is further increased, the channel width further
reduced near the drain.
• This means the resistance of channel increases as VDS is
increased.
• Finally when VDS is increased to a value so that VDS = VGS
- VT, the channel width becomes zero at drain.
• If VDS is further increased, the drain current will remain
unchanged. 24
The drain current iD versus the drain-to-source
voltage vDS for an enhancement-type NMOS
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transistor operated with vGS > Vt.
Increasing vDS causes the channel to acquire a tapered shape.
Eventually, as vDS reaches vGS – Vt’ the channel is pinched off
at the drain end. Increasing vDS above vGS – Vt has little effect
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(theoretically, no effect) on the channel’s shape.
Derivation of the iD–vDS characteristic of the NMOS 27
 Drain Current iD
• Directly Proportional to:
– Mobility of Electrons in the channel μn (μm2/V)
– Gate Capacitance per unit gate area Cox (μF/ μm)
– Width of the substrate (μm)
– Gate-Source Voltage vGS (Volts)
– Drain-Source Voltage v DS (Volts)

• Indirectly Proportional to: Process

traqnsconductance
– Length of the channel (μm)

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 iD – vDS relationship
Troide Mode

Saturation Mode

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 The p Channel MOSFET
• Fabricated on an n-type substrate with p+ regions for
Drain & Source

• Holes are the current carriers.

• vGS & vDS are negative

• Threshold voltage Vt is negative.

• Both NMOS & PMOS are utilized in Complementary

MOS or CMOS circuits
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 Complementary MOS or CMOS

Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is

formed in a separate n-type region, known as an n well. Another
arrangement is also possible in which an n-type body is used and the n
device is formed in a p well. Not shown are the connections made to the
p-type body and to the n well; the latter functions as the body terminal for the
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p-channel device.
Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an
arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c)
Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device
operation is unimportant.

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 iD – vDS Charateristics
• Modes of operation
• Cutoff Region
– The device is cut-off when

• Triode (Saturation in BJT)

– To operate the FET in triode region we must induce a
channel by

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 iD – vDS Charateristics
• In triode region the iD ~ VDS is related as

• Where we have assumed VDS to be very

small then the equation can be approx as:

• Now, the resistance rDS is given as

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 2
The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V . 35
 iD – vDS Charateristics
– Modes of operation
• Saturation (Active Region in BJT)
– To Operate FET in saturation region a Channel must be induced

– Pinched-off at the drain end up by raising vDS to a value

– Or it can be re-written as
– Thus, an N-Channel enhancement MOSFET operates in saturation
region, when vGS is greater than Vt and the Drain voltage does not
fall below the gate voltage by more than Vt volts.
• The boundary region b/w the triode region & saturation
region is characterized by:
– Saturation Current is given as:

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 Saturation current iD is independent of vDS voltage
which shows that iD current is a voltage controlled
current source and is dependent on vGS.

The iD–vGS characteristic for an enhancement-type NMOS transistor in 37

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saturation (Vt = 1 V, k’n W/L = 1.0 mA/V ).
Large-signal equivalent-circuit model of an n-channel 38
 Finite Output Resistance in Saturation

Increasing vDS beyond vDSsat causes the channel

pinch-off point to move slightly away from the drain, thus 39
 Finite Output Resistance in Saturation

Effect of vDS on iD in the saturation region. The MOSFET parameter VA

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depends on the process technology and, for a given process, is proportional
 Finite Output Resistance in Saturation

Large-signal equivalent circuit model of the n-channel MOSFET in

saturation, incorporating the output resistance ro. The output
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resistance models the linear dependence of iD on vDS
Circuit symbol for the p-channel enhancement-type MOSFET.

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Week 2

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Characteristics of PMOSFET
Triode Mode of Operation

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 Characteristics of PMOSFET
Satuaration Mode of Operation

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 The Roll of Substrate :
Body Effect
• Substrate for many Transistors

• Body is connected to the most negative

power supply to maintain cutoff conditions
for all the substrates to channel junctions

• Another gate

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 Temperature Effects
• Vt and K’n are effected by the temperature

• Vt increases by 2mV per 10C rise in

temperature

• K’n decreases with rise in temperature

thus drain current decreases. The effect is
dominant. Thus ID decreases with
increase in temperature
MOSFET in Power circuits 47
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Graphical construction to determine the transfer characteristic 52
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Rs is negative
feed back if I(D
increases

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Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.

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Biasing the MOSFET using a constant-current source

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Conceptual circuit utilized to study the operation of the 59
Recap : Transfer Function

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Transfer characteristic showing operation as an amplifier biased
at point Q.

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Conceptual circuit utilized to study the operation of the MOSFET as a small-signal
amplifier.

The DC BIAS POINT

To Ensure Saturation-region Operation

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Signal Current in Drain Terminal

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Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.

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Total instantaneous voltages vGS and vD

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Small-signal ‘π’ models for the MOSFET

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Small Signal ‘T’ Model : NMOSFET

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Small Signal Models

‘T’ Model

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3 week

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Single Stage MOS Amplifier

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Amplifiers Configurations

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Common Source Amplifier (CS) :Configuration

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Common Source Amplifier (CS)
• Most widely used

• Signal ground or an ac earth is at the source

through a bypass capacitor

• Not to disturb dc bias current & voltages

coupling capacitors are used to pass the signal
voltages to the input terminal of the amplifier or
to the Load Resistance

• CS circuit is unilateral –
– Rin does not depend on RL and vice versa
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Small Signal Hybrid “π” Model
(CS)

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A common-gate amplifier based on the circuit

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 Common Gate (CG) Amplifier
• The input signal is applied to the source

• Output is taken from the drain

• The gate is formed as a common input &

output port.

• ‘T’ Model is more Convenient

• ro is neglected
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A small-signal equivalent circuit

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A small-signal Analusis : CG

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A small-signal Analusis : CG

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The common-gate amplifier fed with a current-signal input.

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 Summary : CG

4. CG has much higher output Resistance

5. CG is unity current Gain amplifier or a Current Buffer
6. CG has superior High Frequency Response.

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 Common Gate
• Rin in independent of RL & Rin = 1/gm & gm in order of
mA/V.

• Input resistance of the CG Amplifier is relatively low (in

order of 1kv) than CS Amplifier

• Loss of signal

• CG is acts as Unity gain current amplifier current buffer

– useful for a Cascade circuitry 85
A common-drain or source-follower amplifier.

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Small-signal equivalent-circuit model

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Small-signal Analysis : CD

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(a) A common-drain or source-follower amplifier :output resistance Rout of
the source follower.

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Common Source Circuit (CS)

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Common Source Circuit (CS) With RS

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Common Gate Circuit (CG)
Current Follower

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Common Drain Circuit (CD)
Source Follower

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Summary & Comparison

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