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    The Federal University of Technology Akure, Ondo State

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    tarvs
    The document describes the design of a 4:1 multiplexer circuit using VHDL code. It lists the objectives as designing a minimal circuit to implement a 4:1 multiplexer and showing its truth table and VHDL code. It provides the equipment needed, describes the design procedure which includes constructing the circuit, observing its operation and truth table, and setting it up using provided VHDL code. The VHDL code implements the 4:1 multiplexer with four data inputs, two select lines, and a single output, using a case statement to select the appropriate output.

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    The Federal University of Technology Akure, Ondo State

    Uploaded by

    tarvs
    57 views5 pages
    The document describes the design of a 4:1 multiplexer circuit using VHDL code. It lists the objectives as designing a minimal circuit to implement a 4:1 multiplexer and showing its truth table and VHDL code. It provides the equipment needed, describes the design procedure which includes constructing the circuit, observing its operation and truth table, and setting it up using provided VHDL code. The VHDL code implements the 4:1 multiplexer with four data inputs, two select lines, and a single output, using a case statement to select the appropriate output.

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    The document describes the design of a 4:1 multiplexer circuit using VHDL code. It lists the objectives as designing a minimal circuit to implement a 4:1 multiplexer and showing its truth table and VHDL code. It provides the equipment needed, describes the design procedure which includes constructing the circuit, observing its operation and truth table, and setting it up using provided VHDL code. The VHDL code implements the 4:1 multiplexer with four data inputs, two select lines, and a single output, using a case statement to select the appropriate output.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    57 views5 pages

    The Federal University of Technology Akure, Ondo State

    Uploaded by

    tarvs
    The document describes the design of a 4:1 multiplexer circuit using VHDL code. It lists the objectives as designing a minimal circuit to implement a 4:1 multiplexer and showing its truth table and VHDL code. It provides the equipment needed, describes the design procedure which includes constructing the circuit, observing its operation and truth table, and setting it up using provided VHDL code. The VHDL code implements the 4:1 multiplexer with four data inputs, two select lines, and a single output, using a case statement to select the appropriate output.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 5

    THE FEDERAL UNIVERSITY OF TECHNOLOGY AKURE,

    ONDO STATE

    DEPARTMENT OF COMPUTER ENGINEERING

    PROJECT TITLE:
    DESIGN OF A 4:1 MULTIPLEXER CIRCUIT

    COMPILED BY:
    GROUP 2

    SUBMITTED TO:
    MR ANTHONY

    19TH OF MARCH, 2021


    GROUP 2 MEMBERS
    1. Abubakar Ibrahim Bocoum CPE/17/3086
    2. Ajiboye Abiodun Emmanuel CPE/17/3097
    3. Ajiteru Emmanuel Dolapo CPE/17/3099
    4. Akinlabi Theophilus Akinloluwa CPE/17/3100
    5. Kilani Ibrahim Tobi CPE/17/3120
    6. Akinjewe Joseph Temidayo CPE/18/6641
    7. Sobowale Olumuyiwa CPE/18/6683
    8. Aje Success Israel CPE/18/6638
    9. Folorunso Nurudeen Ayomide CPE/17/3116
    10. Oluleye Emmanuel Olaoluwa CPE/17/3135
    11. Eniola Sodiq Oladipupo CPE/17/3113
    12. Fadele Okikijesu Joshua CPE/17/3114
    13. Ogundiya Daniel Dare CPE/17/3126
    14. Ogungbile Samuel Oluwasola CPE/17/3127
    15. Ogunjobi Damilare Timothy CPE/17/3128
    16. Akintoye Kafilat CPE/17/3101
    17. Adedoja Isaac Adedayo CPE/17/3089
    18. Oyeku Emmanuel Omolaja CPE/17/3143
    19. Bosun-Kwadjo Okikiola Folagbade CPE/17/3106
    20. Ekundayo Oladayo Olanrewaju CPE/17/3110
    21. Sunday Chidera Joseph CPE/17/3147
    22. Omotola Daniel Iseoluwa CPE/17/3139
    TITLE: DESIGN OF A 4:1 MULTIPLEXER CIRCUIT
    AIM/OBJECTIVES:
     To design a minimal circuit which implements 4:1 Multiplexer (MUX) circuit
    using VHDL Code
     To show the truth table for this design
     To show the VHDL Code to implement combinational logic circuit and case
    statement

    EQUIPMENTS/MATERIALS:
     Althera Quartus Software
     Laptop/PC
     Design Simulators
     USB Blaster
     Field Programmable Gate Array (FPGA)
     Programmable Logic Devices
     Schematic Devices

    PROCEDURES/METHOD:
    In electronics, a multiplexer (MUX) is a device that selects between several
    analog or digital input signals and forwards the selected input to a single output line.
    The selection is directed to a separate set of digital inputs known as select lines.

     DESIGN STEPS:
    1. Firstly, set up the circuit as shown below.

    D0
    D1 4:1 MUX M
    D2
    D3

    S1 S0
    2. After constructing circuit, observe the operation while validating its
    truth table. The truth table is given below:

    TRUTH TABLE FOR 4:1 MULTIPLEXER


    SELECT ENABLE INPUT INPUT OUTPUTS
    INPUTS S
    S1 S0 E D0 D1 D2 D3 M
    X X 1 X X X X 0
    0 0 0 0 X X X 0
    0 0 0 1 X X X 1
    0 1 0 X 0 X X 0
    0 1 0 X 1 X X 1
    1 0 0 X X 0 X 0
    1 0 0 X X 1 X 1
    1 1 0 X X X 0 0
    1 1 0 X X X 1 1

    3. The 4:1 Multiplexer consists four data input lines as D0 to D3, two
    select lines as S0 and S1 and a single output line M.

    4. Now, set up the 4:1 Multiplexer using the VHDL code below:
     VHDL CODE:
    library ieee;
    use ieee.std_logic_1164.all;
    --entity declaration
    entity mux_4 is
    port (d0, d1, d2, d3:in std_logic;
    sel1, sel2: in std_logic;
    M: out std_logic);
    end mux_4;
    architecture dataflow of mux_4 is
    signal s1, s2, t1, t2, t3, t4: std_logic;
    begin
    s1 <= not sel1;
    s2 <= not sel2;
    t1<= d0 and s1 and s2;
    t2<= d1 and s2 and sel1;
    t3<= d2 and sel2 and s1;
    t4<= d3 and sel2 and sel1;
    M<= t1 or t2 or t3 or t4;
    end dataflow;
    5. The corresponding wave form is printed below:

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