Introduction To Power Semiconductors

Introduction Power Semiconductor Applications
Philips Semiconductors
CHAPTER 1
Introduction to Power Semiconductors
1.1 General
1.2 Power MOSFETS
1.3 High Voltage Bipolar Transistors
1
General
3
1.1.1 An Introduction To Power Devices
Today’s mains-fed switching applications make use of a The balance of these losses is primarily determined by the
wide variety of active power semiconductor switches. This switch used. If the on-state loss dominates, operating
chapter considers the range of power devices on the market frequency will have little influence and the maximum
today, making comparisons both in terms of their operation frequency of the device is limited only by its total delay time
and their general areas of application. The P-N diode will (the sum of all its switching times). At the other extreme a
be considered first since this is the basis of all active device whose on-state loss is negligible compared with the
switches. This will be followed by a look at both 3 layer and switching loss, will be limited in frequency due to the
4 layer switches. increasing dynamic losses.
Before looking at the switches let’s briefly consider the

various applications in which they are used. Virtually all CATHODE
mains fed power applications switch a current through an
inductive load. This is the case even for resonant systems
P
where the operating point is usually on the "inductive" side
of the resonance curve. The voltage that the switch is
normally required to block is, in the majority of cases, one
or two times the maximum rectified input voltage depending
on the configuration used. Resonant applications are the
exception to this rule with higher voltages being generated
by the circuit. For 110-240 V mains, the required voltage N
ratings for the switch can vary from 200 V to 1600 V.
Under normal operating conditions the off-state losses in

the switch are practically zero. For square wave systems,
the on-state losses (occurring during the on-time), are
primarily determined by the on-state resistance which gives
rise to an on-state voltage drop, VON. The (static) on-state ANODE
losses may be calculated from: Fig.1 Cross section of a silicon P-N diode
PSTATIC = δ.VON .ION (1) High frequency switching When considering frequency
limitation it is important to realise that the real issue is not
At the end of the "ON" time the switch is turned off. The just the frequency, but also the minimum on-time required.
turn-off current is normally high which gives rise to a loss For example, an SMPS working at 100 kHz with an almost
dependent on the turn-off properties of the switch. The constant output power, will have a pulse on-time tP of about
process of turn-on will also involve a degree of power loss 2-5 µs. This can be compared with a high performance UPS
so it is important not to neglect the turn-on properties either. working at 10 kHz with low distortion which also requires a
Most applications either involve a high turn-on current or minimum on-time of 2 µs. Since the 10 kHz and 100 kHz
the current reaching its final value very quickly (high dI/dt). applications considered here, require similar short
The total dynamic power loss is proportional to both the on-times, both may be considered high frequency
frequency and to the turn-on and turn-off energies. applications.
Resonant systems have the advantage of relaxing turn-on
PDYNAMIC = f.(EON + EOFF ) (2) or turn-off or both. This however tends to be at the expense
of V-A product of the switch. The relaxed switching
The total losses are the sum of the on-state and dynamic conditions imply that in resonant systems switches can be
losses. used at higher frequencies than in non resonant systems.
When evaluating switches this should be taken into
PTOT = δ.VON .ION + f.(EON + EOFF ) (3) account.
5
LOW RESITIVITY INTERMEDIATE CASE HIGH RESISTIVITY
E E E
Thickness Thickness Thickness
Case 1 Case 2 Case 3

-
Fig.2 Field distribution in the N layer
At higher values of throughput power, the physical size of combination of thickness and resistivity. Some flexibility
circuits increases and as a consequence, the stray exists as to what that combination is allowed to be, the
inductances will also tend to increase. Since the required effects of varying the combination are described below.
currents are higher, the energy stored in the stray
Case 1: Wide N- layer and low resistivity
inductances rises significantly, which in turn means the
induced peak voltages also rise. As a result such Figure 2 gives the field profile in the N- layer, assuming the
applications force the use of longer pulse times, to keep junction formed with the P layer is at the left. The maximum
losses down, and protection networks to limit overshoot or field at the P-N junction is limited to 22 kV/cm by the
networks to slow down switching speeds. In addition the breakdown properties of the silicon. The field at the other
use of larger switches will also have consequences in terms end is zero. The slope of the line is determined by the
of increasing the energy required to turn them on and off resistivity. The total voltage across the N- layer is equal to
and drive energy is very important. the area underneath the curve. Please note that increasing
the thickness of the device would not contribute to its
So, apart from the voltage and current capabilities of voltage capability in this instance. This is the normal field
devices, it is necessary to consider static and dynamic profile when there is another P-layer at the back as in 4
losses, drive energy, dV/dt, dI/dt and Safe Operating Areas. layer devices (described later).
The silicon diode Case 2: Intermediate balance
Silicon is the semiconductor material used for all power In this case the higher resistivity material reduces the slope
switching devices. Lightly doped N- silicon is usually taken of the profile. The field at the junction is the same so the
as the starting material. The resistance of this material same blocking voltage capability (area under the profile)
depends upon its resistivity, thickness and total area. can be achieved with a thinner device.
The very steep profile at the right hand side of the profile
l indicates the presence of an N+ layer which often required
R = ρ. (4)
A to ensure a good electrical contact
A resistor as such does not constitute an active switch, this Case 3: High resistivity material
requires an extra step which is the addition of a P-layer. With sufficiently high resistivity material a near horizontal
The result is a diode of which a cross section is drawn in slope to the electric field is obtained. It is this scenario which
Fig.1 will give rise to the thinnest possible devices for the same
required breakdown voltage. Again an N+ layer is required
The blocking diode at the back.
Since all active devices contain a diode it is worth An optimum thickness and resistivity exists which will give
considering its structure in a little more detail. To achieve the lowest possible resistance for a given voltage capability.
the high blocking voltages required for active power Both case 1 (very thick device) and case 3 (high resistivity)
switches necessitates the presence of a thick N- layer. To give high resistances, the table below shows the thickness
withstand a given voltage the N- layer must have the right and resistivity combinations possible for a 1000 V diode.
6
The column named RA gives the resistance area product.

(A device thickness of less than 50 µm will never yield CATHODE
1000 V and the same goes for a resistivity of less than
26 Ωcm.) The first specification is for the thinnest device
possible and the last one is for the thickest device, (required QN P
when a P layer is present at the back). It can be seen that
the lowest resistance is obtained with an intermediate value
of resistivity and material thickness.
I I
Thickness Resistivity RA Comments p N N
-
(µm) (Ωcm) Ωcm2 QP

50 80 0.400 case 3
60 34 0.204
65 30 0.195 N+
70 27 0.189 min. R
ANODE
75 26 0.195 Fig. 3 Diode in forward conduction
80 26 0.208
The exact volume of charge that will result is dependent
90 26 0.234 amongst other things on the minority carrier lifetime, τ.
100 26 0.260 case 1 Using platinum or gold doping or by irradiation techniques
the value of τ can be decreased. This has the effect of
To summarise, a designer of high voltage devices has only reducing the volume of stored charge and causing it to
a limited choice of material resistivity and thickness with disappear more quickly at turn-off. A side effect is that the
which to work. The lowest series resistance is obtained for resistivity will increase slightly.
a material thickness and resistivity intermediate between
the possible extremes. This solution is the optimum for all Three Layer devices
majority carrier devices such as the PowerMOSFET and
the J-FET where the on-resistance is uniquely defined by The three basic designs, which form the basis for all derived
the series resistance. Other devices make use of charge 3 layer devices, are given in Fig.4. It should be emphasised
storage effects to lower their on-state voltage. here that the discussion is restricted to high voltage devices
Consequently to optimise switching performance in these only as indicated in the first section. This means that all
devices the best choice will be the thinnest layer such that relevant devices will have a vertical structure, characterised
the volume of stored charge is kept to a minimum. Finally by a wide N--layer.
as mentioned earlier, the design of a 4 layer device requires The figure shows how a three layer device can be formed
the thickest, low resistivity solution. by adding an N type layer to the P-N diode structure. Two
back to back P-N diodes thus form the basis of the device,
The forward biased diode where the P layer provides a means to control the current
When a diode is forward biased, a forward current will flow. when the device is in the on-state.
Internally this current will have two components: an electron There are three ways to use this P-layer as a control
current which flows from the N layer to the P layer and a terminal. The first is to feed current into the terminal itself.
hole current in the other direction. Both currents will The current through the main terminals is now proportional
generate a charge in the opposite layer (indicated with QP to the drive current. This device is called a High Voltage
and QN in Fig.3). The highest doped region will deliver most Transistor or HVT.
of the current and generate most of the charge. Thus in a
P+ N- diode the current will primarily be made up of holes The second one is to have openings in the P-layer and
flowing from P to N and there will be a significant volume permit the main current to flow between them. When
of hole charge in the N- layer. This point is important when reverse biasing the gate-source, a field is generated which
discussing active devices: whenever a diode is forward blocks the opening and pinches off the main current. This
biased (such as a base-emitter diode) there will be a charge device is known as the J-FET (junction FET) or SIT (Static
stored in the lowest doped region. Induction Transistor).
7
BASE EMITTER GATE SOURCE GATE SOURCE
N N N
P P P
- - -
N N N
N N N
COLLECTOR DRAIN DRAIN
BIPOLAR TRANSISTOR J-FET (SIT) MOS
Fig.4 The three basic three layer devices
The third version has an electrode (gate) placed very close

to the P-layer. The voltage on this gate pushes away the B E B E B
holes in the P-area and attracts electrons to the surface N+ N+
beneath the gate. A channel is thus formed between the
main terminals so current can flow. The well known name I
B P
for this device is MOS transistor.
In practice however, devices bear little resemblance to the Electrons
constructions of Fig.4. In virtually all cases a planar
-
construction is chosen i.e. the construction is such that one N
main terminal (emitter or source) and the drive contact are
on the surface of the device. Each of the devices will now
be considered in some more detail.
The High Voltage Transistor (HVT)

N+
The High Voltage Transistor uses a positive base current
to control the main collector current. The relation is: COLLECTOR
IC = HFE * IB. The base drive forward biases the base emitter
P-N junction and charge (holes and electrons) will pass Fig.5 The HVT
through it. Now the base of a transistor is so thin that the
most of the electrons do not flow to the base but into the condition causes the current gain to drop. For this reason
collector - giving rise to a collector current. As explained one cannot use a HVT at a very high current density
previously, the ratio between the holes and electrons because then the gain would become impractically low.
depend on the doping. So by correctly doping the base The on-state voltage of an HVT will be considerably lower
emitter junction, the electron current can be made much than for a MOS or J-FET. This is its main advantage, but
larger than the hole current, which means that IC can be the resulting charge stored in the N- layer has to be
much larger than IB. delivered and also to be removed. This takes time and the
speed of a bipolar transistor is therefore not optimal. To
When enough base drive is provided it is possible to forward
improve speed requires optimisation of a fine emitter
bias the base-collector P-N junction also. This has a
structure in the form of fingers or cells.
significant impact on the resistance of the N- layer; holes
now injected from the P type base constitute stored charge Both at turn-on and turn-off considerable losses may occur
causing a substantial reduction in on-state resistance, unless care is taken to optimise drive conditions. At turn-on
much lower than predicted by equation 4. Under these a short peak base current is normally required. At turn-off
conditions the collector is an effective extension of the base. a negative base current is required and negative drive has
Unfortunately the base current required to maintain this to be provided.
8
A serious limitation of the HVT is the occurrence of second Its main difficulty is the opening in the P-layer. In order to
breakdown during switch off. The current contracts towards speed up performance and increase current density, it is
the middle of the emitter fingers and the current density can necessary to make a number of openings and this implies
become very high. The RBSOAR (Reverse Bias Safe fine geometries which are difficult to manufacture. A
Operating Area) graph specifies where the device can be solution exists in having the P-layer effectively on the
used safely. Device damage may result if the device is not surface, basically a diffused grid as shown in Fig.6.
properly used and one normally needs a snubber (dV/dt Unfortunately the voltages now required to turn the device
network) to protect the device. The price of such a snubber off may be very large: it is not uncommon that a voltage of
is normally in the order of the price of the transistor itself. 25 V negative is needed. This is a major disadvantage
In resonant applications it is possible to use the resonant which, when combined with its "normally-on" property and
properties of the circuit to have a slow dV/dt. the difficulty to manufacture, means that this type of device
is not in mass production.
So, the bipolar transistor has the advantage of a very low
forward voltage drop, at the cost of lower speed, a The MOS transistor.
considerable energy is required to drive it and there are The MOS (Metal Oxide Semiconductor) transistor is
also limitations in the RBSOAR. normally off: a positive voltage is required to induce a
channel in the P-layer. When a positive voltage is applied
to the gate, electrons are attracted to the surface beneath
the gate area. In this way an "inverted" N-type layer is
The J-FET. forced in the P-material providing a current path between
drain and source.
The J-FET (Junction Field Effect Transistor) has a direct
resistance between the Source and the Drain via the
S G S
opening in the P-layer. When the gate-source voltage is
zero the device is on. Its on-resistance is determined by the P
N+ N+
P
resistance of the silicon and no charge is present to make
the resistance lower as in the case of the bipolar transistor.
When a negative voltage is applied between Gate and
Source, a depletion layer is formed which pinches off the
current path. So, the current through the switch is
determined by the voltage on the gate. The drive energy is -
low, it consists mainly of the charging and discharging of N
the gate-source diode capacitance. This sort of device is
normally very fast.
G S G S G N+
N+ N+
P P P DRAIN
Fig.7 The MOS transistor
Modern technology allows a planar structure with very

narrow cells as shown in Fig.7. The properties are quite
-
like the J-FET with the exception that the charge is now
N across the (normally very thin) gate oxide. Charging and
discharging the gate oxide capacitance requires drive
currents when turning on and off. Switching speeds can
be controlled by controlling the amount of drive charge
during the switching interval. Unlike the J-FET it does not
require a negative voltage although a negative voltage may
N+
help switch the device off quicker.
DRAIN The MOSFET is the preferred device for higher frequency

switching since it combines fast speed, easy drive and wide
Fig.6 The J-FET
commercial availability.
9
Refinements to the basic structure when possible. As previously explained, adjustment of the
lifetime affects the on-state voltage. Carefully adjusting the
A number of techniques are possible to improve upon
lifetime τ will balance the on-state losses with the switching
behaviour of the basic device.
losses.
First, the use of finer geometries can give lower on-state
voltages, speed up devices and extend their energy All four layer devices show this trade-off between switching
handling capabilities. This has led to improved losses and on-state losses. When minimising switching
"Generation 3" devices for bipolars and to lower RDS(ON) for losses, the devices are optimised for high frequency
PowerMOS. Secondly, killing the lifetime τ in the device applications. When the on-state losses are lowest the
can also yield improvements. For bipolar devices, this current density is normally highest, but the device is only
positively effects the switching times. The gain, however, useful at low frequencies. So two variants of the four layer
will drop, and this sets a maximum to the amount of lifetime device generally exist. In some cases intermediate speeds
killing. For MOS a lower value for τ yields the so-called are also useful as in the case of very high power GTOs.
FREDFETs, with an intrinsic diode fast enough for many
half bridge applications such as in AC Motor Controllers.
The penalty here is that RDS(ON) is adversely effected The Thyristor
(slightly). Total losses, however, are decreased
A thyristor (or SCR, Silicon Controlled Rectifier) is
considerably.
essentially an HVT with an added P+-layer. The resulting
P--N--P+ transistor is on when the whole device is on and
Four layer devices provides enough base current to the N+-P-N- transistor to
The three basic designs from the previous section can be stay on. So after an initial kick-on, no further drive energy
extended with a P+-layer at the back, thereby generating is required.
three basic Four Layer Devices. The addition of this extra
layer creates a PNP transistor from the P+-N--P-layers. In
all cases the 3 layer NPN device will now deliver an electron G C G
current into the back P+-layer which acts as an emitter. The +
PNP transistor will thus become active which results in a N
hole current flowing from the P+-layer into the high resistive P
region. This in its turn will lead to a hole charge in the high
resistive region which lowers the on-state voltage
considerably, as outlined above for High Voltage Ip1
Transistors. Again, the penalty is in the switching times -
which will increase. N
All the devices with an added P+-layer at the back will inject
Ip2
holes into the N--layer. Since the P+-layer is much heavier
doped than the N--layer, this hole current will be the major
contributor to the main current. This means that the charge
in the N--layer, especially near the N--P+-junction, will be P+
large. Under normal operation the hole current will be large
enough to influence the injection of electrons from the top ANODE
N+-layer. This results in extra electron current being
injected from the top, leading to extra hole current from the Fig.8 Thyristor
back etc. This situation is represented in the schematic of
Fig.8. The classical thyristor is thus a latching device. Its
construction is normally not very fine and as a result the
An important point is latching. This happens when the
gate contact is too far away from the centre of the active
internal currents are such that we are not able to turn off
area to be able to switch it off. Also the current density is
the device using the control electrode. The only way to turn
much higher than in a bipolar transistor. The switching times
it off is by externally removing the current from the device.
however are very long. Its turn-on is hampered by its
The switching behaviour of all these devices is affected by structure since it takes quite a while for the whole crystal
the behaviour of the PNP: as long as a current is flowing to become active. This seriously limits its dI/dt.
through the device, the back will inject holes into the
N--layer. This leads to switching tails which contribute Once a thyristor is on it will only turn-off after having zero
heavily to switching losses. The tail is strongly affected by current for a few microseconds. This is done by temporarily
the lifetime τ and by the application of negative drive current forcing the current via a so-called commutation circuit.
10
The charge in the device originates from two sources: The

standard NPN transistor structure injects holes in the G C G C G
N--layer (IP1 in Fig.8) and the PNP transistor injects a charge
N+ N+
from the back (IP2 in Fig.8). Therefore the total charge is big P P P
and switching performance is very poor. Due to its slow
switching a normal thyristor is only suitable up to a few kHz.
A major variation on the thyristor is the GTO (Gate Turn Off
Thyristor). This is a thyristor where the structure has been
tailored to give better speed by techniques such as accurate -
lifetime killing, fine finger or cell structures and "anode N
shorts" (short circuiting P+ and N- at the back in order to
decrease the current gain of the PNP transistor). As a result,
the product of the gain of both NPN and PNP is just sufficient
to keep the GTO conductive. A negative gate current is
enough to sink the hole current from the PNP and turn the +
P
device off.
ANODE
G C G C G Fig.10 The SITh
N+ N+
drawback, as is its negative drive requirements.

P Consequently mass production of this device is not
available yet.
- The IGBT
N
An IGBT (Insulated Gate Bipolar Transistor) is an MOS
transistor with P+ at the back. Charge is injected from the
back only, which limits the total amount of charge. Active
charge extraction is not possible, so the carrier lifetime τ
+ + + should be chosen carefully, since that determines the
N N P
switching losses. Again two ranges are available with both
fast and slow IGBTs.
ANODE
Fig.9 The GTO
E G E
A GTO shows much improved switching behaviour but still
N+ N+
has the tail as described above. Lower power applications, P P
especially resonant systems, are particularly attractive for

the GTO because the turn-off losses are virtually zero.
The SITh
The SITh (Static Induction Thyristor) sometimes also -
referred to as FCT (Field Controlled Thyristor) is essentially N
a J-FET with an added P+ back layer. In contrast to the
standard thyristor, charge is normally only injected from the
back, so the total amount of charge is limited. However, a
positive gate drive is possible which will reduce on-state
resistance.
P+
Active extraction of charge via the gate contact is possible
and switching speeds may be reduced considerably by COLLECTOR
applying an appropriate negative drive as in the case of an
Fig.11 The IGBT
HVT. As for the SIT the technological complexity is a severe
11
The speed of the fast IGBT is somewhat better than that of Comparison of the Basic Devices.
a GTO because a similar technology is used to optimise
It is important to consider the properties of devices
the IGBT but only the back P+-layer is responsible for the
mentioned when choosing the optimum switch for a
charge.
particular application. Table 2 gives a survey of the
The IGBT is gaining rapidly in popularity since its essential device properties of devices capable of
manufacturing is similar to producing PowerMOS and an withstanding 1000 V. IGBTs have been classed in terms
increasing market availability exists. Although the latching of fast and slow devices, however only the fast GTO and
of IGBTs was seen as a problem, modern optimised devices slow thyristor are represented. The fast devices are
don’t suffer from latch-up in practical conditions. optimised for speed, the slow devices are optimised for On
voltage.
Comments
Refinements to the basic structure
This table is valid for 1000 V devices. Lower voltage devices
The refinements outlined for 3 layer devices also apply to will always perform better, higher voltage devices are
4 layer structures. In addition to these, an N+-layer may be worse.
inserted between the P+ and N--layer. Without such a layer A dot means an average value in between "+" and "-"
the designer is limited in choice of starting material to Case
The "(--)" for a thyristor means a "--" in cases where forced
3 as explained in the diode section. Adding the extra
commutation is used; in case of natural commutation it is
N+-layer allows another combination of resistivity and
"+"
thickness to be used, improving device performance. An
example of this is the ASCR, the Asymmetric SCR, which Most figures are for reference only: in exceptional cases
is much faster than normal thyristors. The reverse blocking better performance has been achieved, but the figures
capability, however, is now reduced to a value of 10-20 V. quoted represent the state of the art.
HVT J-FET MOS THY GTO IGBT IGBT Unit

slow fast
V(ON) 1 10 5 1.5 3 2 4 V
Positive Drive Requirement - + + + + + + + = Simple to
implement
Turn-Off requirement - - + (--) - + + + = Simple to
implement
Drive circuit complexity - . + (-) . + + - = complex
Technology Complexity + . . + - - - - = complex
Device Protection - . + + - - - + = Simple to
implement
Delay time (ts, tq) 2 0.1 0.1 5 1 2 0.5 µs
Switching Losses . ++ ++ -- - - . + = good
Current Density 50 12 20 200 100 50 50 A/cm2
Max dv/dt (Vin = 0) 3 20 10 0.5 1.5 3 10 V/ns
dI/dt 1 10 10 1 0.3 10 10 A/ns
Vmax 1500 1000 1000 5000 4000 1000 1000 V
Imax 1000 10 100 5000 3000 400 400 A
Over Current factor 5 3 5 15 10 3 3
12
Merged devices Where the GTO would like to be switched off with a negative
gate, the internal GTO in an MCT can turn off by short
Merged devices are the class of devices composed of two
circuiting its gate-cathode, due to its fine structure. Its drive
or more of the above mentioned basic types. They don’t
therefore is like a MOS transistor and its behaviour similar
offer any breakthrough in device performance. This is
to a GTO. Looking closely at the device it is obvious that
understandable since the basic properties of the discussed
a GTO using similar fine geometries with a suitable external
devices are not or are hardly effected. They may be
drive can always perform better, at the cost of some drive
beneficial for the user though, primarily because they may
circuitry. The only plus point seems to be its ease of drive.
result in lower positive and/or negative drive requirements.
Darlingtons and BiMOS

Application areas of the various devices
A darlington consists of two bipolar transistors. The emitter
current of the first (the driver) forms the base current of the The following section gives an indication of where the
output transistor. The advantages of darlingtons may be various devices are best placed in terms of applications. It
summarised as follows. A darlington has a higher gain than is possible for circuit designers to use various tricks to
a single transistor. It also switches faster because the input integrate devices and systems in innovative manners,
transistor desaturates the output transistor and lower applying devices far outside their ’normal’ operating
switching losses are the result. However, the resulting conditions. As an example, it is generally agreed that above
VCE(sat) is higher. The main issue, especially for higher 100 kHz bipolars are too difficult to use. However, a
powers is the savings in drive energy. This means that 450 kHz converter using bipolars has been already
darlingtons can be used at considerably higher output described in the literature.
powers than standard transistors. Modern darlingtons in
high power packages can be used in 20 kHz motor drives As far as the maximum frequency is concerned a number
and power supplies. of arguments must be taken into account.
A BiMOS consists of a MOS driver and a bipolar output
transistor. The positive drive is the same as MOS but First the delay times, either occurring at turn-on or at
turn-off is generally not so good. Adding a "speed-up" diode turn-off, will limit the maximum operating frequency. A
coupled with some negative drive improves things. reasonable rule of thumb for this is fMAX = 3 / tDELAY. (There
is a danger here for confusion: switching times tend to
depend heavily on circuit conditions, drive of the device and
G C G on current density. This may lead to a very optimistic or
P+ P+
pessimistic expectation and care should be taken to
N
N+ N consider reasonable conditions.)
P
Another factor is the switching losses which are proportional
to the frequency. These power losses may be influenced
by optimising the drive or by the addition of external circuits
such as dV/dt or dI/dt networks. Alternatively the heatsink
-
N size may be increased or one may choose to operate
devices at a lower current density in order to decrease
power losses. It is clear that this argument is very subjective.
A third point is manufacturability. The use of fine structures

+ for example, which improves switching performance, is
P
possible only for small silicon chip sizes: larger chips with
very fine MOS-like structures will suffer from unacceptable
ANODE low factory yields. Therefore high power systems requiring
Fig.12 The MCT large chip areas are bound to be made with less fine
structures and will consequently be slower.
MCT The operating current density of the device will influence
MCT stands for MOS Controlled Thyristor. This device is its physical size. A low current density device aimed at high
effectively a GTO with narrow tolerances, plus a P-MOS power systems would need a large outline which tends to
transistor between gate and source (P+-N-P MOS, the left be expensive. Large outlines also increase the physical size
hand gate in Fig.12) and an extra N-MOS to turn it on, the of the circuit, which leads to bigger parasitic inductances
N-P-N--MOS shown underneath the right hand gate. and associated problems.
13
10 MHz
RE
SO
1 MHz SQ NA
UA NT
RE SY
W ST
AV EM
E S
100 kHz SY
ST
EM
S
10 kHz MOS
(fast)-IGBT-(slow)
HVT DARLINGTONS
1 kHz SITr SITh
(fast) GTO (slow)
THYRISTOR
100 Hz
100VA 1kVA 10kVA 100kVA 1MVA 10MVA 100MVA
Fig.13 Comparison of device operating regions
High power systems will, because of the mechanical size, can be achieved however above 50 kHz, darlingtons are
be restricted in speed as explained earlier in the text . This not expected to be used. One should use this table only as
coincides well with the previously mentioned slower guidance; using special circuit techniques, darlingtons have
character of higher power devices. actually been used at higher frequencies. Clearly operation
at lower powers and frequencies is always possible.
Last but not least it is necessary to take the application
topology into account. Resonant systems allow the use of
considerably higher frequencies, since switching losses are Conclusions
minimised. Square wave systems cause more losses in the
devices and thus restrict the maximum frequency. To make The starting material for active devices aimed at high
a comparison of devices and provide insight into which voltage switching are made on silicon of which the minimum
powers are realistic for which devices we have to take all resistivity and thickness are limited. This essentially
the above mentioned criteria into account. determines device performance, since all active switches
Figure 13 shows the optimum working areas of the various incorporate such a layer. Optimisation can be performed
switching devices as a function of switchable power and for either minimum thickness, as required in the case of
frequency. The switchable power is defined as IAV times HVTs, or for minimum resistance, as required for MOS and
VMAX as seen by the device. J-FETs. The thickest variation (lowest resistivity) is required
in the case of some 4 layer devices.
As an example, darlingtons will work at powers up to 1 MVA
i.e. 1000 V devices will switch 1000 A. The frequency is Basically three ways exist to control current through the
then limited to 2.5 kHz. At lower powers higher frequencies devices: feeding a base current into a P-layer (transistor),
14
using a voltage to pinch-off the current through openings be high.

in the P-layer (J-FET) and by applying a voltage onto a gate
which inverts the underlying P-layer (MOS).
The properties of all six derived basic devices are
The HVT is severely limited in operating frequency due to determined to a large extent by the design of the high
its stored hole charge, but this at the same time allows a resistive area and can be optimised by applying
greater current density and a lower on-state voltage. It also technological features in the devices such as lifetime killing
requires more drive energy than both MOS and J-FET. and fine geometries.
When we add a P+-layer at the back of the three basic three
layer devices we make three basic four layer devices. The Resonant systems allow devices to be used at much higher
P+-layer produces a PNP transistor at the back which frequencies due to the lower switching losses and the
exhibits hole storage. This leads to much improved current minimum on-times which may be longer, compared to
densities and lower on-state losses, at the cost of switching square wave switching systems. Figure 13 gives the
speed. The four layer devices can be optimised for low expected maximum frequency and switching power for the
on-state losses, in which case the switching will be poor, discussed devices. The difference for square wave systems
or for fast switching, in which case the on-state voltage will and resonant systems is about a factor of 10.
15
Power MOSFET
17
1.2.1 PowerMOS Introduction
Device structure and fabrication parallels all the individual transistor cells on the chip. The
layout of a typical low voltage chip is shown in Fig.1(b). The
The idea of a vertical channel MOSFET has been known
polysilicon gate is contacted by bonding to the defined pad
since the 1930s but it was not until the mid 1970s that the
area while the source wires are bonded directly to the
technology of diffusion, ion implantation and material
aluminium over the cell array. The back of the chip is
treatment had reached the level necessary to produce
metallized with a triple layer of titanium/nickel/silver and this
DMOS on a commercial scale. The vertical diffusion
enables the drain connection to be formed using a standard
technique uses technology more commonly associated
alloy bond process.
with the manufacture of large scale integrated circuits than
with traditional power devices. Figure 1(a) shows the
The active part of the device consists of many cells
vertical double implanted (DIMOS) channel structure which
connected in parallel to give a high current handling
is the basis for all Philips power MOSFET devices.
capability where the current flow is vertical through the chip.
An N-channel PowerMOS transistor is fabricated on an Cell density is determined by photolithographic tolerance
N+substrate with a drain metallization applied to its’ requirements in defining windows in the polysilicon and
underside. Above the N+substrate is an N- epi layer, the gate-source oxide and also by the width of the polysilicon
thickness and resistivity of which depends on the required track between adjacent cells. The optimum value for
drain-source breakdown voltage. The channel structure, polysilicon track width and hence cell density varies as a
formed from a double implant in to the surface epi material, function of device drain-source voltage rating, this is
is laid down in a cellular pattern such that many thousands explained in more detail further in the section. Typical cell
of cells go to make a single transistor. The N+polysilicon densities are 1.6 million cells per square inch for low voltage
gate which is embedded in an isolating silicon dioxide layer, types and 350,000 cells per square inch for high voltage
is a single structure which runs between the cells across types. The cell array is surrounded by an edge termination
the entire active region of the device. The source structure to control the surface electric field distribution in
metallization also covers the entire structure and thus the device off-state.
Fig.1(a) Power MOSFET cell structure.
19
Fig.1(b) Plan view of a low voltage Power MOS chip
20
A cross-section through a single cell of the array is shown When the gate voltage is further increased a very thin layer
in Fig.2. The channel length is approximately 1.5 microns of electrons is formed at the interface between the P- body
and is defined by the difference in the sideways diffusion and the gate oxide. This conductive N-type channel
of the N+ source and the P-body. Both these diffusions are enhanced by the positive gate-source voltage, now permits
auto-aligned to the edge of the polysilicon gate during the current to flow from drain to source. The silicon in the P-
fabrication process. All diffusions are formed by ion body is referred to as being in an ’inverted’ state. A slight
implantation followed by high temperature anneal/drive-in increase in gate voltage will result in a very significant
to give good parameter reproducibility. The gate is increase in drain current and a corresponding rapid
electrically isolated from the silicon by an 800 Angstrom decrease in drain voltage, assuming a normal resistive load
layer of gate oxide (for standard types, 500 Angstrom for is present.
Logic level and from the overlying aluminium by a thick layer
Eventually the drain current will be limited by the combined
of phosphorus doped oxide. Windows are defined in the
resistances of the load resistor and the RDS(ON) of the
latter oxide layer to enable the aluminium layer to contact
MOSFET. The MOSFET resistance reaches a minimum
the N+ source and the P+ diffusion in the centre of each cell.
when VGS = +10 volts (assuming a standard type).
The P+ diffusion provides a low resistance connection
Subsequently reducing the gate voltage to zero volts
between the P- body and ground potential, thus inhibiting
reverses the above sequence of events. There are no
turn-on of the inherent parasitic NPN bipolar structure.
stored charge effects since power MOSFETS are majority
carrier devices.
20 um
Power MOSFET parameters
GATE
SOURCE Threshold voltage
The threshold voltage is normally measured by connecting
the gate to the drain and then determining the voltage which
P- P- must be applied across the devices to achieve a drain
N+ N+
P+ current of 1.0 mA. This method is simple to implement and
provides a ready indication of the point at which channel
inversion occurs in the device.
N- EPI Layer
The P- body is formed by the implantation of boron through
the tapered edge of the polysilicon followed by an anneal
and drive-in. The main factors controlling threshold voltage
N+ Substrate
are gate oxide thickness and peak surface concentration
in the channel, which is determined by the P-body implant
DRAIN dose. To allow for slight process variation a window is
Fig.2 Cross-section of a single cell. usually defined which is 2.1 to 4.0 volts for standard types
and 1.0 to 2.0 volts for logic level types.
Device operation Positive charges in the gate oxide, for example due to
sodium, can cause the threshold voltage to drift. To
Current flow in an enhancement mode power MOSFET is
minimise this effect it is essential that the gate oxide is
controlled by the voltage applied between the gate and
grown under ultra clean conditions. In addition the
source terminals. The P- body isolates the source and drain
polysilicon gate and phosphorus doped oxide layer provide
regions and forms two P-N junctions connected
a good barrier to mobile ions such as sodium and thus help
back-to-back. With both the gate and source at zero volts
to ensure good threshold voltage stability.
there is no source-drain current flow and the drain sits at
the positive supply voltage. The only current which can flow
from source to drain is the reverse leakage current.
Drain-source on-state resistance
The overall drain-source resistance, RDS(ON), of a power
As the gate voltage is gradually made more positive with
MOSFET is composed of several elements, as shown in
respect to the source, holes are repelled and a depleted
Fig.3.
region of silicon is formed in the P- body below the
silicon-gate oxide interface. The silicon is now in a The relative contribution from each of the elements varies
’depleted’ state, but there is still no significant current flow with the drain-source voltage rating. For low voltage
between the source and drain. devices the channel resistance is very important while for
21
leads to an optimum value for the polysilicon track width for

a given drain-source voltage rating. Since the zero-bias
depletion width is greater for low doped material, then a
wider polysilicon track width is used for high voltage chip
designs.
Spreading resistance. As the electrons move further into

the bulk of the silicon they are able to spread sideways and
flow under the cells. Eventually paths overlap under the
centre of each cell.
Epitaxial layer. The drain-source voltage rating

requirements determine the resistivity and thickness of the
epitaxial layer. For high voltage devices the resistance of
the epitaxial layer dominates the overall value of RDS(ON).
Substrate. The resistance of the N+ substrate is only

Fig.3 Power MOSFET components of RDS(ON).
significant in the case of 50 V devices.
the high voltage devices the resistivity and thickness of the Wires and leads. In a completed device the wire and lead
epitaxial layer dominates. The properties of the various resistances contribute a few milli-ohms to the overall
resistive components will now be discussed: resistance.
Channel. The unit channel resistance is determined by the
For all the above components the actual level of resistance
channel length, gate oxide thickness, carrier mobility,
is a function of the mobility of the current carrier. Since the
threshold voltage, and the actual gate voltage applied to
mobility of holes is much lower than that of electrons the
the device. The channel resistance for a given gate voltage
resistance of P-Channel MOSFETs is significantly higher
can be significantly reduced by lowering the thickness of
than that of N-Channel devices. For this reason P-Channel
the gate oxide. This approach is used to fabricate the Logic
types tend to be unattractive for most applications.
Level MOSFET transistors and enables a similar value
RDS(ON) to be achieved with only 5 volts applied to the gate.
Of course, the gate-source voltage rating must be reduced Drain-source breakdown voltage
to allow for the lower dielectric breakdown of the thinner
oxide layer. The voltage blocking junction in the PowerMOS transistor
is formed between the P-body diffusion and the N- epi layer.
The overall channel resistance of a device is inversely For any P-N junction there exists a maximum theoretical
proportional to channel width, determined by the total breakdown voltage, which is dependent on doping profiles
periphery of the cell windows. Channel width is over and material thickness. For the case of the N-channel
200 cm for a 20 mm2 low voltage chip. The overall channel PowerMOS transistor nearly all the blocking voltage is
resistance can be significantly reduced by going to higher supported by the N- epi layer. The ability of the N- epi layer
cell densities, since the cell periphery per unit area is to support voltage is a function of its resistivity and thickness
reduced. where both must increase to accommodate a higher
Accumulation layer. The silicon interface under the centre breakdown voltage. This has obvious consequences in
of the gate track is ’accumulated’ when the gate is biased terms of drain-source resistance with RDS(ON) being
above the threshold voltage. This provides a low resistance approximately proportional to BVDSS2.5. It is therefore
path for the electrons when they leave the channel, prior to important to design PowerMOS devices such that the
entering the bulk silicon. This effect makes a significant breakdown voltage is as close as possible to the theoretical
contribution towards reducing the overall RDS(ON). maximum otherwise thicker, higher resistivity material has
to be used. Computer models are used to investigate the
Parasitic JFET. After leaving the accumulation layer the influence of cell design and layout on breakdown voltage.
electrons flow vertically down between the cells into the Since these factors also influence the ’on-state’ and
bulk of the silicon. Associated with each P-N junction there switching performances a degree of compromise is
is a depletion region which, in the case of the high voltage necessary.
devices, extends several microns into the N epitaxial region,
even under zero bias conditions. Consequently the current To achieve a high percentage of the theoretical breakdown
path for the electrons is restricted by this parasitic JFET maximum it is necessary to build edge structures around
structure. The resistance of the JFET structure can be the active area of the device. These are designed to reduce
reduced by increasing the polysilicon track width. However the electric fields which would otherwise be higher in these
this reduces the cell density. The need for compromise regions and cause premature breakdown.
22
For low voltage devices this structure consists of a field

plate design, Fig.4. The plates reduce the electric field LOPOX
intensity at the corner of the P+ guard ring which surrounds
the active cell area, and spread the field laterally along the LPCVD NITRIDE
surface of the device. The polysilicon gate is extended to POLYDOX
form the first field plate, whilst the aluminium source
metallization forms the second plate. The polysilicon P- P+ P+ P+ P+ P+
termination plate which is shorted to the drain in the corners
N+
of the chip (not shown on the diagram) operates as a
channel stopper. This prevents any accumulation of Source
Floating Guard Rings
positive charge at the surface of the epi layer and thus Guard
Ring
improves stability. Aluminium overlaps the termination
plate and provides a complete electrostatic screen against
any external ionic charges, hence ensuring good stability N- EPI Layer
of blocking performance.
Fig.5 Ring structure for high voltage devices.

Polysilicon Source Ring Gate Ring Source
Metallization
Termination Electrical characteristics
Plate
The DC characteristic
If a dc voltage source is connected across the drain and
Guard Ring
P- (Source) source terminals of an N channel enhancement mode
N+ P+ MOSFET, with the positive terminal connected to the drain,
the following characteristics can be observed. With the gate
Polysilicon to source voltage held below the threshold level negligible
N- EPI Layer current will flow when sweeping the drain source voltage
positive from zero. If the gate to source voltage is taken
above the threshold level, increasing the drain to source
voltage will cause current to flow in the drain. This current
N+ Substrate will increase as the drain-source voltage is increased up to
a point known as the pinch off voltage. Increasing the
Fig.4 Field plate structure for low voltage devices.
drain-source terminal voltage above this value will not
produce any significant increase in drain current.
For high voltage devices a set of floating P+ rings, see Fig.5, The pinch off voltage arises from a rapid increase in
is used to control the electric field distribution around the resistance which for any particular MOSFET will depend
device periphery. The number of rings in the structure on the combination of gate voltage and drain current. In its
depends on the voltage rating of the device, eight rings are simplest form, pinch off will occur when the ohmic drop
used for a 1000 volt type such as the BUK456-1000A. A across the channel region directly beneath the gate
three dimensional computer model enables the optimum becomes comparable to the gate to source voltage. Any
ring spacing to be determined so that each ring experiences further increase in drain current would now reduce the net
a similar field intensity as the structure approaches voltage across the gate oxide to a level which is no longer
avalanche breakdown. The rings are passivated with sufficient to induce a channel. The channel is thus pinched
polydox which acts as an electrostatic screen and prevents off at its edge furthest from the source N+ (see Fig.6).
external ionic charges inverting the lightly doped N-
A typical set of output characteristics is shown in Fig.7. The
interface to form P- channels between the rings. The
two regions of operation either side of the pinch off voltage
polydox is coated with layers of silicon nitride and
can be seen clearly. The region at voltages lower than the
phosphorus doped oxide.
pinch off value is usually known as the ohmic region.
Saturation region is the term used to describe that part of
All types have a final passivation layer of plasma nitride, the characteristic above the pinch-off voltage. (NB This
which acts as a further barrier to mobile charge and also definition of saturation is different to that used for bipolar
gives anti-scratch protection to the top surface. devices.)
23
To turn the device on and off the capacitances have to be

VGS + charged and discharged, the rate at which this can be
10 V achieved is dependent on the impedance and the current
sinking/sourcing capability of the drive circuit. Since it is
only the majority carriers that are involved in the conduction
Gate Oxide process, MOSFETs do not suffer from the same storage
Polysilicon Gate time problems which limit bipolar devices where minority
carriers have to be removed during turn-off. For most
applications therefore the switching times of the Power
10 V Gate to Channel Id
3 V Net Gate to Channel D
Ohmic Drop
Source 7V Pinch Off
Channel P-
N-
Cgd
Fig.6 Pinch off in a Power MOSFET
Cds
ID / A BUK4y8-800A G
20
VGS / V = 10 6 Cgs
5.5
15
S
10 5
Fig.8. The internal capacitances of a Power MOSFET.
MOSFET are limited only by the drive circuit and can be

4.5 very fast. Temperature has only a small effect on device
5
capacitances therefore switching times are independent of
temperature.
4
In Fig.9 typical gate-source and drain-source voltages for
0 a MOSFET switching current through a resistive load are
0 10 20 30 shown. The gate source capacitance needs to be charged
VDS / V up to a threshold voltage of about 3 V before the MOSFET
Fig.7 A typical dc characteristic for an N-channel begins to turn on. The time constant for this is CGS(RDR+RG)
enhancement mode MOSFET. and the time taken is called the turn-on delay time (tD(ON)).
As VGS starts to exceed the threshold voltage the MOSFET
begins to turn on and VDS begins to fall. CGD now needs to
be discharged as well as CGS being charged so the time
The switching characteristics constant is increased and the gradient of VGS is reduced.
As VDS becomes less than VGS the value of CGD increases
The switching characteristics of a Power MOSFET are sharply since it is depletion dependent. A plateau thus
determined largely by the various capacitances inherent in occurs in the VGS characteristic as the drive current goes
its’ structure. These are shown in Fig.8. into the charging of CGD.
24
50
40 Turn-on Turn-off
30 Drain-Source Voltage
Voltage (Volts)
20
Gate-Source Voltage
10
0
0 0.2 0.4 0.6 0.8 1 1.2
Time (Microseconds)
Fig.9. The switching waveforms for a MOSFET.
When VDS has collapsed VGS continues to rise as overdrive necessary to raise its junction temperature to the rated
is applied. Gate overdrive is necessary to reduce the maximum of 150 ˚C or 175 ˚C (which TJMAX depends on
on-resistance of the MOSFET and thereby keep power loss package and voltage rating). Whether a MOSFET is being
to a minimum. operated safely with respect to thermal stress can thus be
determined directly from knowledge of the power function
To turn the MOSFET off the overdrive has first to be
applied and the thermal impedance characteristics.
removed. The charging path for CGD and CDS now contains
the load resistor (RL) and so the turn-off time will be
A safe operating area calculated assuming a mounting base
generally longer than the turn-on time.
temperature of 25 ˚C is shown in Fig.10 for a BUK438-800
device. This plot shows the constant power curves for a
The Safe Operating Area variety of pulse durations ranging from dc to 10 µs. These
Unlike bipolar devices Power MOSFETs do not suffer from curves represent the power levels which will raise Tj up to
second breakdown phenomena when operated within their the maximum rating. Clearly for mounting base
voltage rating. Essentially therefore the safe operating area temperatures higher than 25 ˚C the safe operating area is
of a Power MOSFET is determined only by the power smaller. In addition it is not usually desirable to operate the
25
device at its TJMAX rating. These factors can be taken into It is important to note that the on-resistance of the MOSFET
account quite simply where maximum power capability for when it is operated in the Ohmic region is dependent on
a particular application is calculated from: the junction temperature. On-resistance roughly doubles
between 25 ˚C and 150 ˚C, the exact characteristics are
(Tj − Tmb ) shown in the data sheets for each device.
Pmax =
Zth
Switching losses - When a MOSFET is turned on or off it
carries a large current and sustains a large voltage at the
Tj is the desired operating junction temperature (must be
same time. There is therefore a large power dissipation
less than Tjmax)
during the switching interval. Switching losses are
Tmb is the mounting base temperature
negligible at low frequencies but are dominant at high
Zth is the thermal impedance taken from the data curves
frequencies. The cross-over frequency depends on the
The safe operating area is bounded by a peak pulse current circuit configuration. For reasons explained in the section
limit and a maximum voltage. The peak pulse current is on switching characteristics, a MOSFET usually turns off
based on a current above which internal connections may more slowly than it turns on so the losses at turn-off will be
be damaged. The maximum voltage is an upper limit above larger than at turn-on. Switching losses are very dependent
which the device may go into avalanche breakdown. on circuit configuration since the turn-off time is affected by
the load impedance.
ID / A Turn-off losses may be reduced by the use of snubber

BUK438-800
100 components connected across the MOSFET which limit the
rate of rise of voltage. Inductors can be connected in series
A with the MOSFET to limit the rate of rise of current at turn-on
/ID tp =
S and reduce turn-on losses. With resonant loads switching
VD B
)= can take place at zero crossing of voltage or current so
ON 10 us
10 S( switching losses are very much reduced.
RD
100 us Diode losses - These losses only occur in circuits which
make use of the antiparallel diode inherent in the MOSFET
structure. A good approximation to the dissipation in the
1 ms
diode is the product of the diode voltage drop which is
1
DC 10 ms typically less than 1.5 V and the average current carried by
the diode. Diode conduction can be useful in such circuits
100 ms
as pulse width modulated circuits used for motor control, in
some stepper motor drive circuits and in voltage fed circuits
0.1 feeding a series resonant load.
10 100 1000 Gate losses - The losses in the gate are given in equation
VDS / V 2 where RG is the internal gate resistance, RDR is the external
Fig.10. The Safe Operating Area of the BUK438-800. drive resistance, VGSD is the gate drive voltage and CIP is
the capacitance seen at the input to the gate of the
In a real application the case temperature will be greater MOSFET.
than 25 ˚C because of the finite thermal impedance of CIP .VGSD
2
.f.RG
practical heatsinks. Also a junction temperature of between PG = (2)
(RG + RDR )
80 ˚C and 125 ˚C would be preferable since this improves
reliability. If a nominal junction temperature of 80 ˚C The input capacitance varies greatly with the gate drain
instead of 150 ˚C is used then the ability of the MOSFET voltage so the expression in equation 3 is more useful.
to withstand current spikes is improved.
QG .VGSD .f.RG
PG = (3)
(RG + RDR )
Causes of Power Loss
(3)
There are four main causes of power dissipation in
Where QG is the peak gate charge.
MOSFETs.
Conduction losses - The conduction losses (PC) are given Parallel Operation
by equation (1). If power requirements exceed those of available devices
then increased power levels can be achieved by parallelling
PC = I .RDS(ON)
2
D (1) devices. Parallelling of devices is made easier using
26
MOSFETs because they have a positive temperature subsequent chapters.

coefficient of resistance. If one parallelled MOSFET carries
Chapter 2: Switched mode power supplies (SMPS)
more current than the others it becomes hotter. This
causes the on-resistance of that particular device to Chapter 3: Variable speed motor control.
become greater than that of the others and so the current
in it reduces. This mechanism opposes thermal runaway Chapter 5: Automotive switching applications.
in one of the devices. The positive temperature coefficient
also helps to prevent hot spots within the MOSFET itself. Conclusions
It can be seen that the operation of the Power MOSFET is
Applications of Power MOSFETs relatively easy to understand. The advantages of fast
Power MOSFETs are ideally suited for use in many switching times, ease of parallelling and low drive power
applications, some of which are listed below. Further requirements make the device attractive for use in many
information on the major applications is presented in applications.
27
1.2.2 Understanding Power MOSFET Switching Behaviour
Power MOSFETs are well known for their ease of drive and for a fixed dc voltage. The shaded area beneath the curve
fast switching behaviour. Being majority carrier devices must be equal to the applied voltage. The electric field
means they are free of the charge storage effects which gradient is fixed, independent of the applied voltage,
inhibit the switching performance of bipolar products. How according to the concentration of exposed charge. (This is
fast a Power MOSFET will switch is determined by the equal to the background doping concentration used during
speed at which its internal capacitances can be charged device manufacture.) A slight increase in voltage above
and discharged by the drive circuit. MOSFET switching this dc level will require an extension of the depletion region,
times are often quoted as part of the device data however and hence more charge to be exposed at its edges, this is
as an indication as to the true switching capability of the illustrated in Fig.1. Conversely a slight reduction in voltage
device, these figures are largely irrelevant. The quoted will cause the depletion region to contract with a removal
values are only a snapshot showing what will be achieved of exposed charge at its edge. Superimposing a small ac
under the stated conditions. signal on the dc voltage thus causes charge to be added
and subtracted at either side of the depletion region of width
This report sets out to explain the switching characteristics
d1. The effective capacitance per unit area is
of Power MOSFETs. It will consider the main features of
the switching cycle distinguishing between what is device Ε
determinant and what can be controlled by the drive circuit. C1 = 2
d1
The requirements for the drive circuit are discussed in terms
of the energy that it must supply as well as the currents it Since the depletion region width is voltage dependent it can
is required to deliver. Finally, how the drive circuit be seen from Fig.1 that if the dc bias is raised to say V2,
influences switching performance, in terms of switching the junction capacitance becomes
times, dV/dt and dI/dt will be reviewed.
Ε
C2 = 3
Voltage dependent capacitance d2
The switching characteristics of the Power MOSFET are Junction capacitance is thus dependent on applied voltage
determined by its capacitances. These capacitances are with an inverse relationship.
not fixed but are a function of the relative voltages between
each of the terminals. To fully appreciate Power MOSFET E
switching, it is necessary to understand what gives rise to
this voltage dependency.
Parallel plate capacitance is expressed by the well known
equation P type silicon N type silicon
a V2
C =Ε 1
d
where ’a’ is the area of the plates, d is the separating
distance and Ε is the permittivity of the insulating material
between them. For a parallel plate capacitor, the plates are V1
surfaces on which charge accumulation / depletion occurs
in response to a change in the voltage applied across them. d1 x
In a semiconductor, static charge accumulation / depletion d2
can occur either across a PN junction or at semiconductor Fig.1 Voltage dependence of a PN junction
interfaces either side of a separating oxide layer. capacitance
i) P-N junction capacitance

The voltage supporting capability of most power
ii) Oxide capacitance
semiconductors is provided by a reverse biased P-N Fig.2 shows two semiconductor layers separated by an
junction. The voltage is supported either side of the junction insulating oxide. In this case the surface layer is polysilicon
by a region of charge which is exposed by the applied (representative of the PowerMOS gate structure) and the
voltage. (Usually referred to as the depletion region lower layer is a P-type substrate. Applying a negative
because it is depleted of majority carriers.) Fig.1 shows voltage to the upper layer with respect to the lower will cause
how the electric field varies across a typical P-N- junction positive charge accumulation at the surface of the P-doped
29
material (positively charged holes of the P material are

attracted by the negative voltage). Any changes in this C
applied voltage will cause a corresponding change in the
accumulation layer charge. The capacitance per unit area Cox
is thus
Ε
Cox = 4
t
where t = oxide thickness

Applying a positive voltage to the gate will cause a depletion
layer to form beneath the oxide, (ie the positively charged
holes of the P-material are repelled by the positive voltage).
The capacitance will now decrease with increasing positive
gate voltage as a result of widening of the depletion layer. Bias Voltage
Increasing the voltage beyond a certain point results in a (Polysilicon to P-type silicon)
process known as inversion; electrons pulled into the
Fig.3 C-V plot for MOS capacitance
conduction band by the electric field accumulate at the
surface of the P-type semiconductor. (The voltage at which
this occurs is the threshold voltage of the power MOSFET.) Power MOSFET capacitances
Once the inversion layer forms, the depletion layer width
will not increase with additional dc bias and the capacitance
D
is thus at its minimum value. (NB the electron charge
accumulation at the inversion layer cannot follow a high
frequency ac signal in the structure of Fig.2, so high
frequency capacitance is still determined by the depletion
layer width.) The solid line of Fig.3 represents the
Cgd
capacitance-voltage characteristic of an MOS capacitor.
Cds
G
Polysilicon
Cgs
oxide t
Fig.4 Parasitic capacitance model

P type silicon
The circuit model of Fig.4 illustrates the parasitic
capacitances of the Power MOSFET. Most PowerMOS
data sheets do not refer to these components but to input
capacitance Ciss, output capacitance Coss and feedback
Fig.2 Oxide capacitance capacitance Crss. The data sheet capacitances relate to
the primary parasitic capacitances of Fig.4 as follows:
In a power MOSFET the solid line is not actually observed;
Ciss: Parallel combination of Cgs and Cgd
the formation of the inversion layer in the P-type material
Coss: Parallel combination of Cds and Cgd
allows electrons to move from the neighbouring N+-source,
Crss: Equivalent to Cgd
the inversion layer can therefore respond to a high
frequency gate signal and the capacitance returns to its Fig.5 shows the cross section of a power MOSFET cell
maximum value, dashed line of Fig.3. indicating where the parasitic capacitances occur internally.
30
The capacitance between drain and source is a P-N junction

Gate
capacitance, varying in accordance with the width of the
Polysilicon
CgsM Oxide depletion layer, which in turn depends on the voltage being
Metalization
supported by the device. The gate source capacitance
Source consists of the three components, CgsN+, CgsP and CgsM.
CgsN+ CgsP N+ Of these CgsP is across the oxide which will vary according
Cgdox P-
to the applied gate source voltage as described above.
P
Cgdbulk Of particular interest is the feedback capacitance Cgd. It
is this capacitance which plays a dominant role during
Cds Depletion Layer
switching and which is also the most voltage dependent.
Cgd is essentially two capacitors in series such that
N-
1 1 1
= + 5
Cgd Cgdox Cgdbulk
N+
Drain
Fig.5 Cross section of a single PowerMOS cell showing

internal capacitance
Gate
Polysilicon Oxide
Metalization
Source
N+
P-
Width for Cgdbulk
at Voltage V3
V1
V2
V3
Depletion Layer Widths
For Three Applied Voltages N-
N+
Area of Oxide
Drain
Capacitance Exposed
for Voltages V1 & V2
Fig.6 How Cgd is affected by voltage
31
Fig.6 illustrates how this capacitance is affected by the drain region the MOSFET is a constant current source where the
to gate voltage. With a large voltage drain to gate, Cgdbulk current is a function of the gate-source voltage. In the ohmic
is very small due to the wide depletion region and thus region the MOSFET is in effect just a resistance.)
maintains Cgd at a low value. As the voltage is reduced
the depletion region shrinks until eventually the oxide
Vdd
semiconductor interface is exposed. This occurs as Vdg
approaches 0 V. Cgdox now dominates Cgd. As Vdg is
further reduced the drain will become negative with respect
to the gate (normal on-state condition) an increasing area
of the oxide-semiconductor interface is exposed and an
accumulation layer forms at the semiconductor surface.
The now large area of exposed oxide results in a large value
for Cgdox and hence Cgd. Fig.7 shows Cgd plotted as a
function of drain to gate voltage. This illustrates the almost
step increase in capacitance at the point where Vgs = Vgd.
Cdg
Fig.8 Gate charge circuit
At time, t0 (Fig.9), the gate drive is activated. Current flows

into the gate as indicated in Fig.11(a), charging both Cgs
and Cgd. After a short period the threshold voltage is
reached and current begins to rise in the MOSFET. The
equivalent circuit is now as shown in Fig.11(b). The drain
0 Vdg source voltage remains at the supply level as long as id < I0
Fig.7 How Cgd varies with drain to gate voltage and the free wheeling diode D is conducting.
Charging cycle - The Gate Charge t0 t1 t2

26
Oscillogram
(V) 24
The switching cycle of a power MOSFET can be clearly 22 BUK555-100A
observed by applying a constant current to the gate and (@ Id = 25 A)
20
using a constant current source as the load, Fig.8. In this
18
circuit the MOSFET is turned on by feeding a constant
16
current of 1 mA on to the gate, conversely the device is
Vds
turned off by extracting a constant current of 1 mA from the 14
gate. The gate and drain voltages with respect to source 12

can be monitored on an oscilloscope as a function of time. 10
Since Q = it, a 1 µsec period equates to 1 nc of charge 8
applied to the gate. The gate source voltage can thus be 6
plotted as a function of charge on the gate. Fig.9 shows 4
Vgs
such a plot for the turn-on of a BUK555-100A, also shown
2
is the drain to source voltage. This gate voltage plot shows
0
the characteristic shape which results from charging of the 0 10 20 30 40
power MOSFETs input capacitance. This shape arises as (1us = 1 nc for Vgs plot) (us)
follows: (NB the following analysis uses the two circuit
Fig.9 Gate charge plot for a BUK555-100A (Logic Level
models of Fig.10 to represent a MOSFET operating in the
FET)
active region (a) and the ohmic region (b). In the active
32
The current in the MOSFET continues to rise until id = I0,

since the device is still in its active region, the gate voltage D D
becomes clamped at this point, (t1). The entire gate current

now flows through Cgd causing the drain-source voltage to Cgd Cgd
drop as Cgd is discharged, Fig.11(c). The rate at which

Vds falls is given by:
G G
dVds dVdg ig
= = 6 Rds(on)
dt dt Cgd
id = f(Vgs)
As Vdg approaches zero, Cgd starts to increase Cgs Cgs
dramatically, reaching its maximum as Vdg becomes

negative. dVds/dt is now greatly reduced giving rise to the S S
voltage tail.
Once the drain-source voltage has completed its drop to (a) (b)
the on-state value of I0.RDS(ON), (point t2), the gate source
Fig.10 Equivalent circuits for a Power MOSFET during
voltage becomes unclamped and continues to rise,
switching
Fig.11(d). (NB dVgs/dQ in regions 1 and 3 indicates the
input capacitance values.)
(a) Vdd (b) Vdd
Io Io
Cgd Cgd
id = f(Vgs)
Cgs Cgs
(c) Vdd (d) Vdd
Io Io
Cgd Cgd
Rds(on)
id = f(Vgs)
Cgs Cgs
Fig.11 Charging the parasitic capacitance during turn-on
33
The gate charge oscillogram can be found in the data for gate drive impedance from a voltage source. Fig.13 shows
all Philips PowerMOS devices. This plot can be used to the voltage on a voltage independent capacitor as a function
determine the required average gate drive current for a of charge. The area beneath the charge vs voltage curve
particular switching speed. The speed is set by how fast equals the stored energy (E = Q.V/2). The area above the
the charge is supplied to the MOSFET. charge vs voltage curve (bounded by the supply voltage)
is the amount of energy dissipated during the charging cycle
Energy consumed by the switching event from a fixed voltage source. The total energy delivered by
the supply is therefore Q.V, where 1/2 Q.V is stored on the
In the majority of applications the power MOSFET will be
capacitor to be dissipated during the discharge phase.
driven not from a constant current source but via a fixed
Vgg
3b
1b 2b
1a 2a 3a
Vdd
4b
4a
Output Capacitance
t0 t1 t2 t3 t4 t5 t6
Fig.12 Gate charging cycle
34
Although the voltage vs charge relationship for the (The energy stored on Cgd during turn-off is dissipated
MOSFETs gate is not linear, energy loss is easily identified. internally in the MOSFET during turn-on.) Additional energy
The following discussion assumes a simple drive circuit is also stored on Cds during turn-off which again is
consisting of a voltage source and drive resistance. dissipated in the MOSFET at turn-on.
From t0 to t1 energy is stored in the gate capacitance which
is equal to the area of region 1a. Since this charge has The energy lost by both the gate and drain supplies in the
fallen through a voltage Vgg - Vgs(t), the area of region 1b charging and discharging of the capacitances is very small
represents the energy dissipated in the drive resistance over 1 cycle; Fig.9 indicates 40 nc is required to raise the
during its delivery. Between t1 and t2 all charge enters gate voltage to 10 V, delivered from a 10 V supply this
Cgd, the area of region 2a represents the energy stored in equates to 400 nJ; to charge Cgd to 80 V from an 80 V
Cgd while 2b again corresponds with the energy dissipation supply will consume 12 nc x 80 V = 1.4 µJ. Only as
in the drive resistor. Finally, between t2 and t3 additional switching frequencies approach 1 MHz will this energy loss
energy is stored by the input capacitance equal to the area start to become significant. (NB these losses only apply to
of region 3a. square wave switching, the case for resonant switching is
some-what different.)
Supply Voltage
Switching performance
1) Turn-on
Voltage
The parameters likely to be of most importance during the

Stored Energy turn-on phase are,
turn-on time
turn-on loss
peak dV/dt
Charge peak dI/dt.
Fig.13 Energy stored on a capacitor
Turn-on time is simply a matter of how quickly the specified
The total energy dissipated in the drive resistance at turn-on charge can be applied to the gate. The average current
is therefore equal to the area 1b + 2b + 3b. The that must be supplied over the turn-on period is
corresponding energy stored on the input capacitance is
1a + 2a + 3a, this energy will be dissipated in the drive
Q
resistance at turn-off. The total energy expended by the Ion = 8
gate drive for the switching cycle is Q.Vgg. ton
As well as energy expended by the drive circuit, a switching

cycle will also require energy to be expended by the drain For repetitive switching the average current requirement of
circuit due to the charging and discharging of Cgd and Cds the drive is
between the supply rail and VDS(ON). Moving from t5 to t6
the drain side of Cgd is charged from Io.RDS(ON) to Vdd. The I = Q.f 9
drain circuit must therefore supply sufficient current for this
charging event. The total charge requirement is given by
where f = frequency of the input signal
the plateau region, Q6 - Q5. The area 4a (Fig.12) under
the drain-source voltage curve represents the energy
stored by the drain circuit on Cgd during turn-on. Region Turn-on loss occurs during the initial phase when current
4b represents the corresponding energy delivered to the flows in the MOSFET while the drain source voltage is still
load during this period. The energy consumed from the high. To minimise this loss, a necessary requirement of
drain supply to charge and discharge Cgd over one high frequency circuits, requires the turn-on time to be as
switching cycle is thus given by: small as possible. To achieve fast switching the drive circuit
must be able to supply the initial peak current, given by
WDD = (Q6 − Q5).(VDD − VDS(ON)) 7 equation 10.
35
The dV/dt in this period is determined by the recovery

Vdd properties of the diode in relation to the dI/dt imposed upon
it by the turn-on of the MOSFET, (reducing dI/dt will reduce
this dV/dt, however it is best to use soft recovery diodes).
Io
T1 D1
0
Diode Current Irr
Io + Irr
MOSFET Current Io
0
Gate Source Voltage Vgt(Io + Irr)
Vgt(Io)
Load
0
Vdd
T2 D2
Drain Source Voltage
0 t
Fig.15 Gate charging cycle for a bridge circuit
0
ii) Turn-off
Fig.14 Bridge Circuit
The parameters of most importance during the turn-off
VGG phase are,
I pk = 10
Rg
turn-off time
One of the main problems associated with very fast turn-off loss
switching MOSFETs is the high rates of change in voltage peak dVds/dt
and current. High values of dV/dt can couple through peak dId/dt.
parasitic capacitances to give unwanted noise on signal
lines. Similarly a high dI/dt may react with circuit inductance Turn-off of a power MOSFET is more or less the inverse of
to give problematic transients and overshoot voltages in the the turn-on process. The main difference is that the
power circuit. dI/dt is controlled by the time taken to charge charging current for Cgd during turn-off must flow through
the input capacitance up to the plateau voltage, while dV/dt both the gate circuit impedance and the load impedance.
is governed by the rate at which the plateau region is moved A high load impedance will thus slow down the turn-off
through. speed.
dVds ig VGG − VGT The speed at which the plateau region is moved through
= = 11
dt Cgd RG .Cgd determines the voltage rise time. In most applications the
charging current for Cgd will be limited by the gate drive
Particular care is required regarding dV/dt when switching circuitry. The charging current, assuming no negative drive,
in bridge circuits, (Fig.14). The free wheeling diode will is simply
have associated with it a reverse recovery current. When
the opposing MOSFET switches on, the drain current rises Vgt
beyond the load current value Io to a value Io + Irr. i= 12
RG
Consequently Vgs increases beyond Vgt(Io) to Vgt(Io + Irr)
as shown in Fig.15. Once the diode has recovered there
is a rapid decrease in Vgs to Vgt(Io) and this rapid decrease and the length of the plateau region will be
provides additional current to Cgd on top of that being
supplied by the gate drive. This in turn causes Vdg and Q.RG
tp = 13
Vds to decrease very rapidly during this recovery period. Vgt
36
The implications for low threshold (Logic Level) MOSFETs speed is essentially determined by how fast the internal
are clear from the above equations. The lower value of Vgt capacitances can be charged and discharged by the drive
will mean a slower turn-off for a given gate impedance when circuit. Switching speeds quoted in data should be treated
compared to an equivalent standard threshold device. with caution since they only reflect performance for one
Equivalent switching therefore requires a lower drive particular drive condition. The gate charge plot is a more
impedance to be used. useful way of looking at switching capability since it
indicates how much charge needs to be supplied by the
Conclusions drive to turn the device on. How fast that charge should be
applied depends on the application and circuit performance
In theory the speed of a power MOSFET is limited only by
requirements.
the parasitic inductances of its internal bond wires. The
37
1.2.3 Power MOSFET Drive Circuits
MOSFETs are being increasingly used in many switching Non-isolated drive circuits
applications because of their fast switching times and low
MOSFETs can be driven directly from a CMOS logic IC as
drive power requirements. The fast switching times can
shown in Fig.1.
easily be realised by driving MOSFETs with relatively
simple drive circuits. The following paragraphs outline the
requirements of MOSFET drive circuits and present various
circuit examples. A look at the special requirements of very
fast switching circuits is also presented, this can be found
in the latter part of this article.
The requirements of the drive circuit 4011
Fig.1 A very simple drive circuit utilizing a standard

The switching of a MOSFET involves the charging and CMOS IC
discharging of the capacitance between the gate and
source terminals. This capacitance is related to the size of Faster switching speeds can be achieved by parallelling
the MOSFET chip used typically about 1-2 nF. A CMOS hex inverting (4049) or non-inverting (4050) buffers
gate-source voltage of 6V is usually sufficient to turn a as shown in Fig.2.
standard MOSFET fully on. However further increases in
gate-to-source voltage are usually employed to reduce the 15 V
MOSFETs on-resistance. Therefore for switching times of
about 50 ns, applying a 10 V gate drive voltage to a
MOSFET with a 2 nF gate-source capacitance would
require the drive circuit to sink and source peak currents of
about 0.5 A. However it is only necessary to carry this
current during the switching intervals.
The gate drive power requirements are given in equation

(1)
PG = QG .VGS .f 1
4049
where QG is the peak gate charge, VGS is the peak gate 0V
source voltage and f is the switching frequency.
Fig.2 Driving Philips PowerMOS with 6 parallelled
buffered inverters.
In circuits which use a bridge configuration, the gate
A push pull circuit can also be used as shown in Fig.3.
terminals of the MOSFETs in the circuit need to float relative
to each other. The gate drive circuitry then needs to The connections between the drive circuit and the MOSFET
incorporate some isolation. The impedance of the gate drive should be kept as short as possible and twisted together if
circuit should not be so large that there is a possibility of the shortest switching times are required. If both the drive
dV/dt turn on. dV/dt turn on can be caused by rapid changes circuit and the terminals of the MOSFET are on the same
of drain to source voltage. The charging current for the PCB, then the inductance of tracks, between the drive
gate-drain capacitance CGD flows through the gate drive transistors and the terminals of the MOSFETs, should be
circuit. This charging current can cause a voltage drop kept as small as possible. This is necessary to reduce the
across the gate drive impedance large enough to turn the impedance of the drive circuit in order to reduce the
MOSFET on. switching times and lessen the susceptibility of the circuit
39
The supply rails should be decoupled near to fast switching

elements such as the push-pull transistors in Fig.3. An
electrolytic capacitor in parallel with a ceramic capacitor are
recommended since the electrolytic capacitor will not be a
low enough impedance to the fast edges of the MOSFET
drive pulse.
Isolated drive circuits

Some circuits demand that the gate and source terminals
of MOSFETs are floating with respect to those of other
MOSFETs in the circuit. Isolated drive to these MOSFETs
can be provided in the following way:
(a) Opto-isolators.
Fig.3 A drive circuit using a two transistor push pull
circuit. A drive circuit using an opto-isolator is shown in Fig.4.
A diode in the primary side of the opto-isolator emits
to dV/dt turn-on of the MOSFET. Attention to layout also
photons when it is forward biased. These photons impinge
improves the immunity to spurious switching by
on the base region of a transistor in the secondary side.
interference.
This causes photogeneration of carriers sufficient to satisfy
One of the advantages of MOSFETs is that their switching the base requirement for turn-on. In this way the
times can be easily controlled. For example it may be opto-isolator provides isolation between the primary and
required to limit the rate of change of drain current to reduce secondary of the opto-isolator. An isolated supply is
overshoot on the drain source voltage waveform. The required for the circuitry on the secondary side of the
overshoot may be caused by switching current in parasitic opto-isolator. This supply can be derived, in some cases,
lead or transformer leakage inductance. The slower from the drain-to-source voltage across the MOSFET being
switching can be achieved by increasing the value of the driven as shown in Fig.5. This is made possible by the low
gate drive resistor. drive power requirements of MOSFETs.
15 V
5V
4049
Opto-Isolator 0V
Fig.4. An isolated drive circuit using an opto-isolator.
40
15 V
5V
4049
Opto-Isolator 0V
Fig.5. An opto-isolated drive circuit with the isolated power supply for the secondary derived from the drain source
voltage of the MOSFET.
Some opto-isolators incorporate an internal screen to V.t

improve the common mode transient immunity. Values as N= 2
B.Ae
high as 1000 V/µs are quoted for common mode rejection
which is equivalent to rejecting a 300V peak-to-peak
where B is the maximum flux density, Ae is the effective
sinewave.
cross sectional area of the core and t is the time that T2 is
The faster opto-isolators work off a maximum collector on for.
voltage on the secondary side of 5V so some form of level
shifting may be required. The circuit in Fig.6(a) is best suited for fixed duty cycle
(b) Pulse transformers. operation. The zener diode has to be large enough so that
the flux in the core will be reset during operation with the
A circuit using a pulse transformer for isolation is shown in maximum duty cycle. For any duty cycle less than the
Fig.6(a). maximum there will be a period when the voltage across
When T2 switches on, voltage is applied across the primary the secondary is zero as shown in Fig.7.
of the pulse transformer. The current through T2 consists
of the sum of the gate drive current for T1 and the In Fig.8 a capacitor is used to block the dc components of
magnetising current of the pulse transformer. From the the drive signal.
waveforms of current and voltage around the circuit shown
in Fig.6(b), it can be seen that after the turn off of T2 the Drive circuits using pulse transformers have problems if a
voltage across it rises to VD + VZ, where VZ is the voltage widely varying duty cycle is required. This causes widely
across the zener diode ZD. The zener voltage VZ applied varying gate drive voltages when the MOSFET is off. In
across the pulse transformer causes the flux in the core to consequence there are variable switching times and
be reset. Thus the net volt second area across the pulse varying levels of immunity to dV/dt turn on and interference.
transformer is zero over a switching cycle. The minimum There are several possible solutions to this problem, some
number of turns on the primary is given by equation (2). examples are given in Figs.9 - 12.
41
Vd
ZD
T1
T1
T2
0V
Fig.6(a) A circuit using a pulse transformer for isolation. Fig.8. A drive circuit using a capacitor to block the dc
component of the drive waveforms.
Primary
Voltage
time
T2
A
Voltage
Across T2
T1
time
Fig.6(b) Waveforms associated with pulse transformer.
B
Secondary
Voltage
Fig.9. A drive circuit that uses a pulse transformer for
isolation which copes well with widely varying duty
High
Duty
cycles.
time
Cycle
Low
Duty
Cycle time
T2
A
Fig.7. The voltage waveforms associated with the circuit
in Fig.6(a) with varying duty cycles.
T1
T3
In the circuit shown in Fig.9 when A is positive with respect
to B the input capacitance of T1 is charged through the
parasitic diode of T2. The voltage across the secondary of B
the pulse transformer can then fall to zero and the input
capacitance of T1 will remain charged. (It is sometimes
necessary to raise the effective input capacitance with an Fig.10. An isolated drive circuit with good performance
external capacitor as indicated by the dashed lines.) When with varying duty cycles and increased noise immunity.
B becomes positive with respect to A T2 will turn on and
the input capacitance of T2 will be discharged. The noise In Fig.10 the potential at A relative to B has to be sufficient
immunity of the circuit can be increased by using another to charge the input capacitance of T3 and so turn T3 on
MOSFET as shown in Fig.10. before T1 can begin to turn on.
42
h.f. clock
Q1 T1
drive signal
Fig.11. A drive circuit that reduces the size of the pulse transformer.
In Fig.11 the drive signal is ANDed with a hf clock. If the transformer is rectified. Q1 provides a low impedance path
clock has a frequency much higher than the switching for discharging the input capacitance of T1 when the hf
frequency of T1 then the size of the pulse transformer is signal on the secondary of the pulse transformer is absent.
reduced. The hf signal on the secondary of the pulse
DC Link
15 V
2n2 8 uF
FX3848
HEF40097
10T 20T
100R
2k2
2k2
18 k
47 pF
1 k c18v
OV
Fig.12 Example of pulse transformer isolated drive with a latching buffer
43
Figure 12 shows a hex non-inverting buffer connected on the boot strap capacitor while the MOSFET is off. For this
the secondary side, with one of the six buffers configured reason these circuits cannot be used for dc switching. The
as a latch. The circuit operates such that the positive going minimum operating frequency is determined by the size of
edge of the drive pulse will cause the buffers to latch into the boot strap capacitor (and R1 in circuit (a)), as the
the high state. Conversely the negative going edge of the operating frequency is increased so the value of the
drive pulse causes the buffers to latch into the low state. capacitor can be reduced. The circuit example in Fig. 14(a)
With the component values indicated on the diagram this has a minimum operating frequency of 500 Hz.
circuit can operate with pulse on-times as low as 1 µs. The
impedance Z represents either the low side switch in a
24V
bridge circuit (which can be a MOSFET configured with
identical drive) or a low side load. C 6.8uF
The impedance of the gate drive circuit may be used to 10k

control the switching times of the MOSFET. Increasing gate
T2
drive impedance however can increase the risk of dV/dt 1k0
T1
turn-on. To try and overcome this problem it may be Vin 22k R1 47R
necessary to configure the drive as outlined in Fig.13.
0V
R1 D1
Fig.14(a) Drive circuit for a low voltage half bridge
circuit.
At high frequencies it may be necessary to replace R1 with

T1 the transistor T3 as shown in Fig.14(b). This enables very
R2
fast turn-off times which would be difficult to achieve with
circuit (a) since reducing R1 to a low value would cause the
(a) boot strap capacitor to discharge during the on-period. The
impedance Z represents either the low side switch part of
the bridge or the load.
24V
T1
T2
T3
(b)
T1
Fig.13. Two circuits that reduce the risk of dV/dt turn on. Vin
Z
The diode in Fig.13(a) reduces the gate drive impedance 0V

when the MOSFET is turned off. In Fig.13(b) when the drive
pulse is taken away, the pnp transistor is turned on. When Fig.14(b) Modification for fast turn-off.
the pnp transistor is on it short-circuits the gate to the source
and so reduces the gate drive impedance.
Very fast drive circuits for frequencies up
High side drive circuits to 1 MHz
The isolated drive circuits in the previous section can be The following drive circuits can charge the gate source
used for either high or low side applications. Not all high capacitance particularly fast and so realise extremely short
side applications however require an isolated drive. Two switching times. These fast transition times are necessary
examples showing how a high side drive can be achieved to reduce the switching losses. Switching losses are directly
simply with a boot strap capacitor are shown in Fig.14. Both proportional to the switching frequency and are greater than
these circuits depend upon the topping up of the charge on conduction losses above a frequency of about 500 kHz,
44
although this crossover frequency is dependent on circuit For the circuit in Fig.17 when MOSFET T1 is turned on the
configuration. Thus for operation above 500 kHz it is driven MOSFET T3 is driven initially by a voltage VDD
important to have fast transition times. feeding three capacitors in series, namely C1, C2 and the
input capacitance of T3. Since the capacitors are in series
At frequencies below 500 kHz the circuit in Fig.15 is often their equivalent capacitance will be low and so the RC time
used. Above 500 kHz the use of the DS0026 instead of the constant of the charging circuit will be low. C1 is made low
4049 is recommended. The DS0026 has a high current to make the turn on time very fast.
sinking and sourcing capability of 2.5 A. It is a National
Semiconductor device and is capable of charging a Vdd
capacitance of 100 pF in as short a time as 25 ns.
T1
15 V
C2
R1 C1
T3
R2
ZD1
T2 ZD2
Fig.17 A drive circuit with reduced effective input

4049 capacitance and prolonged reverse bias at turn off.
0V The voltage across C2 will then settle down to
Fig.15 A MOSFET drive circuit using a hex CMOS (VDD - VZD1) R2/(R1 + R2). Therefore the inclusion of
buffered inverter IC resistors R1 and R2 means that C2 can be made larger
than C1 and still have a large voltage across it before the
turn off of T3. Thus C2 can sustain a reverse voltage across
In Fig.16 the value of capacitor C1 is made approximately
the gate source of T3 for the whole of the turn off time. The
equal to the input capacitance of the driven MOSFET. Thus
initial discharging current will be given by Equation 3,
the RC time constant for the charging circuit is
R2.(VDD − VZD1 )
approximately halved. The disadvantage of this VZD1 + (R1 + R2)
arrangement is that a drive voltage of 30V instead of 15V I= 3
is needed because of the potential divider action of C1 and RSTRAY + RDS(ON)T2
the input capacitance of the driven MOSFET. A small value
Making VDD large will make turn on and turn off times very
of C1 would be ideal for a fast turn on time and a large value
small.
of C1 would produce a fast turn off. The circuit in Fig.17
replaces C1 by two capacitors and enables fast turn on and Fast switching speeds can be achieved with the push pull
fast turn off. circuit of Fig.19. A further improvement can be made by
replacing the bipolar devices by MOSFETs as shown in
Fig.20. The positions of the P and N channel MOSFETs
may be interchanged and connected in the alternative
arrangement of Fig.21. However it is likely that one
C1 = 2 nF MOSFET will turn on faster than the other turns off and so
the circuit in Fig.21 may cause a current spike during the
30 V switching interval. The peak to average current rating of
MOSFETs is excellent so this current spike is not usually
0V
a problem. In the circuit of Fig.20 the input capacitance of
the driven MOSFET is charged up to VDD - VT, where VT is
Fig.16 A simple drive circuit with reduced effective
the threshold voltage, at which point the MOSFET T1 turns
input capacitance
off. Therefore when T2 turns on there is no current spike.
45
critical switching edge, a normal, fast switching edge is

I
provided by using a circuit similar to those given above. For
A1
the non-critical edge there is a resonant transfer of energy.
Thus drive losses of QG.VGS.f become 0.5.QG.VGS.f.
Constant
Current
Vdd
T1 time T1
A1 = A2
Constant
A2
Voltage
T2
T2 time
Fig.18 A comparison of the switching times for

MOSFETs driven from a constant current source and a Fig.20 A push-pull drive circuit using MOSFETs in the
constant voltage source. common drain connection.
Vdd
T1
Fig.19 A push-pull drive circuit using bipolar transistors T2
There may well be some advantages in charging the input

capacitance of the MOSFET from a constant current source
rather than a constant voltage source. For a given drain Fig.21 A push-pull drive circuit using MOSFETs in the
source voltage a fixed amount of charge has to be common source connection
transferred to the input capacitance of a MOSFET to turn
it on. As illustrated in Fig.18 this charge can be transferred (2) It is usual to provide overdrive of the gate source voltage.
more quickly with a constant current of magnitude equal to This means charging the input capacitance to a voltage
the peak current from a constant voltage source. which is more than sufficient to turn the MOSFET fully on.
A few other points are worthy of note when discussing very This has advantages in achieving lower on-resistance and
fast drive circuits. increasing noise immunity. The gate power requirements
are however increased when overdrive is applied. It may
(1) SMPS working in the 1 - 15 MHz range sometimes use well be a good idea therefore to drive the gate with only
resonant drive circuits. These SMPS are typically QRC 12 V say instead of 15 V.
(Quasi Resonant Circuits). The resonant drive circuits do
not achieve faster switching by the fact that they are (3) It is recommended that a zener diode be connected
resonant. But by being resonant, they recoup some of the across the gate source terminals of a MOSFET to protect
drive energy and reduce the gate drive power. There are against over voltage. This zener can have a capacitance
two main types of QRC - zero voltage and zero current which is not insignificant compared to the input capacitance
switching circuits. In one of these types, fall times are not of small MOSFETs. The zener can thus affect switching
critical and in the other, rise times are not critical. On the times.
46
Parallel operation These differential resistors (RD) damp down possible

oscillations between reactive components in the device and
in connections around the MOSFETs, with the MOSFETs
Power MOSFETs lend themselves readily to operation in themselves, which have a high gain even up to 200 MHz.
parallel since their positive temperature coefficient of
resistance opposes thermal runaway. Since MOSFETs
Protection against gate-source
have low gate drive power requirements it is not normally
necessary to increase the rating of drive circuit components overvoltages
if more MOSFETs are connected in parallel. It is however It is recommended that zener diodes are connected across
recommended that differential resistors are used in the the gate-source terminals of the MOSFET to protect against
drive circuits as shown in Fig.22. voltage spikes. One zener diode or two back-to-back zener
diodes are necessary dependent on whether the
gate-source is unipolar or bipolar, as shown in Fig.23.
The zener diodes should be connected close to the
Rd Rd
terminals of the MOSFET to reduce the inductance of the
connecting leads. If the inductance of the connecting leads
is too large it can support sufficient voltage to cause an
overvoltage across the gate-source oxide.
In conclusion the low drive power requirement of Philips
PowerMOS make provision of gate drive circuitry a
Fig.22. A drive circuit suitable for successful parallelling
relatively straightforward process as long as the few
of Philips MOSFETs incorporating differential resistors.
guide-lines outlined in this note are heeded.
T1
4011
Fig.23. Zener diodes used to suppress voltage spikes across the gate-source terminals of the MOSFET.
47
1.2.4 Parallel Operation of Power MOSFETs
This section is intended as a guide to the successful increased. The inevitable inductance in the source
parallelling of Power MOSFETs in switching circuits. connection, caused by leads within the package, causes a
negative feedback effect during switching. If the rate of rise
Advantages of operating devices in of current in one parallelled MOSFET is greater than in the
parallel others then the voltage drop across inductances in its drain
and source terminals will be greater. This will oppose the
Increased power handling capability build up of current in this MOSFET and so have a balancing
effect. This balancing effect will be greater if switching
If power requirements exceed those of available devices
speeds are faster. This negative feedback effect reduces
then increased power levels can be achieved by parallelling
the deleterious effect of unequal impedances of drive circuit
devices. The alternative means of meeting the power
connections to parallelled MOSFETs. The faster the
requirements would be to increase the area of die. The
switching speeds then the greater will be the balancing
processing of the larger die would have a lower yield and
effect of the negative feedback. Parallelling devices
so the relative cost of the die would be increased. The larger
enables higher operating frequencies to be achieved than
die may also require a more expensive package.
using multiple die packages. The faster switching speeds
possible by parallelling at the device level promote better
Standardisation current sharing during switching intervals.
Parallelling devices can mean that only one package, say
the TO220 package, needs to be used. This can result in
reduced production costs.
Increased operating frequency Increased power dissipation capability

Packages are commercially available which contain upto
five die connected in parallel. The switching capabilities of
If two devices, each rated for half the total required current,
these packages are typically greater than 10 kVA. The
are parallelled then the sum of their individual power
parasitic inductances of connections to the parallelled dies
dissipation capabilities will be more than the possible power
are different for each die. This means that the current rating
dissipation in a single device rated for the total required
of the package has to be derated at high frequencies to
current. This is especially useful for circuits operating above
allow for unequal current sharing. The voltage rating of the
100 kHz where switching losses predominate.
multiple die package has to be derated for higher switching
speeds. This is because the relatively large inductances of
connections within the package sustain appreciable
voltages during the switching intervals. This means that the 2
voltages at the drain connections to the dice will be 1.9

1.8
appreciably greater than voltages at the terminals of the 1.7
package. By parallelling discrete devices these problems 1.6

1.5
can be overcome. 1.4
Normalised Resistance
1.3
Faster switching speeds are achieved using parallelled 1.2
devices than using a multiple die package. This is because 1.1
switching times are adversely affected by the impedance 1

0.9
of the gate drive circuit. When devices are parallelled these 0.8
impedances are parallelled and so their effect is reduced. 0.7
Hence faster switching times and so reduced switching 0.6

0.5
losses can be achieved. 0.4
0.3
Faster switching speeds improve parallelling. During 0.2
switching intervals one MOSFET may carry more current 0.1
than other MOSFETs in parallel with it. This is caused by 0

-60 -20 20 60 100 140 180
differences in electrical parameters between the parallelled Junction Temperature ( C)
MOSFETs themselves or between their drive circuits. The
Fig.1. A typical graph of on resistance versus
increased power dissipation in the MOSFET which carries
temperature for a Power MOSFET
more current will be minimised if switching speeds are
49
Advantages of power MOSFETs for to be passed through a parallel resonant tank circuit, the
parallel operation voltage sustained by MOSFETs when they are off will be
half sinusoid. A component of the current carried by
MOSFETs will be a charging current for snubber capacitors
Reduced likelihood of thermal runaway which will be sinusoidal so again symmetrical layout will be
If one of the parallelled devices carries more current then important.
the power dissipation in this device will be greater and its
junction temperature will increase. The temperature
coefficient of RDS(ON) for Power MOSFETs is positive as 50
shown in Fig.1. Therefore there will be a rise in RDS(ON) for
the device carrying more current. This mechanism will
40
oppose thermal runaway in parallelled devices and also in
parallelled cells in the device.
30
Current (A)
Low Drive Power Requirements

The low drive power requirements of power MOSFETs 20
mean that many devices can be driven from the same gate
drive that would be used for one MOSFET. 10
Very good tolerance of dynamic

0
unbalance
The peak to average current carrying capability of power
-10
MOSFETs is very good. A device rated at 8A continuous -500 -300 -100 100 300 500
drain current can typically withstand a peak current of about time (ns)
30A. Therefore, for the case of three 8A devices in parallel,
if one of the devices switches on slightly before the others Fig.2. The waveforms of current through two parallelled
no damage will result since it will be able to carry the full BUK453-50A MOSFETs with symmetrical layout.
load current for a short time.
Design points 50
Derating 40
Since there is a spread in on-resistance between devices

from different batches it is necessary to derate the 30
Current (A)
continuous current rating of parallelled devices by about

20%.
20
Layout
There are two aspects to successful parallelling which are 10
static and dynamic balance. Static balance refers to equal

sharing of current between parallelled devices when they 0
have been turned on. Dynamic balance means equal
sharing of current between parallelled transistors during
-10
switching intervals. -500 -300 -100 100 300 500
Unsymmetrical layout of the circuit causes static imbalance. time (ns)

If the connections between individual MOSFETs and the Fig.3. The waveforms of current through two parallelled
rest of the power circuit have different impedances then BUK453-50A MOSFETS with 50 nH connected in the
there will be static imbalance. The connections need to be source connection on one MOSFET.
kept as short as possible to keep their inductance as small
as possible. Symmetrical layout is particularly important in
resonant circuits where MOSFETs carry a sinusoidal Unsymmetrical layout of the gate drive circuitry causes
current e.g. in a voltage fed inverter feeding a series dynamic imbalance. Connections between the gate drive
resonant circuit. In a current fed inverter, where switching circuitry and the MOSFETs need to be kept short and
in the inversion stage causes a rectangular wave of current twisted together to reduce their inductance. Further to this
50
the connections between the gate drive circuit and

parallelled MOSFETs need to be approximately the same
length.
10 Ohm 10 Ohm
Figures 2 and 3 illustrate the effect of unsymmetrical layout 50 Ohm
on the current sharing of two parallelled MOSFETs. The
presence of 50 nH in the source connection of one of the
two parallelled BUK453-50A MOSFETs causes noticeable
imbalance. A square shaped loop of 1 mm diameter wire
and side dimension only 25 mm is sufficient to produce an
inductance of 50 nH.
Fig.4. Differential gate drive resistors
Symmetrical layout becomes more important if more
MOSFETs are parallelled, e.g. if a MOSFET with an RDS(ON)
The suppression of parasitic oscillations between
of 0.7 Ohm was connected in parallel with a MOSFET with
parallelled MOSFETs can also be aided by passing the
an RDS(ON) of 1 Ohm then the MOSFET with the lower RDS(ON)
connections from the gate drive circuit through ferrite
would carry 18% more current that if both MOSFETs had
beads. The effect of these beads below 1 MHz is negligible.
an RDS(ON) of 1 ohm. If the MOSFET with an RDS(ON) of 0.7
The ferrite beads however damp the parasitic oscillations
ohm was connected in parallel with a hundred MOSFETs
which occur at frequencies typically above 100 MHz. An
with RDS(ON) of 1 ohm it would carry 42% more current than
example of parasitic oscillations is shown in Fig.5.
if all the MOSFETs had an RDS(ON) 1 Ohm.
40
Good Thermal Coupling
30
Vds (V)
There should be good thermal coupling between parallelled 20

MOSFETs. This is achieved by mounting parallelled
MOSFETs on the same heatsink or on separate heatsinks 10
which are in good thermal contact with each other.
0
If poor thermal coupling existed between parallelled
15
MOSFETs and the positive temperature coefficient of
Vgs (V)
resistance was relied on to promote static balance, then the 10

total current carried by the MOSFETs would be less than
with good thermal coupling. Some MOSFETs would also 5
have relatively high junction temperatures and so their
reliability would be reduced. The temperature coefficient of 0
0 400 800 1200 1600 2000
MOSFETs is not large enough to make poor thermal time (ns)
coupling tolerable.
Fig.5. Parasitic oscillations on the voltage waveforms of
a MOSFET
The Suppression of Parasitic Oscillations If separate drive circuits with closely decoupled power
supplies are used for each parallelled device then parasitic
Parasitic oscillations can occur. MOSFETs have transition
oscillations will be prevented. This condition could be
frequencies typically in excess of 200 MHz and parasitic
satisfied by driving each parallelled MOSFET from 3 buffers
reactances are present both in the MOSFET package and
in a CMOS Hex buffer ic.
circuit connections, so the necessary feedback conditions
for parasitic oscillations exist. These oscillations typically To take this one stage further, separate push pull transistor
occur at frequencies above 100 MHz so a high bandwidth drivers could be used for each MOSFET. (A separate base
oscilloscope is necessary to investigate them. The resistor is needed for each push-pull driver to avoid a
likelihood of these parasitic oscillations occurring is very MOSFET with a low threshold voltage clamping the drive
much reduced if small differential resistors are connected voltage to all the push pull drivers). This arrangement also
in the leads to each parallelled MOSFET. A common gate has the advantage that the drive circuits can be positioned
drive resistor of between 10 and 100 Ohms with differential very close to the terminals of each MOSFET. The
resistors of about 10 Ohm are recommended as shown in impedance of connections from the drive circuits to the
Fig.4. MOSFETs will be minimised and so there will be a reduced
51
likelihood of spurious turn on. Spurious turn on can occur is connected to the output of the rectification stage. The
when there is a fast change in the drain to source voltage. other connection of each choke is connected to a group of
The charging current for the gate drain capacitance inherent three MOSFETs. This means that if one MOSFET switches
in the MOSFET structure can cause a voltage drop across on before the others it will carry a current less than its peak
the gate drive impedance large enough to turn the MOSFET pulse value even when many MOSFETs are parallelled.
on. The gate drive impedance needs to be kept as low as
possible to reduce the likelihood of spurious turn on. The parallel operation of MOSFETs in the
Resonant power supplies linear mode
If a resonant circuit is used then there will be reduced The problems of parallelling MOSFETs which are being
interference and switching losses. The reduced used in the linear mode are listed below.
interference is achieved because sinusoidal waveforms are (a) The parallelled devices have different threshold
present in resonant circuits rather than rectangular voltages and transconductances. This leads to poor
waveforms. Rectangular waveforms have large high sharing.
frequency harmonic components.
(b) MOSFETs have a positive temperature coefficient of
MOSFETs are able to switch at a zero crossing of either
gain at low values of gate to source voltage. This can lead
the voltage or the current waveform and so switching losses
to thermal runaway.
are ideally zero. For example, in the case of a current fed
inverter feeding a parallel resonant load switching can take The imbalance caused by differences in threshold voltage
place at a zero crossing of voltage so switching losses are and transconductance can be reduced by connecting
negligible. In this case the sinusoidal drain source voltage resistors (RS) in the source connections. These resistors
sustained by MOSFETs reduces the likelihood of spurious are in the gate drive circuit and so provide negative
dv/dt turn on. This is because the peak charging current for feedback. The negative feedback reduces the effect of
the internal gate to drain capacitance of the MOSFET is different values of VT and gm. The effective
reduced. transconductance gm of the MOSFET is given in
Equation 1.
The current fed approach
1
Switch mode power supplies using the current fed topology gm = 1
Rs + g
1
have a d.c. link which contains a choke to smooth the m
current in the link. Thus a high impedance supply is
presented to the inversion stage. Switching in the inversion RS must be large compared to 1/gm to reduce the effects of
stage causes a rectangular wave of current to be passed differences in gm. Values of 1/gm typically vary between 0.1
through the load. The current fed approach has many and 1.0 Ohm. Therefore values of RS between 1 ohm and
advantages for switch mode power supplies. It causes 10 ohm are recommended.
reduced stress on devices caused by the slow reverse
Differential heating usually has a detrimental effect on
recovery time of the parasitic diode inherent in the structure
sharing and so good thermal coupling is advisable.
of MOSFETs.
The current fed approach can also reduce problems caused
Conclusions
by dynamic imbalance. If more than three MOSFETs are
parallelled then it is advantageous to use more than one Power MOSFETs can successfully be parallelled to realise
choke in the d.c. link rather than wind a single choke out of higher power handling capability if a few guidelines are
thicker gauge wire. One of the connections to each choke followed.
52
1.2.5 Series Operation of Power MOSFETs
The need for high voltage switches can be well illustrated (eg device can survive some overvoltage transients), but
by considering the following examples. In flyback a 1000 V device cannot block voltages in excess of
converters the leakage inductance of an isolating 1000 V.
transformer can cause a large voltage spike across the
Secondly, series operation allows flexibility as regards
switch when it switches off. If high voltage MOSFETs are
on-resistance and so conduction losses.
used the snubber components can be reduced in size and
in some cases dispensed with altogether. The following are problems that have to be overcome for
successful operation of MOSFETs in series. If one device
For industrial equipment operation from a supply of 415 V,
turns off before another it may be asked to block a voltage
550 V or 660 V is required. Rectification of these supply
greater than its breakdown voltage. This will cause a
voltages produces d.c. rails of approximately 550 V, 700 V
reduction in the lifetime of the MOSFET. Also there is a
and 800 V. The need for high voltage switches in these
requirement for twice as many isolated gate drive circuits
cases is clear.
in many circuits.
Resonant topologies are being increasingly used in
The low drive power requirements of Philips PowerMOS
switching circuits. These circuits have advantages of
mean that the provision of more isolated gate drive circuits
reduced RFI and reduced switching losses. To reduce the
is made easier. Resonant circuits can have advantages in
size of magnetic components and capacitors the switching
reducing the problems encountered if one MOSFET turns
frequency of power supplies is increased. RFI and switching
off before another. The current fed full bridge inverter is one
losses become more important at high frequencies so
such circuit.
resonant topologies are more attractive. Resonant circuits
have the disadvantage that the ratio of peak to average To illustrate how devices can be operated in series, a
voltage can be large. For example a Parallel Resonant current fed full bridge inverter is described where the peak
Power Supply for a microwave oven operating off a 240 V voltage requirement is greater than 1200 V.
supply can be designed most easily using a switch with a
voltage rating of over 1000 V. The current fed inverter
In high frequency induction heating power supplies A circuit diagram of the full bridge current fed inverter is
capacitors are used to resonate the heating coil. The use shown in Fig.1. A choke in the d.c. link smooths the link
of high voltage switches in the inversion bridge can result current. Switching in the inversion bridge causes a
in better utilisation of the kVAr capability of these capacitors. rectangular wave of current to be passed through the load.
This is advantageous since capacitors rated at tens of kVAr The load is a parallel resonant tank circuit. Since the Q of
above 100 kHz are very expensive. the tank circuit is relatively high the voltage across the load
is a sinewave. MOSFETs sustain a half sinusoid of voltage
In most TV deflection and monitor circuits peak voltages of when they are off. Thus series operation of MOSFETs is
up to 1300 V have to be sustained by the switch during the made easier because if one MOSFET turns off before
flyback period. This high voltage is necessary to reset the another it only has to sustain a small voltage. To achieve
current in the horizontal deflection coil. If the EHT flashes the best sharing, the gate drive to MOSFETs connected in
over, the switch will have to sustain a higher voltage so series should be as similar as possible. In particular the
1500 V devices are typically required. zero crossings should be synchronised. The MOSFET drive
The Philips range of PowerMOS includes devices rated at circuit shown in Fig.2 has been found to be excellent in this
voltages up to 1000 V to cater for these requirements. respect. For current fed resonant circuits in which the duty
However in circuits, particularly in resonant applications cycle varies over large ranges the circuit in Fig.3 will perform
where voltages higher than this are required, it may be well. A short pulse applied to the primary of the pulse
necessary to operate devices in series. transformer is sufficient to turn MOSFET M4 on. This short
pulse can be achieved by designing the pulse transformer
Series operation can be attractive for the following reasons:
so that it saturates during the time that M1 is on. The gate
Firstly, the voltage rating of a PowerMOS transistor source capacitance of M4 will remain charged until M2 is
cannot be exceeded. A limited amount of energy can be turned on. M3 will then be turned on and the gate source
absorbed by a device specified with a ruggedness rating capacitance of M4 will be discharged and so
53
Semiconductor
Fuse
Hall Effect
Current Sense
LEG 1
Drive
LEG 2
Circuit
Crowbar
Circuit
120 uH
2.2 nF
LEG 4 LEG 3
Fig.1. Circuit diagram of the full bridge current-fed inverter feeding a parallel resonant load.
M4 is turned off. Thus this circuit overcomes problems of Capacitors are shown connected across the drain source
resetting the flux in the core of the pulse transformer for terminals of MOSFETs. The value of the capacitor across
large duty cycles. the drain to source of each MOSFET is 6.6 nF. (Six 10 nF
polypropylene capacitors, type 2222 376 92103.) This
Each leg of the inverter consists of two MOSFETs, type
gives a peak voltage rating of about 850 V at 150 kHz for
BUK456-800B, connected in series. The ideal rating of the
the capacitor combination across each MOSFET. (This
two switches in each leg is therefore 1600 V and 3.5 A. The
voltage rating takes into account that the capacitors will only
inverter is fed into a parallel resonant circuit with values of
have to sustain voltage when the MOSFET is off). The
L = 120 µH (Q = 24 at 150 kHz) and C = 2.2 nF.
function of these capacitors is twofold. Firstly they suppress
spikes caused by switching off current in parasitic lead
15 V
inductance. Secondly they improve the sharing of voltage
33 Ohm between the MOSFETs connected in series. These
T1
capacitors are effectively in parallel with the tank circuit
capacitor. However only half of the capacitors across
MOSFETs are in circuit at any one time. This is because
33 Ohm half of the capacitors are shorted out by MOSFETs which
33 Ohm
have been turned on. The resonant frequency of the tank
circuit and drain source capacitors is given by Equation 1.
0.68 uF
1
f=
FX3434
1
2π√
tot
30 turns secondary
T2
15 turns primary
L.C
0V
Where Ctot is the equivalent capacitance of the tank circuit
capacitor and the drain source capacitors and is given by
Fig.2. The MOSFET drive circuit.
Equation 2.
54
Ctot = Ct + CDS 2 spike in the MOSFET at turn on. These losses are
appreciable at 150 kHz, e.g. the connection of 1 nF across
Therefore the resonant frequency of the tank circuit is a MOSFET switching 600 V would cause losses of more
155 kHz. than 25 W at 150 kHz. In the current fed inverter described
in this article the MOSFETs turn on when the voltage across
An expression for the impedance at resonance of the
the capacitor is ideally zero. Thus there is no need for a
parallel resonant circuit (ZD) is given in Equation 3.
series resistor and the turn on losses are ideally zero.
L
ZD = 3 In this case the supply to the inverter was 470 V rms. This
Ctot .R means that the peak voltage in the d.c. link was 650 V.
The Q of the circuit is given by Equation 4. Equating the power flowing in the d.c. link to the power
dissipated in the tank circuit produces an expression for the

√
1 L peak voltage across the tank circuit (VT) as given in
Q= . 4 Equation 6.
R Ctot
Substituting Equation 3.
VT = 2 × √
 2 ×1.11 × Vdclink 6

√
L Therefore the peak to peak voltage across the tank circuit
ZD = Q. 5 was ideally 2050 V
Ctot
The voltage across each MOSFET should be 512 V.
Thus ZD for the parallel resonant load was 2.7 kOhms.
In a conventional rectangular switching circuit the
Circuit performance
connection of capacitors across MOSFETs will cause The switching frequency of this circuit is 120 kHz. Thus the
additional losses. These losses are caused because when load is fed slightly below its resonant frequency. This means
a MOSFET turns on, the energy stored in the drain source that the load looks inductive and ensures that the MOSFETs
capacitance is dissipated in the MOSFET and in a series do not switch on when the capacitors connected across
resistor. This series resistor is necessary to limit the current their drain source terminals are charged.
15 V
33 Ohm
M1
33 Ohm
33 Ohm
0.68 uF
M3 M4
M2
0V
Fig.3. Drive circuit with good performance over widely varying duty cycles.
55
The waveforms of the voltage across two MOSFETs in

series in a leg of the inversion bridge are shown in Fig.4. It 640
can be seen that the sharing is excellent. The peak voltage
560
across each MOSFET is 600 V. This is higher than 512 V
because of ringing between parasitic lead inductance and 480
Drain-Source Voltage (V)
the drain source capacitance of MOSFETs when they

switch off. 400
The MOSFETs carry two components of current. The first 320

component is the d.c. link current. The second component 240
is a fraction of the circulating current of the tank circuit. The
size of the second component is dependent on the relative 160
sizes of the drain source capacitance connected across
MOSFETs and the tank circuit capacitor. 80
In this circuit the peak value of charging current for drain 0

0 13 26 39 52 65 78 91 104 117 130
source capacitors, which is carried by the MOSFET, is 4 A. time (us)
The on-resistance of the BUK456-800B is about 5 Ohms
Fig.4. The drain-source voltage waveforms for two
at 80 ˚C. This explains the rise in VDS(ON) of about 20 V seen
MOSFETs connected in series in a leg of the inversion
in Fig.4 just above the turn off of the MOSFETs.
bridge.
The sharing of Philips PowerMOS in this configuration is
can be used as the ’capacitance per MOSFET’ in higher
so good that the value of drain source capacitance is not
power circuits where it becomes necessary to use
determined by its beneficial effect on sharing. Therefore,
MOSFETs connected in parallel. A value of between 5 and
the value can be selected solely on the need to control
10 nF is probably sufficient given a sensible layout.
ringing which in turn is dependent on power output and
layout. (The increased current level associated with
Conclusions
increased power output makes the ringing worse).
It has been shown that MOSFETs can be connected in
In any given configuration there is a maximum output power series to realise a switch that is as high as 90% of the sum
that single MOSFETs can handle and there will be a value of the voltage sustaining capabilities of the individual
of drain source capacitance associated with it. This value transistors.
56
1.2.6 Logic Level FETS
Standard Power MOSFETs require a gate-source voltage a 10 V gate-drive results in a reduced RDS(ON) (see Fig.2)
of 10 V to be fully ON. With Logic Level FETs (L2FETs) but the turn-off delay time is increased. This is due to
however, the same level of conduction is possible with a excessive charging of the L2FET’s input capacitance.
gate-source voltage of only 5 V. They can, therefore, be
driven directly from 5 V TTL/CMOS ICs without the need
for the level shifting stages required for standard
MOSFETs, see Fig.1. This makes them ideal for today’s
sophisticated electrical systems, where microprocessors
are used to drive switching circuits.
VDD
+10 V
Standard
MOSFET
input
Fig.2 RDS(ON) as a function of VGS for a standard
TTL / CMOS BUK453-100B MOSFET and a BUK553-100B L2FET. Tj
Standard MOSFET drive = 25 ˚C; VGS = 10 V
VDD
+5 V
Capacitances, Transconductance and
Gate Charge
Figure 3 shows the parasitic capacitances areas of a typical
L 2 FET
input Power MOSFET cell. Both the gate-source capacitance
Cgs and the gate-drain capacitance Cgd increase due to the
TTL / CMOS reduction in gate oxide thickness, although the increase
in Cgd is only significant at low values of VDS, when the
depletion layer is narrow. Increases of the order of 25% in
2
L FET drive input capacitance Ciss, output capacitance Coss and reverse
transfer capacitance Crss result for the L2FET, compared
Fig.1 Drive circuit for a standard MOSFET and an with a similar standard type, at VDS = 0 V. However at the
L2FET standard measurement condition of VDS = 25 V the
differences are virtually negligible.
This characteristic of L2FETs is achieved by reducing the
gate oxide thickness from - 800 Angstroms to - 500
Forward transconductance gfs is a function of the oxide
Angstroms, which reduces the threshold voltage of the
thickness so the gfs of an L2FET is typically 40% - 50%
device from the standard 2.1-4.0 V to 1.0-2.0 V. However
higher than a standard MOSFET. This increase in gfs more
the result is a reduction in gate-source voltage ratings,
than offsets the increase in capacitance of an L2FET, so
from ±30 V for a standard MOSFET to ±15 V for the L2FET.
the turn on charge requirement of the L2FET is lower than
The ±15 V rating is an improvement over the ’industry
the standard type see Fig.4. For example, the standard
standard’ of ±10 V, and permits Philips L2FETs to be used
BUK453-100B MOSFET requires about 17 nC to be fully
in demanding applications such as automotive.
switched on (at a gate voltage of 10 V) while the
Although a 5 V gate-drive is ideal for L2FETs, they can be BUK553-100B L2FET only needs about 12 nC (at a gate
used in circuits with gate-drive voltages of up to 10 V. Using source voltage of 5 V).
57
Fig.3 Parasitic capacitances of a typical Power

MOSFET cell
Fig.5 Comparison of (a) gate-source voltage and (b)

drain-source voltage waveforms during turn-on of a
standard BUK453-100B MOSFET and a BUK553-100B
L2FET. VGS is 5 V, ID is 3 A and VDD is 30 V.
Fig.4 Turn-on gate charge curves of a standard Fast switching in many applications, for example
BUK453-100B and a BUK553-100B L2FET. VDD = 20 V; automotive circuits, is not important. In areas where it is
ID = 12 A important however the drive conditions should be
examined. For example, for a given drive power, a 10 V
drive with a 50 Ω source impedance is equivalent to a 5 V
Switching speed. drive with a source impedance of only 12 Ω. This results in
faster switching for the L2FET compared with standard
Figure 5 compares the turn-on performance of the standard MOSFETs.
BUK453-100B MOSFET and the BUK553-100B L2FET,
under identical drive conditions of 5 V from a 50 Ω Ruggedness and reliability
generator using identical loads. Thanks to its lower gate
threshold voltage VGST, the L2FET can be seen to turn on MOSFETs are frequently required to be able to withstand
in a much shorter time from the low level drive. the energy of an unclamped inductive load turn-off. Since
this energy is dissipated in the bulk of the silicon, stress
Figure 6 shows the turn-off performance of the standard is avoided in the gate oxide. This means that the
BUK453-100B MOSFET and the BUK553-100B L2FET, ruggedness performance of L2FETs is comparable with
again with the same drive. This time the L2FET is slower that of standard MOSFETs. The use of thinner gate oxide
to switch. The turn-off times are determined mainly by the in no way compromises reliability. Good control of key
time required for Cgd to discharge. The Cgd is higher for the process parameters such as pinhole density, mobile ion
L2FET at low VDS, and the lower value of VGST leads to a content, interface state density ensures good oxide quality.
lower discharging current. The net result is an increase The projected MTBF is 2070 years at 90˚C, at a 60%
in turn off time. confidence level.
58
The VGS rating of an L2FET is about half that of a standard

MOSFET, but this does not affect the VDS rating. In principle,
an L2FET version of any standard MOSFET is feasible.
Temperature stability
In general threshold voltage decreases with increasing
temperature. Although the threshold voltage of L2FETs is
lower than that of standard MOSFETs, so is their
temperature coefficient of threshold voltage (about half in
fact), so their temperature stability compares favourably
with standard MOSFETs. Philips low voltage L2FETs
(≤200v) in TO220 all feature Tjmax of 175˚C, rather than
the industry standard of 150˚C.
Applications
The Philips Components range of rugged Logic Level
MOSFETs enable cost effective drive circuit design
without compromising ruggedness or reliability. Since they
enable power loads to be driven directly from ICs they may
be considered to be the first step towards intelligent power
switching. Thanks to their good reliability and 175˚C Tjmax
temperature rating, they are displacing mechanical relays
in automotive body electrical functions and are being
designed in to such safety critical areas as ABS.
Fig.6 Comparison of (a) gate-source voltage and (b)

drain-source voltage waveforms during turn-off of a
standard BUK453-100B MOSFET and a BUK553-100B
L2FET. VGS is 5 V, ID is 3 A and VDD is 30 V.
59
1.2.7 Avalanche Ruggedness
Recent advances in power MOS processing technology device), the peak electric field, located at the p-n junction,
now enables power MOS transistors to dissipate energy rises to the critical value (approx. 200 kV / cm ) at which
while operating in the avalanche mode. This feature results avalanche multiplication commences.
in transistors able to survive in-circuit momentary
overvoltage conditions, presenting circuit designers with Computer modelling has shown that the maximum electric
increased flexibility when choosing device voltage grade field occurs at the corners of the P diffusions. The
against required safety margins. electron-hole plasma generated by the avalanche process
This paper considers the avalanche characteristics of in these regions gives rise to a source of electrons, which
’rugged’ power MOSFETs and presents results from are swept across the drain, and a source of holes, which
investigations into the physical constraints which ultimately flow through the P- and P regions towards the source metal
limit avalanche energy dissipation in the VDMOS structure. contact.
Results suggest that the maximum sustainable energy is a
function of the applied power density waveform,
Polysilicon Gate
independent of device voltage grade and chip size.
The ability of a rugged device to operate reliably in a circuit N+ N+
subject to extreme interference is also demonstrated.
Source Contact Metal
P- P-
Introduction. Source
P
Parasitic
Susceptibility to secondary breakdown is a phenomenon
which limits the power handling capability of a bipolar Bipolar
transistor to below its full potential. For a power MOSFET, Transistor

Drain
power handling capability is a simple function of thermal
resistance and operating temperature since the device is N- Layer
not vulnerable to a second breakdown mechanism. The

previous statement holds true provided the device is
operated at or below its breakdown voltage rating (BVDSS)
and not subject to overvoltage. Should the transistor be
forced into avalanche by a voltage surge the structure of N+ Substrate
the device permits possible activation of a parasitic bipolar

transistor which may then suffer the consequences of Fig. 1 Cross section of a typical Power MOS cell.
second breakdown. In the past this mechanism was typical
of failure in circuits where the device became exposed to
overvoltage. To reduce the risk of device failure during
Clearly the P- region constitutes a resistance which will give
momentary overloads improvements have been introduced
rise to a potential drop beneath the n+. If this resistance is
to the Power MOS design which enable it to dissipate
too large the p-n junction may become forward biased for
energy while operating in the avalanche condition. The term
relatively low avalanche currents.
commonly used to describe this ability is ’Ruggedness’,
however before discussing in further detail the merits of a
rugged Power MOSFET it is worth considering the failure Also if the manufacturing process does not yield a uniform
mechanism of non-rugged devices. cell structure across the device or if defects are present in
the silicon then multiplication may be a local event within
Failure mechanism of a non-rugged Power the crystal. This would give rise to a high avalanche current
density flowing beneath the source n+ and cause a
MOS. relatively large potential drop sufficient to forward bias the
A power MOS transistor is made up of many thousands of p-n junction and hence activate the parasitic npn bipolar
cells, identical in structure. The cross section of a typical transistor inherent in the MOSFET structure. Due to the
cell is shown in Fig. 1. When in the off-state or operating in positive temperature coefficient associated with a forward
saturation, voltage is supported across the p-n junction as biased p-n junction, current crowding will rapidly ensue with
shown by the shaded region. If the device is subjected to the likely result of second breakdown and eventual device
over-voltage (greater than the avalanche value of the destruction.
61
In order that a power MOS transistor may survive transitory Circuit operation:-
excursions into avalanche it is necessary to manufacture a
device with uniform cell structure, free from defects A pulse is applied to the gate such that the transistor turns
throughout the crystal and that within the cell the resistance on and load current ramps up according to the inductor
beneath the n+ should be kept to a minimum. In this way a value, L and drain supply voltage, VDD. At the end of the
forward biasing potential across the p-n junction is avoided. gate pulse, channel current in the power MOS begins to fall
while voltage on the drain terminal rises rapidly in
Definition of ruggedness. accordance with equation 1.
The term ’Ruggedness’ when applied to a power MOS
transistor, describes the ability of that device to dissipate dv d 2I
=L 2 (1)
energy while operating in the avalanche condition. To test dt dt
ruggedness of a device it is usual to use the method of
unclamped inductive load turn-off using the circuit drawn in The voltage on the drain terminal is clamped by the
Fig. 2. avalanche voltage of the Power MOS for a duration equal
to that necessary for dissipation of all energy stored in the
inductor. Typical waveforms showing drain voltage and
VDD source current for a device undergoing successful test are
+ shown in Fig. 3.
L
VDS The energy stored in the inductor is given by equation 2

where ID is the peak load current at the point of turn-off of
VGS
- the transistor.
-ID/100
0 T.U.T.
WDSS = 0.5LID2 (2)
R 01
RGS All this energy is dissipated by the Power MOS while the
shunt
device is in avalanche.
Provided the supply rail is kept below 50 % of the avalanche

Fig. 2 Unclamped inductive load test circuit for voltage, equation 2 approximates closely to the total energy
ruggedness evaluation. dissipation by the device during turn-off. However a more
exact expression which takes account of additional energy
delivered from the power supply is given by equation 3.
BVDSS
WDSS = 0.5LID2 (3)
BVDSS − VDD
Clearly the energy dissipated is a function of both the

inductor value and the load current ID, the latter being set
by the duration of the gate pulse. The 50 Ohm resistor
between gate and source is necessary to ensure a fast
turn-off such that the device is forced into avalanche.
The performance of a non-rugged device in response to the

avalanche test is shown in Fig. 4. The drain voltage rises
to the avalanche value followed by an immediate collapse
to approximately 30 V. This voltage is typical of the
sustaining voltage during Second Breakdown of a bipolar
transistor, [1]. The subsequent collapse to zero volts after
Fig. 3 Typical waveforms taken from the unclamped
12 µS signifies failure of the device. The transistor shown
inductive load test circuit.
here was only able to dissipate a few micro joules at a very
low current if a failure of this type was to be avoided.
62
Fig. 6 Junction temperature during the power pulse for

Fig. 4 Failure waveforms of a non rugged Power MOS the avalanche ruggedness test on a Philips
transistor. BUK627-500B.
Equation 4 predicts that the junction temperature will pass

through a maximum of 325 ˚C during the test. The
calculation of Zth(t) assumes that the power dissipation is
uniform across the active area of the device. When the
device operates in the avalanche mode the power will be
dissipated more locally in the region of the p-n junction
where the multiplication takes place. Consequently a local
temperature above that predicted by equation 4 is likely to
be present within the device.
Work on bipolar transistors [2] has shown that at a
temperature of the order of 400 ˚C, the voltage supporting
p-n region becomes effectively intrinsic as a result of
thermal multiplication, resulting in a rapid collapse in the
Fig. 5 Power and energy waveforms prior to failure for a terminal voltage. It is probable that a similar mechanism is
typical BUK627-500B responsible for failure of the Power MOS with a local
temperature approaching 400 ˚C resulting in a device short
circuit. A subsequent rapid rise in internal temperature will
result in eventual device destruction.
Characteristics of a rugged Power MOS.
Clearly the rise in Tj is a function of the applied power
waveform which is in turn related to circuit current,
i) The energy limitation of a rugged device
avalanche voltage of the device and duration of the energy
The power waveform for a BUK627-500B (500 V, 0.8 Ohm) pulse. Thus the energy required to bring about device failure
tested at a peak current of 15 A is presented in Fig. 5. will vary as a function of each of these parameters. The
ruggedness of Power MOSFETS of varying crystal size and
The area within the triangle represents the maximum
voltage specification together with dependence on circuit
energy that this particular device type may sustain without
current is considered below.
failure at the above current. Figure 6 shows the junction
temperature variation in response to the power pulse,
calculated from the convolution integral as shown in
ii) Sustainable avalanche energy as a
equation 4. function of current.
τ=t The typical avalanche energy required to cause device
Tj (t) = ⌠ P(t − τ)Zth (τ)dτ (4) failure is plotted as a function of peak current in Fig. 7 for
⌡τ = 0 a BUK553-60A (60 V, 0.085 Ohm Logic Level device). This
result was obtained through destructive device testing
where Zth (τ) = transient thermal impedance. using the circuit of Fig. 2 and a variety of inductor values.
63
The plot shows that the effect of reducing current is to permit

greater energy dissipation during avalanche prior to failure.
This is an expected result since lower currents result in
reduced power dissipation enabling avalanche to be
sustained over a longer period. Temperature plots (Fig. 8)
calculated for the 10 A and 22 A failure points confirm that
the maximum junction temperature reached in each case
is the same despite the different energy values. (N.B. The
critical temperature is again underestimated as previously
stated.)
iii) Effect of crystal size.

To enable a fair comparison of ruggedness between
devices of various chip size it is necessary to normalise the
results. Therefore instead of plotting avalanche energy
against current, avalanche energy density and current
density become more appropriate axes. Figure 9 shows the
Fig. 7 Avalanche energy against current for a typical
avalanche energy density against current density failure
Philips BUK553-60A
locus for two 100 V Philips Power MOS types which are
different only in silicon area. Also shown on this plot are
two competitor devices of different chip areas (BVDSS = 100
V). This result demonstrates two points:
a) the rise in Tj to the critical value for failure is dependent
on the power density dissipated within the device as a
function of time,
b) the sustainable avalanche energy scales proportional to
chip size.
Fig. 8(a) Temperature during avalanche test for a

BUK553-60A; ID = 10 A
KEY: x Philips BUK553-100A (6.25 mm2 chip)

+ Philips BUK555-100A (13 mm2 chip)
Competitor Devices (100 V)
Fig. 9 Avalanche energy density against current density
iv) Dependence on the drain source

breakdown voltage rating.
Fig. 8(b) Temperature during avalanche test for a
Energy density against current density failure loci are
BUK553-60A; ID = 22 A
shown for devices of several different breakdown voltages
in Fig. 10.
64
Ruggedness ratings.
It should be stressed that the avalanche energies presented

in the previous section result in a rise of the junction
temperature far in excess of the device rating and in practice
energies should be kept within the specification.
Ruggedness is specified in data for each device in terms
of an unclamped inductive load test maximum condition;
recommended energy dissipation at a particular current
(usually the rated current of the device).
DEVICE RDSON VDS ID WDSS

TYPE (Ω) (V) (A) (mJ)
BUK552-60A 0.15 60 14 30
KEY: x Philips BUK553-60A BUK552-100A 0.28 100 10 30

+ Philips BUK555-100A BUK553-60A 0.085 60 20 45
Philips BUK627-500B
Fig. 10 Avalanche energy density against current BUK553-100A 0.18 100 13 70
density
Table 1 Ruggedness Ratings
Presented in this form it is difficult to assess the relative
ruggedness of each device since the current density is The ruggedness rating is chosen to protect against a rise
reduced for increasing voltage. If instead of peak current in Tj above the maximum rating. Examples of ruggedness
density, peak power density is used for the x-axis then ratings for a small selection of devices are shown in Table 1.
comparison is made very simple. The data of Fig. 10 has
been replotted in Fig. 11 in the above manner. Represented
in this fashion the ruggedness of each chip appears very WDSS%
similar highlighting that the maximum energy dissipation of 120
a device while in avalanche is dependent only on the power 110
density function. 100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig. 12 Normalised temperature derating curve
KEY: x Philips BUK553-60A

This data is applicable for Tj = 25 C. For higher operating
+ Philips BUK555-100A
temperatures the permissible rise in junction temperature
Philips BUK627-500B
during the energy test is reduced. Consequently
Fig. 11 Avalanche energy density against peak power
ruggedness needs to be derated with increasing operating
density
temperature. A normalised derating curve for devices with
Tj max 175 ˚C is presented in Fig. 12.
65
circuit is shown in Fig. 13(a) together with the profile of the

14 V 20 R
38 W interference spike in Fig. 13(b).
LAMP
SQUARE WAVE
The interference generator produces pulses asynchronous
50 % DUTY CYCLE
to the switching frequency of the Power MOS. Figure 14
100 Hz - 1 kHz
VDS shows the drain voltage and load current response at four
7.5 V instances in the switching cycle. Devices were subjected
0 T.U.T. 14 V DC
SOURCE
TRANSIENT
GENERATOR
to 5000 interference spikes at a frequency of 5 Hz. No
degradation in device performance was recorded.
50 R
Conclusions.
Fig. 13(a) Test circuit The ability of power MOS devices to dissipate energy in the
avalanche mode has been made possible by process
optimisation to remove the possibility of turn-on of the
parasitic bipolar structure. The failure mechanism of a
rugged device is one of excessive junction temperature
initiating a collapse in the terminal voltage as the junction
area becomes intrinsic. The rise in junction temperature is
dictated by the power density dissipation which is a function
of crystal size, breakdown voltage and circuit current.
Ruggedness ratings for Philips PowerMOS are chosen to
ensure that the specified maximum junction temperature of
the device is not exceeded.
References.
Fig. 13(b) Output from transient generator.
1. DUNN and NUTTALL, An investigation of the voltage
sustained by epitaxial bipolar transistors in current
Performance of a rugged Power MOS mode second breakdown. Int.J.Electronics, 1978,
device. vol.45, no.4, 353-372
The ability of a rugged Power MOS transistor to survive 2. DOW and NUTTALL, A study of the current distribution
momentary power surges results in excellent device established in npn epitaxial transistors during current
reliability. The response of a BUK553-60A to interference mode second breakdown. Int.J.Electronics, 1981,
spikes while switching a load is presented below. The test vol.50, no.2, 93-108
t1 = point of turn-on of PowerMOS

t2 = point of turn-off of PowerMOS
Fig. 14 VDS and ID waveforms for the circuit in Fig. 13(a)
66
1.2.8 Electrostatic Discharge (ESD) Considerations
Charge accumulates on insulating bodies and voltages as voltage rating, MOSFETs with a larger die area (i.e. the
high as 20,000 V can be developed by, for example, walking devices with lower on-resistance) are less probe to ESD
across a nylon carpet. Electrically the insulator can be than smaller dice.
represented by many capacitors and resistors connected
To prevent the destruction of MOSFETs through ESD a two
as shown in Fig. 1. The value of the resistors is large and
pronged approach is necessary. Firstly it is important to
as a consequence it is not possible to discharge an insulator
minimise the build up of static electricity. Secondly
by connecting it straight to ground. An ion source is
measures need to be taken to prevent the charging up of
necessary to discharge an insulator.
the input capacitance of MOSFETs by static electric
charges.
Insulator
R11 R12 R(1n-1)
R11 R12 Ct
+ +
+
C11 C12 C13 C1n Vgs

C11 C12 C1n Cgs
- - -
Fig. 1. An electrical representation of a charged

insulator. Fig. 3. A charged insulator inducing charge on the
terminals of a MOSFET.
Since MOSFETs have a very high input impedance,
In the Philips manufacturing facilities many precautions are
typically > 109 Ohms at dc, there is a danger of static
taken to prevent ESD damage and these are summarised
electricity building up on the gate source capacitance of the
below.
MOSFET. This can lead to damage of the thin gate oxide.
There are two ways in which the voltage across the gate Precautions taken to prevent the build up
source terminals of a MOSFET can be increased to its
breakdown voltage by static electricity. of static electricity
1. It is important to ensure that personnel working with
Firstly a charged object can be brought into contact with MOSFETs are aware of the problems and procedures that
the MOSFET terminals or with tracks electrically connected have to be followed. This involves the training of staff.
to the terminals. This is represented electrically by Fig. 2. Areas in which MOSFETs are handled are designated
Secondly charge can be induced onto the terminals of the Special Handling Areas (SHA) and are clearly marked as
MOSFET. Electrically this can be represented by the circuit such. Checks are made every month that anti-static rules
in Fig. 3. are being rigourously implemented.
2. Some materials are more prone to the build up of static
R11 R12 electricity than others (e.g. polyester is worse than cotton).
Therefore it is important to minimise the use of materials
that enhance the likelihood of build up of static electricity.
Materials best avoided are acetate, rayon and polyester.
Vgs The wearing of overclothing made from polycotton with 1%
C11 C12 C1n Cgs stainless steel fibre is one solution. In clean rooms nylon
overalls which have been antistatically treated are worn.
The use of insulating materials is avoided.
Fig. 2. The gate source terminals of a MOSFET 3. Work benches and floors are covered in a static
connected to a charged insulator. dissipative material and connected to a common earth. A
high conductive material is not used since it would create
From Figs. 2 and 3, it can be seen that, as the total area of an electric shock hazard and cause too rapid a discharge
the gate source region increases then the sensitivity of the of charged material. From the point of view of ESD
devices to ESD will decrease. Hence power MOSFETs materials can be classified according to their conductivity
are less prone to ESD than CMOS ICs. Also, for a given as shown below.
67
insulator (>1014 ohm/square) should be in antistatic containers. These containers should

9 14 be totally enclosed to prevent charges being induced onto
antistatic (10 - 10 Ohm/square)
the terminals of devices.
static dissipative (105 - 109 Ohm/square)
2. If MOSFETs have to be left out on the bench, e.g. during
conductor (<105 Ohm/square). a test sequence, they should be in sockets which have the
4. Conducting straps are used to electrically connect gate and source pins electrically connected together.
personnel to the point of common earthing. This prevents
The precautions that should be taken at the customers’
the build up of static charge on staff. The connection is
premises are the same as above. It should be remembered
static dissipative to prevent an electric shock hazard.
that whenever a MOSFET is touched by someone there is
5. Air plays an important part in the build up of static a danger of damage. The precautions should be taken in
electricity. every area in which MOSFETs are tested or handled. In
This is particularly troublesome in a dry atmosphere. addition where devices are soldered into circuits with a
soldering iron an earthed bit should always be used.
Many of the techniques mentioned above are referred to in
BS5783. The probability of device destruction caused by ESD is low
even if only the most rudimentary precautions are taken.
Precautions taken to prevent damage to However without such precautions and with large numbers
MOSFETs by electrostatic build up of of PowerMOS devices now being designed into equipment
a few failures would be inevitable. The adoption of the
charge precautions outlined will mean that ESD will no longer be
1. When MOSFETs are being transported or stored they a problem.
68
1.2.9 Understanding the Data Sheet: PowerMOS
All manufacturers of power MOSFETs provide a data sheet A drain current value (ID) and a figure for total power
for every type produced. The purpose of the data sheet is dissipation are also given in this section. These figures
primarily to give an indication as to the capabilities of a should be treated with caution since they are quoted for
particular product. It is also useful for the purpose of conditions that are rarely attainable in real applications.
selecting device equivalents between different (See limiting values.) For most applications the usable dc
manufacturers. In some cases however data on a number current will be less than the quoted figure in the quick
of parameters may be quoted under subtly different reference data. Typical power dissipations that can be
conditions by different manufacturers, particularly on tolerated by the majority of designers are less than 20 W
second order parameters such as switching times. In (for discrete devices), depending on the heatsinking
addition the information contained within the data sheet arrangement used. The junction temperature (TJ) is usually
does not always appear relevant for the application. Using given as either 150 ˚C or 175 ˚C. It is not recommended
data sheets and selecting device equivalents therefore that the internal device temperature be allowed to exceed
requires caution and an understanding of exactly what the this figure.
data means and how it can be interpreted. Throughout this
chapter the BUK553-100A is used as an example, this Limiting values
device is a 100 V logic level MOSFET.
This table lists the absolute maximum values of six
parameters. The device may be operated right up to these
Information contained in the Philips data maximum levels however they must not be exceeded, to
sheet do so may incur damage to the device.
The data sheet is divided into 8 sections as follows: Drain-source voltage and drain-gate voltage have the same
value. The figure given is the maximum voltage that may
* Quick reference data be applied between the respective terminals. Gate-source
* Limiting values voltage, ±VGS, gives the maximum value that may be
allowed between the gate and source terminals. To exceed
* Thermal resistances this voltage, even for the shortest period can cause
permanent damage to the gate oxide. Two values for the
* Static characteristics
dc drain current, ID, are quoted, one at a mounting base
* Dynamic characteristics temperature of 25 ˚C and one at a mounting base
temperature of 100 ˚C. Again these currents do not
* Reverse diode limiting values and characteristics represent attainable operating levels. These currents are
* Avalanche limiting value the values that will cause the junction temperature to reach
its maximum value when the mounting base is held at the
* Graphical data quoted value. The maximum current rating is therefore a
function of the mounting base temperature and the quoted
The information contained within each of these sections is
figures are just two points on the derating curve ,see Fig.1.
now described.
The third current level quoted is the pulse peak value, IDM.
PowerMOS devices generally speaking have a very high
Quick reference data
peak current handling capability. It is the internal bond wires
This data is presented for the purpose of quick selection. It which connect to the chip that provide the final limitation.
lists what is considered to be the key parameters of the The pulse width for which IDM can be applied depends upon
device such that a designer can decide at a glance whether the thermal considerations (see section on calculating
the device is likely to be the correct one for the application currents.) The total power dissipation, Ptot, and maximum
or not. Five parameters are listed, the two most important junction temperature are also stated as for the quick
are the drain-source voltage VDS and drain-source on-state reference data. The Ptot figure is calculated from the simple
resistance, RDS(ON). VDS is the maximum voltage the device quotient given in equation 1 (see section on safe operating
will support between drain and source terminals in the area). It is quoted for the condition where the mounting base
off-state. RDS(ON) is the maximum on-state resistance at the temperature is maintained at 25 ˚C. As an example, for the
quoted gate voltage, VGS, and a junction temperature of BUK553-100A the Ptot figure is 75 W, dissipating this
25 ˚C. (NB RDS(ON) is temperature dependent, see static amount of power while maintaining the mounting base at
characteristics). It is these two parameters which provide 25 ˚C would be a challenge! For higher mounting base
a first order indication of the devices capability. temperatures the total power that can be dissipated is less.
69
Thermal resistance.
ID% Normalised Current Derating
120 For non-isolated packages two thermal resistance values
110 are given. The value from junction to mounting base (Rthj-mb)
100 indicates how much the junction temperature will be raised
90 above the temperature of the mounting base when
80 dissipating a given power. Eg a BUK553-100A has a Rthj-mb
70 of 2 K/W, dissipating 10 W, the junction temperature will be
60
20 ˚C above the temperature of its mounting base. The
other figure quoted is from junction to ambient. This is a
50
much larger figure and indicates how the junction
40
temperature will rise if the device is NOT mounted on a
30 heatsink but operated in free air. Eg for a BUK553-100A,
20 Rthj-a = 60 K/W, dissipating 1 W while mounted in free air
10 will produce a junction temperature 60 ˚C above the
0 ambient air temperature.
0 20 40 60 80 100 120 140 160 180
Tmb / C For isolated packages, (F-packs) the mounting base (the
Fig.1 Normalised continuous drain current. metal plate upon which the silicon chip is mounted) is fully
ID% = 100 . ID/ID25 ˚C = f(Tmb); conditions: VGS ≥ 5 V encapsulated in plastic. Therefore it is not possible to give
a thermal resistance figure junction to mounting base.
Instead a figure is quoted from junction to heatsink, Rthj-hs,
which assumes the use of heatsink compound. Care should
Obviously if the mounting base temperature was made be taken when comparing thermal resistances of isolated
equal to the max permitted junction temperature, then no and non-isolated types. Consider the following example:
power could be dissipated internally. A derating curve is
given as part of the graphical data, an example is shown in The non-isolated BUK553-100A has a Rthj-mb of 2 K/W. The
Fig.2 for a device with a limiting Tj of 175 ˚C. isolated BUK543-100A has a Rthj-hs of 5 K/W. These devices
have identical crystals but mounted in different packages.
At first glance the non-isolated type might be expected to
offer much higher power (and hence current) handling
PD% Normalised Power Derating capability. However for the BUK553-100A the thermal
120
resistance junction to heatsink has to be calculated, this
110 involves adding the extra thermal resistance between
100 mounting base and heatsink. For most applications some
90 isolation is used, such as a mica washer. The thermal
80 resistance mounting base to heatsink is then of the order
70 2 K/W. The total thermal resistance junction to heatsink is
60 therefore
50 Rthj-hs (non isolated type) = Rthj-mb + Rthmb-hs = 4 K/W
40
30
It can be seen that the real performance difference between
the isolated and non isolated types will not be significant.
20
10
Static Characteristics
0
0 20 40 60 80 100 120 140 160 180 The parameters in this section characterise breakdown
Tmb / C voltage, threshold voltage, leakage currents and
Fig.2 Normalised power dissipation. on-resistance.
PD% = 100 PD/PD 25 ˚C = f(Tmb) A drain-source breakdown voltage is specified as greater
than the limiting value of drain-source voltage. It can be
measured on a curve tracer, with gate terminal shorted to
Storage temperature limits are also quoted, usually the source terminal, it is the voltage at which a drain current
between -40 /-55 ˚C and +150 /+175 ˚C. Both the storage of 250 µA is observed. Gate threshold voltage, VGS(TO),
temperature limits and the junction temperature limit are indicates the voltage required on the gate (with respect to
figures at which extensive reliability work is performed by the source) to bring the device into its conducting state. For
our Quality department. To exceed these figures will cause logic level devices this is usually between 1.0 and 2.0 V
a reduction in long-term reliability. and for standard devices between 2.1 and 4 V.
70
ID / A BUK543-100A ID / A SUB-THRESHOLD CONDUCTION

1E-01
15 Tj / C = 25 150
1E-02
10 2% typ 98 %
1E-03
1E-04
5
1E-05
0 1E-06
0 2 4 6 8 0 0.4 0.8 1.2 1.6 2 2.4
VGS / V VGS / V
Fig.3 Typical transfer characteristics. Fig.5 Sub-threshold drain current.
ID = f(VGS); conditions: VDS = 25 V; parameter Tj ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Useful plots in the graphical data are the typical transfer

characteristics (Fig.3) showing drain current as a function
of VGS and the gate threshold voltage variation with junction ID / A BUK553-100A
temperature (Fig.4). An additional plot also provided is the 10 5
24
sub-threshold conduction, showing how the drain current 7
varies with gate-source voltage below the threshold level VGS / V =
20 4
(Fig.5).
Off-state leakage currents are specified for both the 16
drain-source and gate-source under their respective
maximum voltage conditions. Note, although gate-source 12
leakage current is specified in nano-amps, values are
typically of the order of a few pico-amps. 8 3
VGS(TO) / V 4
2
0
max. 0 2 4 6 8 10
2
VDS / V
Fig.6 Typical output characteristics, Tj = 25 ˚C.
typ. ID = f(VDS); parameter VGS
min.
1 The drain-source on-resistance is very important. It is
specified at a gate-source voltage of 5 V for logic level FETs
and 10 V for a standard device. The on-resistance for a
standard MOSFET cannot be reduced significantly by
increasing the gate source voltage above 10 V. Reducing
the gate voltage will however increase the on-resistance.
0
-60 -20 20 60 100 140 180 For the logic level FET, the on-resistance is given for a gate
Tj / C voltage of 5 V, a further reduction is possible however at
gate voltages up to 10 V, this is demonstrated by the output
Fig.4 Gate threshold voltage.
characteristics, Fig.6 and on-resistance characteristics,
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.7 for a BUK553-100A. .
71
The on-resistance is a temperature sensitive parameter, MOSFET refers to the flat portion of the output
between 25 ˚C and 150 ˚C it approximately doubles in characteristics.) Fig.9 shows how gfs varies as a function of
value. A plot of normalised RDS(ON) versus temperature the drain current for a BUK553-100A.
(Fig.8) is included in each data sheet. Since the MOSFET
will normally operate at a Tj higher than 25 ˚C, when making gfs / S BUK543-100A
estimates of power dissipation in the MOSFET, it is 10
important to take into account the higher RDS(ON). 9
8
RDS(ON) / Ohm BUK553-100A 7
0.5
6
VGS / V =
2.5 3 3.5 4 5
0.4
4.5 4
5
3
0.3
2
10 1
0.2
0
0 2 4 6 8 10 12 14 16 18 20
0.1 ID / A
Fig.9 Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
0
0 4 8 12 16 20 24 28
ID / A
C / pF BUK5y3-100
Fig.7 Typical on-state resistance, Tj = 25 ˚C. 10000
RDS(ON) = f(ID); parameter VGS
a Normalised RDS(ON) = f(Tj)

2.4 1000
2.2 Ciss
2.0
1.8
Coss
1.6 100
Crss
1.4
1.2
1.0
0.8 10
0 20 40
0.6
VDS / V
0.4
Fig.10 Typical capacitances, Ciss, Coss, Crss.
0.2
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
0
-60 -20 20 60 100 140 180
Tj / C Capacitances are specified by most manufacturers, usually
in terms of input, output and feedback capacitance. The
Fig.8 Normalised drain-source on-state resistance.
values quoted are for a drain-source voltage of 25 V.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 6.5 A; VGS = 5 V
However this is only part of the story as the MOSFET
capacitances are strongly voltage dependent, increasing
Dynamic Characteristics as drain-source voltage is reduced. Fig.10 shows how these
capacitances vary with voltage. The usefulness of the
These include transconductance, capacitance and capacitance figures is limited. The input capacitance value
switching times. Forward transconductance, gfs, is gives only a rough indication of the charging required by
essentially the gain parameter which indicates the change the drive circuit. Perhaps more useful is the gate charge
in drain current that will result from a fluctuation in gate information an example of which is shown in Fig.11. This
voltage when the device is saturated. (NB saturation of a plot shows how much charge has to be input to the gate to
72
reach a particular gate-source voltage. Eg. to charge a semiconductor however would only be 6.25 V during the
BUK553-100A to VGS = 5 V, starting from a drain-source turn-on period! The switching speed is therefore ultimately
voltage of 80 V, requires 12.4 nc. The speed at which this limited by package inductance.
charge is to be applied will give the gate circuit current
requirements. More information on MOSFET capacitance Reverse diode limiting values and
is given in chapter 1.2.2. characteristics
Resistive load switching times are also quoted by most The reverse diode is inherent in the vertical structure of the
manufacturers, however extreme care should be taken power MOSFET. In some circuits this diode is required to
when making comparisons between different perform a useful function. For this reason the characteristics
manufacturers data. The speed at which a power MOSFET of the diode are specified. The forward currents permissible
can be switched is essentially limited only by circuit and in the diode are specified as ’continuous reverse drain
package inductances. The actual speed in a circuit is current’ and ’pulsed reverse drain current’. The forward
determined by how fast the internal capacitances of the voltage drop of the diode is also provided together with a
MOSFET are charged and discharged by the drive circuit. plot of the diode characteristic, Fig.12. The switching
The switching times are therefore extremely dependent on capability of the diode is given in terms of the reverse
the circuit conditions employed; a low gate drive resistance recovery parameters, trr and Qrr.
will provide for faster switching and vice-versa. The Philips
data sheet presents the switching times for all PowerMOS
IF / A BUK553-100A
with a resistor between gate and source of 50 Ω. The device 30
is switched from a pulse generator with a source impedance
also of 50 Ω. The overall impedance of the gate drive circuit
is therefore 25 Ω.
20
VGS / V BUK553-100
12
Tj / C = 150 25
10
VDS / V =20 10
8 80
6 0
0 1 2
4 VSDS / V
Fig.12 Typical reverse diode current.
2 IF = f(VSDS); conditions: VGS = ) V; parameter Tj
Because the diode operates as a bipolar device it is subject

0
0 2 4 6 8 10 12 14 16 18 20 to charge storage effects. This charge must be removed for
QG / nC the diode to turn-off. The amount of charge stored is given
Fig.11 Typical turn-on gate-charge characteristics. by Qrr, the reverse recovery charge, the time taken to extract
VGS = f(QG); conditions: ID = 13 A; parameter VDS the charge is given by trr, the reverse recovery time. NB. trr
depends very much on the -dIf/dt in the circuit, trr is specified
in data at 100 A/µs.
Also presented under dynamic characteristics are the
typical inductances of the package. These inductances
become important when very high switching speeds are Avalanche limiting value
employed such that large dI/dt values exist in the circuit. This parameter is an indication as to the ruggedness of the
Eg. turning-on 30 A within 60 ns gives a dI/dt of 0.5 A/ns. product in terms of its ability to handle a transient
The typical inductance of the source lead is 7.5 nH, from overvoltage, ie the voltage exceeds the drain-source
V = -L*dI/dt the potential drop from the source bond pad voltage limiting value and causes the device to operate in
(point where the source bond wire connects to the chip an avalanche condition. The ruggedness is specified in
internally) to the bottom of the source lead would be 3.75 V. terms of a drain-source non-repetitive unclamped inductive
Normally a standard device will be driven with a gate-source turn-off energy at a mounting base temperature of 25 ˚C.
voltage of 10 V applied across the gate and source This energy level must be derated at higher mounting base
terminals, the actual voltage gate to source on the temperatures as shown in Fig.13. NB. this rating is
73
non-repetitive which means the circuit should not be

designed to force the PowerMOS repeatedly into ID / A BUK553-100
avalanche. This rating is only to permit the device to survive 100
A tp =
if exceptional circuit conditions arise such that a transient ID 10 us
S/
overvoltage occurs. VD B
N)=
S(
O 100 us
The new generation of Philips Medium Voltage MOSFETs
RD
also feature a repetitive ruggedness rating. This rating is 10
specified in terms of a drain-source repetitive unclamped 1 ms
inductive turn-off energy at a mounting base temperature
of 25 ˚C, and indicates that the devices are able to withstand
repeated momentary excursions into avalanche 10 ms
DC 100 ms
breakdown provided the maximum junction temperature is 1
not exceeded. (A more detailed explanation of Ruggedness
is given in chapter 1.2.7.)
WDSS%
120 0.1
110 1 10 100
100 VDS / V
90 Fig.14 Safe operating area. Tmb = 25 ˚C
80 ID & IDM = f(VDS); IDM single pulse; parameter tp
70
60
The dc curve is based upon the thermal resistance junction
50
to mounting base (junction to heatsink in the case of isolated
40
packages), which is substituted into equation 1. The curves
30
for pulsed operation assume a single shot pulse and instead
20 of thermal resistance, a value for transient thermal
10 impedance is used. Transient thermal impedance is
0 supplied as graphical data for each type, an example is
20 40 60 80 100 120 140 160 180
shown in Fig.15. For calculation of the single shot power
Tmb / C
dissipation capability, a value at the required pulse width is
Fig.13. Normalised avalanche energy rating. read from the D = 0 curve and substituted in to equation 2.
WDSS% = f(Tmb); conditions: ID = 13 A (A more detailed explanation of transient thermal
impedance and how to use the curves can be found in
Safe Operating Area chapter 7.)
A plot of the safe operating area is presented for every
T jmax − Tmb
PowerMOS type. Unlike bipolar transistors a PowerMOS Ptot (dc) = 1
exhibits no second breakdown mechanism. The safe Rthj − mb
operating area is therefore simply defined from the power
dissipation that will cause the junction temperature to reach
T jmax − Tmb
the maximum permitted value. Ptot (pulse) = 2
Zthj − mb
Fig.14 shows the SOA for a BUK553-100. The area is
bounded by the limiting drain source voltage, limiting
current values and a set of constant power curves for Examples of how to calculate the maximum power
various pulse durations. The plots in data are all for a dissipation for a 1 ms pulse are shown below. Example 1
mounting base temperature of 25 ˚C. The constant power calculates the maximum power assuming a Tj of 175 ˚C and
curves therefore represent the power that raises the Tmb of 25 ˚C. This power equates to the 1 ms curve on the
junction temperature by an amount Tjmax - Tmb, ie. 150 ˚C SOA plot of Fig.14. Example 2 illustrates how the power
for a device with a limiting Tj of 175 ˚C and 125 ˚C for a capability is reduced if Tmb is greater than 25 ˚C.
device with a limiting Tj of 150 ˚C. . Clearly in most
applications the mounting base temperature will be higher Example 1: 1 ms pulse at 25 ˚C for a BUK553-100A
than 25 ˚C, the SOA would therefore need to be reduced.
The maximum power curves are calculated very simply. Zth = 0.32 K/W, Tjmax = 175 ˚C, Tmb = 25 ˚C
74
Zth j-mb / (K/W) BUKx53-lv  T jmax − Tmb 2

1E+01 ID (@Tmb ) =   4
 Rthj − mb ⋅ RDS(ON)(@T jmax ) 
D=
1E+00 0.5
To calculate a more realistic current it is necessary to
replace Tjmax in equation 4 with the desired operating
0.2
junction temperature and Tmb with a realistic working value.
0.1
It is generally recommended that devices are not operated
1E-01 0.05
continuously at Tjmax. For reasons of long term reliability,
0.02
125 ˚C is a more suitable junction operating temperature.
tp
A value of Tmb between 75 ˚C and 110 ˚C is also a more
1E-02 PD tp D=
0 T typical figure.
t As an example a BUK553-100A is quoted as having a dc

T
1E-03 current rating of 13 A. Assuming a Tmb of 100 ˚C and
1E-07 1E-05 1E-03 1E-01 1E+01 operating Tj of 125 ˚C the device current is calculated as
t/s
follows:
Fig.15 Transient thermal impedance.
Zthj-mb = f(t); parameter D = tp/T From Fig.8
RDS(ON)(@ 125o C) = 1.75 ⋅ RDS(ON)(@ 25o C) = 1.75 ⋅ 0.18 = 0.315 Ω

175 − 25
Pmax(1 ms pulse) = = 469 W
0.32 Rthj-mb = 2 K/W, using equation 4
The 469 W line is observed on Fig.13, (4.69 A @ 100 V and 1
15.6 A @ 30 V etc)  25  2
ID =  = 6.3 A
Example 2: 1 ms pulse at 75 ˚C for a BUK553-100A  2 ⋅ 0.315 
Zth = 0.32 K/W, Tjmax = 175 ˚C, Tmb = 75 ˚C The device could therefore conduct 6.3 A under these
175 − 75 conditions which equates to a 12.5 W power dissipation.
Pmax(1 ms pulse) = = 312 W
0.32
Conclusions
Therefore with a mounting base temperature of 75 ˚C the
maximum permissible power dissipation is reduced by one The most important information presented in the data sheet
third compared with the 25 ˚C value on the SOA plot. is the on-resistance and the maximum voltage
drain-source. Current values and maximum power
Calculating Currents dissipation values should be viewed carefully since they
are only achievable if the mounting base temperature is
The current ratings quoted in the data sheet are derived
held to 25 ˚C. Switching times are applicable only for the
directly from the maximum power dissipation.
specific conditions described in the data sheet, when
ID (@Tmb )2 ⋅ RDS(ON)(@T jmax ) = Ptot 3 making comparisons between devices from different
manufacturers, particular attention should be paid to these
substituting for Ptot from equation 1 conditions.
75
High Voltage Bipolar Transistor
77
1.3.1 Introduction To High Voltage Bipolar Transistors
This section introduces the high voltage bipolar transistor

and discusses its construction and technology. Specific
transistor properties will be analysed in more detail in nickel-plated
copper lead
subsequent sections and in Chapter 2, section 2.1.2. frame
Basic Characteristics passivated

chip
High voltage transistors are almost exclusively used as
electronic switches. Therefore, the characteristics of these
devices are given for the on state, the off state and the
transition between the two i.e. turn-on and turn-off.
The relative importance of the VCES and VCEO ratings usually
aluminium ultrasonic
depends on the application. In a half bridge converter, for wires wire bonds
instance, the rated VCEO is the dominant factor, whilst in a
forward converter VCES is important. Which rating is most
applicable may also depend on whether a slow rise network
or snubber is applied (see section 1.3.3). tinned copper
leads
The saturation properties in the on state and the switching
times are given at a specific collector current called the
collector saturation current, ICsat. It is this current which is
normally considered to be the practical working current of Base Collector Emitter
the device. If this device is used at higher currents the total Fig. 1 Cut-away View of a High Voltage Transistor
dissipation may be too high, while at low currents the
storage time is long. At ICsat the best compromise is present prime importance in the determination of the characteristics
for the total spread of products. The value of the base of the device. Below the n- region is an extra n+ layer,
current used to specify the saturation and switching needed for a good electrical contact to the heatsink.
properties of the device is called IBsat which is also an
important design parameter. As the device requirements
base emitter
can differ per application a universal IBsat cannot be quoted.
Device Construction n+ special glass n+

p
A drawing of a high voltage transistor, in this case a fully
isolated SOT186 F-pack, is shown in Fig. 1 with the plastic 250V
encapsulation stripped away. This figure shows the three n- n- 600V
leads, two of which are connected with wires to the
850V
transistor chip. The third lead makes contact with the
mounting base on which the crystal is soldered, enabling 1150V
good thermal contact with a heatsink. It is the transistor n+
package which basically determines the thermal properties
of the device. The electrical properties are mainly Fig. 2 Cross-section of a High Voltage Transistor
determined by the design of the chip inside.
Above the collector is the base p layer, and the emitter n+
A cross-section of a transistor chip is given in Fig. 2. Here layer with their respective metallic contacts on top. It is
the transistor structure can be recognised with the emitter important to realise that the characteristics of the device
and the base contacts at the top surface and the collector are determined by the active area, this is the area
connected to the mounting base. The thickest part in the underneath the emitter where the collector current flows
drawing is the collector n- region across which the high and the high voltage can be developed. The active area of
voltage will be supported in the off state. This layer is of two devices with the same chip size may not be the same.
79
N+ N+ N+
P P P
N-
N-
N-
N+
N+
N+
BU2508A BUT11 TIP49

1500 V 850 V 450 V
Fig. 3 Maximum Voltages vs. n- Collector Thickness
In addition to the basic collector-base-emitter structure concentration gradients. Another disadvantage of epitaxial
manufacturers have to add electrical contacts, and special processing is cost: back diffused wafers are much cheaper
measures are needed at the edges of the crystal to sustain than equivalent high voltage epitaxial wafers.
the design voltage. This introduces another very important
feature, the high voltage passivation. The function of the The process technology used to create the edge
passivation, (the example shown here is referred to as glass passivation is also diverse. The expression "planar" is used
passivation), is to ensure that the breakdown voltage of the to indicate the passivation technique which is most
device is determined by the collector-base structure and commonly used in semiconductors. This involves the
not by the construction at the edges. If no special diffusion of additional n-type rings around the active area
passivation was used the breakdown voltage might be as of the device which give an even electric field distribution
low as 50% of the maximum value. Manufacturers optimise at the edge. However, for high voltage bipolar transistors
the high voltage passivation and much work has also been planar passivation is relatively new and the long term
done to ensure that its properties do not change in time. reliability has yet to be completely optimised. For high
voltage bipolar transistors the most common passivation
Process Technology systems employ a deep trough etched, or cut, into the
There are several ways to make the above structure. The device with a special glass coating. Like the planar
starting material can be an n- wafer where first an n+ passivation, the glass passivation ensures an even
diffusion is made in the back, followed by the base (p) and distribution of the electric field around the active area.
emitter (n+) diffusions. This is the well known triple diffused
process.
Another way is to start with an n+ wafer onto which an n- Maximum Voltage and Characteristics
layer is deposited using epitaxial growth techniques. A
further two diffusions (base and emitter) forms the basic
Width of n- layer (um)
transistor structure. This is called a double diffused hFEsat hFE0 30 60 120 tf ts
epitaxial process.
10 50 0.8 6
Another little used technology is to grow, epitaxially, the
base p-type layer onto an n-/n+ wafer and then diffuse an
(us)
n+ emitter. This is referred to as a single diffused epi-base ts, tf
transistor.
5 25 0.4 3
The question often asked is which is the best technology
for high voltage bipolar transistors ? The basic difference
hFE
in the technologies is the concentration profile at the n-/n+
junction. For epitaxial wafers the concentration gradient is
much more steeper from n- to n+ than it is for back diffused 2.5 15 0.2 1.5
wafers. There are more applications where a smoother
concentration gradient gives the better performance. 200 400 800
Vceo (V)
Manufacturers utilising epitaxial techniques tend to use
Fig. 4 Switching Times and hFE vs. VCEO
buffer layers between the n- and n+ to give smoother
80
High voltage and low voltage transistors differ primarily in all these systems, is that a current flows through an inductor,
the thickness and resistivity of the n- layer. As the thickness thus storing energy in its core. When the current is
and resistivity of this layer is increased, the breakdown interrupted by turning off the power switch, the energy must
voltage goes up. The difference over the range of Philips be transferred one way or another. Very often the energy
high voltage transistors of different voltages is illustrated in is converted into an electrical output e.g. in switched mode
Fig. 3. The TIP49 has a VCBO = 450 V, the BUT11 has a power supplies and battery chargers.
VCES = 850 V, while the BU2508A can be used up to
voltages of 1500 V. Two special applications are electronic fluorescent lamp
ballasts and horizontal deflection of the electron beam in
The penalty for increasing the n- layer is a decrease in high
TV’s and monitors. In the ballast, an ac voltage is generated
current hFE and an in switching times. The graph in Fig. 4
to deliver energy to a fluorescent lamp. In the TV and
points this out by giving both switching times and hFE as a
monitor a sawtooth current in the deflection coil sweeps the
function of the breakdown voltage. The values given should
beam across the screen from left to right and back again in
be used as a guide to illustrate the effect. The effect can
a much shorter blanking, or flyback, period
be compensated for by having a bigger chip.
Other ways to transfer the energy are ac and dc motor
Applications of High Voltage Transistors control where the output is delivered as movement, or
High voltage transistors are mainly used as the power induction heating where the output is delivered in the form
switch in energy conversion systems. What is common to of heat.
81
1.3.2 Effects of Base Drive on Switching Times
Introduction Not only is there an excess charge in the base near the
emitter junction but the injection and base width ensure that
The switching processes that take place within a high this excess charge is also present at the collector junction.
voltage transistor are quite different from those in a small Applying a load in series with the collector and a dc supply
signal transistor. This section describes, figuratively, what between load and emitter will trigger some sort of collector
happens within high voltage transistors under various base current, IC. The level of IC is dependent on the base current,
drive conditions. After an analysis of the charges that are IB, the load and supply voltage. For a certain IB, low voltage
present in a high voltage transistor, the switch-off process supply and high impedance load there will be a small IC. As
is described. Then comparisons are made of switching for the supply voltage rises and/or the load impedance falls so
various forward and reverse base drive conditions. A IC will rise. As IC rises so the collector-emitter voltage, VCE,
fundamental knowledge of basic semiconductor physics is falls. The IC is composed mainly of the excess emitter
assumed. electrons that reach the base-collector junction (BC). This
electron concentration will continue into the collector
inducing an excess charge in the collector, Qc.
Charge distribution within a transistor The concentration of electrons decreases only slightly from
the emitter-base junction to some way into the collector. In
An off-state transistor has no excess charge, but to enable
effect, the base width extends into the collector. Decreasing
transistor conduction in the on-state excess charge build
VCE below VBE causes the BC junction to become forward
up within the device takes place. There are three distinct
biased throughout. This creates a path for electrons from
charge distributions to consider that control the current
the collector to be driven back into the base and out of the
through the device, see Fig. 1. These charge distributions
base contact. This electron flow is in direct opposition to
are influenced by the level of collector-emitter bias, VCE,
the established IC. With no change in base drive, the
and collector current, IC, as shown in Fig. 2.
ultimate effect is a reduction in IC. This is the classical
‘saturation’ region of transistor operation. As VCE falls so
Forward biasing the base-emitter (BE) junction causes a
the BC forward bias increases leading to an excess of
depletion layer to form across the junction. As the bias
electrons at the depletion layer edge in the collector
exceeds the potential energy barrier (work function) for that
beneath the base contact. This concentration of electrons
junction, current will flow. Electrons will flow out of the
leads to an excess charge, Qd.
emitter into the base and out of the base contact. For high
voltage transistors the level of BE bias is much in excess The charge flows and excess charges Qb, Qc and Qd are
of the forward bias for a small signal transistor. The bias shown in Fig. 1. An example of the excess charge
generates free electron-hole pairs in the base-emitter distributions for fixed IC and IB are shown in Fig. 2.
leading to a concentration of electrons in the base in excess
of the residual hole concentration. This produces an excess
Q Ic = 5 A
charge in the base, Qb, concentrated underneath the Qd
emitter. Ib = 1 A
B E B
N+ Qc
P
Qb
Qb
Qd Qc Vce (V)
N-
Fig. 2. On-state Charge Distribution (example)
N+ The switching process of a transistor

C Removing the bias voltage, VBE, will cause the electron-hole
pairs to recombine and the excess charge regions to
Fig. 1. On-state Charge Flow
disappear. Allowing this to happen just by removing VBE
83
takes a long time so usually turn-off is assisted in some

way. It is common practice to apply a negative bias
(typically 5V) to the base, via a resistor and/or inductor, B E B
inducing a negative current that draws the charge out of
N+
the transistor. In the sequence that follows, four phases of
P
turn-off can be distinguished (see Fig. 3). Qb
1. First the applied negative bias tries to force a negative Qd Qc

bias across the BC junction. The BC electron flow now N-
stops and the charge Qd dissipates as the bias now causes
the base holes out through the base contact and the
N+
collector electrons back into the bulk collector. When the
BC was forward biased this current had the effect of C
reducing the total collector current, so now the negative VBE
can cause the total collector current to increase (this also
depends on the load). Although the base has been switched B E B
off the load current is maintained by the stored charge
N+
effects; this is called the transistor storage time, ts.
P
Qb
During this stage the applied negative bias appears as a

positive VBE at the device terminals as the internal charge
Qc
distributions create an effective battery voltage. Depleting N-
the charge, of course, lowers this effective battery voltage.
N+
2. The next phase produces a reduction in both Qb, Qc
and, consequently, IC. The BC junction is no longer forward C
biased and Qd has dissipated to provide the negative base
current. The inductance in series in the base path requires
a continuation in the base current. The injection of electrons B E B
into the base opposes the established electron flow from
N+
emitter to collector via the base. At first the opposing
P
electron flows cancel at the edge of the emitter nearest the
base contacts. This reduces both Qb and Qc in this region. Qb 0
Qb and Qc become concentrated in the centre of the emitter
Qc 0
area. The decrease in IC is called the fall time, tf. N-
3. Now there is an extra resistance to the negative base

N+
current as the electrons flow through the base under the
emitter area. This increase in resistance limits the increase C
in amplitude of the negative base current. As Qb and Qc
reduce further so the resistance increases and the negative
base current reaches its maximum value. B E B
N+
As Qb and Qc tend to zero the series inductance ensures P
that negative base current must be continued by other
means. The actual mechanism is by avalanche breakdown
of the base-emitter junction. This now induces a negative
VBE which is larger than the bias resulting in a reverse in N-
polarity of the voltage across the inductance. This in turn Qr
triggers a positive rate of change in base current. The
N+
negative base current now quickly rises to zero while the
base-emitter junction is in avalanche breakdown. C
Avalanche breakdown ceases when the base current tends
Fig. 3. Phases during turn-off
to zero and the VBE becomes equal to the bias voltage.
84
4. If a very small series base inductor is used with the 5V conditions, a satisfactory value for VCEsat is obtained,
reverse bias then the base current will have a very fast rate indicated by N in Fig. 5, and moderate values for Qc and
of change. This will speed up the phases 1 to 3 and, Qd result.
therefore, the switching times of the transistor. However,
there is a point when reducing the inductor further
introduces another phase to the turn-off process. High Q
reverse base currents will draw the charges out closest to Qd
the base contact and leave a residual charge trapped deep
in the collector regions furthest away from the base. This
charge, Qr, must be removed before the transistor returns
fully to the off-state. This is detected as a tail to IC at the
end of turn-off with a corresponding tail to the base current
as it tends to zero. Qc
The switching waveforms for a BUT11 in a forward
converter are given in Fig. 4 where the four phases can
easily be recognised. (Because of the small base coil used Qb
both phases in the fall time appear clearly!).
1 - Removal of Qd until t ≈ 0.7 µs ts 0.2 0.5 1.0 Vce (V)
2 - Qc and Qb decrease until t ≈ 1.7 µs ts
O N D
3 - Removal of Qb and Qc until t ≈ 1.75 µs tf
Fig. 5. Charges as a function of VCE
4 - Removal of Qr until t ≈ 1.85 µs tf
Note the course of VBE: first the decrease in voltage due to With the transistor operating in the active region, for
the base resistance during current contraction and second VCE ≥ 1V, there will be a charge Qc but no charge Qd. This
(because a base coil has been used) the value of VBE is is indicated by D in Fig. 5. At the other extreme, with the
clamped by the emitter-base breakdown voltage of the transistor operating in the saturation region Qc will be higher
transistor. It should be remembered that because and Qd will be higher than Qc. This is indicated by O in
breakdown takes place near the surface and not in the Fig. 5. In this condition there are more excess electron-hole
active region no harm comes to the transistor. pairs to recombine at switch off.
Increasing IB causes Qb to increase. Also, for a given IC,
1 A/div Ic 200 V/div Qc and Qd will be higher as VCE reduces. Therefore, for a
Vce
given IC, the stored charge in the transistor can be controlled
by the level of IB. If the IB is too low the VCE will be high with
low Qc and zero Qd, as D in Fig. 5. This condition is called
underdrive. If the IB is too high the VCE will be low with high
Qc and Qd, as O in Fig. 5. This condition is called
1 A/div 5 V/div overdrive. The overdrive condition (high forward drive)
gives high stored charge and the underdrive condition (low
Vbe
forward drive) gives low stored charge.
Ib
Deep-hole storage
0.5 us/div
As the high free electron concentration extends into the
Fig. 4. BUT11 waveforms at turn-off base and collector regions ther must be an equivalent hole
concentration. Fig. 6 shows results obtained from a
The influence of forward drive on stored computer model which illustrates charge storage as a
function of VCE. Here the hole density, p(x), is given as a
charge function of depth inside the active area; the doping profile
Fig. 5 shows how, for a transistor in the on-state, at a fixed is also indicated. It can be seen that overdrive, O, causes
value of IC and IB the three charges Qb, Qc and Qd depend holes to be stored deep in the collector at the collector -
upon VCE. The base charge, Qb, is independent of VCE, it substrate junction known as "deep-hole storage", this is the
primarily depends upon VBE. For normal base drive main reason for the increase in residual charge, Qr.
85
During overdrive not only Qd becomes very big but also Breakdown voltage vs. switching times
holes are stored far away from the junction: this thus leads
not only to a longer storage time, but also to a large Qr For a higher breakdown voltage transistor the n- layer (see
resulting in tails in the turn-off current. Fig. 1) will be thicker and of higher resistivity (ie a lower
donor atom concentration). This means that when
comparing identical devices the values for Qd and Qc will
p(x)
be higher, for a given IC, in the device with the higher
20
10 p(x) at J = 140 A / cm2 breakdown voltage.
18
10 In general:
16
10 - the higher BVCEO the larger Qd and Qc will be;
14
10
E - during overdrive Qd is very high and there is a charge
B
C
10
12
located deep in the collector region (deep hole storage);
10
10 Vce = 1 V 0.5 V 0.2 V - when desaturated Qd equals zero and there is no deep
D N O hole storage: Qc is minimised for the IC.
0 20 40 60 80 100 120 140 160 x (um)
Fig. 6. Deep hole storage in the collector region Turn-off conditions

Various ways of turning off a high voltage transistor are
Desaturation networks used but the base should always be switched to a negative
A desaturation network, as shown in Fig. 7, limits the stored supply via an appropriate impedance. If this is not done,
charge in the transistor and, hence, aids switching. The (ie turn-off is attempted by simply interrupting the base
series base diode, D1 means that the applied drive voltage current), very long storage times result and the collector
now has to be VBE plus the VF of D1. The anti-parallel diode, voltage increases, while the collector current falls only
D2 is necessary for the negative IB at turn-off. As VCE slowly. A very high dissipation and thus a short lifetime of
reduces below VBE + VF so the external BC diode, D3, the transistor are the result. The charges must be removed
becomes forward biased. D3 now conducts any further using a negative base current.
increase in drive current away from the base and into the
a) Hard turn-off
collector. Transistor saturation is avoided.
With a desaturation network the charge Qd equals zero and The technique widely used, especially for low voltage
the charge Qc is minimised. When examining the transistors, is to switch directly to a negative voltage, (see
distribution of the charge in the collector region (see Fig. 6) Fig. 8a). In the absence of a negative supply, this can be
it can be seen that deep hole storage does not appear. achieved with an appropriate R-C network (Fig. 8b). Also
Desaturation networks are a common technique for applying an "emitter-drive" (Fig. 8c) with a large base
reducing switching times. capacitor in fact is identical to hard-turn-off.
It should be realised that there is a drawback attached to The main drawback for high voltage transistors is that the
operating out of saturation: increased dissipation during the base charge Qb is removed too quickly, leaving a high
on-state. Base drive design often requires a trade-off residual charge. This leads to current tails (long fall times)
between switching and on-state losses. and high dissipation. It depends upon what state the
transistor is in (overdriven or desaturated), whether this way
of turn-off is best. It also depends upon the kind of transistor
C
that must be switched off. If it is a lower voltage transistor
D3
(BVCEO ≤ 200V) then this will work very well because the
B
D1
charges Qc and Qd will be rather low. For transistors with
a higher breakdown voltage, hard turn-off will yield the
shortest storage time at the cost, however, of higher turn-off
dissipation (longer tf).
E b) Smooth turn-off
D2
To properly turn-off a high voltage transistor a storage time
Fig. 7. Desaturation network
to minimise Qd and Qc is required, and then a large negative
(Baker clamp)
base current to give a short fall time.
86
++
Lc
++ ++
Lc Lc
+V +V R
C
+Ib C
+I
R
-V
(a) (b) (c)

Fig. 8. Hard turn-off
The easiest way to obtain these turn-off requirements is to c) Other ways of turn-off
switch the base to a negative supply via a base coil, see
Of course, other ways of turn-off are applicable but in
Fig. 9.
general these can be reduced to one of the methods
The base coil gives a constant dIB/dt (approx.) during the described above, or something in between. The BVCEO has
storage time. When the fall time begins the negative base a strong influence on the method used: the higher BVCEO
current reaches its maximum and the Lb induces the BE the longer the storage time required to achieve proper
junction into breakdown (see Fig. 4). turn-off. For transistors having a BVCEO of 200V or less hard
turn-off and the use of a base coil yield comparable losses,
An optimum value exists for the base coil: if Lb = 0 we have so hard turn-off works well. For transistors having BVCEO
the hard turn-off condition which is not optimum for standard more than 400V hard turn-off is unacceptable because of
high voltage transistors. If the value of Lb is too high it slows the resulting tails.
the switching process so that the transistor desaturates.
The VCE increases too much during the storage time and ++
so higher losses result (see Fig. 10).
For high voltage transistors in typical applications (f = 15 to

40 kHz, standard base drive, not overdriven, not Lc
desaturated) the following equations give a good indication
for the value of Lb.
(−Vdr + VBEsat )
LB = +Ib
 dIB 
 dt 
dIB
with ≈ 0.5 ⋅ IC (A/µs) for BVCEO = 400V, BVCES = 800V
dt
dIB
and ≈ 0.15 ⋅ IC (A/µs) for BVCEO = 700V, BVCES = 1500V
dt
Using - Vdr = 5V, VBEsat = 1V and transistors having

BVCEO = 400V it follows that:
-Vdr
12
LB = H (IC in Amps) Fig. 9. A base coil to aid turn-off.
IC
87
Ic Vce Ic Ic
Vce
Vce
Lb = 0 Lb = opt Lb > Lb opt
Fig. 10. Variations of Lb on IC and VCE waveforms at turn-off
Turn-off for various forward drive With hard turn-off IB reaches its peak negative value as all
conditions the charge is removed from the base. For continuity this
current must be sourced from elsewhere. It has been shown
Using the BUT11 as an example, turn-off characteristics that the BE junction now avalanches, giving instantaneous
are discussed for optimum drive, underdrive and overdrive continuity followed by a positive dIB/dt. However, for hard
with hard and smooth turn-off. turn-off the current is sourced by the residual collector
a) Optimum drive charge without BE avalanche, see Fig. 12. The small
negative VBE ensures a long tail to IC and IB.
The optimum IB and Lb for a range of IC is given in Fig. 11
for the BUT11. The IB referred to is IBend which is the value b) Underdrive (Desaturated drive)
of IB at the end of the on-state of the applied base drive As has been indicated previously, desaturating, or
signal. In most applications during the on-state the IB will underdriving, a transistor results in less internal charge. Qd
not be constant, hence the term IBend rather than IBon. For will be zero and Qc is low and located near the junction.
optimum drive the level of IBend increases with IC. For smooth
If the application requires such a drive then steps should
turn-off the level of Lb decreases with increasing IC.
be taken to optimise the characteristics. One simple way
of obtaining underdrive is to increase the series base
resistance with smooth turn-off. The same effect can be
achieved with optimum IBend and a base coil having half the
value used for optimum drive, ie hard turn-off. Both
methods give shorter ts and tf. For 400V BVCEO devices (like
the Philips BUT range) such a harder turn-off can lead to
reasonable results.
Fig. 13 compares the use of the optimum base coil with
hard turn-off for an undriven BUT11. For underdrive the
final IC is less and hence the collector charge is less.
Therefore, underdrive and hard turn-off gives less of a tail
than for a higher IBend. Underdrive with smooth turn-off gives
longer ts but reduced losses.
c) Overdrive
When a transistor is severely overdriven the BC charge,
Qd, becomes so large that a considerable tail will result
Fig. 11. IBend and Lb for the BUT11 even with smooth turn-off. In general, deliberately
designing a drive circuit to overdrive a transistor is not done:
Deviations from Fig. 11 will generally lead to higher power it has no real value. However, most circuits do have variable
dissipation. If a short storage time is a must in a certain collector loads which can result in extreme conditions when
application then Lb can be reduced but this will lead to the circuit is required to operate with the transistor in
longer fall times and current tails. overdrive.
88
1 A/div 200 V/div 1 A/div 200 V/div
Ic Vce Ic Vce

Vbe
Vbe
Ib Ib
0.5 us/div 0.5 us/div
1 A/div Ic 200 V/div 1 A/div 200 V/div

Vce
Vce Ic
Ib Vbe
Vbe
Ib
0.5 us/div 0.5 us/div
Fig. 12. Optimum drive with hard turn-off (top) Fig. 14. Overdrive with hard turn-off (top)
and smooth turn-off (bottom) for BUT11 and smooth turn-off (bottom) for BUT11
Fig. 14 compares the use of the optimum base coil with

1 A/div 200 V/div hard turn-off for an overdriven BUT11. For overdrive there
Ic Vce
is more base charge, also the final collector current will be
higher and, hence, there will be more collector charge. The
overdriven transistor is then certain to have longer switching
times as there are more electron-hole pairs in the device
1 A/div
that need to recombine before the off-state is reached.
5 V/div
Vbe
Conclusions
Ib
Two ways of turning off a high voltage transistor, hard
turn-off and the use of a base coil, were examined in three
0.5 us/div conditions of the on-state: optimum drive, overdrive and
underdrive.
1 A/div 200 V/div
Ic
For transistors having BVCEO ~ 400 V the use of a base coil
Vce
yields low losses compared to hard turn-off. As a good
approximation the base coil should have the value:
12
LB = µH
1 A/div 5 V/div IC
Vbe
for optimum drive.
Ib
When using a desaturation circuit the value for Lb can be
halved with acceptable results.
0.5 us/div
Overdrive should be prevented as much as possible
Fig. 13. Underdrive with hard turn-off (top)
because considerable tails in the collector current cause
and smooth turn-off (bottom) for BUT11
unacceptable losses.
89
1.3.3 Using High Voltage Bipolar Transistors
This section looks at some aspects of using high voltage In Fig. 1 the characteristic ‘hump’ which often occurs at
bipolar transistors in switching circuits. It highlights points turn-on in forward converters due to the effect of the
such as switching, both turn-on and turn-off, Safe Operating collector series resistance is observed.
Areas and the need for snubber circuits. Base drive design
The turn-on losses are strongly dependent on the value of
curves for the BUT11, BUW12 and BUW13 are discussed
the leakage inductance and the applied base drive. It is
under ’Application Information’ at the end of this section.
generally advised to apply a high initial +IB for a short time
in order to minimise turn on losses.
Transistor switching: turn-on
A deeper analysis can be found in sections 1.3.2, 2.1.2 and
To make optimum use of today’s high voltage transistors, 2.1.3. Turn on losses are generally low for flyback
one should carefully choose the correct value for both the converters but are the most important factor in forward
positive base current when the transistor is on and the converter types.
negative base current when the device is switched off (see
Application Information section). Turn-off of high voltage transistors
When a transistor is in the off-state, there are no carriers All charge stored in the collector when the transistor is on
in the thick n- collector, effectively there is a resistor with a should be removed again at turn-off. To ensure a quick
relatively high value in the collector. To obtain a low turn-off a negative base current is applied. The time needed
on-state voltage, a base current is applied such that the to remove the base - collector charge is called the storage
collector area is quickly filled with electron - hole pairs time. A short storage time is needed to minimise problems
causing the collector resistance to decrease. In the within the control loop in SMPS and deflection applications.
transition time, the so called turn-on time, the voltage and
current may both be high, especially in forward converters,
and high turn-on losses may result. Initially, all the carriers
in the collector will be delivered via the base contact and,
Ic Vce Ic Ic
Vce
therefore, the base current waveform should have a peak Vce
at the beginning. In this way the carriers quickly fill the
collector area so the voltage is lower and the losses
decrease.
In flyback converters the current to be turned on is normally
-Ib is too high -Ib is optimum -Ib is too low
low, but in forward converters this current is normally high.
The collector current, IC, reaches its on-state value in a short Fig. 2 Effects of -IB on turn-off
time which is normally determined by the leakage
inductance of the transformer. Care is needed to implement the optimum drive. First
overdrive should be prevented by keeping +IB to a minimum.
Overdrive results in current tails and long storage times.
Ic = 1 A/div But, decreasing IB too much results in high on-state losses.
Second, the negative base current should be chosen
carefully. A small negative base current (-IB) will give a long
storage time and a high VCEsat at the end of the storage time,
Ic
while the current is still high. As a consequence, the turn-off
losses will be high. If, however, a large negative base
Vce = 50 V/div current is used, the danger exists that tails will occur in the
collector current, again resulting in high losses. There is
an optimum as shown in Fig. 2.
Vce
A circuit which is worth considering, especially for higher
frequencies, is the Baker Clamp or desaturation circuit.
This circuit prevents saturation of the transistor and, hence,
Fig. 1 Turn-on of a high voltage bipolar transistor
faster switching times are achieved.
91
The total losses depend on the base drive and the collector transistors with VCEOmax = 700V and VCESmax = 1500V need
current. In Fig.3 the total losses are shown for a BUW133 a storage time which is approximately double the value in
as a function of the positive base current, for both the the table.
saturated and the desaturated case. Note that when
A recommended way to control the storage time is by
different conditions are being used the picture will change.
switching the base to a negative voltage rail via a base coil.
The application defines the acceptable storage time which
The leakage inductance of a driver transformer may serve
then determines the base drive requirements.
as an excellent base coil. As a guide, the base coil should
be chosen such that the peak value of the negative base
Etot (uJ) current equals half the value of the collector current.
Forward Converter
700
Ic = 10 A Specific problems and solutions
600
A high voltage transistor needs protection circuits to ensure
500
that the device will survive all the currents and voltages it
will see during its life in an application.
400
Saturated a) Over Current
300
Exceeding current ratings normally does not lead to
200
immediate transistor failure. In the case of a short circuit,
the protection is normally fast enough for problems to be
100 avoided. Most devices are capable of carrying very high
With Baker Clamp currents for short periods of time. High currents will raise
the junction temperature and if Tjmax is exceeded the
1 2 3 4
Ib (A)
reliability of the device may be weakened.
Fig. 3 BUW133 losses versus base drive b) Over Voltage
In contrast with over current, it is NOT allowed to exceed
The total number of variables is too large to give unique the published voltage ratings for VCEO and VCES (or VCBO).
base drive advice for each application. As a first hint the In switching applications it is common for the base - emitter
device data sheets give IC and IB values for VCEsat, VBEsat and junction to be taken into avalanche, this does not harm the
switching. However, it is more important to appreciate the device. For this reason VEBO limits are not given in data.
ways to influence base drive and the consequences of a
Exceeding VCEO and VCES causes high currents to flow in
non-optimised circuit.
very small areas of the device. These currents may cause
For a flyback converter the best value of IBend to start with immediate damage to the device in very short times
is about 2/3 of the IB value given in data for VCEsat and VBEsat. (nanoseconds). So, even for very short times it is not
In this application the forward base current is proportional allowed to have voltages above data for the device.
to the collector current (triangular shaped waveforms) and In reality VCEO and VCES are unlikely to occur in a circuit. If
this IBend value will give low on-state losses and fast VBE = 0V the there will probably still be a path between the
switching. base and the emitter. In fact the situation is VCEX where X
is the impedance of this path. To cover for all values of X,
The best turn-off base current depends on the breakdown
the limit is X=∞, ie VCEO. For all VBE < 0V, ie VCEV, the limit
voltage of the transistor. As a guide, Table 1 gives
case is VBE = 0V, ie VCES.
reasonable values for the target storage time and may be
used to begin optimising the base drive: If voltage transients that exceed the voltage limits are
detected then a snubber circuit may limit the voltage to a
f (kHz) tp (µs) target ts (µs) safe value. If the over voltage states last greater than a
few µs a higher voltage device is required.
25 20 2.0
c) Forward Bias Safe Operating Areas (FBSOA)
150 10 1.5
The FBSOA is valid for positive values of VBE. There is a
100 5 1.0
time limit to VCE - IC operating points beyond which device
Table 1 Target ts for varying frequency and pulse width failure becomes a risk. At certain values of VCE and IC there
is a risk of secondary breakdown; this is likely to lead to the
The above table holds for transistors with a VCEOmax rating immediate failure of the device. The FBSOA curve should
of 400-450V and VCESmax between 850-1000V. Transistors only be considered during drastic change sequences; for
with higher voltages require longer storage times, eg. example, start-up, s/c or o/c load.
92
d) Reverse Bias Safe Operating Area (RBSOA)

Ic
20
The RBSOA is valid for negative values of VBE. During
turn-off with an inductive load the VCE will rise as the IC falls.
For each device type there is a VCE - IC boundary which, if 15
exceeded, will lead to the immediate failure of the device.
BUW13A
To limit the VCE - IC path at turn-off snubber circuits are used,
see Fig. 4. 10
Without Snubber
Vs 5
With Snubber
200 400 600 800 1000

Vce
Fig. 5 BUW13A RBSOA limit

VCE - IC path with and without snubber
The following table may serve as a guide to the value of

Fig. 4 HVT with inductive load and typical snubber dVCE/dt for some switching frequencies
At turn-off, as the VCE rises the diode starts conducting f (kHz) 25 50 100
charging the capacitor. The additional diode current means dVCE/dt 1 2 4
that the total load current does not decrease so fast at (kV/µs)
turn-off. This slower current tail in turn ensures a slower
VCE rise. The slower VCE rise takes the transistor through The snubber resistor should be chosen so that the capacitor
a safer VCE - IC path away from the limit, see Fig. 5. will be discharged in the shortest occurring on-time of the
switch.
As a handy guide, the snubber capacitor in a 20-40 kHz
converter is about 1nF for each 100W of throughput power In some cases the losses in the snubber may be
(this is the power which is being transferred via the considerable. Clever designs exist to feed the energy
transformer). This value may be reduced empirically as stored in the capacitor back into the supply capacitor, but
required. this is beyond the scope of this report.
D3 D1
Lo
D2 Co Vo
R6
L6
Vi
D6
D5
D4 R4
TR1
R5
C5 C4
Fig. 6 Transistor with maximum protection networks in SMPS circuit
93
d) Other protection networks maximum collector current amplitude and shape.

In Fig. 6 a "maximum protection" diagram is shown with The operating frequency is usually between 15 and 50 kHz.
various networks connected. R4, C4, and D4 form the The collector current shape varies from rectangular in a
snubber to limit the rate of rise of VCE. The network with forward converter to sawtooth in a flyback converter.
D5, R5 and C5 forms a "peak detector" to limit the peak
VCE. Examples of base drive and losses are given in Appendix 1
for the BUT11, BUW12 and BUW13. In these figures ICM
The inductor L6 serves to limit the rate of rise of IC which represents the maximum repetitive peak collector current,
may be very high for some transformer designs. The slower which occurs during overload. The information is derived
dIC/dt leads to considerably lower turn-on losses. Added from limit-case transistors at a mounting base temperature
to L6 is a diode D6 and resistor R6, with values chosen so of 100 ˚C under the following conditions (see also Fig. 7):
that L6 loses its energy during the off-time of the power
switch. - collector current shape IC1 / ICM = 0.9
- duty factor (tp / T) = 0.45
While the snubber is present in almost all SMPS circuits - rate of rise of IC during turn-on = 4 A/µs
where transistors are used above VCEOmax, the dIC/dt limiter - rate of rise VCE during turn-off = 1 kV/µs
is only needed when the transformer leakage inductance - reverse drive voltage during turn-off = 5 V
is extremely low. The peak detector is applied in circuits - base current shape IB1 / IBe = 1.5
which have bad coupling between primary and secondary
windings. The required thermal resistance of the heatsink can be
calculated from
Application Information 100 − Tamb
Important design factors of SMPS circuits are the maximum Rth(mb − amb) < K/W
Ptot
power losses, heatsink requirements and base drive
conditions of the switching transistor. The power losses To ensure thermal stability a maximum value of the ambient
are very dependent on the operating frequency, the temperature, Tamb, is assumed: Tamb ≤ 40˚C.
Ic 0.9 Icm
Icm
dIc/dt 0.1 Icm
Ic1
tf
Vce
Vce(t1)
t1 = 0.5 us
Ib1
Ib Ib(end)
ts
Vbe -Vdrive
tp
T
Turn-on Turn-off
Fig. 7 Relevant waveforms of the switching transistor in a forward SMPS.
94
As a base coil is normally advised and a negative drive

Ploss
voltage of -5V is rather common, the value for the base coil,
w.c. (tf) typ. w.c. (sat)
LB, is given for these conditions. For other values of -Vdrive
P0
(-3 to -7 volt) the base coil follows from:
(−Vdrive + 1)
LB = LBnom ⋅
6
P1
Where LBnom is the value given in Appendix 1. P2
-20% Ib adv +20%

It should be noted, that this advice yields acceptable power Ibe
losses for the whole spread in the product. It is not just for Fig. 8 Losses as a function of IBend
typical products as is sometimes thought ! This is
demonstrated in Fig. 8, where limit and typical devices are
compared (worst-case saturation and worst-case Conclusion
switching). To avoid exceeding the RBSOA of an HVT, snubbers are
a requirement for most circuits. To minimise both switching
It appears that the worst-case fall time devices have losses and on-state losses, particular attention should be given to
P0 for IBend = (Ib adv) + 20%, while the saturation the design of the base drive circuit. It is generally advised
worst-case devices have the same losses at (Ib adv) - 20%. that a high initial base current is applied for a short time to
A typical device now has losses P1 at Ib adv, while the minimise turn-on loss. As a guide-line for turn-off, a base
optimum IBend for the typical case might yield losses P2 at coil should be chosen such that the peak value of the
an approximately 15% lower IBend (NB: this is not a rule, it negative base current equals half the value of the collector
is an example). current.
95
Appendix 1 Base Drive Design Graphs
BUT11 Base Drive Design Information
BUW12 Base Drive Design Information
BUW13 Base Drive Design Information
96
1.3.4 Understanding The Data Sheet: High Voltage Transistors
Introduction * SOA: Safe Operating Area both in forward and reverse

biased conditions.
Being one of the most important switching devices in
present day switched mode power supplies and other fast Data sheets are intended to be a means of presenting the
switching applications, the high voltage transistor is a essentials of a device and, at the same time, to give an
component with many aspects that designers do not always overview of the guaranteed specification points. This data
fully understand. In spite of its "age" and the variety of is checked as a final measurement of the device and
papers and publications by manufacturers and users of high customers may wish to use it for their incoming inspection.
voltage transistors, data sheets are somewhat limited in the For this reason the data is such that it can be inspected
information they give. This section deals with the data rather easily in relatively simple test circuits. This
sheets of high voltage transistors and the background to somewhat application unfriendly way of presenting data is
their properties. A more detailed look at the background to unavoidable if cheap devices are a must, and they are !
transistor specifications can be found in chapter 2.1.2. Each of the above mentioned items will now be discussed
in more detail, in some instances parts of the data for a
Fig. 1 shows the cross section of a high voltage transistor.
BUT11 will be used as an example. The BUT11 is intended
The active part of the transistor is highlighted (the area
for 3A applications and has a maximum VCES of 850V.
underneath the emitter) and it is this part of the silicon that
determines the primary properties of the device:
breakdown voltages, hFE, switching times. All the added
Limiting Values / Maximum Ratings
parts can only make these properties worse: a bad There is a significant difference between current and
passivation scheme can yield a much lower collector-base voltage ratings. Exceeding voltage ratings can lead to
breakdown voltage, too thin wires may seriously decrease breakdown phenomena which are possibly destructive
the current capability, a bad die bond (solder layer) leads within fractions of a second. The avalanche effects
to a high thermal resistance leading to poor thermal fatigue normally take place within a very small volume and,
behaviour. therefore, only a little energy can be absorbed. Surge
voltages, that are sometimes allowed for other
bonding wire
components, are out of the question for high voltage
transistors.
glass passivation
There is, however, no reason to have a derating on
N
voltages: using the device up to its full voltage ratings - in
worst case situations - is allowed. The life tests, carried out
P
in Philips quality laboratories, clearly show that no voltage
active area solder degradation takes place and excellent reliability is
N maintained.
From the above, it should be clear that the habit of derating
mounting base = collector
is not a good one. If, in a particular application, the
collector-emitter voltage never exceeds, say 800V, the
Fig. 1 Simplified cross section of an HVT required device should be an 850V device not a 1500V
device. Higher voltage devices not only have lower hFE, but
also slower switching speeds and higher dissipation.
The Data Sheet
The rating for the emitter-base voltage is a special case:
The data sheet of a high voltage transistor can specify - to allow a base coil to be used, the base-emitter diode may
* Limiting Values / Ratings: the maximum allowable be brought into breakdown; in some cases a -IBav is given
currents through and voltages across terminals, as well as to prevent excessive base-emitter dissipation. The only
temperatures that must not be exceeded. effect of long term repetitive base-emitter avalanche
breakdown that has been observed is a slight decrease in
* Characteristics: describing properties in the on and off hFE at very low values of collector current (approximately
state (static) as well as dynamic, both in words and in 10% at ≤ 5mA); at higher currents the effects can be
figures. neglected completely.
97
The maximum value for VCEO is important if no snubber is to a real circuit; in practice, currents and voltages will vary
applied; it sets a firm boundary in applications with a very over the switching cycle. The dynamic performance is
fast rising collector voltage and a normal base drive (see different to the static performance. However, a reasonable
also section on SOA). indication can be obtained from these curves.
Currents above a certain value may be destructive if they Both the transition frequency (fT) and the collector
last long enough: bonding wires fuse due to excessive capacitance (Cc or Cob) are minor parameters relating to the
heating. Therefore, short peak currents are allowed well design and processing technology used.
above the rated ICsat with values up to five times this value
Switching times may be given in circuits with an inductive
being published for ICM. Exceeding the published maximum
or a resistive collector load. See Figs. 2a-b for simplified
temperatures is not immediately destructive, but may
test circuits and Figs. 3a-b for waveforms.
seriously affect the useful life of the device. It is well known,
that the useful life of a semiconductor device doubles for
each 10K decrease in working junction temperature. VCC
Another factor that should be kept in mind is the thermal
fatigue behaviour, which strongly depends on the
die-bonding technology used. Philips high voltage devices
are capable of 10,000 cycles with a temperature rise of 90K RL
without any degradation in performance.
VIM
This kind of consideration leads to the following advice: RB
under worst case conditions the maximum 0 T.U.T.
case-temperature should not exceed 115 ˚C for reliable tp
operation. This advice is valid regardless of the maximum
temperature being specified. Of course, for storage the T
published values remain valid.
The maximum total power dissipation Ptot is an industry
standard, but not very useful, parameter. It is the quotient
Fig. 2a Test circuit for resistive load
of Tjmax - Tmb and Rth(j-mb) (Rth(j-mb) is the thermal resistance
from junction to mounting base and Tmb is assumed to be VCC
25˚C). This implies a rather impractical infinite heatsink,
kept at 25˚C !
Electrical Characteristics LC
Static parameters characterise leakage currents, hFE,
saturation voltages; dynamic parameters and switching
times, but also include transition frequency and collector IBon LB
capacitance.
T.U.T.
To start: ICsat, the collector saturation current, is that value -VBB
of the collector current where both saturation and switching
properties of the devices are specified. ICsat is not a
characteristic that can be measured, but it is used as an
indication of the of the peak working current allowed through Fig. 2b Test circuit for inductive load
a device.
When comparing similar devices from different
In the off-state various leakage currents are specified,
manufacturers one is confronted with a great variety of base
however, these are of little use as they indicate the low level
drive conditions. The positive base current (+IB) may be
of dissipation in the off state. Also a VCEOsust is specified,
the same as the one used in the VCEsat spec. but also lower
usually being equal to the max. VCEO. For switching
values (up to 40% lower) or desaturation networks may be
purposes it is the RBSOA that is important (see next
used, yielding better ts and tf values. The negative base
section).
drive, -IB, may equal +IB or it may be twice this value, yielding
In the on state the saturation voltages VCEsat and, to a lesser a shorter ts, and sometimes it is determined by switching
extent, VBEsat are important. VCEsat is an indication of the the base to a negative voltage, possibly via a base coil.
saturation losses and VBEsat normally influences base drive. Altogether it is quite confusing and when comparing
Sometimes worst case VCEsat is given as a function of both switching times one should be well aware of all the
IC and IB. It is not possible to precisely relate these curves differences!
98
The effect of base drive variations on storage and fall times

ICon is given in Table 2. The reference is the condition that both
90 % 90 %
+IB as well as -IB equals the value for IB given for the VCEsat
specification in the data sheet.
IC
ts tf comments
10 %
+IB = ref. normal normal reference
ts
tf
ton
toff
+IB = 40% less ↓ ↓
IBon Desaturated ↓ ↓
IB
-IB = ref. normal normal reference
10 %
-IB = 2 x +IB ↓ ↓
Directly to -5 V ↓ ↑ with normal
-IBoff base drive!
Fig. 3a Waveforms for Resistive Switching. Directly to -5 V ↓ ↓ if underdriven
ICon Via L to -5 V ↓ ↓
90 %
Table 2 Switching times and base drive variations.
IC The turn-on time is a parameter which only partially

correlates with dissipation as it is usually the behaviour
directly after the turn-on time which appears to be most
significant. Both inductive and resistive load test circuits
are only partially useful, as resistive loads are seldom used
10 % and very often some form of slow-rise network is used with
ts tf t inductive loads. Both circuits provide easy lab.
toff measurements and the results can be guaranteed. The
alternative of testing the devices in a real switched mode
IB IBon
power supply would be too costly!
t Safe Operating Area

The difference between forward bias safe operating area
-IBoff (FBSOA) and reverse bias safe operating area (RBSOA)
Fig. 3b Waveforms for Inductive Switching. is in the device VBE: if VBE > 0V it is FBSOA and if VBE < 0V
it is RBSOA. Chapter 2.1.3 deals with both subjects in more
detail, a few of the main points are covered below.
As an example a BUT11 has been measured at IC = 3A in
a resistive test circuit varying both +IB and -IB. The results FBSOA gives boundaries for dc or pulsed operation. In
in Table 1 show that it is possible to turn a normal transistor switching applications, where the transistor is "on" or "off",
into a super device by simple specmanship! normally the excursion in the IC-VCE plane is fast enough to
allow the designer to use the whole plane, with the
boundaries ICmax and VCEO, as given in the ratings. This is
IC = 3 A ts (µs) tf (ns) useful for snubberless applications and for overload, fault
conditions or at switch-on of the power supply
+IB = 0.6 A; -IB = 0.6 A 2.5 260
(normal case) Fig. 4 gives the FBSOA of the BUT11 with the boundaries
of ICmax, ICMmax and VCEO, all as given in the ratings. There
+IB = 0.36 A; -IB = 0.72 A 1.6 210
is a Ptotmax (1) and ISB boundary (2), that both shift at higher
(underdriven)
levels of IC when shorter pulses are used. Note that in the
+IB = 0.36 A; -VBE = -5 V 0.8 50 upper right hand corner pulse times of 20µs are permitted
(underdriven, hard turn-off) leading to a square switching SOA. For overload, fault
condition or power supply switch-on an extra area is added
Table 1 Switching times and base drive for the BUT11
(area III). All these conditions are for VBE ≥ 0V.
99
the chip at turn-off, damage will occur if the limit is

exceeded. In nearly all cases, the damage will result in the
immediate failure of the device to short circuit.
Emitter switching applications force different mechanisms
for carrier recombination in the device which allow a
‘square’ RBSOA. A typical example is shown in Fig. 5,
where for both base and emitter drive the RBSOA of the
BUT11 is given.
Ic (A)
8
6
Vcesm
5
emitter drive
4
base drive
3
0
200 400 600 800 1000
Vce (V)
Fig. 5 RBSOA of BUT11 for Base and Emitter Drive.
It is striking that for emitter drive the whole IC-VCES plane

may be used so no snubber is necessary, however, a small
snubber may prevent overshoot. The base drive RBSOA
normally depends on base drive conditions, but
unfortunately there is no uniform trend in this behaviour.
Therefore, the RBSOA curve in the data gives the worst
(1) Ptotmax and Ptotpeak max. lines case behaviour of the worst case devices. Other data
(2) Second breakdown limits (independent of sheets may give RBSOA curves that at first sight look better
temperature). than the Philips equivalent, but beware, these curves might
I Region of permissible dc operation. hold for only a limited base drive range.
II Permissible extension for repetitive pulse
operation Summary
III Area of permissible operation during turn-on Voltage limiting values / ratings as given in the data must
in single transistor converters, provided never be exceeded, as they may lead to immediate device
RBE ≤ 100 Ω and tp ≤ 0.6 µs. failure. Surge voltages, as sometimes given for other
IV Repetitive pulse operation in this region is components, are not allowed for high voltage transistors.
permissible provided VBE ≤ 0 V and tp ≤ 5 ms. Current limiting values / ratings are less strict as they are
Fig. 4 Safe Operating Area of BUT11. time-dependent and should be used in conjunction with the
FBSOA.
Area IV is only valid for VBE ≤ 0V, so this is an RBSOA
extension to the SOA curve. This is not the full picture for Static characteristics are useful for comparisons but offer
RBSOA, area IV is only for continuous pulsed operation. little in describing the performance in an application. The
For single cycle and short burst fault conditions see the dynamic characteristics may be defined for a simple test
separate RBSOA curve. circuit but the values give a good indication of the switching
performance in an application.
The RBSOA curve is valid when a negative voltage is
applied to the base-emiiter terminals during turn-off. This RBSOA is, for all switching applications, of prime
curve should be used for fault condition analysis only; importance. Philips give in their data sheets a curve for
continuous operation close to the limit will result in 100’s W worst case devices under worst case conditions. For
of dissipation ! Due to localised current contraction within snubber design a value of 1 nF per 100W of throughput
100
power is advised as a starter value; afterwards, the IC-VCE in relatively simple circuits that may be replicated rather
locus must be checked to see if it stays within the published easily e.g. for incoming inspection.
RBSOA curve.
For characteristics both saturation and switching properties Switching times depend strongly on drive conditions. By
are given at ICsat. Most figures are of limited use as they altering them a normal device can be turned into a super
give static conditions, where in a practical situation device. Beware of specmanship, this may disguise poor
properties are time-dependent. Switching times are given tolerance to variations in base drive.
101
Preface Power Semiconductor Applications
Acknowledgments
We are grateful for all the contributions from our colleagues within Philips and to the Application Laboratories in Eindhoven
and Hamburg.
We would also like to thank Dr.P.H.Mellor of the University of Sheffield for contributing the application note of section 3.1.5.
The authors thank Mrs.R.Hayes for her considerable help in the preparation of this book.
The authors also thank Mr.D.F.Haslam for his assistance in the formatting and printing of the manuscripts.
Contributing Authors
N.Bennett D.J.Harper J.Oosterling

M.Bennion W.Hettersheid N.Pichowicz
D.Brown J.v.d.Hooff W.B.Rosink
C.Buethker J.Houldsworth D.C. de Ruiter
L.Burley M.J.Humphreys D.Sharples
G.M.Fry P.H.Mellor H.Simons
R.P.Gant R.Miller T.Stork
J.Gilliam H.Misdom D.Tebb
D.Grant P.Moody H.Verhees
N.J.Ham S.A.Mulder F.A.Woodworth
C.J.Hammerton E.B.G. Nijhof T.van de Wouw
This book was originally prepared by the Power Semiconductor Applications Laboratory, of the Philips Semiconductors
product division, Hazel Grove:
M.J.Humphreys D.Brown L.Burley

C.J.Hammerton R.Miller
It was revised and updated, in 1994, by:
N.J.Ham C.J.Hammerton D.Sharples

Preface Power Semiconductor Applications
Preface
This book was prepared by the Power Semiconductor Applications Laboratory of the Philips Semiconductors product
division, Hazel Grove. The book is intended as a guide to using power semiconductors both efficiently and reliably in power
conversion applications. It is made up of eight main chapters each of which contains a number of application notes aimed
at making it easier to select and use power semiconductors.
CHAPTER 1 forms an introduction to power semiconductors concentrating particularly on the two major power transistor
technologies, Power MOSFETs and High Voltage Bipolar Transistors.
CHAPTER 2 is devoted to Switched Mode Power Supplies. It begins with a basic description of the most commonly used
topologies and discusses the major issues surrounding the use of power semiconductors including rectifiers. Specific
design examples are given as well as a look at designing the magnetic components. The end of this chapter describes
resonant power supply technology.
CHAPTER 3 describes motion control in terms of ac, dc and stepper motor operation and control. This chapter looks only
at transistor controls, phase control using thyristors and triacs is discussed separately in chapter 6.
CHAPTER 4 looks at television and monitor applications. A description of the operation of horizontal deflection circuits is
given followed by transistor selection guides for both deflection and power supply applications. Deflection and power supply
circuit examples are also given based on circuits designed by the Product Concept and Application Laboratories (Eindhoven).
CHAPTER 5 concentrates on automotive electronics looking in detail at the requirements for the electronic switches taking
into consideration the harsh environment in which they must operate.
CHAPTER 6 reviews thyristor and triac applications from the basics of device technology and operation to the simple design
rules which should be followed to achieve maximum reliability. Specific examples are given in this chapter for a number
of the common applications.
CHAPTER 7 looks at the thermal considerations for power semiconductors in terms of power dissipation and junction
temperature limits. Part of this chapter is devoted to worked examples showing how junction temperatures can be calculated
to ensure the limits are not exceeded. Heatsink requirements and designs are also discussed in the second half of this
chapter.
CHAPTER 8 is an introduction to the use of high voltage bipolar transistors in electronic lighting ballasts. Many of the
possible topologies are described.
Contents Power Semiconductor Applications
Table of Contents
CHAPTER 1 Introduction to Power Semiconductors 1
General 3
1.1.1 An Introduction To Power Devices ............................................................ 5
Power MOSFET 17
1.2.1 PowerMOS Introduction ............................................................................. 19

1.2.2 Understanding Power MOSFET Switching Behaviour ............................... 29
1.2.3 Power MOSFET Drive Circuits .................................................................. 39
1.2.4 Parallel Operation of Power MOSFETs ..................................................... 49
1.2.5 Series Operation of Power MOSFETs ....................................................... 53
1.2.6 Logic Level FETS ...................................................................................... 57
1.2.7 Avalanche Ruggedness ............................................................................. 61
1.2.8 Electrostatic Discharge (ESD) Considerations .......................................... 67
1.2.9 Understanding the Data Sheet: PowerMOS .............................................. 69
High Voltage Bipolar Transistor 77
1.3.1 Introduction To High Voltage Bipolar Transistors ...................................... 79

1.3.2 Effects of Base Drive on Switching Times ................................................. 83
1.3.3 Using High Voltage Bipolar Transistors ..................................................... 91
1.3.4 Understanding The Data Sheet: High Voltage Transistors ....................... 97
CHAPTER 2 Switched Mode Power Supplies 103
Using Power Semiconductors in Switched Mode Topologies 105
2.1.1 An Introduction to Switched Mode Power Supply Topologies ................... 107

2.1.2 The Power Supply Designer’s Guide to High Voltage Transistors ............ 129
2.1.3 Base Circuit Design for High Voltage Bipolar Transistors in Power
Converters ........................................................................................................... 141
2.1.4 Isolated Power Semiconductors for High Frequency Power Supply
Applications ......................................................................................................... 153
Output Rectification 159
2.2.1 Fast Recovery Epitaxial Diodes for use in High Frequency Rectification 161
2.2.2 Schottky Diodes from Philips Semiconductors .......................................... 173
2.2.3 An Introduction to Synchronous Rectifier Circuits using PowerMOS
Transistors ........................................................................................................... 179
i
Design Examples 185
2.3.1 Mains Input 100 W Forward Converter SMPS: MOSFET and Bipolar
Transistor Solutions featuring ETD Cores ........................................................... 187
2.3.2 Flexible, Low Cost, Self-Oscillating Power Supply using an ETD34
Two-Part Coil Former and 3C85 Ferrite .............................................................. 199
Magnetics Design 205
2.4.1 Improved Ferrite Materials and Core Outlines for High Frequency Power
Supplies ............................................................................................................... 207
Resonant Power Supplies 217
2.5.1. An Introduction To Resonant Power Supplies .......................................... 219

2.5.2. Resonant Power Supply Converters - The Solution For Mains Pollution
Problems .............................................................................................................. 225
CHAPTER 3 Motor Control 241
AC Motor Control 243
3.1.1 Noiseless A.C. Motor Control: Introduction to a 20 kHz System ............... 245
3.1.2 The Effect of a MOSFET’s Peak to Average Current Rating on Invertor
Efficiency ............................................................................................................. 251
3.1.3 MOSFETs and FREDFETs for Motor Drive Equipment ............................. 253
3.1.4 A Designers Guide to PowerMOS Devices for Motor Control ................... 259
3.1.5 A 300V, 40A High Frequency Inverter Pole Using Paralleled FREDFET
Modules ............................................................................................................... 273
DC Motor Control 283
3.2.1 Chopper circuits for DC motor control ....................................................... 285

3.2.2 A switched-mode controller for DC motors ................................................ 293
3.2.3 Brushless DC Motor Systems .................................................................... 301
Stepper Motor Control 307
3.3.1 Stepper Motor Control ............................................................................... 309
CHAPTER 4 Televisions and Monitors 317
Power Devices in TV & Monitor Applications (including selection

guides) 319
4.1.1 An Introduction to Horizontal Deflection .................................................... 321

4.1.2 The BU25XXA/D Range of Deflection Transistors .................................... 331
ii
4.1.3 Philips HVT’s for TV & Monitor Applications .............................................. 339

4.1.4 TV and Monitor Damper Diodes ................................................................ 345
TV Deflection Circuit Examples 349
4.2.1 Application Information for the 16 kHz Black Line Picture Tubes .............. 351
4.2.2 32 kHz / 100 Hz Deflection Circuits for the 66FS Black Line Picture Tube 361
SMPS Circuit Examples 377
4.3.1 A 70W Full Performance TV SMPS Using The TDA8380 ......................... 379
4.3.2 A Synchronous 200W SMPS for 16 and 32 kHz TV .................................. 389
Monitor Deflection Circuit Example 397
4.4.1 A Versatile 30 - 64 kHz Autosync Monitor ................................................. 399
CHAPTER 5 Automotive Power Electronics 421
Automotive Motor Control (including selection guides) 423
5.1.1 Automotive Motor Control With Philips MOSFETS .................................... 425
Automotive Lamp Control (including selection guides) 433
5.2.1 Automotive Lamp Control With Philips MOSFETS .................................... 435
The TOPFET 443
5.3.1 An Introduction to the 3 pin TOPFET ......................................................... 445

5.3.2 An Introduction to the 5 pin TOPFET ......................................................... 447
5.3.3 BUK101-50DL - a Microcontroller compatible TOPFET ............................ 449
5.3.4 Protection with 5 pin TOPFETs ................................................................. 451
5.3.5 Driving TOPFETs ....................................................................................... 453
5.3.6 High Side PWM Lamp Dimmer using TOPFET ......................................... 455
5.3.7 Linear Control with TOPFET ...................................................................... 457
5.3.8 PWM Control with TOPFET ....................................................................... 459
5.3.9 Isolated Drive for TOPFET ........................................................................ 461
5.3.10 3 pin and 5 pin TOPFET Leadforms ........................................................ 463
5.3.11 TOPFET Input Voltage ............................................................................ 465
5.3.12 Negative Input and TOPFET ................................................................... 467
5.3.13 Switching Inductive Loads with TOPFET ................................................. 469
5.3.14 Driving DC Motors with TOPFET ............................................................. 471
5.3.15 An Introduction to the High Side TOPFET ............................................... 473
5.3.16 High Side Linear Drive with TOPFET ...................................................... 475
iii
Automotive Ignition 477
5.4.1 An Introduction to Electronic Automotive Ignition ...................................... 479

5.4.2 IGBTs for Automotive Ignition .................................................................... 481
5.4.3 Electronic Switches for Automotive Ignition ............................................... 483
CHAPTER 6 Power Control with Thyristors and Triacs 485
Using Thyristors and Triacs 487
6.1.1 Introduction to Thyristors and Triacs ......................................................... 489

6.1.2 Using Thyristors and Triacs ....................................................................... 497
6.1.3 The Peak Current Handling Capability of Thyristors .................................. 505
6.1.4 Understanding Thyristor and Triac Data .................................................... 509
Thyristor and Triac Applications 521
6.2.1 Triac Control of DC Inductive Loads .......................................................... 523

6.2.2 Domestic Power Control with Triacs and Thyristors .................................. 527
6.2.3 Design of a Time Proportional Temperature Controller ............................. 537
Hi-Com Triacs 547
6.3.1 Understanding Hi-Com Triacs ................................................................... 549

6.3.2 Using Hi-Com Triacs .................................................................................. 551
CHAPTER 7 Thermal Management 553
Thermal Considerations 555
7.1.1 Thermal Considerations for Power Semiconductors ................................. 557

7.1.2 Heat Dissipation ......................................................................................... 567
CHAPTER 8 Lighting 575
Fluorescent Lamp Control 577
8.1.1 Efficient Fluorescent Lighting using Electronic Ballasts ............................. 579

8.1.2 Electronic Ballasts - Philips Transistor Selection Guide ............................ 587
8.1.3 An Electronic Ballast - Base Drive Optimisation ........................................ 589
iv
Index Power Semiconductor Applications
Index
Airgap, transformer core, 111, 113 Bridge circuits
Anti saturation diode, 590 see Motor Control - AC
Asynchronous, 497 Brushless motor, 301, 303
Automotive Buck-boost converter, 110
fans Buck converter, 108 - 109
see motor control Burst firing, 537
IGBT, 481, 483 Burst pulses, 564
ignition, 479, 481, 483
lamps, 435, 455 Capacitance
motor control, 425, 457, 459, 471, 475 junction, 29
resistive loads, 442 Capacitor
reverse battery, 452, 473, 479 mains dropper, 544
screen heater, 442 CENELEC, 537
seat heater, 442 Charge carriers, 133
solenoids, 469 triac commutation, 549
TOPFET, 473 Choke
Avalanche, 61 fluorescent lamp, 580
Avalanche breakdown Choppers, 285
thyristor, 490 Clamp diode, 117
Avalanche multiplication, 134 Clamp winding, 113
Commutation
Baker clamp, 138, 187, 190 diode, 164
Ballast Hi-Com triac, 551
electronic, 580 thyristor, 492
fluorescent lamp, 579 triac, 494, 523, 529
switchstart, 579 Compact fluorescent lamp, 585
Base drive, 136 Continuous mode
base inductor, 147 see Switched Mode Power Supplies
base inductor, diode assisted, 148 Continuous operation, 557
base resistor, 146 Converter (dc-dc)
drive transformer, 145 switched mode power supply, 107
drive transformer leakage inductance, 149 Cookers, 537
electronic ballast, 589 Cooling
forward converter, 187 forced, 572
power converters, 141 natural, 570
speed-up capacitor, 143 Crest factor, 529
Base inductor, 144, 147 Critical electric field, 134
Base inductor, diode assisted, 148 Cross regulation, 114, 117
Boost converter, 109 Current fed resonant inverter, 589
continuous mode, 109 Current Mode Control, 120
discontinuous mode, 109 Current tail, 138, 143
output ripple, 109
Bootstrap, 303 Damper Diodes, 345, 367
Breakback voltage forward recovery, 328, 348
diac, 492 losses, 347
Breakdown voltage, 70 outlines, 345
Breakover current picture distortion, 328, 348
diac, 492 selection guide, 345
Breakover voltage Darlington, 13
diac, 492, 592 Data Sheets
thyristor, 490 High Voltage Bipolar Transistor, 92,97,331
MOSFET, 69
i
dc-dc converter, 119 ESD, 67

Depletion region, 133 see Protection, ESD
Desaturation networks, 86 precautions, 67
Baker clamp, 91, 138 ETD core
dI/dt see magnetics
triac, 531
Diac, 492, 500, 527, 530, 591 F-pack
Diode, 6 see isolated package
double diffused, 162 Fall time, 143, 144
epitaxial, 161 Fast Recovery Epitaxial Diode (FRED)
schottky, 173 see epitaxial diode
structure, 161 FBSOA, 134
Diode Modulator, 327, 367 Ferrites
Disc drives, 302 see magnetics
Discontinuous mode Flicker
see Switched Mode Power Supplies fluorescent lamp, 580
Domestic Appliances, 527 Fluorescent lamp, 579
Dropper colour rendering, 579
capacitive, 544 colour temperature, 579
resistive, 544, 545 efficacy, 579, 580
Duty cycle, 561 triphosphor, 579
Flyback converter, 110, 111, 113
EFD core advantages, 114
see magnetics clamp winding, 113
Efficiency Diodes continuous mode, 114
see Damper Diodes coupled inductor, 113
Electric drill, 531 cross regulation, 114
Electronic ballast, 580 diodes, 115
base drive optimisation, 589 disadvantages, 114
current fed half bridge, 584, 587, 589 discontinuous mode, 114
current fed push pull, 583, 587 electronic ballast, 582
flyback, 582 leakage inductance, 113
transistor selection guide, 587 magnetics, 213
voltage fed half bridge, 584, 588 operation, 113
voltage fed push pull, 583, 587 rectifier circuit, 180
EMC, 260, 455 self oscillating power supply, 199
see RFI, ESD synchronous rectifier, 156, 181
TOPFET, 473 transformer core airgap, 111, 113
Emitter shorting transistors, 115
triac, 549 Flyback converter (two transistor), 111, 114
Epitaxial diode, 161 Food mixer, 531
characteristics, 163 Forward converter, 111, 116
dI/dt, 164 advantages, 116
forward recovery, 168 clamp diode, 117
lifetime control, 162 conduction loss, 197
operating frequency, 165 continuous mode, 116
passivation, 162 core loss, 116
reverse leakage, 169 core saturation, 117
reverse recovery, 162, 164 cross regulation, 117
reverse recovery softness, 167 diodes, 118
selection guide, 171 disadvantages, 117
snap-off, 167 duty ratio, 117
softness factor, 167 ferrite cores, 116
stored charge, 162 magnetics, 213
technology, 162 magnetisation energy, 116, 117
ii
operation, 116 Heat sink compound, 567

output diodes, 117 Heater controller, 544
output ripple, 116 Heaters, 537
rectifier circuit, 180 Heatsink, 569
reset winding, 117 Heatsink compound, 514
switched mode power supply, 187 Hi-Com triac, 519, 549, 551
switching frequency, 195 commutation, 551
switching losses, 196 dIcom/dt, 552
synchronous rectifier, 157, 181 gate trigger current, 552
transistors, 118 inductive load control, 551
Forward converter (two transistor), 111, 117 High side switch
Forward recovery, 168 MOSFET, 44, 436
FREDFET, 250, 253, 305 TOPFET, 430, 473
bridge circuit, 255 High Voltage Bipolar Transistor, 8, 79, 91,
charge, 254 141, 341
diode, 254 ‘bathtub’ curves, 333
drive, 262 avalanche breakdown, 131
loss, 256 avalanche multiplication, 134
reverse recovery, 254 Baker clamp, 91, 138
FREDFETs base-emitter breakdown, 144
motor control, 259 base drive, 83, 92, 96, 136, 336, 385
Full bridge converter, 111, 125 base drive circuit, 145
advantages, 125 base inductor, 138, 144, 147
diodes, 126 base inductor, diode assisted, 148
disadvantages, 125 base resistor, 146
operation, 125 breakdown voltage, 79, 86, 92
transistors, 126 carrier concentration, 151
carrier injection, 150
Gate conductivity modulation, 135, 150
triac, 538 critical electric field, 134
Gate drive current crowding, 135, 136
forward converter, 195 current limiting values, 132
Gold doping, 162, 169 current tail, 138, 143
GTO, 11 current tails, 86, 91
Guard ring d-type, 346
schottky diode, 174 data sheet, 92, 97, 331
depletion region, 133
Half bridge, 253 desaturation, 86, 88, 91
Half bridge circuits device construction, 79
see also Motor Control - AC dI/dt, 139
Half bridge converter, 111, 122 drive transformer, 145
advantages, 122 drive transformer leakage inductance, 149
clamp diodes, 122 dV/dt, 139
cross conduction, 122 electric field, 133
diodes, 124 electronic ballast, 581, 585, 587, 589
disadvantages, 122 Fact Sheets, 334
electronic ballast, 584, 587, 589 fall time, 86, 99, 143, 144
flux symmetry, 122 FBSOA, 92, 99, 134
magnetics, 214 hard turn-off, 86
operation, 122 horizontal deflection, 321, 331, 341
synchronous rectifier, 157 leakage current, 98
transistor voltage, 122 limiting values, 97
transistors, 124 losses, 92, 333, 342
voltage doubling, 122 Miller capacitance, 139
Heat dissipation, 567 operation, 150
iii
optimum drive, 88 Ignition

outlines, 332, 346 automotive, 479, 481, 483
over current, 92, 98 darlington, 483
over voltage, 92, 97 Induction heating, 53
overdrive, 85, 88, 137, 138 Induction motor
passivation, 131 see Motor Control - AC
power limiting value, 132 Inductive load
process technology, 80 see Solenoid
ratings, 97 Inrush current, 528, 530
RBSOA, 93, 99, 135, 138, 139 Intrinsic silicon, 133
RC network, 148 Inverter, 260, 273
reverse recovery, 143, 151 see motor control ac
safe operating area, 99, 134 current fed, 52, 53
saturation, 150 switched mode power supply, 107
saturation current, 79, 98, 341 Irons, electric, 537
secondary breakdown, 92, 133 Isolated package, 154
smooth turn-off, 86 stray capacitance, 154, 155
SMPS, 94, 339, 383 thermal resistance, 154
snubber, 139 Isolation, 153
space charge, 133
speed-up capacitor, 143 J-FET, 9
storage time, 86, 91, 92, 99, 138, 144, 342 Junction temperature, 470, 557, 561
sub emitter resistance, 135 burst pulses, 564
switching, 80, 83, 86, 91, 98, 342 non-rectangular pulse, 565
technology, 129, 149 rectangular pulse, composite, 562
thermal breakdown, 134 rectangular pulse, periodic, 561
thermal runaway, 152 rectangular pulse, single shot, 561
turn-off, 91, 92, 138, 142, 146, 151
turn-on, 91, 136, 141, 149, 150 Lamp dimmer, 530
underdrive, 85, 88 Lamps, 435
voltage limiting values, 130 dI/dt, 438
Horizontal Deflection, 321, 367 inrush current, 438
base drive, 336 MOSFET, 435
control ic, 401 PWM control, 455
d-type transistors, 346 switch rate, 438
damper diodes, 345, 367 TOPFET, 455
diode modulator, 327, 347, 352, 367 Latching current
drive circuit, 352, 365, 406 thyristor, 490
east-west correction, 325, 352, 367 Leakage inductance, 113, 200, 523
line output transformer, 354 Lifetime control, 162
linearity correction, 323 Lighting
operating cycle, 321, 332, 347 fluorescent, 579
s-correction, 323, 352, 404 phase control, 530
TDA2595, 364, 368 Logic Level FET
TDA4851, 400 motor control, 432
TDA8433, 363, 369 Logic level MOSFET, 436
test circuit, 321
transistors, 331, 341, 408 Magnetics, 207
waveforms, 322 100W 100kHz forward converter, 197
100W 50kHz forward converter, 191
IGBT, 11, 305 50W flyback converter, 199
automotive, 481, 483 core losses, 208
clamped, 482, 484 core materials, 207
ignition, 481, 483 EFD core, 210
ETD core, 199, 207
iv
flyback converter, 213 safe operating area, 25, 74

forward converter, 213 series operation, 53
half bridge converter, 214 SMPS, 339, 384
power density, 211 solenoid, 62
push-pull converter, 213 structure, 19
switched mode power supply, 187 switching, 24, 29, 58, 73, 194, 262
switching frequency, 215 switching loss, 196
transformer construction, 215 synchronous rectifier, 179
Mains Flicker, 537 thermal impedance, 74
Mains pollution, 225 thermal resistance, 70
pre-converter, 225 threshold voltage, 21, 70
Mains transient, 544 transconductance, 57, 72
Mesa glass, 162 turn-off, 34, 36
Metal Oxide Varistor (MOV), 503 turn-on, 32, 34, 35, 155, 256
Miller capacitance, 139 Motor, universal
Modelling, 236, 265 back EMF, 531
MOS Controlled Thyristor, 13 starting, 528
MOSFET, 9, 19, 153, 253 Motor Control - AC, 245, 273
bootstrap, 303 anti-parallel diode, 253
breakdown voltage, 22, 70 antiparallel diode, 250
capacitance, 30, 57, 72, 155, 156 carrier frequency, 245
capacitances, 24 control, 248
characteristics, 23, 70 - 72 current rating, 262
charge, 32, 57 dc link, 249
data sheet, 69 diode, 261
dI/dt, 36 diode recovery, 250
diode, 253 duty ratio, 246
drive, 262, 264 efficiency, 262
drive circuit loss, 156 EMC, 260
driving, 39, 250 filter, 250
dV/dt, 36, 39, 264 FREDFET, 250, 259, 276
ESD, 67 gate drives, 249
gate-source protection, 264 half bridge, 245
gate charge, 195 inverter, 250, 260, 273
gate drive, 195 line voltage, 262
gate resistor, 156 loss, 267
high side, 436 MOSFET, 259
high side drive, 44 Parallel MOSFETs, 276
inductive load, 62 peak current, 251
lamps, 435 phase voltage, 262
leakage current, 71 power factor, 262
linear mode, parallelling, 52 pulse width modulation, 245, 260
logic level, 37, 57, 305 ripple, 246
loss, 26, 34 short circuit, 251
maximum current, 69 signal isolation, 250
motor control, 259, 429 snubber, 276
modelling, 265 speed control, 248
on-resistance, 21, 71 switching frequency, 246
package inductance, 49, 73 three phase bridge, 246
parallel operation, 26, 47, 49, 265 underlap, 248
parasitic oscillations, 51 Motor Control - DC, 285, 293, 425
peak current rating, 251 braking, 285, 299
Resonant supply, 53 brushless, 301
reverse diode, 73 control, 290, 295, 303
ruggedness, 61, 73 current rating, 288
v
drive, 303 Power MOSFET

duty cycle, 286 see MOSFET
efficiency, 293 Proportional control, 537
FREDFET, 287 Protection
freewheel diode, 286 ESD, 446, 448, 482
full bridge, 287 overvoltage, 446, 448, 469
half bridge, 287 reverse battery, 452, 473, 479
high side switch, 429 short circuit, 251, 446, 448
IGBT, 305 temperature, 446, 447, 471
inrush, 430 TOPFET, 445, 447, 451
inverter, 302 Pulse operation, 558
linear, 457, 475 Pulse Width Modulation (PWM), 108
logic level FET, 432 Push-pull converter, 111, 119
loss, 288 advantages, 119
MOSFET, 287, 429 clamp diodes, 119
motor current, 295 cross conduction, 119
overload, 430 current mode control, 120
permanent magnet, 293, 301 diodes, 121
permanent magnet motor, 285 disadvantages, 119
PWM, 286, 293, 459, 471 duty ratio, 119
servo, 298 electronic ballast, 582, 587
short circuit, 431 flux symmetry, 119, 120
stall, 431 magnetics, 213
TOPFET, 430, 457, 459, 475 multiple outputs, 119
topologies, 286 operation, 119
torque, 285, 294 output filter, 119
triac, 525 output ripple, 119
voltage rating, 288 rectifier circuit, 180
Motor Control - Stepper, 309 switching frequency, 119
bipolar, 310 transformer, 119
chopper, 314 transistor voltage, 119
drive, 313 transistors, 121
hybrid, 312
permanent magnet, 309 Qs (stored charge), 162
reluctance, 311
step angle, 309 RBSOA, 93, 99, 135, 138, 139
unipolar, 310 Rectification, synchronous, 179
Mounting, transistor, 154 Reset winding, 117
Mounting base temperature, 557 Resistor
Mounting torque, 514 mains dropper, 544, 545
Resonant power supply, 219, 225
Parasitic oscillation, 149 modelling, 236
Passivation, 131, 162 MOSFET, 52, 53
PCB Design, 368, 419 pre-converter, 225
Phase angle, 500 Reverse leakage, 169
Phase control, 546 Reverse recovery, 143, 162
thyristors and triacs, 498 RFI, 154, 158, 167, 393, 396, 497, 529, 530,
triac, 523 537
Phase voltage Ruggedness
see motor control - ac MOSFET, 62, 73
Power dissipation, 557 schottky diode, 173
see High Voltage Bipolar Transistor loss,
MOSFET loss Safe Operating Area (SOA), 25, 74, 134, 557
Power factor correction, 580 forward biased, 92, 99, 134
active, boost converted, 581 reverse biased, 93, 99, 135, 138, 139
vi
Saturable choke Storage time, 144

triac, 523 Stored charge, 162
Schottky diode, 173 Suppression
bulk leakage, 174 mains transient, 544
edge leakage, 174 Switched Mode Power Supply (SMPS)
guard ring, 174 see also self oscillating power supply
reverse leakage, 174 100W 100kHz MOSFET forward converter,
ruggedness, 173 192
selection guide, 176 100W 500kHz half bridge converter, 153
technology, 173 100W 50kHz bipolar forward converter, 187
SCR 16 & 32 kHz TV, 389
see Thyristor asymmetrical, 111, 113
Secondary breakdown, 133 base circuit design, 149
Selection Guides boost converter, 109
BU25XXA, 331 buck-boost converter, 110
BU25XXD, 331 buck converter, 108
damper diodes, 345 ceramic output filter, 153
EPI diodes, 171 continuous mode, 109, 379
horizontal deflection, 343 control ic, 391
MOSFETs driving heaters, 442 control loop, 108
MOSFETs driving lamps, 441 core excitation, 113
MOSFETs driving motors, 426 core loss, 167
Schottky diodes, 176 current mode control, 120
SMPS, 339 dc-dc converter, 119
Self Oscillating Power Supply (SOPS) diode loss, 166
50W microcomputer flyback converter, 199 diode reverse recovery effects, 166
ETD transformer, 199 diode reverse recovery softness, 167
Servo, 298 diodes, 115, 118, 121, 124, 126
Single ended push-pull discontinuous mode, 109, 379
see half bridge converter epitaxial diodes, 112, 161
Snap-off, 167 flux swing, 111
Snubber, 93, 139, 495, 502, 523, 529, 549 flyback converter, 92, 111, 113, 123
active, 279 forward converter, 111, 116, 379
Softness factor, 167 full bridge converter, 111, 125
Solenoid half bridge converter, 111, 122
TOPFET, 469, 473 high voltage bipolar transistor, 94, 112, 115,
turn off, 469, 473 118, 121, 124, 126, 129, 339, 383, 392
Solid state relay, 501 isolated, 113
SOT186, 154 isolated packages, 153
SOT186A, 154 isolation, 108, 111
SOT199, 154 magnetics design, 191, 197
Space charge, 133 magnetisation energy, 113
Speed-up capacitor, 143 mains filter, 380
Speed control mains input, 390
thyristor, 531 MOSFET, 112, 153, 33, 384
triac, 527 multiple output, 111, 156
Starter non-isolated, 108
fluorescent lamp, 580 opto-coupler, 392
Startup circuit output rectifiers, 163
electronic ballast, 591 parasitic oscillation, 149
self oscillating power supply, 201 power-down, 136
Static Induction Thyristor, 11 power-up, 136, 137, 139
Stepdown converter, 109 power MOSFET, 153, 339, 384
Stepper motor, 309 pulse width modulation, 108
Stepup converter, 109 push-pull converter, 111, 119
vii
RBSOA failure, 139 Thermal characteristics

rectification, 381, 392 power semiconductors, 557
rectification efficiency, 163 Thermal impedance, 74, 568
rectifier selection, 112 Thermal resistance, 70, 154, 557
regulation, 108 Thermal time constant, 568
reliability, 139 Thyristor, 10, 497, 509
resonant ’two transistor’ model, 490
see resonant power supply applications, 527
RFI, 154, 158, 167 asynchronous control, 497
schottky diode, 112, 154, 173 avalanche breakdown, 490
snubber, 93, 139, 383 breakover voltage, 490, 509
soft start, 138 cascading, 501
standby, 382 commutation, 492
standby supply, 392 control, 497
start-up, 391 current rating, 511
stepdown, 109 dI/dt, 490
stepup, 109 dIf/dt, 491
symmetrical, 111, 119, 122 dV/dt, 490
synchronisation, 382 energy handling, 505
synchronous rectification, 156, 179 external commutation, 493
TDA8380, 381, 391 full wave control, 499
topologies, 107 fusing I2t, 503, 512
topology output powers, 111 gate cathode resistor, 500
transformer, 111 gate circuits, 500
transformer saturation, 138 gate current, 490
transformers, 391 gate power, 492
transistor current limiting value, 112 gate requirements, 492
transistor mounting, 154 gate specifications, 512
transistor selection, 112 gate triggering, 490
transistor turn-off, 138 half wave control, 499
transistor turn-on, 136 holding current, 490, 509
transistor voltage limiting value, 112 inductive loads, 500
transistors, 115, 118, 121, 124, 126 inrush current, 503
turns ratio, 111 latching current, 490, 509
TV & Monitors, 339, 379, 399 leakage current, 490
two transistor flyback, 111, 114 load line, 492
two transistor forward, 111, 117 mounting, 514
Switching loss, 230 operation, 490
Synchronous, 497 overcurrent, 503
Synchronous rectification, 156, 179 peak current, 505
self driven, 181 phase angle, 500
transformer driven, 180 phase control, 498, 527
pulsed gate, 500
Temperature control, 537 resistive loads, 498
Thermal resonant circuit, 493
continuous operation, 557, 568 reverse characteristic, 489
intermittent operation, 568 reverse recovery, 493
non-rectangular pulse, 565 RFI, 497
pulse operation, 558 self commutation, 493
rectangular pulse, composite, 562 series choke, 502
rectangular pulse, periodic, 561 snubber, 502
rectangular pulse, single shot, 561 speed controller, 531
single shot operation, 561 static switching, 497
Thermal capacity, 558, 568 structure, 489
switching, 489
viii
switching characteristics, 517 gate requirements, 492

synchronous control, 497 gate resistor, 540, 545
temperature rating, 512 gate sensitivity, 491
thermal specifications, 512 gate triggering, 538
time proportional control, 497 holding current, 491, 510
transient protection, 502 Hi-Com, 549, 551
trigger angle, 500 inductive loads, 500
turn-off time, 494 inrush current, 503
turn-on, 490, 509 isolated trigger, 501
turn-on dI/dt, 502 latching current, 491, 510
varistor, 503 operation, 491
voltage rating, 510 overcurrent, 503
Thyristor data, 509 phase angle, 500
Time proportional control, 537 phase control, 498, 527, 546
TOPFET protection, 544
3 pin, 445, 449, 461 pulse triggering, 492
5 pin, 447, 451, 457, 459, 463 pulsed gate, 500
driving, 449, 453, 461, 465, 467, 475 quadrants, 491, 510
high side, 473, 475 resistive loads, 498
lamps, 455 RFI, 497
leadforms, 463 saturable choke, 523
linear control, 451, 457 series choke, 502
motor control, 430, 457, 459 snubber, 495, 502, 523, 529, 549
negative input, 456, 465, 467 speed controller, 527
protection, 445, 447, 451, 469, 473 static switching, 497
PWM control, 451, 455, 459 structure, 489
solenoids, 469 switching, 489
Transformer synchronous control, 497
triac controlled, 523 transformer load, 523
Transformer core airgap, 111, 113 transient protection, 502
Transformers trigger angle, 492, 500
see magnetics triggering, 550
Transient thermal impedance, 559 turn-on dI/dt, 502
Transient thermal response, 154 varistor, 503
Triac, 497, 510, 518 zero crossing, 537
400Hz operation, 489, 518 Trigger angle, 500
applications, 527, 537 TV & Monitors
asynchronous control, 497 16 kHz black line, 351
breakover voltage, 510 30-64 kHz autosync, 399
charge carriers, 549 32 kHz black line, 361
commutating dI/dt, 494 damper diodes, 345, 367
commutating dV/dt, 494 diode modulator, 327, 367
commutation, 494, 518, 523, 529, 549 EHT, 352 - 354, 368, 409, 410
control, 497 high voltage bipolar transistor, 339, 341
dc inductive load, 523 horizontal deflection, 341
dc motor control, 525 picture distortion, 348
dI/dt, 531, 549 power MOSFET, 339
dIcom/dt, 523 SMPS, 339, 354, 379, 389, 399
dV/dt, 523, 549 vertical deflection, 358, 364, 402
emitter shorting, 549 Two transistor flyback converter, 111, 114
full wave control, 499 Two transistor forward converter, 111, 117
fusing I2t, 503, 512
gate cathode resistor, 500 Universal motor
gate circuits, 500 back EMF, 531
gate current, 491
ix
starting, 528
Vacuum cleaner, 527
Varistor, 503
Vertical Deflection, 358, 364, 402
Voltage doubling, 122
Water heaters, 537
Zero crossing, 537

Zero voltage switching, 537

Introduction To Power Semiconductors

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Introduction To Power Semiconductors

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Introduction Power Semiconductor Applications

Introduction to Power Semiconductors

1.1.1 An Introduction To Power Devices

Before looking at the switches let’s briefly consider the

Under normal operating conditions the off-state losses in

LOW RESITIVITY INTERMEDIATE CASE HIGH RESISTIVITY

Thickness Thickness Thickness

Case 1 Case 2 Case 3

The silicon diode Case 2: Intermediate balance

The column named RA gives the resistance area product.

(µm) (Ωcm) Ωcm2 QP

BASE EMITTER GATE SOURCE GATE SOURCE

COLLECTOR DRAIN DRAIN

BIPOLAR TRANSISTOR J-FET (SIT) MOS

Fig.4 The three basic three layer devices

The third version has an electrode (gate) placed very close

The High Voltage Transistor (HVT)

Modern technology allows a planar structure with very

DRAIN The MOSFET is the preferred device for higher frequency

The charge in the device originates from two sources: The

drawback, as is its negative drive requirements.

especially resonant systems, are particularly attractive for

HVT J-FET MOS THY GTO IGBT IGBT Unit

Darlingtons and BiMOS

A third point is manufacturability. The use of fine structures

1 kHz SITr SITh

(fast) GTO (slow)

using a voltage to pinch-off the current through openings be high.

1.2.1 PowerMOS Introduction

Fig.1(a) Power MOSFET cell structure.

Fig.1(b) Plan view of a low voltage Power MOS chip

leads to an optimum value for the polysilicon track width for

Spreading resistance. As the electrons move further into

Epitaxial layer. The drain-source voltage rating

Substrate. The resistance of the N+ substrate is only

For low voltage devices this structure consists of a field

Fig.5 Ring structure for high voltage devices.

To turn the device on and off the capacitances have to be

MOSFET are limited only by the drive circuit and can be

ID / A Turn-off losses may be reduced by the use of snubber

MOSFETs because they have a positive temperature subsequent chapters.

1.2.2 Understanding Power MOSFET Switching Behaviour

i) P-N junction capacitance

material (positively charged holes of the P material are

where t = oxide thickness

Fig.4 Parasitic capacitance model

The capacitance between drain and source is a P-N junction

Fig.5 Cross section of a single PowerMOS cell showing

Fig.8 Gate charge circuit

At time, t0 (Fig.9), the gate drive is activated. Current flows

Charging cycle - The Gate Charge t0 t1 t2

gate. The gate and drain voltages with respect to source 12

The current in the MOSFET continues to rise until id = I0,

becomes clamped at this point, (t1). The entire gate current

drop as Cgd is discharged, Fig.11(c). The rate at which

As Vdg approaches zero, Cgd starts to increase Cgs Cgs

dramatically, reaching its maximum as Vdg becomes

(a) Vdd (b) Vdd

(c) Vdd (d) Vdd