The RF Reader

A collection of published articles

on RF from Analog Devices

www.analog.com/RF
 The RF Reader
A collection of published articles
on RF from Analog Devices

Smart Partitioning for WiMAX Radios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

AD8368: A Broadband RF/IF VGA with 34 dB Linear-in-dB Gain Control Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Measuring the RF Power in CDMA2000 and W-CDMA High Power Amplifiers (HPAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Simulating the Effect of Blockers on Data Converter Performance in Wideband Receivers . . . . . . . . . . . . . . . . . . . . . . . . . 15
Converter Performance Approaches Software-Defined Radio Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Calibration and Temperature-Compensation Techniques Using an RMS-Responding RF Detector . . . . . . . . . . . . . . . . . . . . . 21
Improved DDS Devices Enable Advanced Comm Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RF Standards for Short-Range Wireless Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
A Broadband I/Q Modulator for Broadband Radio Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Evaluating Linear Distortion in ADC Driver Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IQ Modulators Advance Reconfigurable Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
How to Determine an Effective Damping Factor for a Third-Order PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Log Amps and Directional Couplers Enable VSWR Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Direct Digital Synthesis Enables Digital PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
A Direct-Conversion Transmitter for WiMAX and WiBro Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Converters for 3G Are Optimized for Cost, Size, and Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
RF Power Detection: Measuring WiMAX Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Measuring VSWR and Gain in Wireless Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Low Power Direct Digital Synthesizer Cores Enable High Level of Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
WIRELESS TECHNOLOGIES

Smart Partitioning
for WiMAX Radios
NOMAN RANGWALA AND RICK MYERS
Analog Devices Inc., Norwood, MA

he need for broadband wireless ac-

T
Figure 1 shows a block diagram of a
cess (BWA) has long been acknowl- traditional WiMAX system. An RF trans-
edged as the next step in the evolu- ceiver is connected through a power am-
tion of Internet access. Unfortunately, the plifier (PA) and RF switches to the anten-
lack of robust technology at a competi- na on one side, and to a digital baseband
tive price has been a barrier to its imple- (DBB) on the other. The interface be-
mentation. Today, though, momentum to tween the RF transceiver and the DBB is
cross the chasm is gathering—early composed of analog signals, which can
adopters have endorsed the technology be at intermediate frequency (IF) or base-
in under-served rural areas of the world, band. Note that the ADCs and DACs in
while standardization efforts have re- this architecture can be discrete devices,
duced costs enough that mainstream or can be integrated on an ASIC.
users can now consider WiMAX a viable In some applications, a two-chip solu-
alternative for broadband access with a tion may have higher performance and
future promise of mobile access. lower cost than a single-chip solution.
WiMAX, based on IEEE 802.16 specifi- The key is to know how to divide the
cations, supports operation in multiple fre- functions between the two chips to best
quencies and multiple air standards. To en- exploit both the circuit topology and the
sure interoperability between multiple available manufacturing technologies.
WiMAX solutions, the WiMAX Forum, an Smart partitioning does just this, allow-
industry consortium, has developed pro- ing an RF system-on-a-chip (SoC) to pro-
files that specify the operating frequency, vide a complete RF-to-bits solution in-
bandwidths, air-interface and medium ac- cluding all required automatic gain con-
cess protocols. These profiles are based on trol, transmit power control and RF
a 256-carrier orthogonal frequency divi- calibration loops. Including control loops
sion multiplexing (OFDM) air interface for on the radio front end enhances ease of
fixed/nomadic operation, and scalable- use, provides for an easier mix-and-
OFDM-access (S-OFDMA) air interface for match capability with different DBB
portable/mobile applications. modems and improves performance. The

Reprinted with permission of MICROWAVE JOURNAL® from the November 2006 issue.
©
2006 Horizon House Publications, Inc.
1
WIRELESS TECHNOLOGIES
accompanying reduction of real- cost, this reduction will require for 90 nm or 65 nm are not avail-
time software control results in significant improvements for able for integration on today’s
simpler system design. All analog market prices to yield an accept- fine-line digital processes. The
and RF specific controls are inte- able profit. opportunity cost for using a 130-
grated on the RF front-end IC. Smart partitioning offers the nm process for the digital base-
This is smart partitioning. Figure opportunity to dramatically re- band instead of a state-of-the-art
2 illustrates a block diagram for a duce the total cost of a WiMAX 90-nm process can be up to
system using smart partitioning. system. Today’s traditional DBBs twice. Data converters integrated
are mixed-signal ASICs, with on a DBB constrain the cost,
COST BENEFITS ENABLED over 90 percent of their area oc- keeping the IC from taking ad-
BY SMART PARTITIONING cupied by digital gates and 5 to vantage of Moore’s law.
For communication systems 10 percent used for data convert-
such as WiMAX and BWA, con- ers. The cost to manufacture such EASE OF USE ENABLED
sumer prices less than $100 are a mixed-signal device is over 1.5 BY SMART PARTITIONING
essential. In CPE equipment for times the cost of manufacturing a By itself, the integration of
asymmetric digital subscriber digital-only IC. The major con- data converters is not sufficient
loop (ADSL) and 802.11g Wi-Fi tributors include higher wafer for smart partitioning. The data
($20 to $30), for example, volumes price (1.2 times), higher test cost converters required for WiMAX
increased dramatically as prices (1.1 times), higher yield cost (1.1 are typically over-sampled, so
declined. Emerging markets such times) and larger die size (1.05 handling the raw data rate in and
as WiMAX are also experiencing times), totaling a 1.5 times in- out of the transceiver would pre-
similar price pressures. End-user crease in cost. sent implementation challenges.
CPE prices are expected to be In addition to the tangible cost, However, integrating decimation
less than $100 by mid-2007. To there is a large opportunity cost and interpolation filters on the
achieve these targets, chipset incurred. Data converters typical- transceiver allows the interface
pricing must fall to $20 or $25. ly lag behind by one generation speed to be reduced. The avail-
Much lower than the current of the process, and proven cores ability of mature fine-line RF
CMOS processes, coupled with
Real Time Control Loops partitioned between advances in analog and RF mod-
two separate chips and vendors Mixed Signal is integrated on eling capabilities, have now made
digital ASIC or Standalone it possible to move data convert-
Real Time Control Signals
ers and other mixed-signal blocks
Ref to the RFIC in WiMAX radio de-
ADC
signs. For cost and power effi-
cient implementation of the digi-
LO ADC tal blocks, fine-line CMOS is a
Digital Modem/MAC
DAC definite plus. This article explores
DAC the choice of digital interface and
the ease of use advantages intro-
PLL
Slow Speed duced by simple RF drivers for
Control Port
receivers and transmitters.
Memory
DIGITAL INTERFACE: CHOICES,
ISSUES AND CHALLENGES
▲ Fig. 1 Block diagram of a traditionally partitioned WiMAX system. The evaluation board design
and layout has a critical impact
Real Time Control Loops Integrated on the performance of the mixed-
on RF Transciever
signal component of the DBB.
90/65nm digital
Real Time Control Signals
only process The analog I/O on the reference
board is sensitive to external
Digital I/Q

Ref
noise, and the supply routes to
ADC the mixed-signal portion of the
ADC Digital Modem/MAC design require high isolation.
LO
DAC
Validated by gate Eliminating the analog I/O mini-
level simulation
mizes these noise-coupling is-
DAC sues, and solves the problem of
PLL Slow Speed interfacing analog cores from dif-
Control Port ferent vendors (such as RF chip
Memory and mixed-signal converter
cores). For example, some ADC
cores require a discrete 5 V driver
▲ Fig. 2 Block diagram of a WiMAX system using smart partitioning. op-amp to obtain specified data

2
WIRELESS TECHNOLOGIES
sheet performance. Modems us- clock, synchronous clocking, or The parallel bit stream ap-
ing smaller processes, such as nibble transfers. Each approach proach offers lower data rates
130 nm or 90 nm, must reduce has its advantages and disadvan- and a standard CMOS I/O, but in-
the signal swing and match the tages. creases the pin count. To reduce
common-mode level to that of the High speed serial links (see the pin count to a manageable
RFIC. These considerations re- Figure 3) have a lower pin count, number, the data bus can use
quire valuable engineering re- reduced switching noise due to time duplexing to multiplex be-
sources. For systems using smart the differential signaling and tween receive and transmit data.
partitioning, the boundary be- larger separation (between DBB Additionally, the I/O can be sin-
tween the transceiver and the and RF transceiver). However, gle-ended if the switching and
DBB is digital, simplifying these the high speed circuit design risk high frequency noise are careful-
issues. is one of the biggest implementa- ly managed and isolated from the
Two basic options for selecting tion challenges. Implementation highly sensitive RF circuitry. The
a digital interface are a high of the serializer and de-serializer design on the DBB is straightfor-
speed serial data stream using is complex and requires clock re- ward, and can be implemented
low voltage digital swing (LVDS) covery circuits and other custom with a standard hardware de-
signaling, or a slower speed par- design blocks that are not readily scription language (HDL)-based
allel bit stream. Variations of available in standard digital li- design flow.
these schemes include embedded braries. The JEDEC Committee (JC-61),
formed in 2002, was chartered to
create an open standard for digi-
tal interface, enabling smart par-
Rx Clock titioning and multi-vendor solu-
Pros tions. The published standard,
Rx Data Low Pin Count JESD96, offers the high speed
Differential Signaling
LVDS approach. A proposal and
Tx Clock
Cons basic configuration for the paral-
Complex Implementation lel interface have also been ac-
High Speed (≈500MHz)
Tx Data cepted. Figure 4 shows an exam-
ple of a parallel interface imple-
RF Transceiver Modem mented on Analog Devices’
AD935x family of smart parti-
tioned transceivers. The ADI/Q™
Header

R/
Sync I Q I Q Control Field
W
CS Address Data CRC P digital I/Q interface provides the
basis of the JC-61 parallel stan-
Data Field Register Field
dard.
S S
Header

Header

y Data Field P Null y Data Field P AUTONOMOUS AUTOMATIC

n n
c c GAIN CONTROL (AGC)
Frame Boundary must be a Multiple of M In addition to ADCs and deci-
(User defined variable)
mation filters, smart partitioned
transceivers also integrate the au-
▲ Fig. 3 Digital interface — Serial interface option. tomatic gain control (AGC) circuit-
ry on the transceiver. The AGC
adjusts the gain of the receiver
10 path such that the input signal to
D0:D9
the ADC is maximized in scenar-
2 AUX_DAC SYNC
SYNC_VALID
ios with and without interference.
RF FE
TXNRX
The AD935x receiver signal chain
TX EN_AGC
is illustrated in Figure 5.
RX
ENABLE MAC Time division duplexing (TDD),
2 Modem the preferred system for the fu-
CTRL_OUT
3 4
ture, supports framed waveforms
GPO SPI (bursts). The media access con-
troller (MAC) at the base station
CLK
generates a downlink frame,
which starts with a preamble,
and follows with a frame control
AD935x
header and multiple data frames.
ADI/Q™ — A Digital I/Q Interface The duration of each frame is
short (1 to 2 ms). The input power
▲ Fig. 4 Parallel interface example from the AD935x family of smart partitioned transceivers. during the burst varies by 3 dB

3
WIRELESS TECHNOLOGIES
detected, the receiver gain is re-
Calibration Settings duced depending on the type of
LPF Gain Setting
LNA Gain Setting over-ranging. If the baseband
VGA Gain Setting peak detector before filters indi-
DC Offset DAC
cates clipping, for example, then
To Modem the LNA gain is stepped down.
ADC The AGC algorithm cycles
Mixer VGA LPF Out of In
OVR Band through these iterations and con-
DAC

Band LNA Gain Setting

LNA AGC/ verges on an optimum gain set-
Peak Offset LPF Gain Setting
Detector Control VGA Gain Setting ting. The system then freezes the
DAC

DC Offset DAC
OVR
Out of
Band In gain for the remainder of the
Band
Mixer VGA frame. For the modem to syn-
ADC
To Modem chronize and correlate to the sig-
LPF
nal, the receiver gain must be
fixed. A fast AGC lock time al-
lows the modem more time to
▲ Fig. 5 Receiver architecture on the AD935x family of smart partitioned transceivers.
synchronize and make accurate
channel estimates, reducing the
DL DL DL UL UL implementation loss and improv-
Preamble FCH Burst Burst Burst Preamble Burst Burst ing the system performance.
1 2 n 1 2
Downlink Transition Uplink Traditional systems achieve
Gap
this by distributing the AGC
function on both modem and
Variable
Gain
Fixed Gain transceiver. The dotted line in the
Signal Coarse Channel receiver architecture indicates
Detection, Frequency and Fine the functional partitioning. In this
AGC, Offset and Frequency
Antenna Timing Offset approach, the DBB must monitor
Selection Synchronization Estimation the gain, detect peaks and set a
new gain. The algorithm is gener-
▲ Fig. 6 The 802.16 OFDM waveform. ally implemented in the RF soft-
ware driver. Every time the gain
for fixed systems and 10 to 12 dB that the waveform is repetitive in is changed, the transceiver must
for mobile systems. the time domain. be recalibrated and the DC-off-
The transceiver uses the frame To detect the minimum desired sets must be removed. The RF
preamble to lock the gain of the signal, the receiver gain is set to driver must maintain accurate
receiver (see Figure 6). The pre- maximum. The in-channel re- timing and must respond to in-
amble is one or two OFDM sym- ceived power is measured at the terrupts generated from the
bols consisting of multiple tones outputs of the ADCs and decima- transceiver, making optimization
whose phases are aligned to cre- tion filters. The peak detectors a tedious, time-consuming task.
ate a waveform with a small distributed along the receiver In the case of multiple vendors,
peak-to-average power ratio. The chain and the ADCs are also each RF driver must be cus-
tones are also distributed such monitored for over-ranging. If tomized for a specific transceiver.

C Preamble C Symbol 1 C C Symbol n C Symbol n+1 C Symbol n+2

Symbol 2
P P P P P P
SQRT (I2 + Q2) vs. time

1.0 Gain Locked

Zone 1 Zone 2
AGC Lock time < 4 μs PUSC
0.8 MIMO
3 dB
ENVELOPE (V)

0.6 Fading within a burst

INPUT POWER

0.4

0.2

0 9-12 dB
0 10 20 30 40 Beam-formed Signal
TIME (μs)
Input Waveform: 802.16 OFDM Downlink

▲ Fig. 7 Digital I/Q receive signal

TIME

measured at the output of the AD935x. ▲ Fig. 8 Power variations in a burst for advanced MIMO and beam-formed signals.

4
WIRELESS
W I R E L E S STECHNOLOGIES
TECHNOLOGIES
In multiple instances, vendors symbol-to-symbol AGC. The transmit power control range of
have struggled to achieve power variation within a burst in 50 dB for the terminal. This will
64QAM operation on their refer- this scenario is 9 to 12 dB. A typi- allow terminals to be distributed
ence designs because of these cal power variation versus time around the cell site to meet the
complex interactions. for a beam-formed or space-time equal power criteria at the base
A transceiver using smart par- coded waveform is shown in Fig- station.
titioning integrates the complete ure 8. To accommodate this pow- During the ranging process,
control loop including monitor- er step, one option is to increase the base station requests the ter-
ing and control algorithms on a the ADC dynamic range and pay minal to send out a ranging sig-
single device. The basic process the corresponding cost of in- nal. The base station will then
to lock the gain remains the creasing a bit in performance. command the terminal to in-
same, but the responsibility for Another option is to reacquire crease or decrease its transmit
control is transferred to the RF lock on a symbol-by-symbol ba- power. The WiMAX Forum is
transceiver. From the modem’s sis. A fast AGC with short lock currently discussing require-
perspective, the loop is au- times, coupled with accurate tim- ments for accuracy and number
tonomous and does not require ing control for starting and stop- of iterations.
any dynamic interactions. The ping the AGC loop, could enable In traditional architectures, ex-
modem can still accurately start symbol-to-symbol AGC. ternal attenuators and true rms
and stop the loop, and can still Figure 9 shows a plot of re- power detectors can be used to
monitor the received signal ceiver input vs. measured receiv- achieve the system specifications.
strength indicator (RSSI) and er error vector magnitude (EVM) Using smart partitioning, the in-
gain settings. All internal calibra- for a WiMAX transceiver, using tegrated ADCs and DACs offer
tions are now self-contained. smart partitioning along with a the transmitter the ability to
With well-managed timing software modem implemented rapidly measure highly accurate
constraints, this smart partition- with Agilent VSA software. The burst output power. Figure 10
ing approach results in two ad- performance curve exemplifies shows the components of the
vantages: a simpler RF driver and the ease of implementation unique transmit power control
shorter AGC locking time. Fig- achieved using the smart parti- scheme implemented on the
ure 7 shows that the AGC lock tioning approach. For low input AD935x transceiver. To utilize the
time, when using the autono- power, the receiver gain is auto- power detector, the transmitted
mous AGC loop on the AD935x, matically adjusted to accommo- signal is sensed from an external
is of the order of four microsec- date the small input signal; the coupler. It is then fed back to the
onds for an 802.16 waveform. gain is then backed off automati- receiver, where it is down-con-
Further advanced techniques cally until the EVM is limited by verted to baseband. The receive
such as stronger signal detection, the linearity of the transceiver. ADCs digitize the signal, which is
radar detection and interference then processed by a digital rms
back-offs can also be easily im- TRANSMITTER POWER power meter block. This takes ad-
plemented. CONTROL vantage of the half-duplex nature
Advanced systems, operating The 802.16 standard specifies a of the system to make an accurate
in mobile environments with fad- ranging process that determines measurement using the idle cali-
ing channels, multiple antennas the correct output power radiated brated receiver path. The detec-
and beam-formed signals, re- by the terminal. This process en- tor is capable of measuring pow-
quire new techniques such as sures that transmissions from er on a TX burst-by-burst basis,
multiple terminals arrive at the providing the modem with near-
base station at the desired power real-time power information. The
2300
2550
level (within a certain range that front-end mixer is designed to be
2700 can be handled by the base sta- temperature and frequency inde-
tion). The standard specifies a pendent, and thus requires only a
−20

External Antenna
−25 Minimum Maximum Interface
Signal Signal
EVM (dB)

DAC Modulator
−30
Decode
pdref
−35 Control
LO
RMS txrssi
−40
−80 −60 −40 −20 0 ADC
INPUT POWER LEVEL (dBm)

▲ Fig. 9 Receiver performance of a smart

partitioned receiver implemented on the
AD935x. ▲ Fig. 10 Smart partitioned transmitter block diagram.

5
WIRELESS
W I R E L E S STECHNOLOGIES
TECHNOLOGIES
one-point factory calibration. SUMMARY iary ADCs and DACs, RF gener-
This feature saves test time and The smart partitioning of a al-purpose outputs for RF switch
reduces calibration complexity. WiMAX system enables the low- and PA control. The AD935x fam-
The ease of use advantage is est system cost and reduces the ily of transceivers exemplifies the
equally applicable to the trans- dependence of real-time control RF system-on-chip features that
mitter. The modem can vary the from the DBB. Integration of the can be implemented. ■
power on a burst-by-burst basis ADCs and DACs by itself is not Noman Rangwala received his bachelor
by simply writing to the register sufficient to achieve these advan- of engineering degree from Victoria
before the burst. The transmit tages. To reduce the speed of the Jubilee Technical Institute, Mumbai, in
power is automatically adjusted digital interface, decimation and 1992, his MSc degree from the University
of New Mexico, Albuquerque, NM, in 1994,
to the open loop accuracy specifi- interpolation filters are also inte- and his MBA degree from San Diego State
cation of the device. If greater ac- grated in the transceiver. These University, San Diego, CA, in 2000. He is a
curacy is required, the transmit stages also include the channel marketing manager with responsibility for
power control loop can be initiat- filters. A large portion of the RF WiMAX transceiver marketing within the
ed and a correction factor can be High Speed Signal Processing division of
driver complexity is managing Analog Devices Inc. (ADI). He also has
applied to the next burst. Other the real-time signaling between over six years of experience in IC design
novel techniques such as self- the modem and transceiver to and development.
generated short test signals can achieve fast and accurate AGC Richard H. “Rick” Myers received his BS
be transmitted before the actual and TPC. To reduce the process- degree from Old Dominion University in
burst to calibrate the device in ing load on the modem, the AGC 1983. He is a senior applications engineer
close loop. These techniques can and TPC algorithm blocks are in- focused on wireless applications for the
be explored as emissions require- tegrated on the transceiver. Other High Speed Signal Processing division of
Analog Devices Inc. (ADI) and is based in
ments and system requirements smart features can be integrated Raleigh, NC. Before joining ADI, he was
evolve. on the transceiver such as auxil- CDMA hardware development manager
for handsets at Ericsson in Research
Triangle Park, NC, and principal electrical
engineer of RF and receivers at E-Systems
(Raytheon) in Falls Church, VA.

6
0!'%s!02), FEATURE ARTICLE 777-0$)'%34#/-

AD8368: A Broadband RF/IF VGA with 34 dB Linear-in-dB

Gain Control Range
by Phillip Sher, Analog Devices

Introduction capacitor. Since the fixed-gain

M
ost wireless receiv- amplifier and output stage have
ers incorporate some an extremely large overall gain,
form of variable gain. small DC offsets at the input
Variable gain, which is usually of the fixed-gain amplifier can
implemented at Intermediate lead to large output offsets. To
Frequency (IF), is used to ampli- correct for these Vgain, supply
fy or attenuate received sig- and temperature variations, a
nals so that a constant signal low-pass offset correction loop
level is presented to subsequent is used which senses and main-
stages in the receiver. Usually tains the output DC level at the
implemented at Intermediate voltage on the DECL pin. The
Frequency (IF), variable gain low-pass corner frequency of
is used to amplify or attenuate this loop is controlled by the
received signals so that a con- size of the capacitor on the
stant level is presented to subse- HPFL pin.
quent stages in the receiver. The AD8368 contains an
Variable Gain Amplifiers accurate stand-alone RMS
(VGAs) will either have digital detector that enables versatile
gain control or analog gain con- AGC operation. To form a com-
trol and are generally optimized plete AGC loop, the MODE pin
for either receive or transmit Figure 1: Simplified Block Diagram is pulled low and the detector
applications. While the choice output pin is directly connected
of an analog controlled or to the GAIN pin and an inte-
digitally controlled VGA often grating capacitor. Then, by con-
comes down to the preferences necting the VGA output OUTP
of the equipment designer and directly to the detector input
the available control signals, DETI, the output is leveled to
there are solid technical reasons the set-point -11 dBm. This ref-
for choosing one over the other. erence level can be raised by
This article will discuss those dividing down the output signal
trade-offs and will go on to before applying it to the detec-
discuss the operation and appli- tor input, allowing for a range
cation of Analog Devices’ new of AGC levels.
analog controlled VGA.
Input and Output Impedances
A Linear-in-dB IF Variable The input to the AD8368
Gain Amplifier should be externally AC cou-
The AD8368 is an IF VGA pled to prevent disrupting
with an operational bandwidth the DC levels on the chip.
from near DC to 800 MHz Thus, a large coupling capaci-
and a gain control range of tor should be used, so that
34 dB from -12 dB to +22 Figure 2: Gain Control Transfer Function and Linearity at the series impedance of the
dB. It also includes an onboard 70 MHz. capacitor is negligible at the
square-law detector that can be frequencies of interest. On
used in an AGC loop with the separate variable transconduc- stages are summed and fed into the chip, the input is connect-
VGA. Using Analog Devices’ tance gm stages, whose out- an integrator. Resistive feed- ed directly to a resistor ladder
patented X-AMP architecture, puts are summed and fed into back from the output of the network whose impedance is
the AD8368 achieves accurate an integrator. Gain control is integrator to the gm stages cre- nominally 50 7.
linear-in-dB gain control. The achieved by using the GAIN ates a low-noise, high-linearity The output of the part
part is designed with 50 7 input pin to control the interpolator. fixed-gain amplifier. The out- should also be AC coupled
and output impedances. As GAIN is swept from 0 V put of this amplifier is fed to prevent disrupting the
The main signal path consists to 1 V, the interpolator selects into the output buffer, which output DC level. As with
of a variable input attenuator different tap points by varying provides an active 50 7 output the input, a sufficiently large
followed by an integrator and the transconductance of the gm impedance and additional 6 value of capacitance should
output buffer. Feedback around stages. For gains between two dB of fixed gain. be used so that the series
the integrator creates a fixed- tap points, the interpolator var- impedance of the capacitor
gain amplifier. Figure 1 shows a ies the transconductance such Output DC Level and Offset is negligible at the frequen-
block diagram of the VGA. that the weighted sum of several Correction cies of interest.
adjacent tap points are chosen. Since the AD8368 is single-end- The output impedance is
Input Attenuator and In this way, an accurate contin- ed, the DC levels at the input synthesized by the output buf-
Interpolator uous linear-in-dB gain control and output are regulated to fer. The fixed gain of the out-
The input attenuator is built response is produced. VPSI/2 by an internal regulator. put buffer combined with the
from a resistor ladder with eigh- The output of this regulator is resistive feedback from output
teen -2 dB tap points. Each Integrator and Output Buffer connected to the DECL line and to input provides a nominally
of these tap points is fed into The current outputs of the gm requires an external decoupling 50 7 output impedance.

7
0!'%s!02), FEATURE ARTICLE 777-0$)'%34#/-

Figure 3: Gain Control Transfer Function vs. Temperature Figure 4: Noise and OIP3 vs. Control Voltage at 140 MHz

Accurate Linear-in-dB Gain of the ideal linear model to The input-referred distortion dBm. This is 178 mV pk-pk
Control the three transfer functions at varies in a similar manner to for sine-wave signals, but the
The AD8368 has a linear-in- 25º C, -40 º C, and +85º C the noise. Figure 4 illustrates peak amplitude for other sig-
dB gain control interface that yields the linear conformance how the third-order inter- nals, such as Gaussian noise, or
can be operated in either a error curves scaled in dB. This cept point at the input, OIP3, those carrying complex modu-
gain-up (positive gain control method of error calculation behaves as a function of VGAIN. lation, will invariably be some-
sense) or gain-down (nega- resembles the expected error At lower levels, a degraded what greater. However, for all
tive gain sense) mode. With from single temperature calibra- OIP3 is acceptable. Overall, the waveforms having a reasonable
the MODE pin pulled high tion during system production. dynamic range, represented by crest factor (less than 13dB),
in the gain-up mode, the gain the difference between IIP3 and the rms value will be correct-
increases with increasing gain Using the AD8368 VGA NF, remains reasonably con- ly measured and delivered at
control voltages; in gain-down The AD8368 is a general pur- stant as a function of gain. The VOUT. The output set-point
mode (MODE pulled low) gain pose VGA suitable for use in output distortion and compres- may be adjusted upwards using
decreases with increasing GAIN a wide variety of applications sion are essentially independent an external resistive divider net-
voltages (Figure 2). where voltage-control of gain is of the gain. At low gains, when work as depicted in Figure 5.
With MODE pulled high, needed. While having 800 MHz the input level is high, input In this configuration, the rms
the ideal gain function is given bandwidth, its use is not limited overload can occur causing output voltage will be equal to
by the equation: to high frequency signal process- premature distortion. (1+n)63mVrms, where n=R1/
ing. Its accurate, temperature- The MODE pin controls R2. For the default set-point
Gain(db) = 37 s VGAIN – 14 stable and supply-stable linear- whether the gain of the part of 63mVrms, simply short R2
in-dB scaling will be valuable is an increasing or decreasing (direct connection from OUTP
With MODE low, the ideal wherever it is important to have function of the GAIN voltage. to DETI) and remove R1. Other
gain function is given by the a more dependable response to The ENBL pin is used to enable setpoints may be implemented
equation: the control voltage than is usu- or disable the part. When ENBL by calculating the ratio of R2/
ally offered by Voltage Variable is high, the part is enabled. With R1. For example, a 0 dBm AGC
Gain(db) = -37.5 s VGAIN + 24.8 Attenuators (VVAs). ENBL low, the part is disabled output corresponds to 222 mV
The input (INPT) and output and draws a fraction of the nor- rms. This is 3.5 times 63 mV
where VGAIN is expressed in Volts. (OUTP) of the AD8368 should mal supply current. rms. Therefore (1+n)=3.5 and
In addition to showing the be externally AC coupled to The DECL pin should be n=2.5. If we start with R1=100
gain-up and gain-down transfer prevent disrupting the DC lev- decoupled using a large capaci- 7 then R2=250 7. These val-
functions, Figure 2 also shows els on the chip. tor so that DECL acts as an ues can be further adjusted as
the error plot that reflects the As a function of the gain AC ground. The HPFL pin is needed.
deviation between the ideal voltage, the noise and distor- used to control the low-pass The AGC mode of operation
gain control transfer function tion characteristics are easily corner frequency of the out- requires that the correct gain
and real performance. From predicted since the AD8368 put offset correction loop. The direction is chosen. Specifically,
Figure 2, it is clear that the consists of a passive variable high pass corner frequency is the gain must fall as VAGC
gain control transfer function attenuator followed by a fixed inversely proportional to the increases to restore the needed
closely follows the ideal for gain amplifier. The input-re- HPFL bypass capacitor. balance against the set-point.
well over 30 dB. ferred noise increases in pro- Therefore, the MODE pin must
Figure 3 shows the effect of portion to the attenuation AGC Operation be pulled low.
temperature on the gain con- level. Figure 4 shows output As already noted, the AD8368
trol function at 140 MHz. To noise floor, as a function of may be used as an AGC ampli- Received Signal Strength
more closely examine the per- VGAIN for the MODE pin pulled fier, as shown in Figure 5. For Indicator (RSSI)
formance over temperature, the high. In receiver applications, this application, the accurate A valuable feature of using a
slope and intercept of the 25º the minimum NF should occur internal square-law detector is square-law detector is that the
C data is calculated over the at the maximum gain where employed. The output of this RSSI voltage is a true reflec-
linear part of the gain control the received signal presum- detector is a current that varies tion of signal power, and may
range. This provides a sim- ably is weak. At higher levels, in polarity depending on wheth- be converted to an absolute
ple linear model to compare a lower gain is needed, and er the rms value of the output is power measurement for any
with the actual response of the increased NF becomes less greater or less than its internally given source impedance. The
the AD8368. The comparison important. determined “set-point” of -11 AD8368 may be employed as a

8
 777-0$)'%34#/- FEATURE ARTICLE 0!'%s!02),

modulation. At lower symbol

rates it may be necessary to
slow down the response of the
AGC loop by increasing the
value of CDETO .

Conclusion
The AD8368 is a high-per-
formance voltage-controlled
variable-gain amplifier/attenu-
ator with a 34 dB linear-in-dB
gain control range up to 800
MHz. The AD8368 operates
from a supply voltage of 4.5 to
5.5 V and consumes 54 mA of
current. It can be fully powered
down to <1mA by grounding
the ENBL pin. The AD8368 is
fabricated in Analog Devices’
proprietary SiGe SOI comple-
Figure 5: AGC Mode of Operation mentary bipolar IC process.
It is available in a 24-pin CSP
and operates over the industri-
al temperature range of –40º C
to 85º C. An evaluation board
is available upon request.

About the Author

Phillip Sher is a Senior Applications
Engineer with the RFW group at Analog
Devices in Wilmington, MA. He received
a BEng in Electrical Engineering from
Lakehead University in Thunder Bay,
Canada and has more than 9 years of
Engineering experience.

ANALOG DEVICES

Figure 6: Output Power vs. Input Power in AGC Mode at

140MHz.

Figure 7: EVM Performance vs. Input Power in AGC Mode

For 16 QAM at 10 Msym/sec

true-power meter by monitor- for a 16-QAM modulation

ing the voltage present at the at 10MSymbols/sec using
DETO/GAIN interface. CDETO=1000pF. At lower
Figure 7 illustrates the symbol rates the AGC loop
measured error-vector-mag- could start to track the peak
nitude (EVM) performance to peak transitions due to the

9
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10
0!'%s./6%-"%2 FEATURE ARTICLE 777-0$)'%34#/-

Measuring the RF Power in CDMA2000 and W-CDMA High

Power Amplifiers (HPAs)
By Larry Hawkins, Analog Devices, Inc.

Introduction vs. temperature and peak-to-

D
esigners of high-pow- average ratio) to ensure spec-
er amplifiers (HPAs) tral mask and EVM compli-
used in CDMA2000 ance. This makes the accuracy
and W-CDMA base stations of the RF Power Measurement
encounter many challenges System critical to reducing the
in achieving accurate trans- cost and efficiency of an HPA.
mit power measurements. Not only do CDMA2000
Complications include high and W-CDMA modulation
peak-to-average ratios, peak- schemes have large peak-to-av-
to-average ratios that change erage values but also the peak-
with base station call load- to-average value changes with
ing, large operating tempera- the call volume of a particular
ture ranges, and large trans- base station. In CDMA2000
mit power ranges. Taking IS-95A, for example, the for-
advantage of accurate RMS ward link crest factor is 6.6
output power measurement dB for pilot only, and 12 dB
allows HPA manufacturers to for 64 channels (using no CF
reduce the maximum power reduction techniques). Large
for which they design. This Figure 1: The errors in a RMS-responding RF detector peak-to-average values cause
article describes several ways (AD8364) vs. a non-RMS-responding RF detector show the errors in non-RMS-responding
to accurately measure and effect of peak-to-average ratio on power detection. While RF power detectors. A modu-
control RMS power over tem- a non-RMS-responding RF detector (AD8318) exhibits lation scheme’s large peak-to-
perature. significant measurement error as the peak-to-average ratio average ratio can be calibrated
Complex modulation of its input signal varies, an RMS-responding RF detector out in production if it stays
schemes like CDMA2000 and (AD8364) is largely immune to changes in peak-to- constant but variation in the
W-CDMA have large peak-to- average ratio. peak-to-average ratio based
average ratios. For a given on the amount of users is
maximum average-output- more difficult to handle. This
power requirement, the max- requires keeping track of how
imum designed-for power many users are on the system,
requirement will generally tight control of which Walsh
increase (or the linearization codes are being used, and a
requirements increase) as the very large look up table in
peak-to-average value increas- order to know the peak-to-
es, due to base station spectral average ratio of the signal at
mask and EVM requirements. a particular time. A better
If the peaks of the modulated option is the use of a RMS-
signal are clipped, third order responding detector. Unlike
distortion will increase, caus- diode detectors or log amps,
ing the base station to fail its RMS-responding detectors are
spectral mask requirements. largely immune to variations in
Clipping the peaks of a modu- crest factors. Figure 1 shows
lated signal can also cause the error of a high performance
a loss of data, making the Log Amp (AD8318) compared
system fail its EVM require- to that of an RMS-responding
ments. Designing an HPA detector (AD8364) as a result
based on peak power trans- of the crest factor change (user
mission requirements is expen- Figure 2: The Analog Devices AD8364 output voltage and loading) in the TX section of a
sive but necessary. The added log conformance error vs. Pin (@ 450 MHz) shows very CDMA2000 IS-95A base sta-
expenses are due to both an little change when temperature is cycled from –40°C to tion. Note that the AD8318’s
increased cost in the electrical +85°C. This remains true for 30 devices taken from differ- output changes by 3.5 dB (or
components and a decreased ent production lots, even though the performance is slightly 86 mV) between CW and 64
efficiency of the HPA. There different over temperature. channel CDMA2000 IS-95A
is always a $/Watt associated and 2.4 dB between Pilot only
with the maximum designed and 64 channel CDMA2000
for power of an HPA and increases its operating cost. a HPA’s saturation point as IS-95A, while the AD8364’s
running a HPA well below its Reducing the maximum close as possible to the average output only changes by 0.1
saturation point is inefficient. designed-for power of an HPA transmitted power, but these dB (or 5 mV). A diode detec-
A decrease in efficiency will is important to HPA manufac- techniques are all limited by tor behaves similarly to a Log
increase the cost of an HPA turers. The closer an HPA’s the system’s ability to measure Amp, in that its output voltage
module because it increases saturation point can get to the output power. The maxi- changes with respect to the
the cost, size, and weight of its average power, the more mum designed-for power of crest factor of the detected sig-
the mechanical structure used efficient and cost effective the HPA needs to be increased nal. If a Log Amp were used
to dissipate the heat, reduc- the HPA will be. There are by the RF power measurement for power detection in this
es the HPA’s reliability, and many techniques used to get tolerance (including variation system, the 2.4 dB variation

11
0!'%s./6%-"%2 FEATURE ARTICLE 777-0$)'%34#/-

in detected power would need formance is slightly different

to be removed through signal over temperature.
processing or added to the It is not only essential to
maximum designed-for power accurately measure an HPA’s
in the HPA. maximum output power, but
The errors in a RMS- it is also necessary to measure
responding RF detector the output power over the
(AD8364) vs. a non-RMS- entire transmit power range
responding RF detector show of the HPA, though the accu-
the effect of peak-to-average racy at lower power levels
ratio on power detection. is sometimes not as critical.
While a non-RMS-responding However, the accuracy of mea-
RF detector (AD8318) exhib- suring over a large dynamic
its significant measurement range is related to both the
error as the peak-to-average detector and the ADC resolu-
ratio of its input signal var- tion. Figure 3 shows the out-
ies, an RMS-responding RF put of two RMS-responding
detector (AD8364) is largely Figure 3: A comparison of a detector whose output is linear detectors, the AD8364 and
immune to changes in peak- to the input RMS power in dBm (Analog Devices AD8364) ADL5500. The ADL5500 is
to-average ratio. to a detector whose output is linear to the input RMS volts linear in RMS volts to the input
Being able to accurate- (Analog Devices ADL5500) shows the difference in RF signal, and the AD8364 is
ly measure the RMS power dynamic range and emphasizes the necessity of choosing linear in RMS power (dB) to
across the operating temper- an ADC with the proper resolution. the input RF signal. Based on
ature range of the HPA is the requirements for dynamic
also critical in determining the range and accuracy at lower
maximum designed-for power power levels, the required res-
of the HPA. The accuracy olution of the ADC used with
of this measurement (or lack the ADL5500 could be much
thereof) will need to be added greater than it would be for
directly to the maximum the AD8364. System require-
designed-for power, unless the ments will dictate which
difficult and costly process of detector/ADC will provide
calibration over temperature the most cost-effective and
is performed. All components easiest-to-implement solution
involved with the detection of based on accuracy at lower
the HPA’s output power (e.g. power levels and dynamic
directional coupler, attenua- range requirements.
tor, etc.) can add errors over A comparison of a detec-
temperature, but most change tor whose output is linear to
very little over the HPA’s oper- the input RMS power in dBm
ating temperature. Generally, (Analog Devices AD8364) to a
the accuracy of measuring the detector whose output is linear
HPA’s output power over tem- to the input RMS volts (Analog
perature is directly related to Devices ADL5500) shows the
the temperature performance difference in dynamic range
of the detector. In recent years Figure 4: In Controller Mode, the detector determines and emphasizes the necessity
RF detection technology has the power at its input and adjusts a VGA (or variable of choosing an ADC with the
made large strides in creating attenuator) until the detected power coincides with the proper resolution.
devices with responses that are level set by the power control input voltage (VSTA). In some instances, accurate-
very stable over temperature ly controlling the power or
(better than ±.5dB from –40°C gain of a system using an ana-
to +85°C). Figure 2 shows the log feedback loop can improve
temperature performance of the the performance and replace
AD8364 dual RMS-responding simple power detection. Many
power detector. This data was currently offered detectors can
taken at +25°C (black), –40°C control power using an analog
(blue), and +85°C (red) @ 450 feedback loop (i.e. a detector
MHz. It includes voltage and used in Controller Mode) in
error over temperature (after addition to detecting it. If
ambient calibration) vs. input an RMS-responding detector
power for at least 30 devices is used in Controller Mode,
from multiple production lots. power can be set very accurate-
Each part behaves slightly dif- ly vs. input power, temperature,
ferently over temperature. and crest factor. This power
The Analog Devices AD8364 can be set very accurately, and
output voltage and log confor- its level can be changed using
mance error vs. Pin (@ 450 an analog voltage controlled
MHz) shows very little change by an ADC. Using a power
when temperature is cycled Figure 5: When one side of Analog Devices AD8364 dual detector in Controller Mode
from –40°C to +85°C. This RMS-responding detector is used to control the power of a sys- to accurately control the input
remains true for 30 devices tem, the power at the input of the detector (and at Pout) stays or output power of an HPA
taken from different produc- constant vs. input power and temperature (less than ±.1 dB). would be an ideal application,
tion lots, even though the per- as it would remove the need

12
 777-0$)'%34#/- FEATURE ARTICLE 0!'%s./6%-"%2

on one input is equal to the power on the

other. Figure 6 shows a basic schematic
of the AD8364 (dual RMS detector) used
to control the gain of a system. Figure
7 shows the performance of this setup.
Everything that needs to be accurately
controlled should be included between the
two couplers. Note that a VGA, variable
attenuator, or even the bias of the HPA can
be used to control the gain. If the control
levels between the detector and VGA are
set properly and power levels are properly
designed for, the usable input power range
will be close to the detectable power range
of the detector (60 dB, in the case of the
AD8364).
Figure 6: When both inputs of a dual detector are used in Controller Mode, the When both inputs of a dual detector
detector will control a VGA (or VVA, etc.) in such a way as to equalize the power it are used in Controller Mode, the detector
detects at both RF inputs. The gain of the system will be determined by the will control a VGA (or VVA, etc.) in such
couplers and attenuators used to set the power being detected by the dual detector. a way as to equalize the power it detects
at both RF inputs. The gain of the system
will be determined by the couplers and
attenuators used to set the power being
detected by the dual detector.
When both inputs of Analog Devices
dual RMS detector (AD8364) are put in
Controller Mode, the gain is controlled
to better than ±.15 dB vs. temperature
and input power, with a dynamic range
almost equal to the dynamic range of the
RMS detector.
Many of the challenges associated
with RF power detection for HPAs used
in CDMA2000 and W-CDMA systems
can be solved using RMS-responding RF
detectors. Variations in detected power
due to large peak-to-average values that
change with base station loading, large
operating temperature ranges, and large
transmit power ranges are now manage-
Figure 7: When both inputs of Analog Devices dual RMS detector (AD8364) are able. New ways to control power and
put in Controller Mode, the gain is controlled to better than ±.15 dB vs. tempera- gain accurately enough to remove the
ture and input power, with a dynamic range almost equal to the dynamic range need for detect power are now available.
of the RMS detector. All of these things allow HPA manufac-
turers to reduce the cost and improve the
reliability of their HPAs.
to detect the input or output power. In (60 dB, in the case of the AD8364).
Controller Mode the detector determines In Controller Mode, the detector deter- ANALOG DEVICES
the power at its input and adjusts a VGA mines the power at its input and adjusts
(or variable attenuator) until the detected a VGA (or variable attenuator) until the
power coincides with the power set by detected power coincides with the level
the Power Control input voltage. Figure set by the power control input voltage
4 shows a basic schematic of an RMS- (VSTA).
responding detector (AD8364) used in When one side of Analog Devices
Controller Mode to control the output AD8364 dual RMS-responding detector is
power. Figure 5 shows the overall cir- used to control the power of a system, the
cuit performance vs. input power and power at the input of the detector (and at
temperature when the VGA is controlled Pout) stays constant vs. input power and
by one side of an AD8364 (dual RMS- temperature (less than ±.1 dB).
responding log detector). Note that an A dual RMS-responding detector oper-
HPA can be put between the VGA and ating in Controller Mode can also be
coupler as long as the power level is set used to control the gain of an HPA very
correctly into the AD8364, and that any accurately vs. input power, temperature,
VGA (or variable attenuator) can be used and crest factor. If the gain of an HPA
if the control voltages are set properly module is controlled with enough accuracy
between it and the AD8364 (an op-amp over input power, temperature, and crest
may be needed to invert and/or level shift factor, the HPA module’s output power
the control voltage). If the control levels would not have to be reported but would
between the detector and VGA are set be directly related to the power feeding it.
properly and power levels are properly If both inputs of a dual detector are put in
designed, the power control range/usable Controller Mode, the detector determines
input power range will be close to the the power at each input and adjusts the
detectable power range of the detector gain of a VGA until the power detected

13
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14
 Semiconductor Highlight 23

by Michael Sink and Pamela Aparo,

Analog Devices
ADCs

Simulating the Effect of Blockers

on Data Converter Performance
in Wideband Receivers
input range. Large-scale blockers

M
any different standards for
wireless communications increase the amplitude of the received
equipment are in use today. signal, limiting the amount of gain that
Narrowband communication standards can be applied before saturating the
use stronger transmission in a small input of the ADC. In-band blockers
slice of bandwidth. Wideband stan- effectively limit the amplitude of the
dards use lower transmission power desired signal. If no blocker was pres-
across a larger bandwidth. Each stan- ent more gain could be applied to the
dard defines minimum performance signal to help overcome the noise floor
characteristics for receivers, and of the ADC.
includes specifications such as band- 2) Nonlinearities within the ADC
width, maximum signal level, and sensitivity. Figure 1. Receiver block diagram. will create intermodulation distortion products
GSM is one narrowband example; the channel within the desired signal band, thus negatively
bandwidth is 200 kHz. A GSM receiver must • Antenna. Selective to the spectrum of impacting spurious free dynamic range (SFDR)
have a minimum sensitivity of –104 dBm and interest — this provides some attenuation for performance. Intermodulation distortion occurs
be able to tolerate a –13 dBm signal at the out-of-band interference. when two frequencies mix together and create
antenna. In contrast, CDMA2000 is a wide- • Down-conversion. Translates the received signals at the sum and difference of the input
band standard that uses a 1.25 MHz band- signal to a lower frequency that can be ampli-
width. CDMA2000 receivers need to have a fied and converted to digital information. This
minimum sensitivity of –117 dBm/1.25 MHz can be accomplished with one or two mixing
and tolerate a maximum signal of –30 dBm at stages. A single mixer stage can reduce the sig-
900 kHz offset.1 nal’s center frequency from a few gigahertz to a
Wideband and narrowband communication couple hundred megahertz. A second mixer
standards can overlap in the crowded RF spec- stage can translate the signal down to tens of
trum, making it even more challenging to megahertz. Using a single mixer stage saves
design receivers that are immune to interfer- board space and the expense of the second
ence. Narrowband receivers can use narrow PLL, VCO, and filter. However, the higher IF
bandpass filters to remove interference, allow- requires an amplifier and analog-to-digital
ing them to amplify and then digitize only the converter (ADC) with very good performance
channel of interest. Unfortunately, designers of at high frequencies.
wideband and multicarrier receivers cannot use • VGA. A variable-gain amplifier is used to
this solution, because channel selection is per- adjust the gain of the circuit depending on the
formed after the signal is digitized. Therefore, received signal strength. Figure 2. ADC performance comparison between CDMA2000 input and
the entire spectrum must be digitized as cleanly • Anti-aliasing filter. Attenuates signals out- CDMA2000 input with blocker.
as possible to allow the digital signal processor side the band of interest.
(DSP) to remove the blockers in the digital Large-scale blockers interfere with convert- frequencies. For example, applying two tones to
realm. Wideband receivers must tolerate large ing the desired signal in two ways: the input of an ADC where F1=50 MHz and
narrowband signals within the band of interest 1. An ADC’s input range is specified as some F2=52 MHz, will create new signals at 2 MHz
without degrading the sensitivity of the receiver. amplitude, typically 1V or 2V peak-to-peak or (F1–F2), 102 MHz (F1+F2), 54 MHz (2F2–F1),
Although they cannot use filters to remove in- in terms of dBm. This input range limits how 48 MHz (2F1–F2), and so on. The amplitude of
band interference, wideband and multicarrier much gain the VGA can apply to the signal these new signals depends on the linearity of the
receivers will use Nyquist filters to remove out- before the ADC starts to distort or clip. An rms ADC and the amplitude of the input signals.
of-band interference. detector or log-amp is frequently used to The same phenomenon happens when a large
In the block diagram of a receiver (Figure 1), determine the amplitude of the composite sig- in-band blocker mixes with another blocker or
the analog portion of the receive signal chain nal, thus determining how much gain the VGA the desired signal. New signals, which can be
consists of: should apply in order to use the ADC’s full very close to the signal of interest, are created.

www.ECNmag.com • 09/2007
15
24 Semiconductor Highlight ADCs

Knowing these blockers can cause problems in calculate the effect of the ADC’s SNR and SFDR
receiver sensitivity, how does the engineer know on receiver sensitivity, the datasheet may not
that a design will meet the required specifications? specify ADC performance at the desired sample
There are a couple ways to do this (aside from trial rate and input frequency. New simulation soft-
and error). The ADC’s signal to noise ratio (SNR) ware makes it possible to quickly and easily eval-
and SFDR performance can be used to calculate uate different ADCs with real-world signals, ulti-
the effect of in-band blockers on a receiver. The mately reducing design risk.
ADC performance will be specified for different
sample rates and input frequencies, which may References
1
not match your application. These specifications AN-808 “Multicarrier CDMA2000 Feasibility”, Brad
are measured with pure sine wave inputs as Brannon and Bill Schofield. ©2006
opposed to the signals received from an antenna.
Alternatively, a software package such as Analog “Correlating high-speed ADC performance to multi-
carrier 3G requirements”, Brad Brannon, RF Design,
Devices’ (ADI) VisualAnalog can simulate ADC
June 2003, pp. 22-28.
performance with a real-world waveform and any
sample rate. Pamela Aparo is a marketing manager in the
Figure 3. VisualAnalog canvas used to analyze the effect of a blocker
The tool’s drag-and-drop GUI allows circuit High Speed Converters Group at Analog Devices,
on ADC performance.
creation from functional blocks. It can create Inc. Pam has worked in marketing and applications
complex waveforms, import waveform data, and VisualAnalog canvas to evaluate the AD9246, a roles with ADI for seven years. Prior to ADI, she
customize FFT analysis to quickly determine if a 14-bit 125 Msps ADC. By creating a signal similar applied her engineering degree to medical applica-
specific ADC will meet the performance specs for to a CDMA2000 waveform with and without an tions working for Baystate Medical Center and OEC
a given communication standard. ADI’s ADC in-band blocker we can use the tool to analyze Medical Systems. Pam earned a BSEE from the
models account for the effects of clock jitter, tran- the ADC’s performance. This same canvas file University of Connecticut. Michael Sink is an appli-
sitions between stages inside the part, the droop (Figure 3) can be easily modified to accept anoth- cations engineer in the High Speed Converters Group
rate of the sample and hold capacitors of the er waveform (W-CDMA, GSM900) or evaluate a at Analog Devices. He has been with ADI for five
ADC input, and ultimately the SNR and SFDR different ADC using another ADC model. years. Michael earned a BSEE from North Carolina
performance over frequency and sample rate. State University. For more information, contact
Using this tool, ADC performance can be simu- Conclusion Analog Devices, One Technology Way, Box 9106,
lated with any input signal — including a com- Wideband communication standards such as Norwood, MA 02062-9106; (800) 262-5643;
plex waveform like CDMA2000. CDMA2000 require receivers that can tolerate www.analog.com.
Figure 2 shows the results of using a large in-band blockers. Although it is possible to

As seen in the September 2007 issue of ECN magazine

16
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RF Bonus Feature

TruPwr™ RMS Power Detectors

Features
Industry’s first patented RF true power detectors
Innovative line of TruPwr rms responding detectors
with frequency ranges from >dc to 6 GHz
Immune to crest factor changes enabling
modulation-independent true power detection
Single- and dual-channel rms detectors with
linear-in-volts or linear-in-dB outputs

Part RF Frequency Dynamic Output Response Temp Stability Supply Supply

Package Comments
Number (MHz) Range (dB) Response Time (dB) Voltage (V) Current (mA)

320 ns 0.25 2.9 mm 2.8 mm, Low power, low cost rms
AD8361 100 to 2500 30 Linear-in-volts 2.7 to 5.5 1
6-lead SOT-23 detector

AD8362 >0 to 3800 60 Linear-in-dB 45 ns 1.0 4.5 to 5.5 20 5 mm 6.4 mm, Wireless infrastructure
16-lead TSSOP

AD8363 >0 to 6000 >50 Linear-in-dB 0.5 4.5 to 5.5 66 4 mm 4 mm, Broadband
8 s
16-lead LFCSP

AD8364 >0 to 2700 60 Linear-in-dB 45 ns 0.5 4.5 to 5.5 70 5 mm 5 mm, Dual-channel rms detector
32-lead LFCSP

AD45102 50 to 3800 60 Linear-in-dB 45 ns 1.0 4.5 to 5.5 20 5 mm 6.4 mm, Operation to 125°C
16-lead TSSOP

6 s 2 mm 2 mm, Reduced size, improved

ADL5501 50 to 4000 30 Linear-in-volts 0.25 2.7 to 5.5 1.1
6-lead SC70 temperature stability

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24
 COMMUNICATIONS SPECIAL

Improved DDS devices enable

advanced comm systems
Today’s DDS ICs offer drastically reduced power dissipation and size
90 dBc) make DDS a more attractive to diffract specific wavelengths of
BY VALOREE YOUNG
solution. light from the incoming spectrum.
Analog Devices
DDS devices are excellent RF drivers
Greensboro, NC
http://www.analog.com
I/Q generation for exciting crystals within an AOTF,
For applications requiring in-phase due to the high resolutions attain-

D
irect digital synthesis (DDS) and quadrature (I and Q) generation, able. Precise frequency switching im-
has come a long way since DDS offers unparalleled matching of plemented by the DDS involves very
the days when implementa- I and Q outputs. By using DDS to little latency and no settling time.
tions were limited to complex, cost- send quadrature signals to the I/Q An on-chip clock multiplier offers
ly designs that consumed large inputs of an analog modulator, the phase noise performance sufficient
amounts of power. Today’s DDS ICs redundant sideband can be attenuat- for AOTF applications, and easy syn-
offer drastically reduced power dissi- ed significantly, relaxing the nor- chronization of additional multi-
pation and size—as well as greatly mally tight filtering requirements. channel chips is possible. Operating
improved phase noise, spurious per- To further simplify this approach, at a maximum system rate of 500
formance, and ease of use—making new two-channel DDS chips provide Msamples/s, a four-channel DDS de-
them attractive alternatives to ana- inherent synchronization across vice produces output frequencies
log synthesis in many communica- channels while maintaining excellent from dc to 250 MHz in steps of about
tions systems. DDS devices now of- isolation between them. Independent 116 mHz, with each DDS channel
fer many levels of integration, frequency, phase, and amplitude con- consuming less than 165 mW.
performance, packaging, and cost trol on each channel provides flexibil-
benefits, allowing customized and ity to correct imbalances between Military systems application
easy selection into new designs. quadrature signals. In Fig. 1, two syn- Military communications, electronic
The primary advantages of using a chronous DDS channels generate digi- countermeasures, and communica-
digital synthesizer over traditional tal I and Q
analog solutions are fast frequency data which is Modular
hopping, extremely fast switching then upcon- Data(I)
speeds with virtually no settling verted using a CH0 LPF
time, finer tuning resolution, and modulator. RF out
2-Channel
channel flexibility. Designers requir-
ing agile frequency sources with ex- Optical
DDS LO 0º/90º +
AD9958
cellent phase noise and low spurious systems
performance often choose DDS. With channel CH1 LPF
Available DDS ICs now support in- bandwidth at Data(Q) AD8349
ternal speeds of 1 Gsample/s, pro- a premium in ADL537x
vide outputs up to 400 MHz, and in- optical net- Fig. 1. A two-channel DDS provides precise, synchronous
clude a high-performance 10-, 12-, working sys- control for in-phase and quadrature data generation.
or 14-bit DAC. With 48-bit frequen- tems, packing
cy tuning, 14-bit phase tuning, and more functionality into a smaller tions surveillance applications de-
10-bit amplitude scaling, extremely space is increasingly desirable and a mand exceedingly fast switching
fine resolution (1 μHz, 0.022°, and 3 single-chip, four-channel DDS IC of- speeds. Traditionally, the challenge
mV) is attainable. fers clear benefits. has been to achieve this without
Once viewed as power-hungry Acousto-optics, a technique often compromising frequency resolution.
monsters, some DDS cores now applied in optical communication The AD9910, from Analog Devices,
boast power consumption less than systems, uses the relationship be- is a 1-Gsample/s DDS with an inte-
165 mW at 400 Msamples/s. A phase tween vibrations and light to target grated 14-bit DAC. 32-bit frequency
noise floor below –150 dBc/Hz at up an optical wavelength. During opti- tuning translates to 0.23-Hz tuning
to 100 MHz is possible, and im- cal transmission, devices such as the resolution.
provements in wideband SFDR (>55 acousto-optic tunable filter (AOTF) The incredibly fast parallel data
dBc) and narrowband SFDR (80 to use a slight adjustment in frequency port, used for writing frequency tun-

ELECTRONIC PRODUCTS http://electronicproducts.com SEPTEMBER 2006 69

25
 COMMUNICATIONS SPECIAL -
IMPROVED DDS DEVICES ENABLE ADVANCED COMM SYSTEMS

Antenna
ple/s DDS core, a high
AD8349
(a) AD9779 ADL537x performance 14-bit
I
D/A DAC, clock multiplier
DUC
DSP for
multiple
Digital
Filtering
0/90 + Amplifier
Components circuitry, digital filters,
carriers
D/A and other DSP func-
Q
tions onto a single
Clock
PLL/VCO
chip.
Distribution
This solution offers
AD9857
cost, power, and space
(b) Antenna
AD9957 savings, while provid-
I ing excellent dynamic
D
DSP
E
+ Amplifier performance. Figure 2
M 0/90 D/A Components
U shows architecture op-
X Power
Q Ramp tions for single analog
Profile
upconversion using
Clock
PLL/VCO
two different ap-
Distribution
proaches.
Fig. 2. Upconversion schemes can use a dual TxDAC Implementing a
(a) or DDS-based modulator (b). QDUC in the trans-
mission path avoids
ing word changes, allows the DDS IC quadrature phase and amplitude im-
to take a 16-bit word every 4 ns. The balance issues. In addition, only one
device offers a 14-bit phase offset mixer and one DAC are required, so
word, a 1,024-element RAM, a linear- the overall noise will be reduced.
sweep block, and other features. The QDUC supports real outputs up
In systems needing to synthesize to 400 MHz. A 250-MHz 18-bit-wide
specific frequencies with very low data input port supports interleaved
spurious components, a recently data rates as high as 125 Msymbols/s,
developed implementation uses and innovations in low-power DDS
auxiliary DDS channels to reduce cores have brought power down to
the magnitude of harmonic spurs in about 1 W at 1 Gsample/s.
the output spectrum. This spur re-
duction approach extends the im- Portable devices
plementation to designs demand- Designers of portable and handheld
ing better wideband SFDR (spurious wireless systems should note the
free dynamic range) performance drastic reduction in power consump-
than was previously attainable by a tion. DDS ICs consuming less than
DDS. 50 mW are typically offered at fre-
In fact, a 12-dB improvement of a quencies of 50 MHz or lower.
single spur can be seen at 200 MHz. Some higher-speed DDS devices
The technique is beneficial to cur- running at up to 250 Msamples/s are
rent DDS users in reducing the tire- now approaching 50-mW power lev-
some task of frequency planning els. These cores are even being used
and in eliminating the need for a as auxiliary components, performing
complex filter design. tasks such as multitone generation
The AD9912 showcases this spur and spur reduction within highly in-
reducing concept, and includes an tegrated complete DDS devices.
on-chip comparator for generating a
square wave output for clock genera- Other communication apps
tion applications. Extremely fine Clock generation applications also
tuning resolution of 3.5 μHz on out- reap the benefits of multipurpose
puts up to 400 MHz is made possible DDS functionality, since the ability
by a 48-bit frequency tuning word. to generate a clean, stable clock is vi-
tal in many systems.
Cellular base station benefits As advances in SFDR performance
In base station transmit architectures and power consumption continue,
that employ a direct-IF approach to DDS will expand into markets that
upconversion, DDS-based modula- were previously off limits. Its role
tors offer an alternative to traditional as a standalone function will
dual-DAC direct-conversion solu- evolve to recognize its potential as
tions. A quadrature digital upcon- a building block in other more
verter (QDUC) integrates a 1-Gsam- complex chips. 

70 ELECTRONIC PRODUCTS http://electronicproducts.com SEPTEMBER 2006

26
 RF / MICROWAVE SPECIAL

RF standards for short-range

New standards provide optimized solutions for the differing
needs and priorities of different applications
BY MARY O’KEEFFE
Analog Devices, Norwood, MA
http://www.analog.com

T
he term “short-range device”
(SRD) refers to a device capable
of wireless communications
over a relatively short distance—
from just a few centimeters up to a
few kilometers. Several wireless stan-
dards defining the communications
processes for such devices exist, with
new standards continuing to evolve.

Constraints
Governments impose restrictions on
the use of the frequency spectrum.
Figure 1 shows the UHF (300-MHz to
3-GHz) ISM unlicensed frequency
bands available in different parts of
the world.
As the figure shows, no common
unlicensed ISM band is available be-
low 2.4 GHz, although some RF
transceivers will support operation
across several of these sub-1-GHz
bands. The Analog Devices
ADF7020/-1, for example, supports
operation from 135 to 950 MHz.
Many designs use proprietary com-
munications protocols in this fre-
quency range.
Despite the inherent range advan-
tage of the lower-frequency bands,
the global nature of the 2.4-GHz
band makes it attractive for many
SRD communications protocols such
as Bluetooth, WLAN and ZigBee. Ir-
respective of the communications
protocol used, countries apply addi-
tional constraints driven by factors
such as safety and quality of perfor-
mance; these constraints are required
to limit interference between differ-
ent equipment. Some examples rele-
vant for the 2.4-GHz band are shown
in Table 1.

Existing standards
The various communications proto-
cols each offer advantages and disad-
vantages, with the optimum choice

ELECTRONIC PRODUCTS http://electronicproducts.com NOVEMBER 2007

27
 RF STANDARDS FOR SHORT-RANGE WIRELESS CONNECTIVITY

wireless connectivity

Fig. 1. Several UHF

(300-MHz to 3-GHz)
ISM unlicensed
frequency bands are
available in different
parts of the world.

depending on the application. Blue- power ZigBee device. Other factors

tooth, for example, offers data rates that differentiate the various stan-
up to 3 Mbits/s, whereas 802.11g en- dards include latency and resilience.
ables data rates as high as 54 Mbits/s
and ZigBee is limited to 250 kbits/s. Developing standards
While 802.11g has the higher data The industrial environment is one
rate, it also has higher cost and high- where resilience is of particular value.
er power consumption. ZigBee has The recently ratified Wireless Hart
the advantage of low power con- standard is targeted at the industrial
sumption. It can also support a high space. The SP100 group is also look-
number of nodes. For example, Blue- ing at a standard for industrial appli-
tooth’s maximum of 8 nodes in a net cations.
could be a limiting factor in an in- Both the Wireless Hart standard
dustrial application. and the ISA-SP100.11a standard,
For sensor applications, where which is in development, indicate
only a limited amount of data must the use of an 802.15.4-compatible ra-

Table 1. Worldwide communication standards

Region Standard Relevant Link
Europe ETSI EN 300 328 http://www.etsi.org/WebSite/
ETSI EN 300 440 homepage.aspx
USA FCC CFR47 part 15 http://www.access.gpo.gov/nara/cfr/
waisidx_04/47cfr15_04.html
Japan ARIB STD-T66 http://www.arib.or.jp/english/

be transferred and low power con- dio. The 802.15.4 radio also consti-
sumption is of significant value, Zig- tutes the physical layer for the Zig-
Bee appears to have an advantage Bee standard.
over Bluetooth or WLAN. For appli- While several short-range device
cations such as wireless headsets, the standards are already in existence,
data rate offered by Bluetooth meets new standards are continuing to
the requirements while maintaining evolve. These are driven by and tar-
a relatively low cost. geted at providing optimized solu-
The Wibree standard currently in tions for the differing needs and pri-
development can operate in a stand- orities of different applications. N
alone mode or as a complement to
Bluetooth, offering a lower-power so- For more on RF ICs and RF
lution than Bluetooth and a maxi- standards, visit
mum data rate of 1 Mbit/s. This is a www.electronicproducts.com/
higher data rate than ZigBee, but its linear.asp
range would be shorter than a low-

28
 A BROADBAND
I/Q MODULATOR
FOR BROADBAND
RADIO DESIGNS

M
odern digital radio transmitter design critical. Minimizing gain variations in the sig-
poses increasing challenges for nal chain over frequency eases the burden of
equipment designers. The ongoing signal chain planning and budgeting. This arti-
trend towards increased throughput of data is cle focuses on I/Q modulators, which are a
increasing the modulation density and carrier critical component in modern transmitters.
bandwidths of transmitted signals. Peak-to-av-
erage ratios increase with higher order modu- A BROADBAND I/Q MODULATOR
lation schemes and to maintain good adjacent I/Q modulators perform the frequency
channel power ratio (ACPR) while transmit- translation that mixes the baseband signal to
ting the same rms power level, components the desired location in the RF spectrum. An
with lower intermodulation distortion and I/Q modulator consists of a local oscillator
lower noise must be used. (LO) input that is split into in-phase (I) and
Fig. 1 The ADL5385 I/Q Baseband, IF and RF bandwidth must be quadrature (Q) components that are separated
modulator’s basic block flat across the channel to maintain the spectral
diagram. ▼
by 90°. These two signals drive separate mixers
shape of the modulated carrier. that are also driven by I and Q baseband sig-
ENBL Furthermore, if digital pre-dis- nals. The outputs from both mixers are then
Temperature tortion techniques are being summed to provide a modulated carrier either
BIAS TEMP
IBBP Sensor used then the higher order har- at RF or IF. The ADL5385 contains these ba-
monics need to be passed sic blocks (see Figure 1) and is able to
IBBN through the baseband inputs achieve a wide tuning range that spans five oc-
and gain flatness must be main- taves (50 MHz to 2.2 GHz) through the use of
LOIP Divide-by-2
Quadrature
tained up to the higher order an active divide-by-two LO splitter instead of
VOUT
LOIN
Phase harmonics of the baseband sig- the more traditional passive polyphase filter.
Splitter nal. When a radio transmitter Its wideband performance can be seen in
QBBP design calls for operation over a
very wide range of RF frequen-
QBBN cies the RF gain flatness of the ANALOG DEVICES INC.
overall signal chain becomes Norwood, MA

Reprinted with permission of MICROWAVE JOURNAL® from the September 2006 issue.
©
2006 Horizon House Publications, Inc.

29
 P RODUCT F EATURE
Figure 2, where the output power be gauged by observing the level of range, allows the modulator to be
has a very flat response over the en- sideband suppression in a single-side- used without factory calibration.
tire output frequency range, with a 1 band spectrum. Figure 2 shows that This can significantly reduce the
dB bandwidth of 1300 MHz. This the native uncompensated sideband time and effort required for design
new modulator is designed to directly suppression of the ADL5385 I/Q mod- and manufacturing.
drive a 50 Ω load and also includes an ulator is better than –38 dBc out to
integrated temperature sensor. 900 MHz. This level of sideband sup- DIVIDE-BY-TWO SPLITTER
pression typically yields EVM perfor- ENABLES BROADBAND
GAUGING SIGNAL QUALITY mance that is more than acceptable for OPERATION
USING ERROR VECTOR most communication standards. If Systems such as cable modem head
MAGNITUDE higher performance is required, side- end equipment must be able to dy-
Error vector magnitude (EVM) is a band suppression can be optimized by namically place carriers anywhere in
measure of the quality of modulation adjusting the relative gain and phase of the the 40 to 900 MHz range. Tradi-
of a signal and it is directly affected by the baseband signals. tional modulators that use a passive re-
the quadrature and amplitude errors The 64QAM constellation, eye-di- sistor-capacitor polyphase network to
within the modulator. The amount of agram and spectrum, shown in Fig- split the LO into quadrature compo-
quadrature and amplitude errors can ure 3, was generated using random nents have generally been unable to
data at 5.056941 MSym/s with a filter span such a wide frequency range.
alpha of 0.18. This closely mimics the This is because the resistor-capacitor
−40°C Output Power
+25°C Output Power data rate and modulation for a typical networks are tuned for a particular
+85°C Output Power cable modem head end application. center frequency and typically have a
−40°C Carrier Leakage
+25°C Carrier Leakage
It can be seen that the EVM for this useful range of just over two octaves.
+85°C Carrier Leakage signal is 0.33 percent rms with a Traditional cable modem headend
−40°C Undesired Sideband Suppression quadrature error of 0.27° and a gain equipment designs use a two-stage up-
+25°C Undesired Sideband Suppression
+85°C Undesired Sideband Suppression
error of 0.003 dB. conversion. The baseband signal is up-
10
converted using an I/Q modulator to
SIGNAL QUALITY
Output Power and Carrier Feedthrough (dBm)

an IF frequency above the cable band,

VS. POWER LEVEL typically around 1100 MHz. This IF
Undesired Sideband Supression (dBc)

−10
Figure 4 shows how ACPR varies signal is then mixed down into the ca-
with output power for the same ble band using a mixer. These solutions
−20 64QAM modulated carrier. The high require more components and the
−30
OIP3 of the ADL5385 I/Q modulator complexity associated with such de-
enables it to achieve high output
−40 power levels with minimal adjacent −55

−50
channel leakage. This results in less
−60
gain required in the subsequent
ACPR (dBc)

−60 stages of the radio. −65

0 400 800 1200 1600 2000
Output Frequency (MHz)
The displayed performance was
obtained without digital compensa- −70
▲ Fig. 2 Single-sideband performance vs. tion of the baseband data. This,
−75
output frequency from –40° to +85°C. along with the wide RF tuning
−80
−18 −14 −10 −6 −2 2
CHANNEL POWER (dBm)

▲ Fig. 4 64QAM ACPR vs. output power

(symbol rate = 5.056941 MSym/s with a filter
alpha of 0.18, adjacent channel bandwidth =
5.25 MHz).

D I

LO
I

D Q

I
Q
Q

▲ Fig. 5 The ADL5385 modulator’s

divide-by-two phase splitter showing the
applied LO at twice that of the desired LO
▲ Fig. 3 The spectrum, constellation and eye-diagram of a 64QAM carrier at 350 MHz. frequency in the mixer.

30
 P RODUCT F EATURE
and its inversion. In the ADL5385 The ADL5385 offers a 0.1 dB base-
2 the inversion is achieved by crossing band gain flatness out to 85 MHz.
FREQUENCY RESPONSE (dB)
NORMALIZED BASEBAND

1 the polarities of the inputs on one of This means that for most applica-
0 the differential D-flip-flops. The I tions, there should be no need to per-
−1 and Q signals that drive the mixer form any sort of precompensation.
−2
cores shown in the ADL5385 block
diagram are generated through the A SEAMLESS INTERFACE
−3 TO BASEBAND I/Q DACS
alternate clocking of the D-flip-flops
−4 by the two LO input signals. Close in- The ADL5385 is designed to in-
−5 spection of the timing diagram on the terface seamlessly with Analog De-
6 126 246 366 486 606 726 846
BASEBAND FREQUENCY (MHz)
left of the figure will reveal that it is vices’ family of transmit digital-to-
imperative that the applied LO signal analog converters (TxDAC). The in-
be at twice the desired RF output terface between the two devices
▲ Fig. 6 The ADL5385 baseband section’s frequency and that the duty-cycle of typically involves six resistors and a
normalized frequency response.
that LO signal be exactly 50 percent. simple LC filter (see Figure 7). The
Any deviation from 50 percent will four 50 Ω resistors shunting to
AD9779 ADL5385 degrade the 90° split and this will in ground from each of the DAC out-
IOUTA1 IBBP turn degrade sideband suppression. puts provide the 500 mV DC bias for
Optional
Low Pass
the ADL5385 baseband inputs while
IOUTB1 Filter IBBN
WIDE BASEBAND BANDWIDTH the 100 Ω resistor in shunt between
INCREASES DATA CAPACITY each differential pair sets the AC
In single-channel modulation sys- swing of the baseband inputs. With
IOUTB2 QBBN
Optional tems, data capacity can be increased this simple interface the need for sin-
Low Pass by either using a higher order modu- gle-ended-to-differential or level-
IOUTA2 Filter
QBBP lation scheme or by using more band- shifting amplifiers is eliminated.
width. Figure 6 shows the normal-
ized baseband frequency response of PACKAGE, AVAILABILITY,
▲ Fig. 7 AD9779 and ADL5385 interface
the ADL5385. With wider carrier EVALUATION BOARDS
schematic.
bandwidths, the challenge is to main- The ADL5385 is packaged in a
signs increases the design time and ef- tain a flat gain across the bandwidth RoHS-compliant 24-lead LFCSP
fort. System cost and complexity can of the carrier. This ensures that the with exposed paddle. Samples and
clearly be reduced if this signal chain spectrum is not distorted by gain rip- evaluation boards are currently avail-
could be simplified to a single-stage di- ple. If the gain ripple is too great able and may be ordered on the com-
rect launch architecture. then precompensation might be re- pany’s web site.
The ADL5385 overcomes the two- quired in the digital domain. This
octave limitation of traditional I/Q process will require the characteriza-
modulators by utilizing a divide-by- tion of the frequency response of Analog Devices Inc.,
two LO splitter. This architecture is every radio and will increase the Norwood, MA
illustrated in Figure 5, where two D- complexity of the design and drive up (781) 329-4700,
flip-flops are clocked by an LO signal the cost to manufacture the radio. www.analog.com.

31
RF Bonus Feature

RF/IF Amplifiers
Features
Broadband and narrow-band Internal active bias
RF/IF amplifiers Most amplifiers internally
High linearity and output matched to 50
power Low power consumption
Fully characterized Small footprint packages
over frequency range,
temperature and power
supply variation

Part RF Frequency Gain Output Output Noise Supply Supply Specs

Package Comments
Number (MHz) (dB) P1dB (dBm) IP3 (dBm) Figure (dB) Voltage (V) Current (mA) @ (MHz)
1
AD8353 1 to 2700 19.5 9 22.8 5.6 2.7 to 5.5 42 900 2 mm 3 mm, 8-lead LFCSP Gain block

AD83541 1 to 2700 20 5 19.3 4 2.7 to 5.5 23 900 2 mm 3 mm, 8-lead LFCSP Gain block

ADL5320 400 to 2700 17 25.4 45 4 4.75 to 5.25 104 880 4.25 mm 4.6 mm, Driver
3-lead SOT-89
ADL5321 2300 to 4000 14 25 40 4 4.75 to 5.25 84 2600 4.25 mm 4.6 mm, Driver
3-lead SOT-89
ADL5322 700 to 1000 20 28 45 5 4.75 to 5.25 320 880 3 mm 3 mm, 8-lead LFCSP Matched driver

ADL5323 1700 to 2400 19.5 28 43.5 5 4.75 to 5.25 320 2140 3 mm 3 mm, 8-lead LFCSP Matched driver

ADL55211 400 to 4000 15 22.5 35 0.82 3.0 to 5.25 65 1950 3 mm 3 mm, 8-lead LFCSP Single LNA
1 2
ADL5523 400 to 4000 17.5 22 36 1 3.0 to 5.25 65 1950 3 mm 3 mm, 8-lead LFCSP Single LNA

ADL55301 DC to 1000 17 22 37 3 3.0 to 5.5 110 190 3 mm 2 mm, 8-lead LFCSP Matched IF amplifier

ADL5531 20 to 500 21 20.4 41 2.5 4.75 to 5.25 100 70 3 mm 3 mm, 8-lead LFCSP Matched IF amplifier

ADL5534 20 to 500 19.4 20 40 2.7 4.75 to 5.25 180 190 5 mm 5 mm, 8-lead LFCSP Dual ADL5531
Broadband matched
ADL5541 50 to 6000 15 20 44 3.5 4.5 to 5.5 90 500 3 mm 3 mm, 8-lead LFCSP gain block
Broadband matched
ADL5542 50 to 6000 19.5 20.6 46 2.8 4.5 to 5.5 93 500 3 mm 3 mm, 8-lead LFCSP gain block
1
ADL5570 2300 to 2400 29 31 — — 3.2 to 4.2 130 2350 4 mm 4 mm, 16-lead LFCSP WiMAX power amplifier

ADL55711 2500 to 2700 29 31 — — 3.2 to 4.2 130 2600 4 mm 4 mm, 16-lead LFCSP WiMAX power amplifier
1
3 V bias supported.
2
NF includes external input match.

32
 3IGNAL0ROCESSING

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RF Bonus Feature

High Frequency ADC Drivers

Features
Low distortion, fully differential amplifiers
Range of adjustable and fixed gain devices
Drive high resolution (12-bit to 16-bit) analog-to-digital
converters (ADCs) at high speed (100 MHz)
Small footprint packages, single- and/or dual-supply

Distortion Noise Supply

Part Bandwidth @ Gain Output IP3 Input Noise Supply
2nd (dBc) Figure Current Package Comments
Number –3 dB (MHz) (dB) (dBm) (nV/√Hz) Voltage (V)
3rd (dBc) (dB) (mA)
–65/–66 28 3.1 mm 5.05 mm,
AD8350-15 900 15 6.8 1.7 4 to 11 28
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–66/–66 28 3.1 mm 5.05 mm,
AD8350-20 700 20 5.6 1.7 4 to 11 28
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2200 –79/–81 31 3 mm 4.9 mm, Gain adjustable with
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ADA4938-1/ –82/–82 16-lead LFCSP differential output or
1000 Adjustable — 15.8 2.6 5 to 5 37
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25 dB isolation between channels

Part Number I/O Configuration Input:Outputs 1 dB Bandwidth (MHz) Max Gain (dB) CSO (dBc) CTB (dBc) Noise Figure (dB) Package

ADA4302-4 Differential 1:4 900 5.7 –73 –66 4.4 3 mm 3 mm, 20-lead LFCSP

ADA4303-2 Single-ended 1:2 1200 4 –62 –72 4.4 3 mm 3 mm, 12-lead LFCSP

ADA4304-2 Single-ended 1:2 1000 3 –62 –72 4.6 3 mm 3 mm, 16-lead LFCSP

ADA4304-3 Single-ended 1:3 1000 3 –62 –72 4.6 3 mm 3 mm, 16-lead LFCSP

ADA4304-4 Single-ended 1:4 1000 3 –62 –72 4.6 3 mm 3 mm, 16-lead LFCSP

Demodulators
Features
Wide frequency range from 50 MHz to 2.7 GHz
On-chip RF and baseband amplifiers
Wide demodulation bandwidth enables most high
order modulation formats, including QAM, QPSK,
and 8 PSK
Small footprint packages, single supply

Part RF Frequency VGA Range I/Q Frequency Phase Error Amplitude Noise P1dB Input IP3 Supply Supply Current
Package
Number (MHz) (dB) (MHz) (deg) Error (dB) Figure (dB) (dBm) (dBm) Voltage (V) (mA)
5 mm 5 mm,
AD8333 DC to 50 N/A N/A 0.1 0.05 7.8 14.5 30 5.0 +44/–20
32-lead LFCSP
9.8 mm 6.5 mm,
AD8347 800 to 2700 69.5 65 1 0.3 11 –2 11.5 2.7 to 5.5 64
28-lead TSSOP
9.8 mm 6.4 mm,
AD8348 50 to 1000 45 75 0.5 0.25 11 13 28 2.7 to 5.5 48
28-lead TSSOP
4 mm 4 mm,
ADL5382 700 to 2700 N/A 500 0.5 0.25 14 13 30 4.75 to 5.25 195
24-lead LFCSP
4 mm 4 mm,
ADL5387 50 to 2000 — 240 0.5 0.25 15 14 30 4.75 to 5.25 180
24-lead LFCSP

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DAB/DAB-IP/T-DMB (Europe,
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1450 to 1490 (L-Band)
T-DMB/DAB/FM RF+Demod 88 to 108 (FM), 90/180
ADMTV316 –103 9 mm 9 mm, 192-lead FBGA
Dual SoC 174 to 245 (Band-III) (FM/T-DMB dual)
88 to 108 (FM),
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ITD3020 RF 174 to 245 (Band-III), 6 mm 6 mm, 40-lead LFCSP
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1450 to 1592 (L-Band)
88 to 108 (FM), 100/100
ITD3010 RF 2.5 6 mm 6 mm, 40-lead LFCSP
174 to 245 (Band-III) (FM/band-III)
88 to 108 (FM),
2.5/3.5 100/100/140
MTV330 S-/T-DMB/FM Dual RF 174 to 245 (Band-III), 6 mm 6 mm, 48-lead LFCSP
(T-DMB/S-DMB) (FM/T-DMB/S-DMB)
2605 to 2655 (S-Band)
MTV320 S-DMB RF 2605 to 2655 (S-Band) 3.5 140 5 mm 5 mm, 36-lead LFCSP
ADMTV340 CMMB RF 2635 to 2660 (S-Band) 6.7 150 5 mm 5 mm, 32-lead LFCSP
DVB-H/DVB-T 171 to 245 (VHF), 180/200
ADMTV102 RF 2.8 5 mm 5 mm, 32-lead LFCSP
CMMB/DTMB 470 to 862 (UHF) (VHF/UHF)
ADMTV202 RF 470 to 806 (UHF) 2.5 75 2.1 mm 2.1 mm, 23-lead WLCSP
90 to 222 (VHF),
ADMTV203 RF 2.5 75 2.1 mm 2.1 mm, 23-lead WLCSP
470 to 806 (UHF)
ISDB-T 90 to 222 (VHF),
ITD2010 RF 4 100 6 mm 6 mm, 40-lead LFCSP
470 to 770 (UHF)
RF + Demod
MTV211 470 to 806 (UHF) –109 140 9 mm 9 mm, 46-lead LGA
SiP
1
Numbers for typical value in center frequency.

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7KH 9*$ VKRXOG SURYLGH OLQHDU KLJK JDLQ FRQWURO UDQJH ZLWK

WWWRFDESIGNCOM *ANUARY
59
RF Bonus Feature

Logarithmic Amplifiers
Features
Wide frequency range from dc to 10 GHz
Superior accuracy, better than 0.2 dB and wide
dynamic range up to 100 dB
Available with both log and limiter outputs, single and
dual channel
Wide range of package options to save board space in
RF designs

Part RF Frequency Dynamic Temp Response Supply Supply

Package Comments
Number (MHz) Range (dB) Stability (dB) Time (ns) Voltage (V) Current (mA)
Dual-channel gain and
AD8302 >0 to 2700 60 1.0 60 2.7 to 5.5 19 5 mm 6.4 mm, 14-lead TSSOP
phase detector
AD8306 5 to 400 100 1.0 73 2.7 to 5.5 16 10 mm 6.2 mm, 16-lead SOP Military-specified part available

AD8307 DC to 500 92 1.0 400 2.7 to 5.5 8 5 mm 6.2 mm, 8-lead SOIC/DIP High dynamic range

AD8309 5 to 500 100 1.0 67 2.7 to 6.5 16 5.1 mm 6.5 mm, 16-lead TSSOP Amplitude and limiter outputs

AD8310 DC to 440 100 1.0 15 2.7 to 5.5 8 3.1 mm 4.9 mm, 8-lead SOIC Low cost, high dynamic range

AD8313 100 to 2500 70 1.25 40 2.7 to 5.5 14 3 mm 4.9 mm, 8-lead SOIC Industry standard

AD8314 100 to 2700 45 1.0 70 2.7 to 5.5 4.5 2 mm 3 mm, 8-lead SOIC/LFCSP Industry standard
Smaller package, lower cost
AD8317 1 to 10,000 55 0.5 6 3.0 to 5.5 22 2 mm 3 mm, 8-lead LFCSP
version of the AD8318
AD8318 1 to 8000 70 0.5 10 4.5 to 5.5 68 4 mm 4 mm, 16-lead LFCSP High accuracy, fast responding

AD8319 1 to 10,000 45 0.5 6 3.0 to 5.5 22 2 mm 3 mm, 8-lead LFCSP Pin-compatible with AD8317

ADL5513 1 to 4000 75 0.5 <20 3.0 to 5.5 30 3 mm 3 mm, 16-lead LFCSP Next-generation AD8313
Dual-channel version of
ADL5519 1 to 10,000 62 0.5 6 3.3 to 5.5 56 5 mm 5 mm, 24-lead LFCSP
the AD8317

60
 FEATURE

Converters for 3G are optimized

for cost, size and power
b y C h r i s C l o n i n g e r, Analog Devices

Industry demand The transition from 2G to 3G standards also means that ADC power and
performance specifications have changed as well.
for lower-cost
A
s communications systems have and deployed in the late '90s and early
systems and an evolved from second-generation (2G) 2000s, many designers needed state-of-the-
standards to third-generation (3G) art converters to address the performance
ever-increasing standards, the performance requirements of requirements for these systems. At that time,
the analog-to-digital converters (ADCs) and the highest available performance was found
array of features digital-to-analog converters (DACs) used have in the AD6645 14-bit, 80-MSPS pipelined
also evolved. In original 2G basestations, ADC, which was designed on a bipolar
have caused designers often selected the highest-perform- process and consumed 1.5 watts. Similarly,
ance converters available to provide as much the best-performing 14-bit, 100-MSPS DACs
designers to shift system margin as possible and improve man- were based on bipolar or BiCMOS technolo-
ufacturability. This also allowed the manufac- gies and consumed more than 500 mW.
their priorities. turer to differentiate its basestation with a Although this level of performance was
performance advantage over its competitors— required for early-generation systems, the
for example, a higher receive sensitivity. devices represented leading-edge technology,
so they tended to be somewhat costly.
Focus on cost As time has passed, the cost of the con-
This is not usually the case with 3G designs, verter technology has decreased. Since that
however. Industry demand for lower-cost time, there are at least three 14-bit, 125-
systems and an ever-increasing array of fea- MSPS ADCs that dissipate less than 800 mW.
tures have caused designers to shift their With the introduction of these new competi-
priorities. Instead of focusing solely on per- tive devices, the price of high-performance
formance, they are now focusing first on has decreased by at least 50 percent.
other system-enhancing elements, such as Although these new devices do not equal the
cost, power, size and integration, and sec- performance of the higher-power ADCs, they
ondarily on performance. This article will do offer extremely good performance at less
explore the transition from the highest-per- than half the power of the first-generation
formance converters in 2G systems to the device. The latest CMOS DACs, such as the
small, low-cost, low-power, highly integrated AD9707, dissipate a mere 60 mW at 175
converters needed for 3G platforms. MSPS and outperform their BiCMOS cousins.
As early 2G/2.5G systems were designed The first-generation ADCs were designed
on a bipolar process, and the
first-generation DACs were
designed using 0.6-micron
BiCMOS technologies. The
current generation of convert-
ers is designed using 0.18-
micron CMOS technology.
This allows for much smaller
die size, increased feature sets
and lower power dissipation,
all of which allow semiconduc-
tor manufacturers to support
Figure 1: ADC power an overall lower cost struc-
consumption has ture. This benefit gets passed
decreased on to the end customer.
dramatically during
the last decade. Power dissipation
At first glance, power dissipa-

14 • www.PlanetAnalog.com March 27, 2006

61
 FEATURE

tion would seem somewhat insignificant in a dynamic logic elements are employed, fur-
cellular basestation, especially when consid- ther reducing switching transients by using
ering that the power amplifiers (PAs) can a parasitic capacitance to store the logic
output 40 watts. As basestation OEMs are state. In the case of ADCs, the architecture
looking to reduce cost, however, they are has transitioned from pure flash to pipelined
looking everywhere. In particular, some single- and multibit converters, greatly
basestation deployments are now occurring reducing the number of comparators
at the top of towers directly connected to the required and hence the overall power. The
PA itself. The advantage to this type of data in Figure 1 demonstrates the dramatic
basestation is that it does not need to com- decrease in power consumption for 12-bit
pensate for the cabling losses normally asso- and 14-bit ADCs during the last decade.
ciated with putting the transceiver at the
bottom of the cellular tower. Size
However, when a system is mounted at Like power dissipation, size has become a
the top of the tower, no active cooling is pos- major factor in determining the best convert-
sible, while the temperature must be kept as er for an application. In deployments such
low as possible because there is a log-linear as the tower-mounted system mentioned
relationship between temperature and MTBF above, OEMs are not only limited on power,
(mean time between failures). In addition to but are also trying to implement more carri-
ers on the same form factor that orig-
inally supported a single sector of a
basestation. This increased density
allows operators to deploy more car-
riers and thus support more users in
heavily populated areas.
In addition to simply reducing
the actual size of the converters,
another trend is increasing integra-
tion. Digital-to-analog converters now
include extensive digital signal pro-
cessing, such as interpolating filters,
complex modulation, inverse sinc
filters and numerically controlled
oscillators (NCOs). For ADCs, integra-
tion has included adding NCOs and
decimating filters to improve per-
formance. Both interpolating filters
for DACs and decimating filters for
ADCs have the added benefit of
Figure 2a: Traditional reducing the high-speed switching
superheterodyne noise between the converter and the
architecture digital logic.
While it may not be obvious, new-
generation converters have also
the cost of active cooling, OEMs are attempt- reduced size by enabling simpler architec-
ing to save money in the mechanicals of the tures. In particular, new low-power, high-
basestation. Higher-power converters with- performance DACs now make direct-conver-
out active cooling require the mechanical sion architectures feasible. In early genera-
unit in which the transceiver is housed to be tions, a low intermediate frequency (IF) was
more complex and more expensive in order used, and then multiple mixer stages were
to dissipate the heat efficiently. used to achieve the proper RF signal, Figure
Converter manufacturers have addressed 2a. By removing multiple mixers and ampli-
power concerns through advances in process fiers from this signal chain, as shown in
technology and architectural changes. As Figure 2b, a significant size and cost
mentioned previously, the latest ADCs and advantage can be realized.
DACs are being designed in fine-line CMOS Although direct conversion has not yet
technologies. This greatly reduces switching been realized for basestation receivers, the
transients in the logic cells. In some cases, IF-sampling capability of many A/D convert-

16 • www.PlanetAnalog.com March 27, 2006

62
 FEATURE

Figure 2b: A direct-

conversion architec-
ture reduces compo-
nent count and cost
compared with a tra-
ditional superhetero-
dyne architecture.

ers has been greatly improved. It is now pos- leading-edge converters can lower overall
sible to IF sample at up to 450 MHz and development and manufacturing costs by
maintain very good performance. That will reducing the number of design variants
allow the removal of a single mixer stage and required, but that must be weighed against
again reduce overall system cost. the higher bill-of-materials cost.

Performance Conclusion
Although performance is still an important It's clear that the driving force behind choos-
factor, it is no longer the first priority for ing a converter for a basestation design is to
most designers. As the number of competi- remove cost from the system. Cost is mani-
tors in the converter space has increased fested in many subtle ways, including power
over the last five to seven years, the number dissipation, size and performance. These
of basestation suppliers has also increased. attributes affect choices such as system
This, in conjunction with the high price paid architectures, number of carriers and even
by operators for 3G licenses, has led to deployment locations. This shift in thinking
increased cost pressure for all basestation is driving many converter manufacturers to
OEMs. It is this cost pressure that has introduce parts that meet as many of these
forced many designers to look at converters dimensions as possible. Since it's very diffi-
that just meet the system requirements cult to meet every attribute with a single
instead of paying the price premium for the device, a broad product portfolio offers the
highest performance converters. The good best chance of providing the right converter
news for many designers, though, is that it for the specific radio architecture and per-
is easier to meet many of the 3G (W-CDMA) formance requirements. ■
converter requirements for the 2,100-MHz
band than those of the GSM 900-MHz band. Chris Cloninger joined Analog Devices Inc. in 1995 after receiving
For example, a 12-bit, 65-MSPS ADC and a bachelor’s degree in computer engineering from Clemson
University. He is a mixed-signal marketing/systems engineer for
14-bit, 65-MSPS DAC can meet the require- high-speed analog/digital converters for wireless infrastructure
ments for a two-carrier W-CDMA system, and can be reached at chris.cloninger@analog.com.
and a 14-bit, 65-MSPS ADC and 14-bit, 125-
MSPS DAC can meet the requirements of a
ON THE WEB

three- to four-carrier system. On the other

hand, only a small number of ADCs and For more information
DACs can meet the requirements for the Planet Analog: monthly in print, plus much
multicarrier GSM 900-MHz band. These, as more on the Web at www.planetanalog.com,
noted, represent leading-edge technology covering all things "analog" (including
and thus carry a price premium. Multicarrier power, too)
and multistandard architectures utilizing

18 • www.PlanetAnalog.com March 27, 2006

63
RF Bonus Feature

Variable Gain Amplifiers

Features
Wide selection of VGAs with Analog or digital, choice of
frequencies ranging from dc gain control suited for your
to 3 GHz applications
Wide dynamic range up to Differential or single-ended I/O
60 dB

Gain Output Noise Input Supply Supply

Part Control Bandwidth Gain
Accuracy IP3 Figure Noise Voltage Current Package Comments
Number Type (MHz) (dB)
(dB) (dBm) (dB) (nV/√Hz) (V) (mA)
–11 to +31, 15 4.75 to 5 mm 6.2 mm,
AD603 Analog DC to 90 0.5 8.8 1.3 12.5 Single-ended input/output
+9 to +51 (40 MHz) 6.3 8-lead SOIC/DIP
0 to +48, 35 8.2 mm 7.8 mm,
AD604 Analog DC to 40 0.3 8.4 1.8 5 64 Single-ended input/output
+6 to +54 (10 MHz) 24-lead SSOP/SOIC/DIP
–14 to +34, 33 10 mm 6.2 mm,
AD605 Analog LF to 40 0.2 8.4 1.8 5 36 Single-ended input/output
0 to +48 (10 MHz) 16-lead SOIC/DIP
42 3.3 to 5 mm 5 mm,
AD8260 Digital LF to 180 –6 to +24 1.25 — 2.4 28.2 Single-channel transceiver
(10 MHz) 5 32-lead LFCSP
27 3 mm 3 mm,
AD8330 Analog DC to 150 0 to +50 0.5 — 5.0 2.7 to 6 20 Differential input/output
(10 MHz) 16-lead LFCSP/QSOP
–5 to +43, 33 9 mm 8.75 mm, Single-ended input LNA/
AD8331 Analog LF to 120 0.3 4.2 0.8 4.5 to 5.5 25
+7 to +55 (10 MHz) 20-lead QSOP differential output
–5 to +43, 32 5 mm 5 mm, 28-lead Single-ended input LNA/
AD8332 Analog LF to 100 0.3 4.2 0.8 4.5 to 5.5 58
+7 to +55 (10 MHz) TSSOP, 32-lead LFCSP differential output
–5 to +43, 32 9 mm 9 mm, Single-ended input LNA/
AD8334 Analog LF to 100 0.3 4.2 0.8 4.5 to 5.5 116
+7 to +55 (10 MHz) 64-lead LFCSP differential output
–10 to +38, 31 9 mm 9 mm, Single-ended input/
AD8335 Analog DC to 85 0.2 7.0 1.3 4.5 to 5.5 76
–2 to +46 (10 MHz) 64-lead LFCSP differential output
–14 to +46, 3 to 4 mm 4 mm,
AD8336 Analog DC to 100 0.3 — — 3.1 150 Single-ended input/output
0 to +60 12 16-lead LFCSP
28 2.5 to 3 mm 3 mm,
AD8337 Analog DC to 280 0 to +24 0.25 14 2.2 15 Single-ended input/output
(45 MHz) 5 8-lead LFCSP
–2.5 to 36.5 5.1 mm 6.5 mm, Single-ended input/output
AD8367 Analog DC to 500 0.2 6.2 1.9 2.7 to 5.5 26
+42.5 (70 MHz) 14-lead TSSOP VGA/AGC operation
33.7 4 mm 4 mm, Single-ended input/output
AD8368 Analog LF to 800 –12 to +22 0.4 9.5 1.3 4.5 to 5.5 60
(70 MHz) 24-lead LFCSP VGA/AGC operation
0.001 19.5 5.1 mm 6.4 mm,
AD8369 Digital –5 to +40 0.5 7.0 2.0 3 to 5.5 37 Differential input/output
to 600 (70 MHz) 16-lead TSSOP
0.001 –11 to +17, 31 5.1 mm 6.4 mm,
AD8370 Digital 0.5 7.4 2.1 2.7 to 5.5 78 Differential input/output
to 700 +6 to +34 (70 MHz) 16-lead TSSOP
35 5 mm 5 mm, Differential input/output,
AD8372 Digital 1 to 130 –9 to +32 — 7.9 1.7 4.5 to 5.5 106
(65 MHz) 32-lead LFCSP dual-channel
50 4 mm 4 mm,
AD8375 Digital 700 –4 to +20 — 8.5 1.9 4.5 to 5.5 130 Differential input/output
(70 MHz) 24-lead LFCSP
50 5 mm 5 mm,
AD8376 Digital 700 –4 to +20 — 8.5 2.0 4.5 to 5.5 260 Dual-channel AD8375
(70 MHz) 32-lead LFCSP
31 4 mm 4 mm,
ADL5330 Analog 1 to 3000 –34 to +22 1.5 7.8 1.3 4.75 to 6 240 Differential input/output
(900 MHz) 24-lead LFCSP
30.5 4.75 to 6 mm 6 mm, Single-ended dual 30 dB
ADL5334 Digital 150 to 2400 60 0.25 5.7 — 250
(1900 MHz) 5.25 40-lead LFCSP attenuators

64
RF POWER DETECTION:
MEASURING WIMAX
SIGNALS
W
iMAX, which offers high speed data WIMAX STANDARDS
access to large geographical areas — IEEE 802.16, the formal specification of
covering distances up to 30 km — is WiMAX, is targeted at providing broadband
defined by the IEEE 802.16 family of stan- wireless access beyond that which is currently
dards. It uses orthogonal frequency division available using IEEE 802.11x (WLAN).
multiplexing (OFDM) to attain the high data 802.16-2004 (sometimes called 802.16d), the
rates. Consequently, the composite signal en- latest full revision of the WiMAX standard, fo-
velopes of the data bursts have significant cuses primarily on fixed position point-to-
peaks, which cause large modulation crest fac- point or point-to-multipoint networks. The
tors. Accurate measurement and control of standard defines OFDM modulation, a fre-
WiMAX signals is challenging, due to the typi- quency range of 2 to 11 GHz, and data rates
cally high WiMAX crest factors of 12 dB and up to 70 Mbps. OFDM modulation in 802.16d
to its susceptibility to the varying modulation utilizes up to 256 subcarriers with bandwidths
patterns. As WiMAX users move towards or from 1.25 to 28 MHz. The subcarriers are
away from the base station, the transmitter spaced such that they are orthogonal to each
changes the waveform composition (or modu- other, thus reducing signal interference. The
lation) to optimize data speed and reception choice of signal bandwidth can be determined
reliability. As the waveform changes, the cor- in multiple ways. The base station can change
responding crest factor variation introduces the signal bandwidth based on transmission
RF power measurement errors. distance and signal environment, or network
This article describes several methods to providers may determine the bandwidth avail-
accurately measure and control the power of able to a user, based on various pricing plans.
WiMAX transmitters. WiMAX transmit signal Figure 1 shows a basic diagram of the signal
paths can employ high dynamic range loga- structure for an 802.16d network.
rithmic amplifiers and accurate rms detectors
to ensure accurate control of the transmitted
signal across changing modulation types and
over temperature. Some of the highlighted CARLOS CALVO
topics will cover the difficulties in dealing with AND MATTHEW PILOTTE
changing crest factors and rapid envelope Analog Devices Inc.
changes. Norwood, MA

Reprinted with permission of MICROWAVE JOURNAL® from the September 2006 issue.
©
2006 Horizon House Publications, Inc.

65
 T ECHNICAL F EATURE
carrier will add together is very low. A
Frame Control
Preamble Header Data Burst #1 Data Burst #2 Data Burst #N crest factor of 12 dB still poses signifi-
cant design considerations with regards
to the selection of high linearity devices
Burst bandwidth=1.25 to 28 MHz (mixers, modulators, power amplifiers,
200 Subcarriers-5.6 to 90 kHz spacing etc.) in the RF signal chain. Because
WiMAX systems can be used for non-
line-of-sight applications, gain control
8 Fixed Position of the transmitter is necessary to adjust
BPSK Pilots the output TX level depending on the
channel quality. It is also necessary to
accurately control the power amplifier’s
output in order to avoid signal clipping
Modulated Subcarriers and increased distortion. Some systems
BPSK, QPSK, 16QAM, 64QAM employ crest factor reduction schemes,
▲ Fig. 1 806.16d OFDM data burst and signal spectrum. typically in the digital baseband pro-
cessing, to minimize these effects.
Symbol Number broadband access, was introduced in
February 2002 when the Korean gov- RF POWER DETECTION IN THE
FCH
Uplink Map

Downlink Burst #4 ernment allocated 100 MHz of spec- TRANSMIT SIGNAL CHAIN
trum from 2.3 to 2.4 GHz. This band Figure 3 shows the block diagram
Subchannel Number

Downlink Burst #5 was then standardized by the Korean of a typical WiMAX transmit signal
Downlink Map

Telecommunications Technology As- chain. The transmit signal path con-

Preamble

Downlink Burst #1 sociation (TTA) in late 2004. WiBro sists of three consecutive stages: digi-
Downlink base stations offer a theoretical data tal baseband processor or digital sig-
Burst #6
Downlink Burst #2 rate up to 50 Mbps and cover a radius nal processor, radio and power ampli-
of 1 to 5 km, allowing the use of fier. A portion of the transmitted
Downlink Burst #3 Downlink portable and mobile Internet devices signal is sampled by the directional
Burst #7
within the range of a base station. coupler before it reaches the anten-
Time Under 802.16e, WiBro is defined as na. The sampled RF power is deliv-
▲ Fig. 2 806.16e OFDMA data burst. one of the available system profiles ered to the power detector where it is
and consists of 1024 subcarriers with- converted to a DC voltage. The out-
A recent amendment to 802.16- in an 8.75 MHz bandwidth. put voltage of the power detector is
2004 focuses on the OFDMA physi- As shown in the figures, WiMAX is digitized and fed to the digital signal
cal layer. This updated standard, transmitted using OFDM and is made processor (DSP). Once the power
802.16e-2005 (or Mobile WiMAX), up of 256 to 2048 subcarriers, each of measurement is available as a digital
introduces specifications that allow which is modulated using BPSK, level, a decision is made based on the
for mobility in a WiMAX network at QPSK, 16QAM or 64QAM. The com- measured output power versus the
speeds up to 75 MPH (120 kPH). In bination of all these subcarriers and dif- desired output power. The DSP will
order to accomplish this, 802.16e in- ferent modulation schemes results in adjust the output power using a digi-
creases the number of available carri- the potential for large peaks and tal-to-analog converter to drive the
ers from 256 to 2048, with the BPSK troughs during each signal burst. In signal path power control, either at
pilot tones no longer at fixed intervals theory, it is possible for these extremes the baseband, radio or power amplifi-
during each data burst. The band- to fall on top of each other causing a er. The RF power management loop
width for each data burst includes large peak-to-average ratio (PAR) or will reach a steady-state once the
1.25, 5, 10 and 20 MHz. It is also pos- crest factor (CF). Variations in data rate measured output power and the de-
sible that additional bands at 3.5, 5.5 and burst length will affect the overall sired output power are balanced. A
and 7 MHz will be made available for signal crest factor. This can cause issues temperature sensor can also be intro-
use in Europe. While the 802.16d even in the simplest
standard includes specifications for of WiMAX systems. ANTENNA
the entire 2 to 11 GHz band, 802.16e For example, a sys-
focuses on licensed bands below 4 tem which utilizes PA Radio
GHz. Figure 2 shows how the data 256 subcarriers will
bursts for an OFDMA network over- have a theoretical DIRECTIONAL
COUPLER
lap in time, as opposed to the individ- crest factor of 10
DSP
ual bursts of OFDM. This added log(256) = 24 dB. In RF Detector
complexity allows for a larger number practice, it is more (Log Amp or
of users and handles the necessary likely to only have a TruPWR)
complexity for a multi-path mobile peak crest factor of
environment. 802.16e also merges Temp
12 dB because the Sensor
WiBro under this IEEE standard. probability that the
WiBro, a Korean system for wireless phase of every sub- ▲ Fig. 3 WiMAX transit signal chain with RF power management.

66
 T ECHNICAL F EATURE
noise or AC-resid- fiers. Each amplifier has a gain of 5 to
V I SETPOINT ual on the detector’s 20 dB. The combination of gain and
DC output. To miti- number of amplifiers determines the
Σ I V OUTPUT gate this effect, detection range of the log amp. The
DET DET DET DET multiple measure- output of each amplifier stage is fed
INHI ment points can be into a full wave rectifier (marked
INLO
taken throughout DET). The outputs of each rectifier
the burst to average are summed together, and the sum-
▲ Fig. 4 Basic block diagram of a logarithmic amplifier. out the AC-residual mer’s output is applied to a low pass
error. filter to remove the ripple of the rec-
CW QPSK 1/2 tified signal. This yields the logarith-
16QAM 1/2 64QAM 2/3 DETECTOR BACKGROUND mic output (often referred to as the
BPSK QPSK 3/4
16QAM 3/4 64QAM 3/4
Historically, diode detectors have “video” output), which will be a
2.0 5 been used in RF power control cir- steady-state DC output for a steady-
cuitry to regulate transmitted power. state AC input signal. It is the band-
LINEARITY ERROR (dB)

1.6 3 The simple diode circuitry offers a width of this video output that is par-
OUTPUT (V)

1.2 1
small dynamic range with poor tem- ticularly important in a WiMAX sys-
perature stability. Even with tempera- tem. The wider the video bandwidth,
0.8 −1 ture compensation circuitry, a diode the faster the log amp is able to re-
detector can only offer a small detec- spond to changes in the peak voltage,
0.4 −3 tion range with worsening tempera- or amplitude, of the input signal. This

−060 −50 −40 −30 −20 −10 0

−5 ture performance at low input powers.
A popular alternative to the diode
makes the log amp particularly suited
to accurately keep up with the enve-
INPUT (dBm)
detector is the demodulating logarith- lope of the WiMAX burst. With re-
▲ Fig. 5 Log amp output voltage and
mic amplifier (log amp). The log amp sponse times as low as 8 ns, log amps
linearity error at various 2.35 GHz OFDM
modulations. offers an easy to use linear-in-dB RF can easily keep up and measure small
power detection response, a wide dy- periods of the RF burst, such as the
duced as an input to the DSP to add namic range, temperature stability and preamble, which last about 26 μs.
temperature compensation capabili- nanosecond response times. The Using a peak-detecting device like
ties. This RF power management newest RF power measurement alter- a log amp is advantageous when mea-
configuration is not limited to a par- native is the TruPWR rms-responding suring the signal power of a waveform
ticular application. Both base stations detector, which offers wide dynamic at an exact point in time. Because the
and subscriber stations alike may in- ranges and temperature stability. In log amp is able to track the envelope
corporate variations of this same RF addition, rms detectors are insensitive of its input, provided the modulation
power control system. to changes in the peak-to-average ra- rate is lower than the video band-
There are two basic methods by tios, whereas diodes and log amps are width of the log amp, the DC output
which the RF power detector and the both waveform dependent. will be an instant-by-instant measure-
DSP can interact to control the pow- Each WiMAX application has di- ment of the peak amplitude of the in-
er of the WiMAX burst. The first verse power control and RF detec- put signal. This kind of measurement
method, which is similar to the tech- tion needs. Subscriber stations can be is useful in a WiMAX system to detect
nique used in envelope ramping in designed with dynamic ranges as high crest factor signals during a burst
GSM applications, shapes the RF small as 30 dB, but are susceptible to and make the appropriate adjust-
burst instantaneously. It uses the supply power consumption. Base sta- ments in power amplifier biasing or
feedback of the detector to shape the tions have more allowance for power implement a crest factor reduction
envelope of the RF burst, made up of consumption, but need to control dy- scheme in the next burst. Figure 5
the preamble, frame control header namic ranges of up to 60 dB. Both, shows the output voltage and linearity
and data. This envelope shaping similarly, require temperature stabili- error of a log amp at various 2.35
method requires high speed detec- ty for improved accuracy. Only log GHz OFDM modulations, 256 sub-
tors and fast feedback paths. A more amps and rms detectors are able to carrier signals with 10 MHz band-
commonly adopted method is that of meet those needs. width. The error, normalized to
output power monitoring. This QPSK with 3/4 encoding rate, is
method takes a power measurement LOGARITHMIC AMPLIFIERS graphed on the secondary y-axis,
during a burst and adjusts the RF The first detection method to be scaled in dB. While the log amp is
power accordingly during the subse- looked at is a peak-detecting device, able to maintain approximately 50 dB
quent burst. The power adjustments the logarithmic amplifier. A wide va- of measurement range within ±1 dB
are highly dependent on the linearity riety of log amps is available with de- or error for each modulation, there is
of the radio components to scale and tection ranges from 40 to 100 dB, and an obvious shift in the intercept of the
shape the RF burst. A single mea- frequencies from DC to 10 GHz. A transfer function. The intercept is the
surement of RF output power can be typical block diagram of a log amp is point on the x-axis through which the
affected by the high frequency com- shown in Figure 4. transfer function would pass if the
ponents in the measured signal, The core architecture of a log amp output voltage could go to 0 V. This
which can manifest themselves as is a cascaded chain of linear ampli- intercept shift is a byproduct of the

67
 T ECHNICAL F EATURE
successive detection architecture of a to-average ratio of the RF signal varies, the accuracy in measuring various
log amp. The amount of intercept the output response of a log amp will OFDM waveform types. The method
shift is based on the crest factor of the also vary. This introduces an uncertain- used to calculate the error is similar
signal. Because the log amp behavior ty that in many cases must be compen- in nature to that used in the log amp
is repeatable over manufacturing sated for by the DSP. error calculation. The linearity error
process variations, the intercept shift of the detector is within ±0.5 dB
of the log amp for a sine wave versus a RMS-RESPONDING DETECTORS across the dynamic range of the de-
modulated input signal can be easily Unlike diodes and log amps, mean vice. The various waveforms lie on
characterized. The DSP can then use power detectors (or rms detectors) top of each other with a deviation of a
an offset correction to compensate for have responses which are indepen- couple tenths of a dB. This 30 dB dy-
the detector’s output voltage and yield dent of waveform. The waveform-in- namic range and low 1 mA power
accurate RF power measurement. dependence is particularly useful as consumption is useful for subscriber
The low power consumption, of the WiMAX systems optimize the quality applications. The slower response
order of 15 to 30 mA, makes log amps of the link by dynamically adjusting time, in the range of 25 μs, limits the
viable in both base stations and sub- the signal modulation. The composite rms detector use to output power
scriber stations alike. The well-estab- signal envelopes of the data bursts monitoring. Figure 8 shows the
lished log amp architecture offers ex- may have significant peaks that can block diagram of a 60 dB rms detec-
cellent temperature stability across drastically change over time and tor, which is appropriate for wider dy-
large dynamic ranges as well as fast re- throw off measurement accuracy. Us- namic range base station applications.
sponse times for burst tracking and ing log amps in the RF power control The input signal is applied to a 12-
peak sampling. However, as the peak- system require some method of com- step, continuously variable gain am-
pensation; however, plifier, which is controlled by the set-
RFIN X 2 i rms detectors sim- point, a logarithmic control voltage.
plify the complexity The output of the VGA is fed to an
TRANS-
CONDUCTANCE
+
Error
of the system by re- accurate squaring-cell. The fluctuat-
ducing and in some ing output is filtered and compared
CELLS
2 i
−
Amp
cases eliminating with the output of an identical squar-
X Buffer OUTPUT
compensation er. At this point, the square and mean
schemes. operations of the rms calculation are
▲ Fig. 6 Block diagram of a TruPWR rms detector with 3 dB Figure 6 shows complete. The output is fed back to
linear-in-volts response. the block diagram the VGA setpoint, making the output
of a 30 dB rms de- proportional to the logarithm of the
tector. It achieves independence rms value of the input. The detector
BPSK QPSK 3/4 from peak-to-average ratios by com- response is linear-in-dB, allowing the
16QAM 1/2 64QAM 3/4
QPSK 1/2 16QAM 3/4 puting the square, mean and root device to measure RF signals in a 60
64QAM 2/3 functions of an rms calculation. The dB dynamic range. The final step of
3 10
RF input is fed to one of two identi- performing the square-root function
LINEARITY ERROR (dB)

2 cal squaring-cells. The squared signal is not needed for accurate rms detec-
is then averaged through a low pass tion. Figure 9 shows the perfor-
OUTPUT (V)

1 1
filter network. The signal is fed to a mance of the 60 dB rms detector
0 high gain error amplifier that has the when measuring various OFDM
−1 0.1 second squaring-cell in its feedback modulated input signals. Again, the
path. This feedback loop performs various waveforms lie on top of each
−2 the square-root function, thus com- other with negligible deviation. The
−−325 −20 −15 −10 −5 0 5 100.01 pleting the rms calculation. The out-
INPUT (dBm) put is a linear-responding DC voltage CW QPSK 1/2
▲ Fig. 7 Linear-in-volts rms detector whose conversion gain has units of 16QAM 3/4 64QAM 2/3
output voltage and linearity error at various VDC/Vrms. The linear-in-volts rms de- BPSK QPSK 3/4
16QAM 1/2 64QAM 3/4
2.35 GHz OFDM modulations. tector is able to operate at frequen- 2.0 4.0
cies as high as 6
LINEARITY ERROR (dB)

1.5 3.5
INHI GHz. The rms-re- 1.0 3.0
X2 sponding detector
OUTPUT (V)

+
INLO 0.5 2.5
allows the RF pow-
− Σ OUTPUT 0 2.0
er control system to
monitor and dy-
−0.5 1.5

namically adjust the −1.0 1.0

X2
−1.5
VTGT
0.5
transmitter’s output
power even as the −2.0−60 −50 −40 −30 −20 −10 0 10
0

SETPOINT peak-to-average ra- INPUT (dBm)

tio of the transmit- ▲ Fig. 9 Linear-in-dB rms detector output
▲ Fig. 8 Block diagram of a linear-in-dB TruPWR rms detector with ted signal changes. voltage and linearity error at various 2.35
60 dB dynamic range. Figure 7 illustrates GHz OFDM modulations.

68
 T ECHNICAL F EATURE
humps in the linearity error curve speed networks. The large crest fac- Carlos Calvo received his BS and MS degrees
correspond to the steps of the loga- tors associated with the OFDM mod- in electrical engineering from Worcester
Polytechnic Institute. He is an applications
rithmic VGA. Still, the linearity error ulation scheme require accurate trans- engineer in the Advanced Linear Products
across the dynamic range stays well mit power measurements for PA con- Division at Analog Devices Inc.
within ±0.5 dB. As in the case of the trol and the implementation of crest Matthew Pilotte received his BS degree in
linear-in-volts detector, the 70 μs re- factor reduction algorithms. Designs electrical engineering from Worcester
sponse time of this 60 dB detector requiring fast response to the OFDM Polytechnic Institute. He is an applications
also limits this detector application to envelope should consider the accuracy engineer in the Advanced Linear Products
output power monitoring. of log amps. The waveform-indepen- Division at Analog Devices Inc.
dence provided by rms detectors can
CONCLUSION reduce, or even eliminate, the need
The emerging WiMAX standard for compensation schemes in these
has great potential to offer wide area networks, simplifying the overall de-
coverage and mobile access to high sign of the transmit chain. ■

69
RF Bonus Feature

Mixers/Multipliers
Features
High linearity active mixers provide conversion gain
Broadband family portfolio with operation up to 4 GHz
Integrated LO driver on-chip
Small footprint packages, single supply

LO LO Noise Supply Supply

Part RF Frequency IF Frequency Conversion IP3 P1dB
Frequency Drive Figure Voltage Current Package Comments
Number (MHz) (MHz) Gain (dB) (dBm) (dBm)
(MHz) (dBm) (dB) (V) (mA)

AD831 400 200 400 0 0 24 10 10 5 100 10.02 mm 8.38 mm, IF active mixer
20-lead PLCC
4.75 to 3 mm 3 mm, RF/IF active
AD8342 LF to 500 DC to 350 LF to 850 0 3 24 8.5 12 97
5.25 16-lead LFCSP mixer
5.1 mm 6.5 mm, RF/IF active
AD8343 DC to 2500 DC to 2500 DC to 2500 –10 7 16.5 2.8 14 5 50
14-lead TSSOP mixer

4.75 to 3 mm 3 mm, RF/IF active

AD8344 400 to 1200 70 to 400 470 to 1600 0 4 24 8.0 11 90
5.25 16-lead LFCSP mixer

3 mm 2 mm, RF/IF passive

ADL5350 LF to 4000 LF to 4000 LF to 4000 4 –6 26 20 6 2.7 to 3.5 16
8-lead LFCSP mixer
4.75 to 4 mm 4 mm,
ADL5390 20 to 2400 20 to 2400 DC to 230 N/A 5 24 11 21 135 Vector multiplier
5.25 24-lead LFCSP

ADL5391 DC to 2000 DC to 2000 DC to 2000 N/A Variable 29 15.1 — 4.5 to 5.5 130 3 mm 3 mm, RF/IF multiplier
16-lead LFCSP

70
WIRELESS TECHNOLOGIES

Measuring VSWR
and Gain in Wireless
Systems
EAMON NASH
Analog Devices, Wilmington, MA

easurement and control of gain and used to measure gain and VSWR can re-

M reflected power in wireless trans-

mitters are critical auxiliary func-
tions that are often overlooked. The power
duce overall component count. This article
will focus on techniques that can be used
to perform these in-situ measurements in
reflected back from an antenna is speci- wireless transmitters.
fied using either the voltage standing
wave ratio (VSWR) or the reflection coeffi- A TYPICAL WIRELESS TRANSMITTER
cient (also referred to as return loss). Poor Figure 1 shows a typical wireless
VSWR can cause shadowing in a TV transmitter. It consists of mixed-signal
broadcast system as the signal reflected base band circuitry, an up-converter
off the antenna reflects again off the pow- (which generally includes one or more
er amplifier and is then rebroadcast. In intermediate frequencies or IFs), ampli-
wireless communications systems, shad- fiers, filters and a power amplifier. These
owing will produce multi-path-like phe- components may be located on different
nomena. While poor VSWR can degrade PCBs or may even be physically separat-
transmission quality, the catastrophic ed. In the example shown, an indoor unit
VSWR that results from damage to coaxial is connected to an outdoor unit with a ca-
cable or to an antenna can, at its worst, ble. In such a configuration, both units
destroy the transmitter. The gain of a sig- may be expected to have well defined,
nal chain is measured and controlled as temperature-stable gains. Alternatively,
part of the overall effort to regulate the each unit might be expected to deliver a
transmitted power level. If too much or well-defined output power. There are two
too little power is transmitted, the result different approaches to the ultimate goal
will be either violation of emissions regu- of delivering a known power level to the
lations or a poor quality link. The reflec- antenna: power control or gain control.
tion coefficient is calculated by measuring With power control, the system relies on
the ratio between forward and reverse being able to precisely measure the output
power. Gain, on the other hand, is calcu- power (using detector D in this example).
lated by measuring input and output pow- Once the output power has been mea-
er. The high commonality of hardware sured, the gain of some component in the

Reprinted with permission of MICROWAVE JOURNAL® from the November 2005 issue.
©
2005 Horizon House Publications, Inc.

71
 WIRELESS TECHNOLOGIES
range (typically 20 to 30 dB). As a
INDOOR UNIT OUTDOOR UNIT
result, the relationship between
output voltage and input power
IF in dBm is exponential (see Fig-
VGA
SAW BPF ure 2). While the temperature
IF RF
DAC AMP AMP HPA stability of a temperature-com-
pensated diode detector is excel-
lent at high input powers (+10 to
DET
A
DET
B
DET
C Σ
DET
D +15 dBm), it degrades significant-
ly as the input drive is reduced. A
log detector, on the other hand,
Mixed Signal (ADCs/DACs) and μProcessor/DSP delivers an output voltage pro-
portional to the log of the input
▲ Fig. 1 Power control versus gain control. signal over a large dynamic
range (up to 100 dB). The temper-
system (in this case, it might be the would be made using the IF VGA.
ature stability is usually constant
IF VGA) is varied until the correct Gain control, on the other hand,
over the complete dynamic
output power is measured at the may make more sense in a recon-
range. A log-responding device
antenna. It is not necessary to figurable system whose compo-
offers a key advantage in gain
know the gain of the circuit or the nents come from different vendors.
and VSWR measurement applica-
exact input signal amplitude; it is In the example, the input power
tions. In order to compute the
just a matter of varying the gain or and output power of the HPA are
gain or the reflection loss, the ra-
input signal until the output power being measured (using detectors C
tio of the two signal powers
is correct. This approach is often and D) so the gain can be regulat-
(either OUTPUT/INPUT or
(incorrectly) referred to as auto- ed independent of the other blocks
REVERSE/FORWARD) must be
matic gain control or AGC. To be in the circuit. Note that the pow-
calculated (see Figure 3). An
correct, it should be referred to as er/gain control loops can be all
analog divider must be used to
automatic power control or APC analog or microprocessor based.
perform this calculation with a
since it is power not gain that is be- Gain control would be less practi-
linear-responding diode detector,
ing precisely regulated. cal in the example since the two re-
but only simple subtraction is re-
Gain control takes a different quired detector signals (detectors
quired when using a log-
approach. Here, at least two power A and D) are physically remote
responding detector (since log
detectors are used to precisely reg- from one another. A more practical
(A/B) = log (A) – log (B)). A dual
ulate the gain of the complete sig- approach would be to indepen-
RF detector has an additional ad-
nal chain or a part thereof. A pre- dently control the gain of the in-
vantage compared to a discrete
cise input signal is then applied to door and outdoor units.
implementation. There is a natur-
the signal chain. A number of fac-
RF DETECTORS al tendency for two devices (RF
tors ultimately determine which
detectors in this case) to behave
approach is used. Power control Until recently, most RF power
similarly when they are fabricat-
requires only one power detector detectors were built using a tem-
ed on the same silicon wafer.
and makes sense in a non-config- perature-compensated half-wave
Both devices will have similar
urable transmitter whose compo- rectifying diode circuit. These de-
temperature drift characteristics,
nents are fixed. For example, pow- vices deliver an output voltage
for example. At the summing
er could be measured at the output that is proportional to the input
node, this drift will cancel to yield
of the RF HPA but adjustments voltage over a limited dynamic
a more temperature-stable result.
DIODE DETECTOR
GAIN MEASUREMENT
Diode Detector
Pin A Pin B
EXAMPLE
Log Detector
Figure 4 shows a transmitter
2.5 whose gain is regulated using a
dual power detector. The simplified
OUTPUT VOLTAGE (V)

2.0 Vout = Vin A/Vin B

= Gain(V/V) transmit signal chain shown con-
1.5 sists of a high performance IF-syn-
LOG DETECTOR
thesizing DAC, a VGA, a mixer/up-
1.0 + -
Pin A ᏸ Σ ᏸ Pin B
converter and a high power ampli-
0.5
fier. High performance DACs, such
as the AD9786 and AD9779 that
0 Vout = log(Pin A) - log(Pin B) run at sampling frequencies up to
-70 -60 -50 -40 -30 -20 -10 0 10 20 500 MSPS and beyond, are capable
= log(Pin A/Pin B)
INPUT POWER (dBm)
= Gain(dB) of synthesizing intermediate fre-
▲ Fig. 2 Transfer functions of diode ▲ Fig. 3 Calculating the gain using quency outputs (100 MHz in this
and log detectors. diode and log detectors. example). The output of the DAC is

72
WIRELESS TECHNOLOGIES
Nyquist filtered using a bandpass below –10 dBm. Thus, the power precision is required, care must be
filter before being applied to an coming from the directional cou- paid to the temperature stability of
ADL5330 variable gain amplifier. pler (+25 dBm max) must be atten- the power detectors. This issue is
Conveniently, the amplifier accepts uated before being applied to the further complicated if the tempera-
a differential input that can be tied detector. If maximizing the detec- ture drift characteristics of the de-
directly to the output of the differ- tor dynamic range is not critical to tectors change with frequency. The
ential filter. This, in turn, is tied to the application, the attenuation can dual detector shown provides tem-
the DAC output. The VGA output be conservatively set at 41 dB so perature compensation nodes. The
is converted from differential to that the detector sees a maximum temperature compensation is acti-
single-ended using a balun trans- input power of –16 dBm. This still vated by connecting a voltage to
former, and is then applied to the leaves about 34 dB of useful dy- the ADJ pins of each detector (this
ADL5350 mixer. After appropriate namic range over which the gain voltage can be conveniently de-
filtering (not shown), the signal is can be controlled. To detect the in- rived using a resistor divider from
amplified and transmitted at a put power level at the DAC output, the 2.5 V on-chip reference). No
maximum output power level of a directional coupler is impractical compensation is required for the
30 W (approximately +45 dBm). at this low frequency. In addition, low frequency input (ADJB is
The gain of the signal chain is directional coupling is not neces- grounded), while a 1 V compensa-
measured by detecting the power sary since there will be little or no tion voltage is required at ADJA to
at the DAC output and at the out- reflected signal at this point in the minimize temperature drift at 2.1
put of the HPA. The gain is then circuit. Furthermore, the power GHz. While the focus of the appli-
regulated by adjusting the gain of a being delivered to the VGA is –10 cation circuit is gain measurement,
VGA. At the DAC and PA outputs, dBm, so the power to be delivered it should be noted that input power
a sample of the signal is taken and to the detector is only 6 dB lower. and output power can also be mea-
fed to the detectors. At the HPA Since the detector has an input im- sured. The outputs of the individ-
output, a directional coupler is pedance of 200 Ω and the VGA has ual detectors are available and can
used to tap off some of the power an input impedance of 50 Ω, it be separately sampled. Because
going to the antenna. The transfer quickly becomes clear that the two the detectors are log responding,
function of the AD8364 dual detec- devices can simply be connected in their outputs can be simply sub-
tor (see Figure 5) shows that at the parallel. With the same voltage tracted to yield gain. This subtrac-
output frequency used (2140 MHz present at both inputs, the 50 to tion is performed on chip and the
in this case), the detector has the 200 Ω impedance ratio will result in gain result is delivered as a differ-
best linearity and the most stable a convenient 6 dB power differ- ential voltage. The full-scale differ-
temperature drift at power levels ence. Where high measurement ential voltage is approximately ±4
V (biased up to 2.5 V) with a slope
LO of 100 mV/dB. Digitizing with a 10-
100 MHz bit ADC with an LSB size of ~10
-10 dBm +45dBm
50Ω
Directional
mV (±5 V full scale), 0.1 dB mea-
1nF 1nF 1.1
Coupler surement resolution is achievable.
IF HPA
Synthesizing 50Ω 60dB
VGA
20dB
DAC
100 1nF 1nF
Mixer
VSWR MEASUREMENT
41dB
MHz
EXAMPLE
50Ω
A dual log detector can also be
used to measure the reflection co-
DAC efficient of an antenna. In Figure
CLPF
6, two directional couplers are
Output
used, one to measure the forward
1:4
VGA Control IERR Power
VSTA
0.1uF 0.1uF INHA ISIG2 OUTA
ADC +85° +25° -40°
Channel A ITGT2
μProcessor/DSP

INLA TruPwrTM 5
FBKA 2.5
Gain 4
OUTP 2.0
OUTA
GAIN ERROR (dB)

ADJA 3
GAIN OUTPUT (V)

OUTB
OUTN ADC 1.5
VREF FBKB 2 1.0
Vref
1 0.5
-16 dBm(max)
ADJB 0 0
-1 -0.5
0.1uF INLB ISIG2 -2 -1.0
Channel B OUTB
INHB ITGT2 ADC -3
TruPwrTM -1.5
0.1uF VSTB -4 -2.0
Input
VGA Control Power -5 -2.5
-60 -50 -40 -30 -20 -10 0 10 20
CHANNEL A INPUT POWER (dBm)
CLPF (CHANNEL B = -25 dBm)

▲ Fig. 5 Gain transfer function of a

▲ Fig. 4 Gain control using a dual rms-responding log detector. dual rms-responding log detector.

73
WIRELESS TECHNOLOGIES
a natural by product. These lim-
Pout = +20 to +50 dBm iter outputs are multiplied togeth-
er to yield a phase-detected out-
HPA put with a range of 180° centered
20 dB 20 dB
around an ideal operating point
of 90°. In a VSWR application, this
40 dB 40 dB
information constitutes the phase
MFLT Forward
angle of the reflected signal (with
Log AMP A + +
Power respect to the incident signal) and
0.1μF Σ
-
Σ
- VMAG
ADC may be of use in optimizing the

μProcessor/DSP
60dB Log Amps
INPA (7 Detectors) MSET power delivered to the antenna.
Pin = -10 to -40 dBm
PSET Reverse AMPLIFIER GAIN
Power
Pin = -10 to -60 dBm 0.1μF 60dB Log Amps
Σ
- VPHS ADC
MEASUREMENT USING A
(7 Detectors)
INPB
+ PFLT SINGLE LOG DETECTOR AND
Log AMP B
AN RF SWITCH
▲ Fig. 6 Return loss measurement using a dual log detector. Figure 8 shows an alternative
approach to gain measurement,
power and one to measure the re- The power from the reverse which is also applicable to VSWR
verse power. As in the previous ex- path is padded down by the same measurement. In this application,
ample, additional attenuation is re- amount. This means that the sys- measuring and controlling the
quired before applying these sig- tem is capable of measuring re- gain of a PA is desired. The PA in
nals to the detectors. The AD8302 flected power up to 0 dB. This the example is running at 8 GHz
dual detector has a measurement may not be necessary if the sys- and has an output power range
range of ±30 dB. The level planning tem is designed to shut down from +20 to +50 dBm. This is a
used in this example is graphically when the reflection coefficient fixed-gain PA, so the output pow-
depicted in Figure 7. In this exam- degrades below a certain mini- er is adjusted by changing input
ple, the expected output power mum (such as 10 dB), but it is power. Two directional couplers
range from the HPA is 30 dB, from permissible because the detector are used to detect input and out-
+20 to +50 dBm. Over this power has so much dynamic range. For put power. However, there is only
range, reflection coefficients from example, when the HPA is trans- a single log detector so the two
0 dB (short or open load) up to –20 mitting +20 dBm, the reverse signals are alternately connected
dB should be able to be accurately path detector will see an input to the detector using a single-
measured. Each of the AD8302’s power of –60 dBm if the antenna pole, double-throw RF switch.
detectors has a nominal input has a return loss of 20 dB. The The AD8317 detector has a 0 to
range from 0 to –60 dBm. In this application circuit provides a di- –50 dBm input range at this fre-
example, the maximum forward rect reading of return loss, but no quency. To measure the gain, the
power of +50 dBm is padded down information is provided about the input and output powers are al-
to –10 dBm at the detector input. absolute forward or reverse pow- ternately measured and digitized.
When the HPA is transmitting at its er. If this information is required, The results are then simply sub-
lowest power level of +20 dBm, the the dual detector used in the gain tracted to yield gain. Once the
detector sees a power of –40 dBm, control would be more useful be- gain is known, the digital control
still well within its input range. cause it would provide a measure loop is completed by making any
of absolute for- necessary adjustments to the gain
ward and reflect- of the PA via a bias adjustment.
+50 ed power along The level planning for this exam-
+40 Forward Reverse with the reflec- ple is shown in Figure 9. Attenu-
Power Power
+30 Range Range tion coefficient. ation is used so that the two input
+20
60 dB
Attenuation The dual log de- power levels at the RF switch are
tector used in the close together and within the in-
POWER (dBm)

Detector A/B
+10 Input
Range
return loss mea- put range of the detector.
0 60 dB
Attenuation surement also
-10 provides a phase PRECISE GAIN MEASUREMENT
-20 output. Because WITHOUT FACTORY
Power
at Input A Power of the large gain CALIBRATION
-30
at Input B
in the main signal In addition to reducing compo-
-40
path of a progres- nent count, this gain measure-
-50 sive compression ment method has a number of in-
-60 log amp, a limited teresting features. Because the
(amplitude satu- same circuit is being used to
▲ Fig. 7 Level planning for VSWR measurement using a dual rated) version of measure input and output power,
log detector. the input signal is it is possible to make precise,

74
WIRELESS TECHNOLOGIES
VOUT1 = SLOPE
Pout = +20 to +50 dBm
@ 8 GHz • (PIN1 – INTERCEPT)
+5V To figure out the unknown, PIN, the
Pin = -20 to +10 dBm 100pF 0.1uF equation can be rewritten as
HPA 500R
20 dB
40 dB
20 dB VPOS PIN1 = (VOUT1/SLOPE) – INTERCEPT
V 1
Since gain is the difference in the

μProcessor/DSP
PA Slope Gain Bias VSET
BIAS 40 dB
CONTROL
ADC
measured input powers (the differ-
Σ
DET DET DET DET VOUT ent attenuation levels of the two
B 1nF INHI CLPF
0.7 220pF
paths still have to be factored in), it
A
1nF INLO
pF can be written as
GAIN = (VOUT1 – VOUT2)/SLOPE
COMM Select
Input/Output
DAC
Therefore, the intercept of the detec-
tor is not required to calculate the
▲ Fig. 8 Gain measurement using a single log detector. gain. Even though the slope of a de-
tector will change from device to de-
vice and over temperature, if Vout1 and Vout2 are close
+50 to each other (it can be done with good level plan-
+40 PA ning and because of the finite input range of the de-
Output
+30 Power tector), a typical value for the slope can be taken di-
Range
+20
rectly from the datasheet and used in the above cal-
culation.
POWER (dBm)

+10 Detector
Input 20 dB
0 PA
Input
Range Coupler
+ OUTPUT POWER MONITORING
40 dB
-10 Power
Range
Attenuation In the gain measurement using a single log detec-
-20 Power Power
tor, the power is measured in order to calculate gain,
-30 20 dB
at Switch at Switch so the system shown can also be used to monitor the
Input A Input B
Directional
Coupler output power. However, this cannot be done pre-
-40
cisely without factory calibration. To calibrate the
-50 circuit, the antenna must be temporarily replaced by
▲ Fig. 9 Level planning for gain measurement using a single a power meter. The output power and detector volt-
log detector. ages are then measured at two points within the lin-
ear range of the detector. These numbers would
-40°C +25°C +85°C then be used to calculate the slope and intercept of
Vout = Slope x (Pin-Intercept) the detector. For optimum precision, the detector in-
Slope (mV/dB) = (Vout2-Vout1)/(Pin2-Pin1) cludes a temperature compensation pin. A resistor is
Intercept (dBm) = Pin1- (Vout1/Slope)
2.00 2.0
connected between this pin and ground to reduce
the temperature drift to approximately ±0.5 dB at the
1.75 1.5 frequency of operation (8 GHz in the example
shown). As a result, it is not necessary to do any ad-
1.50 1.0 ditional calibration over temperature.
Vout2
1.25 0.5
CONCLUSION
Error (dB)
Vout (V)

1.00 0 Because of their linear-in-dB transfer function, log

amplifiers can be easily used to measure gain and re-
0.75 -0.5
Vout1 turn loss. When dual devices are used, very high mea-
0.50 -1.0 surement precision is achievable. In some cases, this
can be achieved without factory calibration. In all cas-
0.25 -1.5 es, careful power level planning is necessary so that
the power detectors are driven at power levels that of-
0
-65 -55 -45 -35 -25 -15 -5 5 15 fer good linearity and temperature stability. ■
Pin (dBm) P Intercept
Pin2 in1

▲ Fig. 10 Calibrating a log detector. Eamon Nash holds a BEng degree in electronics from the
University of Limerick, Ireland. He has worked at Analog Devices for
15 years, first as a field applications engineer, based in Germany,
temperature-stable gain measurements without covering mixed signal and DSP products, then as a product line
ever calibrating the circuit. A look at the nominal applications engineer specializing in RF building block components
transfer function of a log detector will help in un- for wireless applications. He is now applications engineering
derstanding why (see Figure 10). manager for RF Standard Products at Analog Devices.

75
RF Bonus Feature

Analog I/Q and Vector Modulators

Features
Wide range of modulators covering frequencies of operation
from 20 MHz to 4 GHz
Vector modulators provide simultaneous control of both gain
and phase within a single IC
Pin compatibility to cover all cellular frequency bands
High dynamic range direct conversion

RF I/Q 3 dB Phase Amplitude Carrier Sideband Output Supply

Part Noise Floor P1dB Supply
Frequency Bandwidth Error Error Suppress Suppress IP3 Current Package
Number (dBm/Hz) (dBm) Voltage (V)
(MHz) (MHz) (deg) (dB) (dBm) (dBc) (dBm) (mA)
4 mm 4 mm,
AD8340 700 to 1000 230 — — –30 –32 –148 11 24 4.75 to 5.25 130
24-lead LFCSP
1500 to 4 mm 4 mm,
AD8341 230 — — –25 –34 –150.5 9 18 4.75 to 5.25 125
2400 24-lead LFCSP
5.1 mm 6.5 mm,
AD8345 140 to 1000 80 0.5 0.2 –42 –42 –155 2.5 25 2.7 to 5.5 65
16-lead TSSOP
6.5 mm 5.1 mm,
AD8346 800 to 2500 70 1 0.2 –42 –36 –147 –3 20 2.7 to 5.5 45
16-lead TSSOP
5.1 mm 6.4 mm,
AD8349 700 to 2700 160 0.3 0.1 –42 –43 –156 6 19 4.75 to 5.5 135
16-lead TSSOP
4 mm 4 mm,
ADL5370 300 to 1000 >500 0.76 0.03 –50 –41 –160 11 24 4.75 to 5.25 205
24-lead LFCSP
4 mm 4 mm,
ADL5371 500 to 1500 >500 0.1 0.03 –50 –55 –158.6 14 27 4.75 to 5.25 175
24-lead LFCSP
1500 to 4 mm 4 mm,
ADL5372 >500 0.21 0.09 –45 –45 –158 14 27 4.75 to 5.25 165
2500 24-lead LFCSP
2300 to 4 mm 4 mm,
ADL5373 >500 1 0.13 –39 –39 –157 14 25 4.75 to 5.25 166
3000 24-lead LFCSP
2800 to 4 mm 4 mm,
ADL5374 >500 0.2 0.02 –32 –50 –158 12 22 4.75 to 5.25 175
4000 24-lead LFCSP
4 mm 4 mm,
ADL5375 400 to 6000 >500 –0.05 –0.07 –46 –50 –160 9.4 23 4.75 to 5.25 131
24-lead LFCSP
4 mm 4 mm,
ADL5385 50 to 2200 >500 0.39 0.03 –46 –50 –159 11 26 4.75 to 5.25 215
24-lead LFCSP_VQ
4 mm 4 mm,
ADL5390 20 to 2400 230 N/A 0.5 N/A N/A –148 11 24 4.75 to 5.25 135
24-lead LFCSP

76
77
78
 10
CARRIER = 399MHz
0 SFDR WITHOUT SPURKILLER = –63.7dBc
SFDR WITH SPURKILLER = –69.3dBc
–10 FREQUENCY SPAN = 500MHz
RESOLUTION BW = 3kHz
–20 VIDEO BW = 30kHz
SIGNAL POWER (dBm)

–30

–40

–50 CANCELLED CANCELLED

SPUR SPUR
–60

–70

–80

–90

–100
0 100 200 300 400 500
FREQUENCY (MHz)

Figure 1. The plot shows the synthesizer’s output spectrum for a 399 MHz sine wave, with a 1 GHz sampling rate.

AD9549
AD9514
DIGITAL PLL
R, S DIVIDERS /1...../32 LVPECL
REF A HOLDOVER
REF MONITORS
AND SWITCHING
REF B DDS/ LOW-PASS /1...../32 LVPECL
DAC FILTER

/1...../32 Δt LVDS/CMOS
SYSTEM CLOCK
MULTIPLIER

Figure 2. Shown is a complete clock synchronization, generation, jitter clean-up, and distribution circuit with the DDS at the heart of the system.

79
RF Bonus Feature

Direct Digital Synthesizers (DDS)

Features
AD9913: 250 MSPS DDS consumes only 50 mW power
Low power DDS moves into portable/handheld markets
Low cost DDS with integrated DAC replaces standalone DAC
required after FPGA
Programmable modulus mode available for exact rational
frequency synthesis

Narrow-Band
Master Tuning DAC SFDR Power Supply
Part SFDR (dB)/ REFCLK On-Board
Clock Word Width Resolution (dBc) to Dissipation Package Voltage I/O Interface Comments
Number AOUT (MHz)/ Multiplier Comparator
(MHz) (Bits) (Bits) Nyquist (mW) (V)
Window (MHz)
3.3 to Serial or
AD9850 125 32 10 54 80/40.1/0.5 480 28-lead SSOP
5.0 parallel
3.3 to Serial or
AD9851 180 32 10 53 85/40.1/0.5 650 28-lead SSOP
5.0 parallel
80-lead Serial or
AD9852 300 48 12 48 83/10/1 2200 3.3 Chirp function
LQFP/TQFP_EP parallel
80-lead Serial or Quadrature outputs,
AD9854 300 48 12 48 83/10/1 2200 3.3
LQFP/TQFP_EP parallel chirp function
Integrated charge
100-lead Serial or
AD9858 1000 32 10 58 80/40/1 1900 3.3 pump, phase detector,
TQFP_EP parallel
analog multiplier
AD9859 400 32 10 56 80/160/0.1 200 48-lead TQFP_EP 1.8 Serial
AD9951 400 32 14 56 80/160/0.1 200 48-lead TQFP_EP 1.8 Serial
AD9952 400 32 14 56 80/160/0.1 200 48-lead TQFP_EP 1.8 Serial
Programmable RAM
AD9953 400 32 14 56 80/160/0.1 200 48-lead TQFP_EP 1.8 Serial
LUT
Programmable RAM
AD9954 400 32 14 56 80/160/0.1 200 48-lead TQFP_EP 1.8 Serial LUT, automatic
frequency sweep
AD9956 400 48 14 56 80/160/0.1 400 48-lead LFCSP 1.8 Serial On-board 2.7 GHz PLL
AD9958 500 32 10 53 81/200/1 420 56-lead LFCSP 3.3/1.8 Serial 2 complete channels
AD9959 500 32 10 53 81/200/1 680 56-lead LFCSP 3.3/1.8 Serial 4 complete channels
RAM, polar
100-lead Serial or
AD9910 1000 32 14 53 86/300/0.5 800 3.3/1.8 modulation, phase/
TQFP_EP 16-bit parallel
frequency/amp ramp
Multimode modula-
56-lead
AD9911 500 32 10 53 81/200/1 275 3.3/1.8 Serial tion, targeted spur
LFCSP
reduction
64-lead
AD9912 1000 48 14 58 86/398.7/0.5 800 3.3/1.8 Serial Spur reduction
LFCSP
Serial or
AD9913 250 32 10 58 88/99.7/0.03 50 32-lead LFCSP 1.8
parallel

80
 Analog Devices, Inc.
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