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A Dc-Dc Converter with High Voltage Gain and

Two Input Boost Stages

Article in IEEE Transactions on Power Electronics · January 2015

DOI: 10.1109/TPEL.2015.2476377

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4206 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 6, JUNE 2016

A DC–DC Converter With High Voltage Gain

and Two Input Boost Stages
Venkata Anand Kishore Prabhala, Student Member, IEEE, Poria Fajri, Student Member, IEEE,
Venkat Sai Prasad Gouribhatla, Student Member, IEEE, Bhanu Prashant Baddipadiga, Student Member, IEEE,
and Mehdi Ferdowsi, Member, IEEE

Abstract—A family of nonisolated high-voltage-gain dc–dc

power electronic converters is proposed. The suggested topologies
can be used as multiport converters and draw continuous current
from two input sources. They can also draw continuous current
from a single source in an interleaved manner. This versatility
makes them appealing in renewable applications such as solar
farms. The proposed converters can easily achieve a gain of 20
while benefiting from a continuous input current. Such a converter
can individually link a PV panel to a 400-V dc bus. The design and
component selection procedures are presented. A 400-W prototype Fig. 1. High-voltage-gain dc–dc converter in dc microgrid system.
of the proposed converter with Vin = 20 and Vout = 400 V has
been developed to validate the analytical results.
voltage would further degrade the efficiency of the converter
Index Terms—Diode-capacitor voltage multiplier stages, high- [5]. Typically high-frequency transformers or coupled induc-
voltage-gain dc-dc power electronic converters. tors are used to achieve high-voltage conversion ratios [6]–[15].
The transformer design is complicated and the leakage induc-
I. INTRODUCTION tances increase for achieving larger gains, as it requires higher
number of winding turns. This leads to voltage spikes across
ITH the increased penetration of renewable energy
W sources and energy storage, high-voltage-gain dc–dc
power electronic converters find increased applications in green
the switches and voltage clamping techniques are required to
limit voltage stresses on the switches. Consequently, it makes
the design more complicated.
energy systems. They can be used to interface low voltage To achieve high-voltage conversion ratios, a new family of
sources like fuel cells, photovoltaic (PV) panels, batteries, etc., high-voltage-gain dc–dc power electronic converters has been
to the 400-V bus in a dc microgrid system (see Fig. 1) [1]– introduced. The proposed converter can be used to draw power
[3]. They also find applications in different types of electronic from two independent dc sources as a multiport converter [16],
equipment such as high-intensity-discharge lamps for automo- [17] or one source in an interleaved manner. They draw contin-
bile headlamps, servo-motor drives, X-ray power generators, uous input current from both the input sources with low current
computer periphery power supplies, and uninterruptible power ripple which is required in many applications, e.g., solar. Several
supplies [4]. diode-capacitor stages are cascaded together to boost up the volt-
To achieve high voltage gains, classical boost and buck-boost age which limits the voltage stresses on the switches, diodes, and
converters require large switch duty ratios. Large duty cycles capacitors. Due to the advantages listed above, these converters
result in high current stress in the boost switch. The maximum are good solutions to integrate solar panels into a dc microgrid.
voltage gain that can be achieved is constrained by the para- In conventional approaches, as the output voltage of PV panel
sitic resistive components in the circuit and the efficiency is is low, several panels are connected in series when connecting
drastically reduced for large duty ratios. There are diode reverse the PV array to the 400-V dc bus through conventional step-up
recovery problems because the diode conducts for a short period converters. This results in reduced system reliability which can
of time. Also, larger ripples on the high input current and output be addressed by connecting high-voltage-gain converter to each
individual PV panel. Moreover, since it is a multiport converter
Manuscript received August 8, 2014; revised September 26, 2014, November
28, 2014, and February 3, 2015; accepted March 16, 2015. Date of publication with a high voltage gain, independent sources can be connected
September 3, 2015; date of current version January 7, 2016. Recommended for and power sharing, MPPT algorithms, etc., can be implemented
publication by Associate Editor V. Agarwal. independently at each input port.
V. A. K. Prabhala is with International Rectifier, An Infineon Technologies
Company, El Segundo, CA 90245-4318 USA (e-mail: vkpzvf@mst.edu). Similar converters with interleaved boost input have been pro-
P.Fajri is with the department of Electrical and Computer Engineering, North posed earlier using the Cockcroft–Walton (CW) voltage multi-
Carolina State University, Raleigh, NC 27965 USA (e-mail: pfajri@ncsu.edu). plier (VM) [18], [19]. Current fed converters are superior in
V. S. P. Gouribhatla, B. P. Baddipadiga and M. Ferdowsi are with the
Department of Electrical and Computer Engineering, Missouri University of comparison to the voltage fed counterparts as they have lower
Science and Technology, Rolla, MO 65401 USA (e-mail: vgwg3@mst.edu; input current ripple [19]. The limitation with the CW-based con-
bbt68@mst.edu; ferdowsi@mst.edu). verters is that the output impedance increases rapidly with the
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. number of multiplying stages [20]. The efficiency and the out-
Digital Object Identifier 10.1109/TPEL.2015.2476377 put voltage regulation of these converters depend on the output
0885-8993 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
PRABHALA et al.: DC–DC CONVERTER WITH HIGH VOLTAGE GAIN AND TWO INPUT BOOST STAGES 4207

Fig. 3. Switching signals for the input boost stage for the proposed converter.

Fig. 2. Proposed high-voltage-gain dc–dc converter with four VM stages.

impedance; thus, for high gains the converter efficiency would

be affected.
In this paper, a topology is proposed which can easily achieve
a gain of 20 while benefiting from a continuous input current.
Such a converter can individually link a PV panel to a 400-V dc
bus. In Section II, the proposed converter topology is introduced
and different modes of operation are explained. In Section III,
the voltage gain of the converter is derived and an alternative
topology is also explained. In Section IV, current and voltage
stresses required for component selection and loss calculations Fig. 4. Mode-I of operation for the proposed converter with four VM stages.
along with simulation results are provided. In Section V, ex-
perimental results for the prototype converter are provided and
Section VI concludes the paper.

II. TOPOLOGY INTRODUCTION AND MODES OF OPERATION

The proposed converter is inspired from a Dickson charge
pump [20]. Diode-capacitor VM stages are integrated with two
boost stages at the input. The VM stages are used to help the
boost stage achieve a higher overall voltage gain. The voltage
conversion ratio depends on the number of VM stages and the
switch duty ratios of the input boost stages. Fig. 2 shows the
proposed converter with four VM stages. For simplicity and
better understanding, the operation of the converter with four
multiplier stages has been explained here. Similar analysis can Fig. 5. Mode-II of operation for the proposed converter with four VM stages.
be expanded for a converter with N stages.
For normal operation of the proposed converter, there should VM capacitor voltages remain unchanged and the output diode
be some overlapping time when both the switches are ON and Dout is reverse biased (see Fig. 4); thus, the load is supplied by
also one of the switches should be ON at any given time (see the output capacitor Cout .
Fig. 3). Therefore, the converter has three modes of operation.
The proposed converter can operate when the switch duty ratios B. Mode-II
are small and there is no overlap time between the conduction of
the switches. However, this mode of operation is not of interest In this mode, switch S1 is OFF and S2 is ON (see Fig. 5).
as it leads to smaller voltage gains. All the odd numbered diodes are forward biased and the in-
ductor current IL 1 flows through the VM capacitors charging
the odd numbered capacitors (C1 , C3 , . . .) and discharging the
A. Mode-I
even numbered capacitors (C2 , C4 , . . .). If the number of VM
In this mode, both switches S1 and S2 are ON. Both the stages is odd, then the output diode Dout is reverse biased and
inductors are charged from their input sources Vin1 and Vin2 . the load is supplied by the output capacitor. However, if the
The current in both the inductors rise linearly. The diodes in number of VM stages is even, then the output diode is forward
different VM stages are reverse biased and do not conduct. The biased charging the output capacitor and supplying the load.
4208 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 6, JUNE 2016

Fig. 7. Proposed converter with N number of VM stages.

Fig. 6. Mode-III of operation for the proposed converter with four VM stages.
Vin1 Vin2
In the particular case considered here, since there are four VM VC 2 = +
(1 − d1 ) (1 − d2 )
stages, the output diode is forward biased.
2Vin1 Vin2
VC 3 = +
C. Mode-III (1 − d1 ) (1 − d2 )

In this mode, switch S1 is ON and S2 is OFF (see Fig. 6). 2Vin1 2Vin2
VC 4 = + . (4)
Now, the even numbered diodes are forward biased and the (1 − d1 ) (1 − d2 )
inductor current IL 2 flows through the VM capacitors charging The output voltage is derived from (2), which is given by
the even numbered capacitors and discharging the odd numbered
capacitors. If the number of VM stages is odd, then the output Vin1 3Vin1 2Vin2
Vout = VC 4 + = + . (5)
diode Dout is forward biased charging the output capacitor and (1 − d1 ) (1 − d1 ) (1 − d2 )
supplying the load. However, if the number of VM stages is
Similar analysis can be extended to a converter with N number
even, then the output diode is reverse biased and the load is
of VM stages (see Fig. 7). Thus, the VM stage capacitor voltages
supplied by the output capacitor.
are given by
   
III. VOLTAGE GAIN OF THE CONVERTER n+1 Vin1 n−1 Vin2
VC n = +
The charge is transferred progressively from input to the out- 2 (1 − d1 ) 2 (1 − d2 )
put by charging the VM stage capacitors. For a converter with if n is odd & n ≤ N,
four stages of VM (see Fig. 2), the voltage gain can be derived n V n V
in1 in2
from the volt-sec balance of the boost inductors. For L1 , one VC n = +
2 (1 − d1 ) 2 (1 − d2 )
can write
if n is even & n ≤ N. (6)
vL 1  = 0. (1)
The output voltage equation of the converter with N number
Therefore, from Fig. 5, it can be observed that the capacitor of VM stages depends on whether N is odd or even and is given
voltages can be written in terms of upper boost switching node by
voltage as
Vin2
Vin1 Vout = VC N + if N is odd
VC 1 = VC 3 − VC 2 = Vout − VC 4 = (2) (1 − d2 )
(1 − d1 )    
N +1 Vin1 N +1 Vin2
where d1 is the switching duty cycle for S1 . = + (7)
2 (1 − d1 ) 2 (1 − d2 )
Similarly, from the volt-sec balance of the lower leg boost
inductor L2 , one can write the capacitor voltages (see Fig. 6) in Vin1
Vout = VC N + if N is even
terms of lower boost switching node voltage as (1 − d1 )
   
Vin2 N +2 Vin1 N Vin2
VC 2 − VC 1 = VC 4 − VC 3 = (3) = + . (8)
(1 − d2 ) 2 (1 − d1 ) 2 (1 − d2 )
where d2 is the switching duty cycle for S2 . When the converter operates in an interleaved manner with
From (2) and (3), the capacitor voltages for the proposed single input source, if d1 and d2 are also chosen to be identical,
converter with four VM stages can be derived as i.e., d1 = d2 = d, then the output voltage is given by
Vin1 Vin
VC 1 = Vout = (N + 1) . (9)
(1 − d1 ) (1 − d)
PRABHALA et al.: DC–DC CONVERTER WITH HIGH VOLTAGE GAIN AND TWO INPUT BOOST STAGES 4209

Fig. 8. Alternative to the proposed converter with N number of VM stages.

In [21], an interleaved boost power factor corrected converter

with voltage-doubler characteristics is introduced. It can be ob-
served that it is a special case of the proposed converter with a
single VM stage (N = 1).
It is worth noting that there is an alternative to the proposed Fig. 9. Combined topology with single VM stage.
converter (see Fig. 8) where diode D1 of the first VM stage is
connected to the lower boost switching node and capacitor C1
is connected to the upper boost switching node (compare with
Fig. 7).
The output voltage equation for this alternative topology is
given by
   
N +1 Vin1 N +1 Vin2
Vout = +
2 (1 − d1 ) 2 (1 − d2 )
if N is odd (10)
    Fig. 10. Combined topology with N number of VM stages.
N Vin1 N +2 Vin2
Vout = +
2 (1 − d1 ) 2 (1 − d2 ) output voltage to be
if N is even. (11) Vin
Vout = (N + 1) if N is even. (13)
For N = 1, if one combines the topology depicted in Fig. 7 (1 − d)
with its alternative (see Fig. 8), then the resulting converter in For the combined topology with a single input source and
Fig. 9 is similar to the multiphase converter introduced in [22]. identical duty ratios d1 and d2 , i.e., d1 = d2 = d, both the boost
In general, when both topologies with N number of VM stages stages will always have symmetrical inductor and switch cur-
are combined, then the resulting converter is shown in Fig. 10. rents irrespective of the number of VM stages.
When N is odd, then from (7) and (10), the voltage gain of the
combined topology is given by IV. COMPONENT SELECTION AND SIMULATION RESULTS
   
N +1 Vin1 N +1 Vin2
Vout = + A. Inductor Selection
2 (1 − d1 ) 2 (1 − d2 )
The inductor currents in both the boost stages depend on
if N is odd. (12) the number of VM stages connected to each leg. The average
In this case, the original topology and its alternative each inductor current in each boost stage (see Fig. 2) is given by
process half of the output power. In other words, the average  
N +1 Iout
currents of Dout1 and Dout2 are equal. IL 1,avg = if N is odd
2 (1 − d1 )
When N is even, the output voltage of the combined topology  
would be either (8) or (11) and will be dictated by the topology N +1 Iout
IL 2,avg = (14)
that provides a higher output voltage. Both legs (see Fig. 10) 2 (1 − d2 )
would compete with each other and only one of the output  
N +2 Iout
diodes (Dout1 and Dout2 ) would process the entire power while IL 1,avg = if N is even.
2 (1 − d1 )
the other will be reverse biased. When N is even, putting the  
converters in parallel only makes sense if there is only one source N Iout
IL 2,avg = (15)
used and d1 = d2 . In that case both (8) and (11) determine the 2 (1 − d2 )
4210 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 6, JUNE 2016

The peak value of the inductor currents is given by

(N + 1)Iout Vin1 d1
IL 1,pk = + if N is odd
2(1 − d1 ) 2L1 fsw
(N + 1)Iout Vin2 d2
IL 2,pk = + (20)
2(1 − d2 ) 2L2 fsw
(N + 2)Iout Vin1 d1
IL 1,pk = + if N is even
2(1 − d1 ) 2L1 fsw
N Iout Vin2 d2
IL 2,pk = + . (21)
2(1 − d2 ) 2L2 fsw
For inductor copper loss calculation, it is important to know
the rms value of the inductor currents, which can be calculated
as
 2  2
(N + 1)Iout Vin1 d1
IL 1,rm s = + √ if N is odd
2(1 − d1 ) 2 3L1 fsw
 2  2
(N + 1)Iout Vin2 d2
IL 2,rm s = + √ (22)
2(1 − d2 ) 2 3L2 fsw
 2  2
(N + 2)Iout Vin1 d1
IL 1,rm s = + √ if N is even.
2(1 − d1 ) 2 3L1 fsw
 2  2
N Iout Vin2 d2
IL 2,rm s = + √ (23)
2(1 − d2 ) 2 3L2 fsw
Fig. 11. (a) Inductors currents for odd number of VM stages. (b) Inductors
currents for even number of VM stages.
B. MOSFET Selection

It can be observed from (14) and (15) that for a converter with The peak blocking voltage of both the switches is similar to
single input source and identical duty ratios d1 and d2 , when N that of the normal boost converter (see Fig. 2) which is given by
is odd, then both the boost stages have equal average inductor Vin1
VS 1 = (24)
currents [see Fig. 11(a)]. Whereas when N is even, then IL 1,avg (1 − d1 )
is larger than IL 2,avg as observed in Fig. 11(b).
Vin2
The inductor design is similar to that of the normal boost VS 2 = . (25)
converter. The inductor value is selected such that both the (1 − d2 )
boost stages operate in continuous conduction mode (CCM). The current stresses on both the switches depend on the num-
The minimum inductor value for the CCM operation of both the ber of VM stages. The average current through the switches is
boost stages is given by given by
 
(N + 1)d1 (N − 1)
Vin1 d1 (1 − d1 ) IS 1,avg = + Iout if N is odd
L1,crit = if N is odd 2(1 − d1 ) 2
(N + 1)Iout fsw  
Vin2 d2 (1 − d2 ) (N + 1)d2 (N + 1)
IS 2,avg = + Iout (26)
L2,crit =
(N + 1)Iout fsw
(16) 2(1 − d2 ) 2
 
Vin1 d1 (1 − d1 ) (N + 2)d1 N
IS 1,avg = + Iout if N is even
L1,crit =
(N + 2)Iout fsw
if N is even 2(1 − d1 ) 2
 
Vin2 d2 (1 − d2 ) N d2 N
L2,crit = . (17) IS 2,avg = + Iout . (27)
N Iout fsw 2(1 − d2 ) 2
From (26) and (27), for a converter with single input source
The inductor values selected for the assumed ripple current is and identical duty ratios d1 and d2 , it can be observed that when
N is odd, the average current through S2 is greater than S1 [see
Vin1 d1
L1 = (18) Fig. 12(a)]. When N is even, the average current through S1 is
ΔIL 1 fsw greater than S2 [see Fig. 12(b)]. Also, the rms values of switch
Vin2 d2 currents required for loss calculations are given by (28) and (29)
L2 = . (19) shown at the bottom of the next page.
ΔIL 2 fsw
PRABHALA et al.: DC–DC CONVERTER WITH HIGH VOLTAGE GAIN AND TWO INPUT BOOST STAGES 4211

Fig. 13. Switch and diode currents for the proposed converter with four VM
stages.

than vC 1 and vout − vC 4 . When vC 3 − vC 2 and vout − vC 4 are

both balanced, then diodes D3 and Dout start conducting and
share almost equal inductor current IL 1 /2. Diode D1 starts con-
ducting when vC 1 , vC 3 − vC 2 , and vout − vC 4 are all balanced.
During this period, diode current ID 1 is greater than ID 3 and
ID out since the impedance seen by the current path is lower. The
ratio between the currents is dependent on the values chosen for
the VM stage capacitors. Switch current IS 2 during this period
is the sum of IL 2 , ID 1 , and ID 3 , and hence, there is spike and
distortion of the switch current. The magnitude of spike is equal
to the sum of both the inductor currents IL 1 and IL 2 . It can
be observed that the currents exhibit characteristics similar to
Fig. 12. (a) Switch current for odd number of VM stages. (b) Switch current charging/discharging of an RC circuit which is mainly due to
for even number of VM stages. the circuit parasitic resistances such as switch RDS(on) , inductor
DCR, and VM stage capacitor ESR.

It is observed that there is a distortion and spike in the switch

C. Diode Selection
current waveforms [see Figs. 12(a), (b), and 13]. The spike
is observed in IS 1 , when the number of VM stages is odd. The voltage stresses across the diodes depend on the capacitor
However, when the number of VM stages is even, the spike voltages as it is connected between two VM stage capacitors (see
is observed in IS 2 . The spike in switch currents is due to the Fig. 2). It can be observed that in Mode-II of operation, when
voltage imbalance between VM stage capacitors. Fig. 13 shows S1 is OFF and S2 is ON, the odd numbered diodes are forward
the switch and diode currents for the converter with four VM biased and even numbered diodes are in blocking mode.
stages (see Fig. 2). The spike in IS 2 appears during Mode-II Similarly, the odd numbered diodes are in blocking mode
of operation of the converter (see Fig. 5). Initially diode D3 in the Mode-III of operation, when S1 is ON and S2 is OFF
conducts the total inductor current IL 1 , since vC 3 − vC 2 is less (see Fig. 14). The maximum blocking voltage of the VM stage

⎛ ⎞
 2
2
(N + 1) (N − 1) (N + 1)
IS 1,rm s = ⎝ (d1 + d2 − 1) + + (1 − d2 )⎠ Iout if N is odd
2(1 − d1 ) 2(1 − d2 ) 2(1 − d1 )
⎛ ⎞
 2
2
(N + 1) (N + 1) (N + 1)
IS 2,rm s = ⎝ (d2 + d1 − 1) + + (1 − d1 )⎠ Iout (28)
2(1 − d2 ) 2(1 − d1 ) 2(1 − d2 )
⎛ ⎞
 2
2
(N + 2) N (N + 2)
IS 1,rm s = ⎝ (d1 + d2 − 1) + + (1 − d2 )⎠ Iout if N is even
2(1 − d1 ) 2(1 − d2 ) 2(1 − d1 )
⎛ ⎞
 2
2
⎝ N N N
IS 2,rm s = (d2 + d1 − 1) + + (1 − d1 )⎠ Iout . (29)
2(1 − d2 ) 2(1 − d1 ) 2(1 − d2 )
4212 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 6, JUNE 2016

TABLE I
COMPONENT LIST FOR THE EXPERIMENTAL PROTOTYPE

Item Reference Rating Part No

Inductor L1 , L2 100 μH DCR = CTX100-10-52LP

11 mΩ
MOSFET S1 , S2 150 V, 43 A IPA075N15N3G
R D S ( o n ) = 7.5
mΩ
Diode D1 , D2 , D3 , D4 , Dou t 250 V, 40 A MBR40250T
V D = 0.97 V
Capacitor C1 , C2 , C3 , C4 20 μF, 450 V ESR = C4ATGBW5200A3MJ
2.2 mΩ
Capacitor Cou t 22 μF, 450 V B32774D4226

Fig. 14. Diode voltages for odd and even number of VM stages.

As explained earlier, the odd numbered diodes conduct dur-

ing Mode-II of operation and the even numbered diodes conduct
during Mode-III of operation. The average and rms diode cur-
rents required for diode selection and loss calculation is given by
ID o dd,avg = ID even,avg = ID out,avg = Iout (33)

1
ID o dd,rm s = Iout (34)
1 − d1

1
ID even,rm s = Iout (35)
1 − d2

1
ID out,rm s = Iout if N is odd (36)
1 − d2

1
ID out,rm s = Iout if N is even. (37)
1 − d1

V. EXPERIMENTAL RESULTS

The laboratory prototype with four VM stages and with in-

terleaved boost input stage with a single source was built to test
and validate the proposed converter operation. The components
used for building the prototype are listed in Table I. The con-
verter is rated at 400 W with input voltage of 20 V and output
voltage of 400 V. The switching frequency of the converter is
100 kHz.
The component selection is critical as it determines the output
Fig. 15. (a) Output diode voltage for odd number of VM stages. (b) Output
diode voltage for even number of VM stages. voltage regulation and the efficiency of the converter. The output
capacitor is selected based on the amount of charge that is
diodes is given by transferred to the output for a desired output voltage ripple
which is given by
Vin1 Vin2
VD n = + . (30) Iout
(1 − d1 ) (1 − d2 ) qout = Cout ΔVout = (1 − d) (38)
fsw
However, the output diode conducts during Mode-III of op- where d is either d1 or d2 based on whether the number of
eration when there is odd number of VM stages as shown in VM stages are even or odd. The same amount of charge qout is
Fig. 15(a) and conducts during Mode-II of operation when there transferred progressively by the VM stage capacitors. The VM
is even number of VM stages as shown in Fig. 15(b). The peak stage capacitors for a desired ripple voltage is given by
blocking voltage of the output diode is given by
Iout
Vin2 Cn ΔVC n = (1 − d) . (39)
VD out = if N is odd (31) fsw
(1 − d2 ) The VM stage capacitors are selected such that the equivalent
Vin1 series resistance due to charging/discharging of the capacitors
VD out = if N is even. (32)
(1 − d1 ) is low keeping the total capacitance to reasonable levels; thus,
PRABHALA et al.: DC–DC CONVERTER WITH HIGH VOLTAGE GAIN AND TWO INPUT BOOST STAGES 4213

Fig. 16. Loss distribution of the proposed converter at 400 W output power.

Fig. 19. Voltage stresses on the boost switches.

Fig. 17. Efficiency of the proposed converter with interleaved input and four
VM stages.

Fig. 20. Voltage waveform across diode D 4 .

verter at 400 W output power. The switching losses in both the

MOSFETs are calculated by a commonly used formula given by
1
PSW = × IL ,avg × VS × (tOFF + tON )
2
1
+ × fsw × Coss × VS2 (40)
2
where IL ,avg , VS , and fsw are the inductor current, switch volt-
Fig. 18. Inductor current waveforms at 200 W output power.
age, and switching frequency respectively, while tON and tOFF
are the MOSFET turn-on and turn-off switching times [23].
improving the efficiency and output voltage regulation. It is The power loss associated with the charging/discharging of
important to select VM stage capacitors with low ESR to min- the VM stage capacitors can be calculated by calculating the
imize the losses, for that purpose thin-film capacitors are se- series equivalent resistance [20]. When all the VM stage capac-
lected as they have low ESR values. Furthermore, the VM stage itors are assumed to be the same, then the power loss is given by
capacitors and the output capacitor are selected based on the
ripple current ratings of the capacitors. For the VM stage ca- N
2
PC = Iout × (41)
pacitors, the ripple current will be higher, therefore, capacitor C × fsw
C4ATGBW5200A3MJ (20 μF, 450 V) is selected which has where C is the value of the VM stage capacitors. The total
a ripple current rating of 29 A. Since the output capacitor has power loss in the proposed converter is given by
lower ripple currents, capacitor B32774D4226 (22 μF, 450 V)
is selected which has a ripple current rating of 9 A. The output PLoss = PL 1 + PL 2 + PS 1 + PS 2 + PSW 1 + PSW 2
voltage gain and efficiency also depends on the inductor DCR, +PD + PC . (42)
forward voltage drop of the diode, and the MOSFET RD S (on) .
The losses in the proposed converter can be easily calculated Based on the loss breakdown, the efficiency of the proposed
based on the average and rms currents calculated in the previous converter comes out to be 96.6% at 400 W with total power
section. Fig. 16 shows the loss distribution of the proposed con- loss being 13.61 W. Compared with this, the efficiency of the
4214 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 6, JUNE 2016

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PRABHALA et al.: DC–DC CONVERTER WITH HIGH VOLTAGE GAIN AND TWO INPUT BOOST STAGES 4215

Venkata Anand Kishore Prabhala (S’14) received Venkat Sai Prasad Gouribhatla (S’15) received the
the B.S. degree from the National Institute of Tech- B.Tech. degree in electrical and electronics engineer-
nology, Warangal, India, in 2005, and the M.S. and ing from the VNR Vignana Jyothi Institute of Engi-
Ph.D. degrees from the Missouri University of Sci- neering and Technology, Hyderabad, India, in 2010.
ence and Technology, Rolla, MO, USA, in 2010 and After that, he was an Engineer R&D with Medha
2014, respectively. Servo Drives Pvt. Ltd., Hyderabad, India. He is cur-
From 2005 to 2008, he was a Project Engineer at rently working toward the Master’s degree at the Mis-
Larsen & Toubro Ltd., India. Since 2014, he has been souri University of Science and Technology, Rolla,
a Global Rotation Engineer at International Recti- MO, USA.
fier, An Infineon Technologies Company, El Segundo, His research interest include power electronics.
CA, USA. His research interests include design and
control of power electronic converters, ac and dc microgrids, electric drive ve-
Bhanu Prashant Baddipadiga (S’12) received the
hicles, and renewable energy systems.
B.Tech. degree from the Sreenidhi Institute of Sci-
ence and Technology, Hyderabad, India, in 2011. He
is currently working toward the Ph.D. degree in elec-
trical engineering from the Missouri University of
Science and Technology, Rolla, MO, USA.
His research interests include power electronic
converters, dc microgrids, and integration of renew-
able energy in microgrids.

Poria Fajri (S’13) received the B.S. degree in elec-

tronics from Urmia University, Urmia, Iran, in 2005, Mehdi Ferdowsi (S’02–M’04) received the B.S. de-
the M.S. degree in electrical engineering from the gree in electronics from the University of Tehran,
University of Tehran, Tehran, Iran, in 2008, and the Tehran, Iran, in 1996, the M.S. degree in electronics
Ph.D. degree in electrical engineering from the Mis- from the Sharif University of Technology, Tehran,
souri University of Science and Technology, Rolla, Iran, in 1999, and the Ph.D. degree in electrical en-
MO, USA, in 2014. gineering from the Illinois Institute of Technology,
He is currently a Postdoctoral Research Asso- Chicago, IL, USA, in 2004.
ciate with the NSF FREEDM Systems Center, North He is currently a Professor at the Missouri Uni-
Carolina State University, Raleigh, NC, USA. His versity of Science and Technology, Rolla, MO, USA.
research interests include electric-drive vehicles, re- His research interests include electric-drive vehicles,
newable energy systems, flexible ac transmission systems, and power electronic multiinput power converters, multilevel power con-
converters. verters, and battery charge equalization.
Dr. Ferdowsi received the US National Science Foundation CAREER Award
in 2007. He is an Associate Editor of the IEEE TRANSACTIONS ON POWER
ELECTRONICS.