MP1009

Nu-PulseTM, Half-Bridge and Push-Pull

CCFL Inverter Controller
The Future of Analog IC Technology
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY
DESCRIPTION FEATURES
The MP100 9 is a fixe d operating frequency • Drives Two Exter nal, L ow Co st, N -Channel
inverter controller that controls t wo external MOSFETs
power MOSFETs in Nu-Pulse TM, Half-Bridge or • Fixed Operating Frequency
Push-Pull configuration for powering one or • Input Voltage Range of 8V to 30V
more cold cathode fluor escent lamps (CCFL) to • Lamp Current and Voltage Regulation
backlight liquid crystal displays (LCD). • Burst Mode Dimming Control
The MP1009 offers cost effective solutions with • Integrated Burst Mode Oscillator andModulator
minimized external components. Th e controller • Soft-On and Soft-Off Burst Envelope
provides high efficiency power conversion of • Open Lamp & Short circuit Protection
unregulated DC input voltages to nearly pur e • Fault Timer and Indicator
sine waves. The featured fault detection and • Available in SOIC 16 Package
protection scheme (patent pendin g) includes
open lamp regulation, open lamp protection and APPLICATIONS
short lamp protection. • Desktop LCD Flat Panel Displays
Burst mode dimming is controlled w ith either an • Flat Panel Video Displays
external analog or digital signal. Lam p voltages • LCD TVs and Monitors
and lamp currents are continuously regulated "MPS", "The Future of Analog IC Technology", and "Nu-Pulse" are Trademarks
under any operating conditions. of Monolithic Power Systems, Inc.
MP1009 and Nu-Pulse configuration are MPS proprietary technologies covered
The MP100 9 is available in a 16-pin SOIC by US Patents:
6,683,422 6,114,814
package. 6,316,881 7,161,305
Other patents are pending.

TYPICAL APPLICATION
MP1009
OV2 OV2 OV1 OV1

LI1 LI1 C1
OL1
R12 LV1
LI2 LI2 R1
C9 C2
C11
COMP REF
C12
FT

R9 R13 C18 C3
FSET OL2
C10
C14 LV2 R2
BOSC
R10 C4
R11
DBRT VIN
C13 R14

R15 C5
C15 OL3
REF LV3
C6 R3

R5 R8 R7 R6
LV1 LI2 LI1
R18
OV1 C7
R16 R17 OL4
LV4 R4
LV4
D4 D3 C8
LV2
R19
OV2 OL1 OL4 OL2 OL3

LV3

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 MP1009 – NU-PULSETM CCFL INVERTER CONTROLLER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY

ORDERING INFORMATION
Part Number* Package Top Marking Free Air Temperature (TA)
MP1009ES SOIC16 MP1009ES -20°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP1009ES–Z).
For RoHS Compliant packaging, add suffix –LF (e.g. MP1009ES–LF–Z)

PACKAGE REFERENCE

ABSOLUTE MAXIMUM RATINGS (1) Recommended Operating Conditions (3)

Input Voltage VIN......................................... 34V Input Voltage VIN .................................8V to 30V
BT and TG ............................ -0.3V to VIN+VCC Digital Brightness Voltage VDBRT ........0V to 1.2V
SW. ................................................. -0.3V to VIN Operating Frequency .............. 20kHz to 100kHz
VCC and BG ................................ -0.3V to +6.5V Operating Frequency (Typical) ................ 50kHz
Logic Inputs ................................. -0.3V to +6.5V Operating Junct. Temp (TJ).... –20°C to + 125°C
LI1 and LI2 Inputs ........................ -5.8V to +5.8V
Thermal Resistance (4) θJA θJC
OV1 and OV2 inputs ..................-0.3V to +14.5V
(2) SOIC16 ...................................80 ...... 30 ... °C/W
Continuous Power Dissipation (TA = +25°C)
Notes:
……………………………………………....1.56W 1) Exceeding these ratings may damage the device.
Junction Temperature ...............................150°C 2) The maximum allowable power dissipation is a fun ction of the
maximum junction temperatu re T J (MAX), the junction-to-
Power Dissipation ...................................... 0.6W ambient thermal resistance θJA, and the a mbient temperature
Lead Temperature (Solder).......................260°C TA. The maximu m allow able con tinuous po wer di ssipation at
any ambient te mperature is ca lculated by P D (MAX) = (T J
Operating Frequency ............................. 150kHz (MAX)-TA)/θJA. Exceeding the maximum allowable powe r
Storage Temperature............... -55°C to +150°C dissipation w ill cause ex cessive die tempe rature, and t he
regulator will g o into thermal shutdown. Inte rnal thermal
shutdown circuitr y pr otects the device from permanent
damage.
3) The device is not guarant eed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.

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 MP1009 – NU-PULSETM CCFL INVERTER CONTROLLER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
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ELECTRICAL CHARACTERISTICS
VIN = 17.5V, TA = +25°C, unless otherwise noted.
Parameter Sy mbol Condition Min Typ Max Units
Gate drive TG, BG
Gate Pull-Down RGD 1.6 Ω
Gate Pull-Up RGU 5 Ω
Brightness Control Range
DBRT Full Scale VDBRT DC burst dimming 1.1 1.2 1.3 V
DBRT Logic Input Threshold PWM dimming 1.6 1.9 2.2 V
DBRT Logic Input Hysterisis PWM dimming 0.3 V
Burst Rate Generator
Source Current ISRC(BRS) VBRS = 2V 120 150 180 µA
Lower Threshold VV(BRS) 2.20 2.40 2.60 V
Upper Threshold VP(BRS) 3.3 3.55 3.8 V
Supply Current
Supply Current (Enabled) IPR No Switching 1.7 3 mA
Supply Current (Disabled) IPR 7 15 µA
Operating Frequency fO 100 kΩ FSET to GND 44 48 52 kHz
Frequency Set Voltage VSWS 1.1 1.2 1.3 V
Lamp Current Feedback (LI1 and LI2)
Pull Up Current Source Isource 55 µA
Open Lamp Detect Threshold VTH_OL 0.9 1.1 1.3 V
Protection Delay TD_SC 220 µs
Magnitude |V LI| 2.87 3.05 3.23 V
Lamp Voltage Feedbacks (OV1 and OV2)
Open La mp Voltage
VTH 10.7 11.5 12.3 V
Feedback Threshold (Peak)
Input Resistance OV1, OV2 pin to GND 300 kΩ
Short Circuit Detect Threshold VTH_SC DC bias 6V 4.5 4.9 5.3 V
Protection Delay TD_SC 300 µs
Fault Indicator
Threshold Vt(FT) 1.15 1.21 1.27 V
Sink Current ISINK(FT) –1 µA
Open Lamp Source Current IPU_OL(FT) 1 µA
Short Lamp Source Current IPU_SL(FT) 100 µA

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PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
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ELECTRICAL CHARACTERISTICS (continued)

VIN = 17.5V, TA = +25°C, unless otherwise noted.
Parameter Sy mbol Condition Min Typ Max Units
Comp
IC On Threshold
VON_TH Rising threshold 0.55 0.65 0.75 V
(Used as EN Function)
Enable Hysteresis 150 mV
Clamp Voltage VCOMP 0.8 0.9 1 V
Reference Current ICOMP+ 20 µA
Decay Current ICOMP- End of Burst 12 µA
Output (VCC)
Voltage V CC 5.6 5.9 6.2 V
Current I CC 5 mA

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PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY

PIN FUNCTIONS
Pin # Name Description
Open lam p voltage feedb ack input 2. Con nect this pin to the tap of a cap divider and a bias
resistor to VCC for lamp voltage feed ba ck. In multi-lamp application, connect this pin through a
diode in “or” relationship to all lamp voltage feed back points, which are AC in phase.
If the peak voltage value at OV2 pin e xceeds +11.5 V, the control ler treat s this as lamp ove r-
1 OV2 voltage condition. A pulse of current will pull-do wn the COMP pin voltage to regulate the lamp
voltage. The burst dimming signal is ignored and the Fault Timer starts ramping up.
This signal is also use d for short circuit prot ection. If the voltage at OV2 is always above 4.9V,
the controller will treat this as a short circuit condition after a certain delay. The Fault Timer will
start ramping up. In single lamp application, connect OV1and OV2 pins together.
Lamp curren t feedback 1. Conn ect this pin to the cu rrent sense re sistor. In multi-lamp
application, connect this pin through a diode in “and” relationship to call lamp current feed back
points, which are A C in phase. Combined with the lamp current feedback signal from LI2, the
signal is fed t o the internal error a mplifier. Selecting the feedback resistors can easily program
2 LI1 the lamp current.
The signal is also used for open lamp protection. If the voltage at L I1 is always below 1.1V, the
controller treats this a s an open l amp condition after a ce rtain delay. The bu rst dimming signal
is ignored and the Fault Timer starts ramping up. In single lamp application, short LI1 to LI2 pin
and connect to the lamp current feedback resistor through a small RC filter.
Lamp current feedback 2. The function of this pin is same as LI1. In multi-lamp application, this
3 LI2
pin is used for lamp current feedback which is out-of-phase of LI1.
Feedback Compensation Node. Connect a compensation capacitor from this pin to GND.
4 COMP This pin is also used for IC enable control. A logic low (below 0.5V) input turns off the IC. The
enable logic input signal should have open collector (OC) structure.
Fault Indicator. Connect a capacitor from this pin to GND to program the open lamp and short
5 FT lamp protection delay time. When the voltage on this pin reaches 1.2V, the IC is shutdown until
it is enabled again.
Switching Frequency Set. Connect a resistor from this pin to GND. This resistor sets the
6 FSET
operating frequency of the MP1009.
Burst Repetition Rate Setting. For DC input internal burst dimming, connect a resistor and a
capacitor from this pin to GND. The burst dimming frequency and minimum dimming duty is
7 BOSC
programmed by the resistor and capacitor values. For external logic PWM input dimming,
connect BOSC to VCC and apply the logic signal to the DBRT pin.
Burst-Mode (Digital) Brightness Control Input. For DC input internal burst dimming, the voltage
range of 0V to 1.2V at DBRT linearly sets the burst-mode duty cycle from minimum to 100%.
8 DBRT
For external logic PWM input dimming, drive DBRT pin higher than 2.2V and lower than 1.6V to
directly control the inverter dimming duty. If burst dimming is not used, connect DBRT to VCC.
Input Power Rail. Decouple this pin to GND with >1µF ceramic capacitor. It is desirable to add a
9 VIN
10Ω resistor between VIN pin and the input bus.
Output Bootstrap. BT provides gate driver bias for the high-side MOSFET. Connect a capacitor
10 BT
from BT to SW.
High-Side MOSFET Gate Output. Connect TG to the gate of the high-side, external power
11 TG
MOSFET.
Bridge Output. Connect SW to the source of the high-side MOSFET and the drain of the
12 SW
low-side MOSFET.

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 MP1009 – NU-PULSETM CCFL INVERTER CONTROLLER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
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PIN FUNCTIONS (continued)
Pin # Name Description
Voltage Rail Output. VCC provides power supply for the low-side gate driver and the internal
13 VCC
control circuitry. Bypass VCC to GND with a ceramic capacitor.
14 BG Low-Side MOSFET Gate Output. Connect BG to the gate of the low-side MOSFET.
Circuit Ground. Connect power GND and analog GND of the PCB to this pin. The power GND
15 GND for power switches and the analog GND for the control signals is desired to be separated and
only connected at this pin.
Open lamp voltage feedback input 1. The function of this pin is same as OV2. In multi-lamp
16 OV1
application, this pin is used for lamp voltage feedback which is out-of-phase of OV2.

BLOCK DIAGRAM
Vin

5 FT Vin 9 REF
6V Reg Lamp1

VCC 13 REF

16 OV1 Short
OV1
Circuit
Protection TG 11
0.2X
(SCP)
1 OV2
OV2 Fault
Over
+ Management BT 10
Voltage
Protection REF
2.4V - Lamp2
(OVP) PWM
Driver
EN(OC) 4 COMP SW 12

+
Chip EN BG 14
600mV -
CONTROL LOGIC

1.2V + GND 15
55uA
-
2 LI1 REF
LI1 Lamp3
Vin
OR 0.5X
3 LI2
LI2

Open Lamp
Protection
(OLP)
REF
Lamp4

6 FSET Lamp Lamp PWM

Clock OV2

OV1
7 BOSC Burst Rate
Generator
Burst
PWM LI1
8 DBRT
Dimming

LI2

Figure 1—Functional Block Diagram

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OPERATION Fault Protection
The MP10 09 is a fixed frequency inverter When the lamp is open, the voltage feedback
controller f or CCFL application, especially on OV1 an d OV2 pin is used to r egulate the
optimized for multi-lamp applications. The lamp voltag e. The volt age feedback on OV1
MP1009 ha s an integ rated bootstrap driver and OV2 is scale d do wn with an internal 0. 2
stage which offers the advantage of adopting gain stage. If the peak value exceeds 2.4V after
low cost N-MOSFET as the upper switch. the gain st age, the COMP pin will be pulled
down by a 20µA current pulse. At the same
EN Function
time, the F T timer will be charged by the 1µA
The MP1009 has integrated EN function with
current. If t he FT voltage exceeds 1.2V, the
the feedback compensation pin COMP. A logic
controller will shut-down.
low (typical below 0.5V) turns off the IC. An
open collector (OC) si gnal is req uired as EN Also, the lamp current feedback pin LI1 and LI2
signal which connected to COMP. can be use d for open lamp protection. In open
lamp condition, the corresponding current
Lamp Current/Voltage Regulation
feedback si gnal will be zero, which will trigge r
The MP10 09 features two current and two
the internal FT timer.
voltage feedback pin s to achieve: la mp current
regulation, lamp over-voltage regulation and When the lamp is sho rted, the re lated lamp
protection. When the lamp is lit, the duty c ycles voltage feedback will be zero, which will change
of the power devices ar e regulated to maintain the waveform fed into OV1/ OV2 pin. If the
the lamp current feedback. In open or unstuck voltage signal is always above 4.9 V, the short
lamp condit ions the pe ak value of the lamp circuit detector will trigg er the FT ti mer, and the
voltage is similarly regulated via the lamp FT timer will be charg ed by a 100uA current
voltage feedback. source.
Both pair s of fe edback signals are Burst Dimming
simultaneously functional during operation. In MP1009 implements burst dimming (digital
multi-lamp applications, the in-phase and out- brightness) control to the lamp. Burst mode
of-phase signal current and voltage signals can operation dims the lamp by modulating the duty
be connected to separate pins, which cycle of a burst of AC lamp current and features
dramatically simplify the external circuit. In soft-on/soft-off control of the lamp current
addition the MP1009 d erives Fault conditions envelope. Burst dimming can be a chieved by
via these feedback pins, further simplifying either a DC voltage input or an ext ernal PW M
external circuitry. signal. The MP1009 has a built-in burst
oscillator which can generate a triangle
Switching Frequency
waveform on the BOSC pin. A DC voltage can
The switching frequency is set by the resistance
be applied on the DBRT pin a nd it linearly
from the FSET pin to ground.
controls the burst dimming duty cycle. If the
At open lamp condition, the internal open lamp BOSC pin is tied to VCC (6V), the DBRT pin
control circuit adopts t he adaptive frequency can be d irectly driven with an external PWM
control method based on the in put, output dimming signal (100Hz - 500Hz).
condition, w hich sets th e open lamp frequency
Thermal Shutdown
automatically. The adaptive frequency control
Thermal shutdown is implemented to prevent
method can guarantee the striking voltage at
the chip from operati ng at exce edingly high
any te mperature, which is also not sensitive to
temperatures. When the silicon die temperature
the parameters variation in practical production.
is higher th an 150 °C, it shuts down the whole
The maxi mum frequen cy under this operation
chip. When the temperature is lower than its
mode is set to be 1.4 times of normal frequency.
lower threshold, typica lly 145 °C, the chip is
enabled again.

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APPLICATION INFORMATION Pin1 (OV2) & Pin 16 (OV1): Lamp Voltage
Regulation and Short Circuit Protection
The typical 4-lamp half bridge application circuit OV1 and OV2 are u sed for lamp voltage
is used as an example to describe the design feedback a nd short cir cuit protection with the
procedure. unique protection method (patent protected).
Pin 2 (LI1) & Pin 3 (LI2): Lamp Current
In multi-lamp applicatio n, the lamps should also
Regulation and Open Lamp Protection
be divided into two gro ups, i.e. in- phase group
R1~R4 is used to set th e current for each lamp.
and out-of-phase group. OV1 and OV2 pin can
For multi-lamp application, the lamps can b e
be used for these two gr oups separately, which
divided into two groups, in-phase group and
is just the same as lamp current feedback. Also,
out-of-phase group. LI1 and LI2 can be used for
if the lamps are all in-phase, th ey can be
these two groups separately. In each group, the
divided into two groups equally.
lamp current feedback signal is co nnected to
LI1/LI2 pin via a diode, which forms an AND A DC bias (REF, 6V) is added to la mp voltage
gate with an internal 55uA pull up current feedback for short circuit protection. An internal
source. resistor divider with 0.2X gain scales down the
input signal.
The lamp current sig nal on LI1 and LI2 is
combined in a full wave rectifier and scale down In normal operation, the OV1 and OV2
with an internal resistor divider, the gain is 0.5. waveforms should be sinusoidal with 6V DC
The internal reference is 1.2V for average value, bias a s so wn in Figur e 3. In the short circuit
For the 4 lamp application with diode on LI pin, condition, the negative half cycle will be missed,
the lamp current se nse resisto r can be which will tr igger the in ternal protection cir cuit.
calculated as: The protection threshold for OV1/ OV2 pin is
R1≈2.7V/I(LAMP)rms 4.9V.
Where I (LAMP)rms is the lamp rms current. For
7.4mA rms, R1~R4 is 374Ω.

Figure2—Open lamp protection with LI1/LI2

Also, the lamp curren t feedback signal on Figure3— Short Circuit protection with
LI1/LI2 pin is compared to internal 1.1V OV1/OV2
reference before the internal resisto r divider. In
normal operation, the v oltage waveform should The regulated open lamp voltage is proportional
be sinusoidal wavefo rms. In open lamp to the ratio of C1 to C2 (also, C3 to C4, C5 to
condition, the positive half cycle will be missed C6 and C7 to C8).
as shown in Figure 2, which will trigger the C1 has to be rated at 3kV and is typically
open lamp protection. between 5pF to 22pF. T he value of C2 is set by

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customer to program t he required open lamp For short circuit:
voltage. The value of DC bias resistors (R5~R8)
The internal current for short circuit protection is
is typically 10kΩ.
100uA instead of 1uA fo r open lamp protection,
For safety operation, VPP for nor mal operation the off time will be approximately 100 times
should be a t least 3V, thus the maximu m open faster than open lamp time. To reduce the short
lamp voltage ratio (open lamp voltage to normal turn off timer further, the connection at FT node
operation lamp voltage) is 4:1. can be modified to:
Pin 4 (COMP): C11 100k
C11 is the feedback compensation capacito r FT
(connected between COMP and analog GND).
C12 Cft
A 1.5nF~4.7nF (X 7R ceramic) cap is
recommended. The value of C11 affects the
soft-on rising time and soft-off falling time of the
lamp current at each b urst dimming cycle by Figure 4— Turn off time Adjustment
changing the comp voltage slew rate.
Cft can be used to adjust the short circuit turn
The EN fun ction is also combined with COMP off time.
pin. If the COMP pin is pulled down below 0.5V,
the IC will turn off. The EN signal connected to Pin 7 (BOSC): C14, R10
COMP pin should have t he open collector (OC) BOSC is used to set the Burst Rep etition Rate.
structure to avoid any affecting in COMP pin C14 and R10 will set the bur st repetiti on
under normal operation . If the EN signal from frequency (f BURST) and the minimum burst on
system is not an OC signal, an extra NPN time (tMIN) as shown in Figure 5.
transistor is required to get the OC structure. Be Set t MIN to achieve t he minimum required
careful, if th e extra NPN transistor is used, th e system brightness and ensure that t MIN is long
polarity of EN is reversed (Active at low input). enough so that the la mp does not extinguish.
Pin 5 (FT): C12 These values are determined as follows:
The capacit or C12 fro m FT to GND sets the Select a Minimum Burs t Duty Cyc le (D MIN)
fault timer. This capacitor will determine th e where:
time MP1009 takes to r each the fault threshold
(1.2V). User can choose the capacitor value to D=
MIN tMIN × fBURST
program the protection delay time.
Pin 6 (FSET): R9
R9 is used to set the lamp operating clock. The
value for R9 is calculated by:
48kHz
R9 = 100kΩ ×
fS
For R9 = 10 0kΩ, the op erating clock will be 48
kHz.
For open lamp:
C12=T(open lamp)*(1uA)/1.2V
Figure 5—Burst Mode with DC input voltage
For a C12=820nF, then the time o ut for open at DBRT pin.
lamp is 0.98s.

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R10 and C14 can be estimated by the following Pin 9 (VIN): C15, C18 Input Power Rail
equations: An electrolytic capacitor and a ceramic
capacitor ar e recomme nded between VIN and
⎛⎞ 1 power ground. The ceramic capacitor C18
R10 ≈ 21.16kΩ ⎜⎟ -1 + 21.43kΩ
⎝⎠DMIN should be placed clo se to the MOSFETs to
supply the high frequency energy and attenuate
1- DMIN the switchin g noise. N ote that th e loop are a
C14 = formed by U2, U3 and C18 must be minimized.
BURST ×× 10
fR 0.405
Pin 10 (BT): C10
For D MIN=0.1, f b=200Hz, we get R10=212k Ω, BT is the bias supply for the level shift of the
C14=52nF. upper MOSFETs. C10 should be large enoug h
If the burst dimming is to be con trolled by an to supply the energy required for driving the
external log ic signal, connect BOSC to VCC MOSFET. A 100nF capacitor of X7R ceramic
and apply the logic signal to the DBRT pin. material is recommended.
Table 1—Function Mode Pin 11 (TG), Pin 14 (BG): R12, R13
These pins are used to drive the MOSFETs. A
Pin Connection 0Ω~15Ω se ries gate r esistor is optional to
Function
DBRT BOSC reduce the switching noise.
Burst Mode with Pin 12 (SW)
0V to 1.2V C14, R10
DC Input Voltage This pin connects to the source of the high-side
Burst Mode with MOSFET and the drain of the low-side
PWM V CC
External Source MOSFET in the output bridge. One end of the
Burst Brightness Polarity: 100% duty cycle at primary tra nsformer is also conn ected to this
DBRT voltage 1.2V. pin.
Pin 8 (DBRT): R11, C13 Another end of the transformer is connected to
DBRT is used for bur st brightness control. The a capacitor divider as shown in Figure 1. The
DC voltage on this pin will control the burst capacitors C16 and C17 should be ceramic and
percentage on the outp ut. The sign al should be have a ripp le current rating greater than the
locally filter ed for optimal operation. A voltage primary current. X 7R type of cap acitors are
ranging fro m 0V to 1.2V on DBRT wi ll preferred. Their value is typically in a range o f
correspond to a Burst Duty Cycle from 2.2µF~6.3µF. R14 and R15 are used to ensure
minimum to 100%, respectively. R11 and C13 the voltages across the capacitors are zero at
form a low pass filter to reduce the noise of the start up. Typically, R14 and R15 are 10kΩ.
input DC voltage. Recommended values are Pin 13 (VCC): C9
10kΩ and 0.1µF. This capacitor bypasses the 6V gate supply for
For direct P ulse Width Modulation of the burst the low-side switches. It also supplies power to
signal, connect BOSC to VCC and drive DBRT the internal logic circuit of MP1009. This pin
with a logic level PWM signal. A logic-High is should be bypassed with a ceramic X7R
Burst-On and a logic-Low is Burst-Off. capacitor. The recommended value is 1uF.

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TYPICAL APPLICATION CIRCUIT
MP1009
OV2 OV2 OV1 OV1

LI1 LI1 C1
OL1
8pF/3kV
R12 LV1
LI2 LI2 R1
3 C2
C11 C9 1uF/16V 374/1%
2.2nF/50V
COMP REF
3.3nF/50V
C12 1uF/16V
FT

R9 97.6k/1% R13 C18 C3

FSET 1uF/25V OL2
C10 3 8pF/3kV
C1468nF/50V 100nF/50V LV2 R2
BOSC
C4 374/1%
R10 221k/1%
R11 2.2nF/50V
DBRT VIN
10k
C13 R14
0.1uF/50V 10k

R15 C5
C15 8pF/3kV OL3
220uF/25V10k
REF LV3
C6 R3
2.2nF/50V 374/1%
R5 R8 R7 R6
10k 10k 10k 10k
LV1
LI2 LI1
R18
OV1 C7
BAV70 8pF/3kV
OL4
2k R16 2k R17 2k
LV4 R4
LV4
BAW56 BAW56
C8 374/1%
LV2 2.2nF/50V
D4 D3
R19
OV2
2k BAV70
OL1 OL4 OL2 OL3
LV3

MP1009 Rev. 0.91 www.MonolithicPower.com 11

4/15/2010 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
 MP1009 – NU-PULSETM CCFL INVERTER CONTROLLER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY

PACKAGE INFORMATION
SOIC16
0.386( 9.80)
0.394(10.00) 0.024(0.61) 0.050(1.27)

16 9
0.063
(1.60)

0.150 0.228
(3.80) (5.80) 0.213
PIN 1 ID 0.157 0.244 (5.40)
(4.00) (6.20)

1 8

TOP VIEW RECOMMENDED LAND PATTERN

0.053(1.35)
0.069(1.75)
SEATING PLANE 0.0075(0.19)
0.0098(0.25)
0.013(0.33) 0.050(1.27) 0.004(0.10)
0.020(0.51) BSC 0.010(0.25) SEE DETAIL "A"

FRONT VIEW SIDE VIEW

NOTE:
0.010(0.25)
x 45o
0.020(0.50) 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
GAUGE PLANE 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
0.010(0.25) BSC PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
0.016(0.41) SHALL BE 0.004" INCHES MAX.
0o-8o 0.050(1.27) 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AC.
6) DRAWING IS NOT TO SCALE.
DETAIL "A"

NOTICE: The information in this docum ent is subject to chang e without notice. Users sh ould warrant and guarantee that third
party Int ellectual Prop erty r ights are n ot inf ringed u pon when i ntegrating MPS product s into any application. MPS w ill not
assume any legal responsibility for any said applications.

MP1009 Rev. 0.91 www.MonolithicPower.com 12

4/15/2010 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.