MP1006

OFF LINE CCFL/EEFL CONTROLLER

The Future of Analog IC Technology

MPS CONFIDENTIAL AND PROPRIETARY INFORMATION –TCL USE ONLY

DESCRIPTION FEATURES
The MP1006 is a high performance off-line • 9V Enhanced Gate Driver, Can Directly Drive
CCFL/EEFL controller designed for powering the the Gate Driving Transformer
Cold Cathode Fluorescent Lamp (CCFL) and • Programmable Fixed Operating Frequency
External Electrode Fluorescent Lamp (EEFL), • Input Voltage Range from 9V to 30V
especially for multi-lamp Liquid Crystal Display • Lamp Current and Voltage Regulation
(LCD) backlighting applications. • Burst Mode Dimming Control
The MP1006 utilizes fixed operating frequency • Integrated Burst Mode Oscillator and Modulator
PWM control to the inverter. It outputs two 180 • Soft-On and Soft-Off Burst Envelope
degree phase shifted driving signals for various • Smart Fault Protection Interface
external power stages. Its enhanced 9V gate • Built-in fault management
driver provides adequate driving capability for • Dual Mode Fault Timer
the external MOSFETs. It is able to directly • Programmable Striking Frequency, Striking
drive the external gate driving transformer. The Time and Burst Dimming Frequency
inverter converts unregulated DC voltage to a • Unique Short Circuit Current Limitation
nearly sinusoidal lamp voltage to power up • Available in SOIC 16 Package
CCFL or EEFL lamps.
The MP1006 implements burst mode dimming
APPLICATIONS
to the lamp. Burst mode dimming is controlled • LCD TV and LCD Monitor in Off-line System
with either an external DC voltage or PWM • Flat Panel Video Displays
signal. • Off Line Inverter for CCFL/EEFL driver
The Built-in fault management features include “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
open lamp regulation and protection, short circuit

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The MP1006 is covered by US Patents 6,683,422, 6,316,881, and
protection and over temperature protection. The 6,114,814. Other Patents Pending.
protection interface is flexible for various setups

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and is easy to use.
The MP1006 is available in a 16-pin SOIC

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package.

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 MP1006—OFF LINE CCFL/EEFL CONTROLLER

MPS CONFIDENTIAL AND PROPRIETARY INFORMATION –TCL USE ONLY

SIMPLIFIED TYPICAL APPLICATION

400V LV1
LI1

MP1006
1 16
OLP OLP GR

2 15
LV LV GND LI2
LV2
3 14
VDRV SLP GL
VDRV
LV3
4 13
LI LI VDRV
LI3
5 12
COMP VIN
11

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6
FT EN

7 10
LCC DBRT

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9 400V GND
8
LCS BOSC
LV4

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LI4

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DBRT
LV1
EN LV LV2
LV3

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VIN
LV4

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LV1
LI1 LV4
OLP

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LI LI2
400V LV2
LI3
LV3
400V GND LI4

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 MP1006—OFF LINE CCFL/EEFL CONTROLLER

MPS CONFIDENTIAL AND PROPRIETARY INFORMATION –TCL USE ONLY

PACKAGE REFERENCE ABSOLUTE MAXIMUM RATINGS (1)

Input Voltage VIN .......................................... 35V
GL, GR ........................................ -0.3V to 10.7V
Logic Inputs, LV, OLP ................. –0.3V to +6.5V
LI, SLP ........................................ –5.8V to +5.8V
Junction Temperature .............................. 150°C
Lead Temperature (Solder)...................... 260°C
Operating Frequency .............................150KHz
Storage Temperature .............. –55°C to +150°C
(2)
Recommended Operating Conditions
Input Voltage VIN .................................9V to 30V

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Operating Frequency ............. 20KHz to 100KHz
Operating Frequency (Typical) ................50KHz

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Operating Temperature............ –20°C to + 85°C

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Part Number* Package (3)
Thermal Resistance θJA θJC
MP1006ES SOIC16 SOIC16 ...................................80 ...... 30 ... °C/W

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Temperature Top Marking
Notes:
–20°C to +85°C MP1006ES 1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
* For Tape & Reel, add suffix –Z (eg. MP1006ES–Z)

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operating conditions.
For RoHS Compliant Packaging, add suffix –LF (eg. 3) Measured on JESD51-7, 4-layer PCB
MP1006ES–LF–Z)

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ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Gate driver GL, GR
Gate Pull-Down RGD 2 Ω
Gate Pull-Up RGU 4 Ω
Output Source Current ISOURCE 1 A
Output Sink Current ISINK 2 A
Maximum Duty Cycle DMAX 46%
EN
EN Turn On Threshold VEN-ON 2 V
EN Turn Off Threshold VEN-OFF 1 V
Internal Pull-down Resistor REN-IN 60 kΩ
Brightness Control Range
DBRT Full Scale VDBRT DC burst dimming 1.1 1.2 1.3 V
DBRT Logic Input Threshold VTH-DBRT PWM dimming 1.6 1.9 2.2 V
DBRT Logic Input Hysteresis VTH-DBRT-Hyst PWM dimming 0.3 V
Burst Rate Generator
Source Current ISRC(BRS) VBRS = 2V 120 150 180 µA
Lower Threshold VV(BRS) 2.2 2.4 2.6 V
Upper Threshold VP(BRS) 3.3 3.55 3.8 V

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, TA = +25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Supply Current
Supply Current (Enabled) IIN-EN No driver output 1.5 2.5 mA
Supply Current (Disabled) IIN-OFF VIN=30V 1 µA
Operating Frequency fO 25kΩ LCS to GND 46 50 54 kHz
Frequency Set Voltage VLCS 1.1 1.2 1.3 V
Lamp Clock Control (LCC)
Start Sweeping
LCC Enable Threshold VLCC-EN 0.8 0.9 1.0 V

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Frequency
At Fault Condition,

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LCC Source Current ILCC-FT 44 48 51 µA
25kΩ LCS to GND
Frequency Increase Slope ∆F0/∆VLCC 0.9V<VLCC<4.9V 14 15.5 17 kHz/V

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Lamp Current Feedback (LI)
Magnitude |VLI| 1.13 1.20 1.27 V

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Sine Equivalent VLI 1.33 Vrms
Input resistance RLI_IN 60 kΩ

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Lamp Voltage Feedbacks (LV)
Open Lamp Voltage
VTH(LV) 2.2 2.4 2.6 V

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Feedback Threshold (Peak)
Fault Timer

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Threshold Vt(FT) 2.2 2.4 2.6 V
Sink Current ISINK(FT) –1 µA
Open Lamp Source Current IPU_OL(FT) 1 µA
Short Lamp Source Current IPU_SL(FT) 100 µA
Comp
Clamp Voltage VCOMP 0.60 V
Reference Current ICOMP+ 20 µA
Reference Current at Fault µA
ICOMP+FT Fault Condition 3.7
Condition
Pull Down Current at Voltage µA
ICOMP-VR LV>2.4V 30
Regulation
Decay Current ICOMP- End of Burst 12 µA
Fault Detection Threshold (OLP, SLP, LI)
OLP Threshold VOLP 2.2 2.4 2.6 V
SLP Threshold VSLP 2.2 2.4 2.6 V
SLP Detection Delay Time TSLP Start when VCOMP>0.9V 400 us
LI threshold VLI 0.55 0.60 0.65 V
LI Detection Delay Time TLI Start when VCOMP>0.9V 400 us
Output Gate Driver (VDRV)
Voltage VVDRV No load 8.7 9.7 10.4 V
Current IVDRV 20 mA

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MPS CONFIDENTIAL AND PROPRIETARY INFORMATION –TCL USE ONLY

PIN FUNCTIONS
Pin # Name Description
1 OLP Open Lamp Protection Input. A comparator is integrated in this pin for open lamp protection.
If the voltage on this pin gets higher than 2.4V, the open lamp protection will be generated. It
starts the fault timer by sourcing a 1uA current from FT pin, sweeps up the operating
frequency by generating an internal current source flowing out of LCC pin, and disables the
burst dimming.
2 LV Lamp Voltage Feedback Input. The lamp voltage is sensed by this pin through a voltage
divider from the hot end of the lamp to ground. If the voltage at LV exceeds +2.4 V, the
COMP pin voltage is regulated to keep the lamp voltage at a high constant value. At the
same time, the fault protection is triggered and the fault timer is started. The burst dimming is
disabled when fault protection is triggered.
3 SLP Short Lamp Protection Input. A comparator is integrated in this pin for short lamp protection.

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If the voltage on this pin gets lower than 2.4V for 400us (counting when VCOMP>0.9V), the
short protection will be generated. It starts the fault timer by sourcing a 100uA current from
FT pin, sweeps up the operating frequency by generating an internal current source flowing

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out of LCC pin, and disables the burst dimming. The reference for the lamp current feedback
is lowered down to 1/6 in order to limit the short current. The protection function is disabled at

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burst off interval.
4 LI Lamp Current Feedback Input. Connect this pin to the cold end of the lamp and shunt a

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sense resistor to ground. The internal error amplifier will sink a current from the COMP pin
proportional to the absolute value of the voltage at this pin. The average of the absolute value
of the voltage at this pin is regulated to 1.2V reference voltage.
The voltage on this pin is also used for open lamp detection and protection. When the voltage

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on this pin gets lower than 0.6V for 400us (counting when VCOMP>0.9V), the IC recognize this
as open lamp condition and generate a signal to sweep up the operating frequency and

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disable the burst dimming. At the same time, the fault protection is triggered and fault timer is
started. At burst off interval, the detection and protection are disabled.

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5 COMP Feedback Compensation Node. Connect a compensation capacitor from this pin to GND.
6 FT Fault Timer. Connect a timing capacitor from this pin to GND to set the fault timeout period.
When the voltage on this pin gets higher than the 2.4V threshold, the IC latches up until EN is
toggled.
7 LCC Lamp Clock Control. The voltage on LCC will control the switching frequency. Connect a
resistor paralleled with a capacitor from this pin to GND. If open lamp or short circuit is
detected, an internal current will source from this pin. The sourcing current is determined by
the LCS pin resistor. The voltage on this pin from 0.9V to 4.9V will linearly increase the
operating frequency by 0 to 61kHz. LCC pin is also a flag that the fault condition is triggered.
8 LCS Lamp Clock Set. Connect a resistor from this pin to GND. This resistor sets the operating
frequency of the MP1006. A 25kOhm resistor sets the operating frequency at typical 50kHz.
9 BOSC Burst Repetition Set. Connect a resistor in parallel with a capacitor from BOSC to GND. The
resistor and capacitor programs the burst repetition rate and the minimum burst duty cycle. If
the burst dimming is to be controlled by an external logic signal, pull up BOSC to VDRV
through a 20kΩ resistor and apply the logic signal to the DBRT pin.
10 DBRT Burst-Mode (Digital) Brightness Control Input. The voltage range from 0 V to 1.2V at DBRT
linearly sets the burst-mode duty cycle from the minimum duty to 100%. For external PWM
input dimming, directly apply the logic signal on this pin. The MP1006 has positive dimming
polarity.
11 EN Enable Input. Pull EN high to turn on the chip, and pull EN low to turn it off.

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PIN FUNCTIONS (continued)
Pin # Name Description
12 VIN Supply voltage input.
13 VDRV Linear Regulator Output and Bias Supply of the Gate Driver. It provides the supply for the
gate driver and also the external control circuit, the typical value is 9.7V. Bypass VDRV with a
1μF or larger ceramic capacitor.
14 GL Driving signal output, 180 degree phase shifted of GR
15 GND Ground.
16 GR Driving signal output, 180 degree phase shifted of GL

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OPERATION

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6 FT

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1 OLP
2.4V VDRV

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3 SLP
2.4V Fault
Management GL 14
2 C

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LV Gate
2.4V O Driver
N

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0.6V
4 T
LI
R

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Error L
1.2V Amplifier VDRV
0.2V at short L
Lamp
5 COMP
PWM O
G 16
GR
8 LCS I Gate
Lamp Driver
7 Clock
C
LCC 15
GND

9 BOSC

Burst
Rate
Generater
10 DBRT VIN 12 VIN
Regulator

11 EN
VDRV 13

Figure 1—MP1006 Block Diagram

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MPS CONFIDENTIAL AND PROPRIETARY INFORMATION –TCL USE ONLY

DESIGN INFORMATION duty cycle. When burst dimming with external

PWM signal, pull up BOSC pin to VDRV through
Steady State and Enable Control
a 20kΩ resistor and apply the PWM signal on
The MP1006 is a fixed operating frequency off- DBRT pin.
line inverter controller specifically designed for
Fault Protection
the backlighting of multiple lamp liquid crystal
displays (LCD). Powered by 9V to 30V input System fault management facilities include the
supplies, the MP1006 outputs two 180 degree on-chip open-lamp detector and regulator, a dual
phase shifted driving signals for the external mode fault timer and two smart comparators for
power stages. Its enhanced 9V gate driver open lamp and short circuit protection.
provides adequate driving capability to the
The lamp voltage is monitored by the LV pin
external MOSFETs. It is able to directly drive the
through a capacitor divider, once the voltage on
external gate driving transformer.
LV pin exceed 2.4V reference, the MP1006 will
The operating frequency is set by an external pull down the COMP voltage by a current pulse

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resistor to minimize the possibility of interference and reduce the power delivering to the power
with the refresh rate of the display. The operating stage. Thus smoothly and stably regulate the

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frequency can be set by the resistor connected lamp voltage to a user programmed striking
from LCS pin to GND. voltage. At the same time when LV pin voltage

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hits the 2.4V threshold, the Open Lamp Mode is
The lamp striking frequency under open lamp
triggered.
condition is programmed by the LCC pin. The

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voltage on LCC in range of 0.9~4.9V linearly At Open Lamp Mode, the IC generates an
increases the operating frequency by 0 to 61kHz. internal current source flowing out of the LCC pin.
When LCC voltage is lower than 0.9V, the Together with the resistor connected from LCC to

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operating frequency is not influenced. GND, a user programmed voltage is generated,
which linearly increases the operating frequency.

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The MP1006 utilizes PWM control to the inverter.
The LCC pin voltage in range of 0.9~4.9V linearly
The lamp current is sensed at LI pin and compared
programs the frequency increase by 0 to 61kHz.
with internal reference. The internal error amplifier

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The LCC pin internal current source is
generates the error signal on COMP pin to control
determined by the LCS pin resistor. And the
the PWM duty cycle. The full-wave lamp current
capacitor on LCC pin helps to program the
sense amplifier provides superior output pulse
frequency sweeping speed. Meanwhile, a 1uA
symmetry and loop response time.
current source will charge the FT cap. If the
The system power is controlled by EN pin. When voltage on FT pin exceeds 2.4V, the controller
the chip is enabled, the built-in regulator for VDRV will shutdown and latch until the EN pin is toggled
is powered up and the internal circuit starts. to restart the IC. Choose a proper capacitor on
FT pin to obtain a desired timeout. In normal
Brightness Control
condition a 1μA sink current keeps the FT pin at
MP1006 implements burst dimming (digital 0V. During Open Lamp Mode, the IC ignores the
brightness) of the lamp. Burst mode operation burst control and runs continuously to ensure
dims the lamp by modulating the duty cycle of a either the lamp has a chance to re-ignite or the
burst of AC lamp current and features soft- fault timer can smoothly and accurately time out.
on/soft-off control of the lamp current envelope.
The MP1006 has a built-in burst oscillator which The lamp current feedback LI pin also functions
can generate a triangle waveform on the BOSC as the open lamp detection. If the peak voltage
pin. Burst dimming can be achieved by either a on LI pin is lower than 0.6V for 400us (count
DC voltage input or external PWM signal. When when VCOMP>0.9V), the IC recognizes the lamp is
burst dimming with a DC input voltage, add a open, and triggers the Open Lamp Mode. At
capacitor in parallel with a resistor on BOSC pin burst dimming off interval, the fault detection on
to set the burst frequency and apply the DC LI pin is disabled.
voltage on the DBRT pin to program the burst

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Two smart comparators are integrated for the
open lamp and short circuit protection. It
simplifies the protection design in multiple lamps
application.
The OLP pin is used for open lamp protection.
When the voltage on OLP pin is higher than 2.4V,
the IC recognizes this as open lamp condition
and triggers the Open Lamp Mode.
The SLP pin is used for short lamp protection.
When the voltage on SLP pin is lower than 2.4V
for 400us (count when VCOMP>0.9V), the IC
recognizes it as short lamp condition and triggers

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the Short Lamp Mode. At burst dimming off

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interval, the fault detection on SLP pin is disabled.
At Short Lamp Mode, the IC also charges up the

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LCC pin to sweep up the frequency and ignores
the burst dimming. It starts the short mode fault
timer by sourcing a 100uA current to charge the

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FT capacitor, which is 100 times faster than that
in the Open Lamp Mode. During Short Lamp
Mode, the internal current feedback reference is

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reduced to 1/6 of the normal value, which helps
for limiting the short circuit current to meet the

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safety requirement.

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APPLICATION INFORMATION Pin 5 (COMP):

Pin 1 (OLP): This pin is used for compensation. Connect a

1~4.7nF capacitor from COMP to GND. This cap
Open Lamp Protection: This pin is used for open should be X7R ceramic. The value of this cap
lamp protection, when the voltage on this pin is determines the stability of the lamp current
higher than 2.4V, the IC recognize this as open regulation and open lamp voltage regulation. It
lamp condition and triggers Open Lamp Mode. also affects the soft-on rise time and soft-off fall
Connect the signals which can indicate open time at burst dimming.
lamp condition to this pin. The maximum lamp
voltage, the maximum lamp voltage difference or Pin 6 (FT):
the maximum lamp current difference are usually Connect a capacitor from this pin to GND to set
used to indicate the open lamp condition. the fault timer.
Pin 2 (LV): Open Lamp Time Out:
Open Lamp Voltage Regulation: This pin is used t OPEN LAMP × 1μA
C1 =
for open lamp voltage regulation and open lamp 2.4V

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protection. When the voltage on this pin exceeds
2.4V, an internal current source will discharge For a C1 = 1uF, then the time out for open lamp

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COMP to regulate the open lamp voltage. The will be 2.4 sec.
regulated open lamp voltage is proportional to Short lamp Timeout: When Short Lamp Mode is

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the ratio of the voltage divider in the voltage triggered, the IC charges the FT cap with 100uA
feedback. When LV voltage hits 2.4V, the IC current. The short lamp timeout is about 1/100 of
recognizes this as open lamp condition and the open lamp timeout. To further reduce the

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triggers Open Lamp Mode. short lamp timeout, modify the network at the FT
Pin 3 (SLP): pin as shown in Figure 2.

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Short Lamp Protection: This pin is used for short FT
lamp protection, when the voltage on this pin

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gets lower than 2.4V for 400us (Count when C2A C2B
VCOMP>0.9V), the IC takes it as short lamp

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condition and triggers Short Lamp Mode. The
minimum lamp voltage is usually used to indicate
the short lamp condition. Figure 2—Timeout Adjustment
Pin 4 (LI): For C2B = 100nF, then the short lamp timeout is
as short as 2.4ms.
Lamp Current Regulation: This pin is used for
Current regulation. The lamp current is fed back Note: The open lamp time out will remain the
to the LI pin. The absolute voltage on this pin is same value as defined by C2A.
regulated with 1.2V average value. For the
Pin 8 (LCS):
sinusoid waveform on this pin, its RMS value is
regulated to 1.33Vrms. At Short Lamp Mode, the Connect a resistor from this pin to GND to set
reference voltage for LI is reduced to 0.2V (1/6) the lamp operating frequency (fo). The value for
to limit the short circuit current. this resistor R1 is calculated by
LI pin also functions as open lamp detection, 1.25 × 10 9
when the voltage on this pin gets lower than 0.6V R1 =
for 400us (count when VCOMP>0.9V), the IC fo
recognizes this as open lamp condition and For R1 = 25kΩ, operating clock will be 50kHz.
triggers Open Lamp Mode.

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Pin 7 (LCC): PWM signal. Logic High is Burst On and a logic
Low is Burst Off.
This pin is used to program the striking frequency
at open lamp condition. The voltage on this pin in Pin 9 (BOSC):
range of 0.9V~4.9V increases the operating
BOSC pin is used to set the burst dimming
frequency by 0~61 kHz, as shown in figure 3.
frequency. Connect a resistor (R2) in parallel with
a capacitor (C3) on this pin to set the burst
dimming frequency and the minimum burst on
time: tMIN, as shown in figure 4.

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Figure 3—Striking Frequency vs. LCC Voltage

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At Open Lamp Mode or Short Lamp Mode, an
internal current source flows out of this pin. With

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a resistor in parallel with a capacitor on this pin,
the IC softly sweeps up the striking frequency.

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The resistor determines the striking frequency
value and the capacitor determines the sweeping
speed. It helps to establish the striking voltage to Figure 4—Burst Mode with DC Input Voltage

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ignite the lamp and also helps to eliminate the at DBRT Pin
voltage spike by its soft sweeping.
Set tMIN to achieve the minimum required system

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The LCC voltage is:
brightness. Ensure that tMIN is long enough that
1.2V the lamp does not extinguish.
V LCC = × RLCC

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RLCS
These values are determined as follows:
The striking frequency is:
Fstrike = Fop + (VLCC − 0.9) × 15.5 × 10 3 Select a Minimum Duty Cycle, DMIN, where:

The sweeping frequency can also be D MIN = t MIN × fBurst

programmed externally by applying a voltage to R2 and C3 are determined by:
LCC pin. At this condition, connect a 100Ω
resistor on LCC pin to limit the flowing out current. ⎛ 1 ⎞
R 2 ≈ 21.16k ⎜⎜ − 1⎟⎟ + 21.43k
Pin 10 (DBRT): ⎝ DMIN ⎠
This pin is used for burst brightness control. For
1 − DMIN
C3 =
DC input burst dimming, the DC voltage on this f Burst × R 2 × 0.405
pin controls the burst percentage on the output. For DMIN = 0.1, fBurst = 200Hz, then R2 = 212k, C3 =
The signal is filtered for optimal operation. A voltage 52nF
ranging from 0 to 1.2V on DBRT programs the For direct PWM burst dimming, pull BOSC high
burst dimming duty cycle from the minimum duty to VDRV through a 20kΩ resistor and apply the
cycle to 100%. PWM signal to DBRT pin.
For direct Pulse Width Modulation (PWM) burst
dimming, Pull BOSC high to VDRV through a
20kΩ resistor and connect DBRT to a logic level

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Pin 13 (VDRV):
Table 1—Function Mode
This pin provides the gate driver supply voltage,
Pin Connection
Function its typical value is 9.7V. Connect a 1uF or greater
DBRT BOSC ceramic capacitor on this pin to bypass the
Burst Mode with supply voltage. This voltage is also used to
0V to 1.2V C3, R2
DC Input Voltage supply the external control circuit.
To VDRV
Burst Mode with Pin 14(GL), Pin 16 (GR):
PWM through 20kΩ
External Source
resistor Gate driving signals output. GL and GR are 180
Burst Brightness Polarity: 100% duty cycle at degree phase shifted driving signals. With its
DBRT voltage 1.2V. enhanced driving capability, GL and GR are able
to directly drive the externally MOSFET in the off-
Pin 11 (EN): line system through a gate driving transformer.
Pull this pin high to enable the chip, and pull it Connect two 5Ω resistors in series with GL and
low to disable the chip. GR to eliminate the EMI noise injected to the IC.

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Pin 12 (VIN):
Supply voltage input. By pass the supply voltage

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with a 0.1uF or greater ceramic cap. This cap
should be placed close to the IC.

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O
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P1006—OFF LINE CCFL/EEFL CONTROLLER

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Figure 6—MP1006 400V EEFL Driver for 32” Panel

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PACKAGE INFORMATION
SOIC16
0.386( 9.80)
0.394(10.00) 0.024(0.61) 0.050(1.27)

16 9
0.063
(1.60)

0.150 0.228
(3.80) (5.80) 0.213
PIN 1 ID 0.157 0.244 (5.40)
(4.00) (6.20)

1 8

TOP VIEW RECOMMENDED LAND PATTERN

0.053(1.35)
0.069(1.75)
SEATING PLANE 0.0075(0.19)
0.0098(0.25)
0.013(0.33) 0.050(1.27) 0.004(0.10)
0.020(0.51) BSC 0.010(0.25) SEE DETAIL "A"

FRONT VIEW SIDE VIEW

NOTE:
0.010(0.25)
x 45o
0.020(0.50) 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
GAUGE PLANE 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
0.010(0.25) BSC PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
0.016(0.41) SHALL BE 0.004" INCHES MAX.
0o-8o 0.050(1.27) 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AC.
6) DRAWING IS NOT TO SCALE.
DETAIL "A"

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.

MP1006 Rev. 0.9 www.MonolithicPower.com 14

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