UNIT I

ARM 7, ARM 9, ARM 11 PROCESSORS

Prof. M. N. Kakatkar
Sinhgad College of Engineering
 Unit- I:ARM7,ARM9,ARM11 Processors
2

Syllabus:
• ARM and RISC design philosophy
• Introduction to ARM processors and its versions
• ARM7, ARM9 & ARM11 features, advantages &
suitability in embedded application
• ARM7 :-
• data flow model
• programmer’s model, Registers , CPSR, SPSR
• modes of operations
• Introduction to Tiva TM4C123G Series Overview
• Programming model
• Tivaware Library
Text Book: “ARM System Developer’s Guide”, Andrew Sloss ( T1)
 RISC PROCESSORS
 It is a design philosophy aimed at delivering
simple but powerful instruction set that execute
within a single cycle at high clock speed.
 RISC is an acronym for Reduced Instruction
Set Computers

 CISC – Complex Instruction Set Computer

 The RISC Philosophy
(four major design rules)
4

1. Instructions
• Reduced number of instruction classes to provide simple
operations that can each execute in a single cycle.
• Each instruction is a fixed length to allow the pipeline to
fetch future instructions before decoding the current
instruction. (Unlike CISC)
2. Pipelines
• The processing of instructions is broken down into smaller
units that can be executed in parallel by pipelines.
• Ideally the pipeline advances by one step on each cycle for
maximum throughput. Instructions can be decoded in
one pipeline stage.
 The RISC Philosophy…
(four major design rules)…
5

3. Registers
• RISC machines have a large general-purpose register set.
• Any register can contain either data or an address.
• (CISC : Have dedicated registers for specific purposes)
4. Load-Store Architecture
• The processor operates on data held in registers.
• Separate load and store instructions : transfer data
between the register bank and external memory. Because
memory accesses are costly.
 RISC vs. CISC
RISC CISC
1. Simple instruction taking 1. Complex instruction may
one cycle. take one or more clock
cycles.
2. Large symmetric register 2. Few registers to store
file data.
3. Less instructions to access 3. More instructions to
memory. access memory.
4. Few addressing modes. 4. More addressing modes.
 RISC vs. CISC

5. Instruction Decoder is 5. Instruction decoder is

simple. Hardwired logic complex. Decoder using
is used for decoder. ROM which consists
6. Supports pipelining. microcode.
i.e. overlapping of fetch, 6. Does not support
decode, execute takes pipelining.
place.
7. Fixed instruction size. 7. Variable instruction size.
 RISC vs. CISC

8. Core takes less chip area 8. More chip area is taken by

so more space for cache, core CPU.
MMU.
9. Complexity in software. 9. Complexity in Hardware.
Compiler design is difficult. Emphasis is on hardware.
10. Higher clock rates. 10. Lower clock rates. So,
So faster. comparatively slower.
11. Cache memory is 11. Cache memory is absent
or unified cache is present.
present.
 ARM
 ARM is not pure RISC processor. It is combination of RISC
with CISC. Because it gives more attention to system
performance, not the clock speed.
 Its target good code density, and low power
consumption.
 The key points are to improve performance using simple
instructions, to speed up using pipeline, provide larger
register file, use a load store architecture.
 Difference of ARM from pure RISC

1) It adds a barrel shifter to expand the capability.

2) It uses Thumb 16 bit instructions to improve code
density.
3) It improve code density and performance by
conditionally executing instructions.
4) It allows variable cycle execution to save code size,
power.
ARM
ARM
ARM Partnership Model
 ARM History
14

• In1983, developed by Acorn computers.

• First, ARM prototype in 1985.
• In 1990’s TI incorporated ARM for mobile phones
• One of the most licensed and thus widespread processor cores
in the world
• Used in PDA (Personal Digital Assistant), cell phones,
multimedia players, handheld game console, digital TV and
cameras
• ARM7: GBA , iPod
• ARM9: NDS , PSP (Play Station Portable), Sony Ericsson, BenQ
• ARM11: Apple iPhone, Nokia N93, N800
• Used especially in portable devices due to its low power
consumption and reasonable performance
First Look at ARM Processor
 ARM family comparison
16
 Nomenculature (ARM Variants)
17

ARMxyzTDMIEJFS
• x: series - 7/9/11/cortex
• y: Memory management, protection unit
• z: cache
• T: Thumb 16 bit instruction set
• D: On chip Debug support
• M: Enhanced Multiplier
• I: Embedded ICE (built-in debugger hardware-)
• E: Enhanced instruction
• J: Jazelle (JVM): - 8 bit mode
• F: Floating-point
• S: Synthesizable version (source code version for EDA tools)
 ARM Variants
 T – Thumb Variant
 M – Long multiplication instruction variant
 D- The ARM core supports debug via JTAG interface.
 E- The ARM core supports Enhanced DSP instructions.
 F- ARM core supports hardware Floating point unit.
 I- ARM core supports hardware breakpoints and watchpoints via
Embedded ICE cell.
 J – ARM core supports Jazzle architecture.
 Note : All ARM core after ARM 7TDMI supports features,
even name is not given.
 ARM7 - Features
19

 32-bit RISC processor (32-bit data & address bus)

 Big and Little Endian operating modes
 High performance RISC (17 MIPS sustained @ 25 MHz (25
MIPS peak) @ 3V)
 Low power consumption (0.6mA/MHz @ 3V fabricated in
.8µm CMOS)
 Fully static operation (ideal for power-sensitive applications)
 Fast interrupt response (for real-time applications)
 Virtual Memory System Support
 Excellent high-level language support
 Simple but powerful instruction set
 ARM7 - Applications
20

 The ARM7 is ideally suited to those applications requiring

RISC performance from a compact, power-efficient processor
 Telecomms - GSM terminal controller

 Datacomms - Protocol conversion

 Portable Computing - Palmtop computer

 Portable Instrument - Hendheld data acquisition unit

 Automotive - Engine management unit

 Information systems - Smart cards

 Imaging - JPEG controller

 ARM9 - Features
21

Some of the features offered by the ARM9 processor are:

 Java acceleration
 DSP extensions
 Optional floating point unit
 Flexible local memory system with cache and exceptional
Tightly Coupled Memory (TCM) integration
 Binary compatibility with the ARM7TDMI® processor
 ARM9 - Applications
22

Product Type Application

Smartphones, PDA, Set top box,

Consumer Electronic toys, Digital still cameras,
Digital video cameras etc

Wireless LAN, 802.11, Bluetooth,

Networking
Firewire, SCSI, 2.5G/3G Baseband etc

Power train, ABS, Body systems,

Automotive
Navigation, Infotainment etc

USB controllers,bluetooth controllers,

Embedded
medical scanners etc

Storage HDD controllers, solid state drives etc

 ARM11 - Features
23

 Powerful ARMv6 instruction set architecture.

 ARM Thumb® instruction set reduces memory bandwidth and size
requirements by up to 35%.
 ARM Jazelle® technology for efficient embedded Java execution.
 ARM DSP extensions SIMD (Single Instruction Multiple Data)
media processing extensions deliver up to 2x performance for
video processing.
 ARM TrustZone® technology for on-chip security foundation.
 ARM11 - Applications
24

 Consumer:- Smart Phone, Home Video Security

 Automotive :-Electronic Control unit of automobiles

 ARM Processor Dataflow Model
25
 Using Barrel shifter for second operand
26
 Working of ARM Processor Core Operation
27

1. Data (instruction to execute or a data item ) enters the processor core

through the Data bus. Data items and instructions share the same bus.

2. The instruction decoder translates instructions before they are executed.

The ARM processor : uses a load-store architecture & has two instruction
types for transferring data in and out of the processor.
a. Load instructions copy data from memory to registers in the core, and
b. Store instructions copy data from registers to memory.
c. No data processing instructions that directly manipulate data in memory.

3. Data processing is carried out solely in registers.

 Working of ARM Processor Core Operation
28

4. Data items are placed in register file of 32-bit registers.

5. ARM instructions typically have two source registers, Rn
and Rm, and a single result or destination register, Rd.
6. The ALU or MAC (multiply-accumulate) takes the
register values Rn and Rm from A & B buses and
computes a result.
7. Data processing instructions write the result in Rd
directly to the register file.
8. For load and store instructions the incrementer updates
the address register before the core reads or writes the
next register from or to next sequential memory location.
 Pipeline
29

• Mechanism a RISC processor to execute instructions

• It Speeds up execution by fetching the next instruction while
other instructions are being decoded and executed.
• Allows the core to execute an instruction every cycle
30

■ Fetch : Loads an instruction from memory

■ Decode: Identifies the instruction to be executed
■ Execute : Processes the instruction and writes the result
back to a register.

• As the pipeline length increases, the amount of work

done at each stage is reduced, which allows the processor to
attain a higher operating frequency.

• System latency also increases because it takes more

cycles to fill the pipeline before the core can execute an
instruction.
 Programmer’s Model
31

It contains the following :

 Registers
 Processor operating states
 Operating modes
 Data types
 The program status registers
 Exceptions
 Reset
 The ARM Register Set

Current Visible Registers

r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr

39v10 The ARM Architecture TM

32 32
 Programmer’s Model
33
 Banked Registers & States…
34
 Registers
35

They are of two types-

General purpose

Special Purpose

The ARM7TDMI processor has a total of 37

registers:
• 31 general-purpose 32-bit registers
• 6 status registers.
These registers are not all accessible at the same time
 Registers…
36

General Purpose Registers

1. Hold either data or an address. All registers are 32 bits in size.
2. Up to 18 active registers: 16 data registers and 2 processor
status registers.
3. Three special function registers : r13, r14, and r15.
■ Register r13 = Stack Pointer (sp) : stores the head of the
stack in the current processor mode.
■ Register r14 = Link register (lr) : whenever the core calls a
subroutine, it puts the return address in this register.
■ Register r15=Program Counter (pc): contains the address of
the next instruction to be fetched by the processor.
Registers r13 and r14 can also be used as general-purpose
registers
 Banked and Unbanked Registers
37

 r0 to r7 are unbanked registers- Means in all processing modes

they are representing same 32 bit physical register.
They are completely general-purpose registers.
No special use.
20 registers are hidden from a program at different times. These
registers are called banked registers.
They are available only when the processor is in a particular
mode. For example, abort mode has banked registers r13_abt, and
r14_abt and spsr_abt.
 Banked Registers…
38

User registers r13 and r14 to be banked

The user registers are replaced with registers r13_irq
and r14_irq
Respectively r14_irq contains the return address and
r13_irq contains the stack pointer for interrupt reques
mode.
The saved program status register (spsr), stores the
previous mode’s cpsr.
 Program Counter
39
 Program Status Register
40
 Current Program Status Register (Bits 27-31)
41

 Condition Flags

Condition flags are updated by comparisons and the result

of ALU operations that specify the S instruction suffix.
 Current Program Status Register… (Bits 6-7)
42

Interrupt Masks

Interrupt masks are used to stop specific interrupt requests

from interrupting the processor

The I and F bits are the interrupt disable bits:

• when the I bit is set, IRQ interrupts are disabled

• when the F bit is set, FIQ interrupts are disabled
 Current Program Status Register (Bits 0-4)
43
 Current Program Status Register…(Bit 5)
44

T bit
The T bit reflects the operating state:
• when the T bit is set, the processor is executing in Thumb state
• when the T bit is clear, the processor executing in ARM state.

Processor operating states:

The ARM7TDMI processor has two operating states:
ARM 32-bit, word-aligned ARM instructions are
executed in this state.
Thumb 16-bit, halfword-aligned Thumb instructions
are executed in this state.
 Thumb Instruction
45
 Exceptions
46

 Exceptions arise whenever the normal flow of a program

has to be halted temporarily, for example, to service an
interrupt from a peripheral.

 Before attempting to handle an exception, the

ARM7TDMI processor preserves the current processor
state so that the original program can resume when the
handler routine has finished
 ARM Interrupts/ Exceptions
47
 Exception Priority
48
 Exception Handling
49
 Processor Modes
50

Processor modes
1. Privileged
2. non-privileged

•Privileged mode : Allows full read-write access to the cpsr

•Six (abort, fast interrupt request, interrupt request, supervisor,
system, undefined)
•Non-privileged mode: allows only read operation access to the
control field in the cpsr but still allows read-write access to the
condition flags. One Non-privileged mode (user)
 Operating modes
51

The ARM7TDMI processor has seven modes of operation:

• User mode is the usual ARM program execution state, and is
used for executing most application programs.
• Fast Interrupt (FIQ) mode supports a data transfer or channel
process.
• Interrupt (IRQ) mode is used for general-purpose interrupt
handling.
• Supervisor mode is a protected mode for the operating
system.
 Operating modes
52

• Abort mode is entered after a data or instruction Prefetch

Abort.
• System mode is a privileged user mode for the operating
system.
• Undefined mode is entered when an undefined
instruction is executed.

Note
You can only enter System mode from another privileged
mode by modifying the mode bit of the Current Program
Status Register (CPSR).
 Exceptions…
Abort
53

An abort indicates that the current memory access cannot be

completed. It is signaled by the external ABORT input.

The ARM7TDMI-S checks for the abort exception at the end of

memory access cycles.

There are two types of abort:

• A Prefetch Abort occurs during an instruction prefetch.
• A Data Abort occurs during a data access.
 Exceptions…
Undefined instruction
54

When the ARM7TDMI-S processor encounters an instruction

neither belongs to it not to coprocessor, the ARM7TDMI-S core
takes the undefined instruction trap.

Software can use this mechanism to extend the ARM instruction

set by emulating undefined coprocessor instructions.

MOVS PC,R14_und
This action restores the CPSR and returns to the next instruction after the
undefined instruction.
 Priorities of Exceptions
55

1. Reset (highest priority).

2. Data Abort.
3. FIQ.
4. IRQ.
5. Prefetch Abort.
6. Undefined instruction.
7. SWI (lowest priority)-Software Interrupt- is used to enter Supervisor
mode, usually to request a particular supervisor function.
 TIVA Microcontrollers
56

• Texas Instrument's Tiva™ C Series microcontrollers offers a 80

MHz Cortex-M with FPU, a variety of integrated memories
and multiple programmable GPIO.
• All members of the Tiva™ C Series, including the TM4C123G
microcontroller, are designed around an ARM Cortex-M
processor core.
• The ARM Cortex-M processor provides the core for a high-
performance, low-cost platform that meets the needs of
minimal memory implementation, reduced pin count, and low
power consumption, while delivering outstanding
computational performance and exceptional response to
interrupts.
 TIVA Microcontrollers
57

• Tiva™ C Series microcontrollers are the leading choice in

high-performance 32-bit applications.
• The product family is positioned for cost-conscious
applications requiring significant control processing and
connectivity capabilities such as:
• Low power, hand-held smart devices
• Gaming equipment
• Home and commercial site monitoring and control
• Motion control
• Medical instrumentation
• Test and measurement equipment
• Smart Energy/Smart Grid solutions
 TIVA Microcontrollers
58

• Factory automation
• Fire and security
• Intelligent lighting control
Features:
• Core- ARM Cortex-M4 processor core
• Performance- 80-MHz operation; 100 DMIPS
• Flash- 256 KB single-cycle Flash memory
• System SRAM 32 KB single-cycle SRAM
• EEPROM 2KB
• Communication Interfaces-
Universal Asynchronous Receivers/Transmitter- Eight UARTs
Synchronous Serial Interface (SSI) Four SSI modules
 TIVA Microcontrollers
59

• Inter-Integrated Circuit (I2C)- Four I2C modules with four

transmission speeds including high-speed MODE
• Controller Area Network (CAN)- Two CAN 2.0 A/B
controllers
• Universal Serial Bus (USB) USB 2.0 OTG/Host/Device
• General-Purpose Timer (GPTM) Six 16/32-bit GPTM blocks
• Watchdog Timer (WDT) Two watchdog timers
• General-Purpose Input / Output (GPIO) Six physical GPIO
blocks
Pulse Width Modulator (PWM)- Two PWM modules, each with
four PWM generator blocks and a control block, for a total of 16
PWM outputs.
 TIVA Microcontrollers
60

• Analog-to-Digital Converter (ADC)- Two 12-bit ADC

modules, each with a maximum sample rate of one million
samples/second
• Analog Comparator Controller Two independent integrated
analog comparators
• JTAG and Serial Wire Debug (SWD) One JTAG module with
integrated ARM SWD
TIVA Microcontrollers
Special Purpose Registers
 PRIMASK: The PRIMASK register is used to disable all
exceptions except NMI and hard fault. It effectively changes
the current priority level to 0 (highest programmable level).

 FAULTMASK: FAULTMASK is just like PRIMASK except that it

changes the effective current priority level to -1, so that even
the hard fault handler is blocked. Only the NMI can be
executed .
 BASEPRI: In some cases, you might want to disable interrupts
only with priority lower than a certain level.
 Tivaware Library
63

• The TivaWare software provided with the Tiva C Series

LaunchPad provides access to all of the peripheral devices
supplied in the design.
• The Tiva C Series Peripheral Driver Library is used to operate
the on-chip peripherals as part of TivaWare.
• TivaWare includes a set of example applications that use the
TivaWare Peripheral Driver Library.
• These applications demonstrate the capabilities of the
TM4C123GH6PM microcontroller, as well as provide a
starting point for the development of the final application for
use on the Tiva C Series LaunchPad evaluation board.
 Tivaware Library
64

• TivaWare™ software for C Series is an extensive suite of

software tools designed to simplify and speed development of
Tiva C Series-based MCU applications.
• All TivaWare for C Series software has a free license, and
allows royalty-free so users can create and build full-function,
easy-to-maintain code.
• TivaWare for C Series software is written entirely in C to make
development and deployment efficient and easy.
 High-level API interface to complete peripheral set

 License & royalty free use for TI Cortex-M parts

 Available as object library and as source code

 Programmed into the on-chip ROM

 Tivaware Library
65

• The Texas Instruments® TivaWare™ Peripheral Driver Library

is a set of drivers for accessing the peripherals found on the
Tiva™ family of ARM® Cortex™-M based microcontrollers.
• While they are not drivers in the pure operating system sense,
they do provide a mechanism that makes it easy to use the
device’s peripherals.
• The drivers are governed by the following design goals:
• They are written entirely in C except where absolutely not
possible. They demonstrate how to use the peripheral in its
common mode of operation.
• Where possible, computations can be performed at compile
time instead of at run time. They can be built with more than
one tool chain.
 Tivaware Library
66

• TivaWare™ is written using the ISO/IEC 9899:1999 (or C99)

C programming standards.
• The C99 C programming conventions make better use of
available hardware, including the IEE754 floating point
unit.
Graphics Library
Graphics primitive and widgets
153 fonts plus Asian and Cyrillic
Graphics utility tools
67