Intel 8086 Microprocessor

By Habtamu W.
Definition
The intel 8086: is a 16 –bit microprocessor, implemented in
N-channel, depletion load, silicon gate technology (HMOS).
- It consists of powerful instruction set, which provides
operations like multiplication and division easily.
- It supports two modes of operation, i.e. Maximum mode
and Minimum mode. Maximum mode is suitable for
system having multiple processors and Minimum mode is
suitable for system having a single processor.
Definition

A ceramic D8086 variant

A plastic P8086 variant

The 8086 pin assignments in min
and max mode
Features
- The 8086 is a 16-bit microprocessor.
- The term 16-bit means that the arithmetic and logic
unit, internal registers and most of the instructions are
designed to work with 16-bit binary word.
- The 8086 has 16-bit data bus.
- So it can read data from or write data to memory and
ports either 16 bit or 8 bit at a time.
- The 8086 has 20-bit address bus.
- So it can directly access 220 or 10,48,576(1MB)
memory locations.
Features
- The 8086 has 16-bit external data bus resulting in faster
processing.
- The 8086 can generate 16-bit I/O address, hence it can
access 216 = 65536 I/O ports
- The 8086 provides fourteen 16-bit registers.
- The 8086 has multiplexed address and data bus which
reduces the number of pins needed, but does slow down
the transfer of data.
Features
- The 8086 requires one phase clock with 33% duty cycle to
provide optimized internal timing.

- It can fetches up to six instruction bytes from memory and

queues stores them in order to speed up instruction
execution.
Internal Architecture
 The Execution Unit (EU)
- Execution unit gives instructions to BIU stating from
where to fetch the data and then decode and execute
those instructions.
- Its function is to control operations on data using the
instruction decoder & ALU.
- EU has no direct connection with system buses.
- It performs operations over data through BIU.
- the EU contains control circuitry, which directs internal
operations.
 The Execution Unit (EU)
- A decoder in the EU translates instructions fetched from
memory into a series of actions which the EU carries
out.
- The EU has a 16 - bit arithmetic logic unit which can add,
subtract, AND, OR, XOR, increment, decrement,
complement, or shift binary numbers.
The Execution Unit (EU)
 Flag Register
- It is a 16-bit register that behaves like a flip-flop, i.e. it
changes its status according to the result stored in the
accumulator.
- It indicates some conditions produced by the
execution of an instruction or controls certain
operations of the EU.
- It has 9 flags and they are divided into 2 groups −
Conditional Flags and Control Flags.
Flag Register

8086 flag register

Conditional flags Register
It represents the result of the last arithmetic or logical
instruction executed.
1. Carry Flag (CF): this flag is set when there is a carry out of MSB
in case of addition or a borrow in case of subtraction.
2. Zero Flag (ZF): this flag is set when the result of an arithmetic
operation is zero.
3. Sign Flag (SF): This flag is set when the result an arithmetic
operation is negative.
For signed computations, the sign flag = the MSB of the result.
4. Parity Flag (PF): This flag is set when the lower byte of the result
contains even number of 1s.
5. Overflow Flag (OF): This flag is set, if an overflow occurs, i.e. if
the result of a signed operation is large enough to be
accommodated in a destination register.
 Conditional flags Register
for addition this flag is set when there is a carry into the MSB and
no carry out of the MSB or vice versa.
For subtraction this flag is set when the MSB needs a borrow and
there is no borrow from the MSB, vice versa
6. Auxiliary flag(AF): - When an operation is performed at ALU, it
results in a carry/barrow from lower nibble (i.e. D0 – D3) to
upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by
D3 bit to D4 is AF flag. The processor uses this flag to perform
binary to BCD conversion.
E.g. Give the content of the flag register after execution of following
instruction.
a. b.
0110 0101 1101 0001 0110 0111 0010 1001
+ 0010 0011 0101 1001 - 0011 0101 0100 1010
 Conditional flags Register
E.g. Give the content of the flag register after execution of following
instruction.
a.
0110 0101 1101 0001
+ 0010 0011 0101 1001
1000 1001 0010 1010
therefore, SF = 1, ZF = 0, PF = 1, CF = 0, AF = 0 and OF = 1

b. 0110 0111 0010 1001

- 0011 0101 0100 1010
0011 0001 1101 1111
therefore, SF = 0, ZF = 0, PF = 1, CF = 0, AF = 1 and OF = 0
 Control Flags Register
It represents the result of the last arithmetic or logical
instruction executed.
1. Interrupt flag(IF): If this flag is set, the maskable interrupts are
acknowledged by the CPU, otherwise they are ignored.
2. Trap flag(TF): if this flag is set, the processor enters the single
step execution mode.
- in other words, it is generated after execution of each
instruction.
- The processor executes the current instruction and the control
is transferred to the trap interrupt service routine.
3. Direction Flag (DF): This is used by string manipulation
instructions.
- If this flag bit is '0’ the string is processed beginning from the
lowest to the highest address (auto-incrementing mode).
Control Flags Register
Otherwise, the string is processed from the highest to the lowest
address (auto-decrementing mode).
- It is used in string operation. As the name suggests when it is set
then string bytes are accessed from the higher memory address to
the lower memory address and vice-a-versa.
 General Purpose Registers
The 8086 has four 16-bit general purpose registers labeled AX,
BX, CX, and DX.
- Each 16-bit general purpose register can be split into two 8-
bit registers.
- They are used either for holding data, variables and
intermediate results temporarily.
- They can also be used as counters or used for storing offset
address for some particular addressing modes.
- The valid register pairs are AH and AL, BH and BL, CH and CL,
and DH and DL. It is referred to the AX, BX, CX, and DX
respectively.
General Purpose Registers
 Pointer and index registers
- All segment registers are 16-bit wide. But it is necessary to
generate 20-bit address on the address bus.
- To get 20-bit physical address one or more pointer or index
registers are associated with each segment register.
- The pointer registers IP, BP and SP are associated with code,
data and stack segments respectively. They hold the offset
within the code, data and stack segments.
- The index registers DI and SI are used as a general purpose
registers as well as for offset storage in case of indexed, base
indexed and relative based indexed addressing modes.
Pointer and index registers
 Bus interface Unit
- The bus interface unit is the 8086 microprocessor interface
to the outside world.
- It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
- It is responsible for performing all external bus operation as
the following.
- It sends address of the memory or I/O
- It fetches instruction from memory
- It reads data from port/memory
- It writes data in to port/memory
 Bus interface Unit
- EU has no direct connection with System Buses so this is
possible with the BIU.
- EU and BIU are connected with the Internal Bus.
- It has the following functional parts :−
Instruction queue
- While the EU is decoding or executing an instruction,
which does not require use of the buses, the BIU
fetches up to 6 instruction bytes for the next
instructions.
- The BIU stores these pre-‐fetched bytes in a FIFO
register set called a queue.
- When the EU is ready for its next instruction, it simply
reads the instruction byte(s) for the instruction from
the queue in the BIU.
Segment registers
- The physical address of the 8086 is 20-bit wide to access 1 MB
memory locations.
- However, it’s registers and memory locations which contain
logical addresses are just 16-bits wide.
- Hence 8086 uses memory segmentation, It treats the 1 MB of
memory as divided in to segments, with a maximum size of a
segment as 64 KB.
- Thus any location with in the segment can be accessed using
16 bit. The 8086 allows only four active segments at a time.
The register can hold up the upper
16-bits of the starting addresses of
the four memory segments.
The starting address means the
lowest addressed byte in the
active code segment. Also known
as base address or segment base.
E.g The value in CS identifies the
starting address of 64KB segment
known as code segment.
 Memory segmentation
- There are two types of memory organization are commonly
used. These are linear addressing and segmented
addressing.
- In linear addressing the entire memory space is available to
the processor in one linear array.
- And in segmented addressing the available memory space is
divided into “chunks” called segments. Such a memory is
known as segmented memory.
- The 1MB address memory is divided in to number of logical
segments.
- Each segment is 64KB in size and addressed by one of the
segment registers. The 16-bit contents of the segment
register gives the starting/base address of a particular
segment
Memory segmentation
 Memory segmentation
Rules for Memory segmentation
1. The four segments can overlap for small programs. In a
minimum system all four segments can start at the
address 00000H
2. The segment can begin at any memory address which is
divisible by 16.
Advantages of Memory segmentation
1. It allows the memory addressing capacity to be 1MB
even though the address associated with individual
instruction is only 16-bit.
2. It allows instruction code, data, stack, and portion of
program to be more than 64 KB long by using more than
one code, data, stack and extra segment.
Memory segmentation
3. It facilitates use of separate memory areas for program, data
and stack.
4. It permits a program or its data to be put in different areas of
memory, each time the program is executed. i.t program can
be relocated which is very useful in multiprogramming.
e.g. if the segment address is 1005H and the offset is 5555H,
then the physical address is calculated as below.

Segment address -‐-‐-‐-‐-‐-‐-‐-‐-‐ 1005H

Offset address ‐-‐-‐-‐-‐-‐-‐-‐-‐-‐ 5555H
Segment address-‐-‐-‐-‐-‐-‐-‐-‐-‐1005H -‐-‐-‐-‐-‐-‐-‐-‐-‐0001
0000 0000 0101
Shifted by 4 bit Positions ‐-‐-‐-‐-‐-‐-‐-‐-‐-‐ 0001 0000 0000 0101 0000
Offset address ‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐ + 0101 0101 0101 0101
Physical address -‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐ 0001 0101 0101 1010 0101
1 5 5 A 5 H
 Bus interface Unit …
Instruction Pointer
- The IP contains the distance or offset from the base address in
Code Segment (CS) to the next instruction byte to be fetched.
- The 16-‐bit offset in IP is added to the 16-‐bit segment base
address in CS to produce the 20-‐bit physical address.
- Location of the next instruction in memory is, therefore
address of next ins. = (CS << 4) + IP;
 Bus interface Unit …
Instruction Pointer
Example: Let CS holds 348AH,
and IP holds 4214H

Now the actual address in the

physical memory space is
given by CS:IP and calculated
as:
CS is first shifted left four
times 16*CS = 348A0H
Then the offset in IP is added
348A0H
+ 4214H
Actual address 38AB4H
Other registers in the EU
Stack Pointer
- A stack is a section of memory set aside to store addresses and
data while a subprogram is executing.
- The 8086 allow to set aside an entire 64KB segment as a stack.
- The upper 16 bits of the starting address for this segment are
kept in the stack segment register (SS).
- The stack pointer (SP) register holds the 16-‐bit offset from the
start of the segment to the memory location where a word was
most recently stored on the stack (Top of stack).
Other registers in the EU…

Example: Let SS hold 5000H,

and SP hold FFE0H

Now the actual address in the

physical memory space is
given by SS:SP and calculated
as:
SS is first shifted left four
times 16*SS = 50000H
Then the offset in SP is added
50000H
+ FFE0H
Top of stack 5FFE0H
Summary of 8086 registers

AX [Accumulator] AH:AL
BX [Base Register] BH:BL General Purpose
CX [Count Register] CH:CL Registers
DX [Data Register] DH:DL
CS [Code Segment]
DS [Data Segment] Segment Registers
Base address of segments
SS [Stack Segment]
ES [Extra Segment]
IP [Instruction pointer]
Pointer Registers
SP [Stack pointer]
Offset within a segment
BP [Base pointer]
SI [Source Index] Flags
DI [Destination Index] x x x x O D I T S Z x A x P x C
 Bus interface Unit …
Physical address generation
- There’re two types of address generation
1. Real Mode (8086 can only operate in this mode)
- Allows the μP to address the first 1MB of memory only
- The first 1MB of memory is called real or physical memory
2. Protected Mode (80286 , 80386, …)
- Uses the segment register contents (called selector) to
access a descriptor from the descriptor table.
- The descriptor describes the memory segment’s location,
length and access right.
Summary … Address generation I

Real mode memory addressing

- Memory addresses consist of segment address plus offset
address in the segment.
- A segment address defines the start of a 64KB block of memory
- The offset address points to the location within the 64KB block
- Memory locations are often wrilen as:

Segment : offset
eg. 03C1H : 38A0H
This notation is referred to as logical address
Summary … Address generation II
\WAXCH .00

Segment Offset

<< 4 - The segment-‐offset

Segment 0000 scheme allows programs to
Adder be relocated in memory on
Physical Address 16-byte boundaries.

- Memory segments may

overlap.
Summary … Address generation III
Rule of thumb
- The micro processor has a set of rules that apply whenever
memory is addressed, which defines the segment-‐offset register
combinations used by certain addressing modes.
Segment offset Special Purpose
CS IP Instruction Address

DS BX, BP, DI or SI Data Address

SS SP or BP Stack Address

ES SI/DI String source/destination

INTEL 8086 - Pin Diagram
 INTEL 8086 - Pin Details
Power Supply
5V  10%
Ground

Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
 INTEL 8086 - Pin Details

Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
D0 when ALE is 0. multiplexed
address/data bus
contains address
information.
 INTEL 8086 - Pin Details

INTERRUPT

Non - maskable
interrupt

Interrupt
acknowledge

Interrupt request
INTEL 8086 - Pin Details
Direct
Memory
Access

Hold

Hold
acknowledge
INTEL 8086 - Pin Details

Address/Status Bus
Address bits A19 – A16
& Status bits S6 – S3
 INTEL 8086 - Pin Details
Min/Max mode
Minimum Mode: +5V
Maximum Mode:0v

Minimum Mode Pins

Maximum Mode
Pins
Minimum Mode- Pin
 Maximum Mode - Pin

S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory Status Signal
110: write memory
111: none -passive Inputs to 8288 to
generate eliminated
signals due to max
mode.
 Maximum Mode - Pin

QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of Queue Status
opcode Used by numeric
coprocessor (8087)
Minimum Mode 8086 System
Minimum Mode 8086 System

51
‘Read’ Cycle timing Diagram for Minimum
Mode
‘Write’ Cycle timing Diagram for
Minimum Mode