PCF7991AT
PCF7991AT
PCF7991AT
DATA SHEET
PCF7991AT
Advanced Basestation IC
Product Specification (Rev. 1998 Apr 20) printed 1998 Apr 20
Philips Semiconductors Product Specification (Rev. 1998 Apr 20)
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 QUICK REFERENCE DATA
6 PINNING INFORMATION
6.1 Pinning Diagram
6.2 Pin Description
7 MINIMUM APPLICATION CIRCUITRY
8 FUNCTIONAL DESCRIPTION
8.1 Power Supply
8.2 Antenna driver
8.3 Modulator
8.4 Oscillator
8.5 Receiver
8.5.1 Synchron Demodulator
8.5.2 Bandpass Filter, Amplifier and Digitizer
8.5.3 Phase Measurement
8.5.4 Determining the Sampling Time
8.5.5 Data Amplitude Comparison
8.5.6 System Diagnostics
8.6 Power-on reset
8.7 Power-down modes
8.8 Serial Interface
8.8.1 Serial Interface Mode
9 COMMAND SET
9.1 READ_TAG
9.2 WRITE_TAG_N
9.3 WRITE_TAG
9.4 READ_PHASE
9.5 SET_SAMPLING_TIME
9.6 GET_SAMPLING_TIME
9.7 SET_CONFIG_PAGE
9.8 GET_CONFIG_PAGE
10 LIMITING VALUES
11 DC CHARACTERISTICS
12 AC CHARACTERISTICS
13 PACKAGE
14 DEFINITIONS
15 LIFE SUPPORT APPLICATIONS
3 ORDERING INFORMATION
PCF7991AT/1081 SO14 plastic small outline package; 14 leads SOT108-1 −40 to +85
4 BLOCK DIAGRAM
VDD
TX1 XTAL1
Antenna Drivers Modulator Oscillator
TX2 XTAL2
Control
Unit
DIN
Synchron Bandpass Filter
RX Amplifier Serial Interface DOUT
Demodulator
Dynamic Control SCLK
Digitizer
Phase
Measurement
Control Register
VALUE
PARAMETER
MIN. MAX. UNIT
Supply voltage 4.5 5.5 V
Power-down current 20 µA
Clock/Oscillator frequency 4 16 MHz
(antenna carrier frequency 125 kHz)
Antenna driver current 400 mAp
Receiver sensitivity 2 mVpp
Serial interface CMOS compatible
Package SO14
Operation temperature range −40 °C to +85 °C
6 PINNING INFORMATION
6.1 Pinning Diagram
Pin 1 ID
VSS 1 14 RX
TX2 2 13 QGND
VDD 3 12 CEXT
TX1 4 11 N.C.
PCF7991AT
MODE 5 10 DOUT
XTAL1 6 9 DIN
XTAL2 7 8 SCLK
VDD
+
10 µF 100nF
La
Ca
XTAL2
TX2
DIN
Rv TO
DOUT
RX MICRO-
SCLK PROCESSOR
100nF 100nF
8 FUNCTIONAL DESCRIPTION order to match the receiver input voltage specification. The
receive signal passes an on-chip second order low pass
8.1 Power Supply filter and is further attenuated before it is fed to the
The PCF7991AT operates from an external 5 V power synchron demodulator and phase measurement circuitry.
supply. For optimum performance a stabilized supply
voltage should be applied. 8.5.1 SYNCHRON DEMODULATOR
The antenna current and therefore the tap voltage is
8.2 Antenna driver modulated by the transponder in amplitude and/or phase
The antenna drivers are configured as a full bridge capable depending on various system parameters. By employing a
to deliver a square wave shaped voltage to the series unique Adaptive Sampling Time (AST) demodulation
resonant antenna circuit, which is connected between TX1 technique, amplitude and phase modulation of the receive
and TX2. The full bridge drivers are characterized by a low signal is detected featuring an extended system operation
output impedance featuring a large drive voltage to the range. The receive sampling time is set by the
resonant antenna circuit. The antenna carrier frequency is SET_SAMPLING_TIME command (see Table 2). The
125 kHz typically. appropriate sampling time can be derived from an on-chip
phase measurement and an offset that accounts for the
8.3 Modulator external antenna interface component values.
The modulator enables ASK (Amplitude Shift Keying) Receive signal sampling is inhibited when a WRITE_TAG
modulation of the antenna RF signal after switching the or WRITE_TAG_N command is issued in order to avoid
device into transparent mode (WRITE_TAG mode) by a that write pulses de-sensitize the amplifier and digitizer
WRITE_TAG or WRITE_TAG_N command (see Table 2). circuitry. Signal sampling is resumed when the
ASK modulation is achieved by blanking the antenna drive WRITE_TAG mode is terminated. For better receiver
signal under control of the data input (DIN). The modulator setting a short delay after the last write pulse has to be
features a timer circuitry that supports carrier blanking with provided before the WRITE_TAG mode is terminated.
a programmable duration (see Table 2).
8.5.2 BANDPASS FILTER, AMPLIFIER AND DIGITIZER
8.4 Oscillator After demodulation the receive signal passes a baseband
The on-chip oscillator operates either with a crystal or filter and amplifier prior to digitization. The amplifier gain
ceramic resonator connected to XTAL1/2. Alternatively, an and bandpass filter cutoff frequencies are adjustable by
external clock source (CMOS compatible) may be applied the SET_CONFIG_PAGE 0 command, in order to adapt
at XTAL1. The oscillator frequency feeds a programmable the receiver path to the system coupling factor and
divider in order to derive the system clock and the antenna transponder data rate.
carrier frequency of 125 kHz. The programmable divider For fast receiver settling after device power-up, sampling
supports an oscillator frequency of 4, 8, 12 and 16 MHz time shift or when switching from WRITE_TAG mode to
(see Table 11). READ_TAG mode the bandpass filter, amplifier and
digitizer circuit biasing condition can be initialized and
8.5 Receiver restored by a set of control bits accessible via the
The receiver senses and demodulates the absorption SET_CONFIG_PAGE commands.
modulation applied by a transponder that is inside the
antenna RF field. The demodulated and digitized signal is 8.5.3 PHASE MEASUREMENT
available at the data output (DOUT) after switching the The optimum receive signal sampling time depends on the
device into transparent mode (READ_TAG mode) by a actual tuning condition of the resonant antenna circuitry.
READ_TAG command (see Table 2). The actual tuning condition of the resonance antenna is
The receiver features a high sensitivity and an extended determined by measuring the phase relationship between
input voltage range to ensure a large receiver dynamic the exciting signal at the antenna driver output and the
range. The antenna tap signal is fed to the receiver input antenna tap voltage applied to the receiver input. In case
(RX) after attenuation by means of an external series of perfect tuning, the phase should be 90 degree plus an
resistor (RV) and the receiver input impedance (RIRX) in offset that accounts for the receiver input attenuation and
low pass filter. Miss-tuning of the resonance antenna time and when the antenna drivers are disabled.
circuit by component spreads or due to ambient Advanced system diagnostics are feasible by considering
temperature changes results in a change of the phase the phase measurement information also.
relationship. The actual phase relationship is determined
by a READ_PHASE command (see Table 6) and used to 8.6 Power-on reset
calculate the optimum receive signal sampling time with
The device generates an internal power-on reset to
support of an external microcontroller.
initialize the chip after power-on or power fail condition. As
a result the control register is initialized according to
8.5.4 DETERMINING THE SAMPLING TIME
Table 11.
Measurement, calculation and setting of the sampling time
is typically implemented during system power-up 8.7 Power-down modes
initialization when the transponder is also in its power-up
After a power-on reset condition the device operates in
sequence not sending any data. As soon as the oscillator
ACTIVE mode. The PCF7991AT supports an Idle and
and resonance antenna circuit are settled a phase
Power-down mode for power saving means. The mode of
measurement is initiated and the sampling time
operation is determined by control bits addressed by an
determined according to the following relation:
SET_CONFIG_PAGE 1 command (see Table 10).
TS = 2 * TANT + TOFFSET
In Idle mode only the oscillator and a minimum of other
TS Receive signal sampling time
circuitry is active. In Power-down mode the device is in
TANT Actual phase measurement OFF state completely. The serial interface is operational in
TOFFSET Offset that accounts for the phase shift due any case in order to provide access to the control register.
to the antenna tap voltage attenuation and
low pass filtering 8.8 Serial Interface
After setting the sampling time the receiver has to settle The communication between the PCF7991AT and the
before data can be demodulated and digitized properly. microcontroller is done via a three wire digital interface.
The interface is used to issue commands for writing and
8.5.5 DATA AMPLITUDE COMPARISON reading of device configuration data and for writing and
reading to the transponder in one of the transparent
For advanced receiver sampling time optimization the modes (READ_TAG, WRITE_TAG). Device configuration
demodulated data signal strength can be weighted by is stored in a control register with read back feature.
amplitude comparison and the result reported in the status
bit AMPCOMP (see Table 13). The interface is operated by the following signals:
When the ACQAMP control bit (see Table 10) is set by a SCLK Clock
SET_CONFIG_PAGE command, the actual demodulated DIN Data Input
data signal amplitude is stored as reference. After DOUT Data Output
resetting the ACQAMP control bit the status bit
AMPCOMP is set, when the actual data signal amplitude SCLK and DIN are realized as Schmitt-Trigger inputs.
is larger than the stored reference otherwise it is cleared. DOUT is an open drain output with internal pullup resistor.
Any communication between the PCF7991AT and the
8.5.6 SYSTEM DIAGNOSTICS microcontroller begins with an initialization of the serial
In order to detect an antenna short or open condition the interface before the desired command can be issued. The
receiver input voltage at the RX-pin is monitored and an interface initialization condition is a low-to-high transition
antenna fail condition is reported in the status bit ANTFAIL, of the signal DIN while SCLK is high (see Fig.4).
(see Table 13). If the receiver input voltage does not All commands are transmitted to the PCF7991AT serial
exceed the diagnostic threshold level VDTH (see interface starting with Most Significant Bit (MSB). DIN is
Chapter 11), the status bit ANTFAIL is set, otherwise it is latched with a high state at SCLK. DOUT is valid during the
cleared. The status bit is updated once per antenna carrier high state of SCLK (MODE pin connected to VSS).
period and can be read by a GET_CONFIG_Page 2 or 3
command (see Table 13). The status bit is undefined in DOUT and DIN may be connected to each other in order to
Power-down or Idle mode, during the oscillator start-up form a two wire communication link with the
microcontroller.
8.8.1 SERIAL INTERFACE MODE internal state of these signals is updated only, if two
successive samples are equal. Due to the sampling
The serial interfaces supports two modes of operation,
operation a state change at the SCLK or DIN input is
filtered and non-filtered communication.
delayed at least by 16 µs before it is recognized by the
If MODE is connected to VSS no filtering is applied and the internal circuitry. If DIN and DOUT are connected to each
state of the interface signals is directly available at the other to form a two wire communication link, the filtering
internal circuitry. The maximum data rate of the serial delay between DIN and DOUT must be considered. Due to
interface is limited by the set-up and hold time as specified the digital filtering, the maximum serial interface data rate
(see Chapter 12). is limited to approximately 30 kbit/sec.
If MODE is connected to VDD, digital filtering of SCLK and If digital filtering of SCLK and DIN is enabled and the device
DIN is performed offering improved immunity against has been forced into Power-down mode, this mode can be
glitches on these interface signals. This mode of operation terminated by setting SCLK to LOW and DIN unequal to the
is intended for use for so called ‘Active Antenna status bit TXDIS (see Table 10). As a result the XTAL
Applications’, where the PCF7991AT and the oscillator is restarted and the configuration bit PD_MODE
microcontroller have to communicate via long interface is cleared, which causes the device to enter Idle mode.
wires. The digital filtering is provided by sampling the
SCLK and DIN inputs at a rate of 1/fTX, 8 µs typically. The
TS TH
SCLK
DIN D7 D6 D5 D4 D3 D2 D1 D0
initialization
DOUT
D7 D6 D5 D4 D3 D2 D1 D0
9 COMMAND SET
Table 2 Command set summary
MSB BIT NO. LSB
COMMAND NAME RESPONSE
7 6 5 4 3 2 1 0
GET_SAMPLING_TIME 0 0 0 0 0 0 1 0 8 bit (0 0 D5-D0)
GET_CONFIG_PAGE 0 0 0 0 0 1 P1 P0 8 bit (X3 X2 X1 X0 D3-D0)
READ_PHASE 0 0 0 0 1 0 0 0 8 bit (0 0 D5 - D0)
READ_TAG 1 1 1 − − − − − enter READ_TAG-mode
WRITE_TAG_N 0 0 0 1 N3 N2 N1 N0 enter WRITE_TAG-mode with pulse
width programming
WRITE_TAG 1 1 0 − − − − − enter WRITE_TAG-mode
SET_CONFIG_PAGE 0 1 P1 P0 D3 D2 D1 D0 4 bit per config page addressed
SET_SAMPLING_TIME 1 0 D5 D4 D3 D2 D1 D0 8 bit (00 D5 - D0)
9.1 READ_TAG
This command is used to read the demodulated bit stream from a transponder: After the assertion of the three command
bits the PCF7991AT instantaneously switches to READ_TAG-mode and the demodulated, filtered and digitized data
from the transponder is available at the data output DOUT for decoding by the microcontroller.
READ_TAG-mode is terminated immediately by a low to high transition at SCLK.
9.2 WRITE_TAG_N
This command is used to write data to a transponder and to set the modulator blanking characteristics.
If N3-N0 are set to zero, the signal from DIN is transparently switched to the drivers. A high level at DIN corresponds to
antenna drivers switched off, a low level corresponds to antenna drivers switched on.
If any binary number between 1 and 1111 is loaded into N3-N0, the drivers are switched off at the next positive transition
of DIN. The driver off state is maintained for a time interval equal to N * T0 (T0=8 µs) regardless the state of DIN. This
method relaxes the timing resolution requirements to the microcontroller and to the software implementation while
providing an exact, selectable write pulse timing.
WRITE_TAG-mode is terminated immediately by a low to high transition at SCLK. As a result, the driver resume their
initial state, regardless the actual state of the modulation pulse timer.
9.3 WRITE_TAG
This is the 3 bit short form of the command WRITE_TAG_N. It allows to switch into WRITE_TAG-mode with a minimum
communication time.
The behaviour of the WRITE_TAG command is identical to WRITE_TAG_N with two exceptions:
WRITE_TAG-mode is entered after assertion of the 3rd command bit.
No N parameter is specified with this command; instead the N value which has been programmed with the most recent
WRITE_TAG_N command is used. If no WRITE_TAG_N was issued so far, a default N=0 (transparent mode) will be
assumed.
WRITE_TAG-mode is terminated immediately by a low to high transition at SCLK. As a result, the driver resume their
initial state, regardless the actual state of the modulation pulse timer.
9.4 READ_PHASE
This command is used to read the antenna´s phase TANT, which is measured at every carrier cycle. The phase is coded
binary in D5-D0.
9.5 SET_SAMPLING_TIME
This command specifies the demodulator sampling time Ts. The sampling time is coded binary in D5-D0.
9.6 GET_SAMPLING_TIME
This command is used to read back the sampling time Ts set with SET_SAMPLING_TIME. The sampling time is coded
binary in D5-D0.
9.7 SET_CONFIG_PAGE
This command is used to configure the receiver characteristics (cutoff frequencies, gain factors) and the different
operation modes. P1 and P0 select one of four configuration pages.
Note
1. In order to achieve fast receiver settling the amplifier and filter characteristics can temporarily be overridden:
2. In order to derive an antenna carrier frequency fTX of 125 kHz; the clock divider has to be programmed as follows:
3. If the THRESET is set, the threshold generator is disabled and initialized according to the receive signal conditions.
9.8 GET_CONFIG_PAGE
This command has three functions:
1. Reading back the configuration parameters set by SET_CONFIG_PAGE command
2. Reading back the transmit pulse width programmed with WRITE_TAG_N
3. Reading the system status information
P1 and P0 select one of four configuration pages. The response (X3 X2 X1 X0 D3 D2 D1 D0) contains the contents of
the selected configuration page in its lower nibble. For P = 0 or P = 1 the higher nibble reflects the current setting of N
(the transmit pulse width). For P = 2 or P = 3 the system status information is returned in the higher nibble.
BIT NUMBER
COMMAND / PAGE NO.
7 6 5 4 3 2 2 0
GET_CONFIG_PAGE 0 N3 N2 N1 N0 D3 D2 D1 D0
GET_CONFIG_PAGE 1 N3 N2 N1 N0 D3 D2 D1 D0
GET_CONFIG_PAGE 2 0 0 AMPCOMP ANTFAIL D3 D2 D1 D0
GET_CONFIG_PAGE 3 0 0 AMPCOMP ANTFAIL D3 D2 D1 D0
10 LIMITING VALUES
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings
only and operation of the device at these or at any other conditions above those given in the characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
11 DC CHARACTERISTICS
All voltages are measured to VSS, Tamb = −40 to +85°C, fTX = 125 kHz; unless otherwise specified.
VDTH diagnostic threshold level VDTH with respect to QGND −1.5 −1.15 −0.8 V
Digital input (DIN, SCLK)
VIH data input voltage HIGH 0.7 VDD VDD +0.3 V
VIL data input voltage LOW −0.3 V 0.3 VDD
Digital output (DOUT)
VOL output voltage LOW IOL max = +1 mA 0.4 V
IOL output drive capability VOL ≤ 0.4 V 1 mA
Note
1. Does not include power consumption of XTAL or other external components.
12 AC CHARACTERISTICS
Tamb = −40 to +85°C, fTX = 125 kHz; unless otherwise specified.
Note
1. Specific command sequence required.
2. Applicable for WRITE_TAG and WRITE_TAG_N commands. Due to device internal signal synchronization
measures, TDITX is the response delay between a change at DIN and the resulting change at the antenna drivers.
In the case of N is zero, TDITX applies for both the rising and failing transition at DIN, while for N unequal zero it applies
for the rising transition at DIN only.
13 PACKAGE
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
D E A
X
y HE v M A
14 8
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 7 L
e w M detail X
bp
0 2.5 5 mm
scale
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0o
inches 0.069 0.01 0.050 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
95-01-23
SOT108-1 076E06S MS-012AB
97-05-22
14 DEFINITIONS
Peak-to-peak of arbitrary shaped signals: Vpp, Ipp
Zero-to peak of arbitrary shaped signals: V p, Ip
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