Preliminary

FM24CL16B
16Kb Serial 3V F-RAM Memory
Features
Low Power Operation
16K bit Ferroelectric Nonvolatile RAM • 2.7 - 3.65V Operation
• Organized as 2,048 x 8 bits • 100 µA Active Current (100 kHz)
• High Endurance 1014 Read/Writes • 3 µA (typ.) Standby Current
• 38 year Data Retention
• NoDelay™ Writes Industry Standard Configuration
• Advanced High-Reliability Ferroelectric Process • Industrial Temperature -40° C to +85° C
• 8-pin “Green”/RoHS SOIC and TDFN Packages
Fast Two-wire Serial Interface
• Up to 1MHz Maximum Bus Frequency
• Direct Hardware Replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz

Description Pin Configuration

The FM24CL16B is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
NC 1 8 VDD
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a NC 2 7 WP
RAM. It provides reliable data retention for 38 years
NC 3 6 SCL
while eliminating the complexities, overhead, and
system level reliability problems caused by EEPROM VSS 4 5 SDA
and other nonvolatile memories.

The FM24CL16B performs write operations at bus

Top View
speed. No write delays are incurred. Data is written to
the memory array in the cycle after it has been NC 1 8 VDD
successfully transferred to the device. The next bus NC 2 7 WP
cycle may commence immediately without the need
NC 3 6 SCL
for data polling. The FM24CL16B is capable of
VSS 4 5 SDA
supporting 1014 read/write cycles, or a million times
more write cycles than EEPROM.
Pin Names Function
These capabilities make the FM24CL16B ideal for
SDA Serial Data/Address
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection SCL Serial Clock
where the number of write cycles may be critical, to WP Write Protect
demanding industrial controls where a long write time VDD Supply Voltage
can cause data loss. The combination of features VSS Ground
allows the system to write data more frequently, with
less system overhead. Ordering Information
FM24CL16B-G “Green”/RoHS 8-pin SOIC
The FM24CL16B provides substantial benefits to FM24CL16B-GTR “Green”/RoHS 8-pin SOIC,
users of serial EEPROM, yet these benefits are Tape & Reel
available in a hardware drop-in replacement. The FM24CL16B-DG “Green”/RoHS 8-pin TDFN
FM24CL16B is available in an industry standard 8- FM24CL16B-DGTR “Green”/RoHS 8-pin TDFN,
pin SOIC package and uses a familiar two-wire Tape & Reel
protocol. The specifications are guaranteed over the
industrial temperature range from -40°C to +85°C.

This is a product that has fixed target specifications but are subject Ramtron International Corporation
to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Rev. 1.4 www.ramtron.com
Feb. 2011 Page 1 of 13
 FM24CL16B - 16Kb 3V I2C F-RAM

Address 256 x 64
Counter
Latch FRAM Array

SDA Serial to Parallel

Data Latch
Converter

SCL
WP Control Logic

Figure 1. Block Diagram

Pin Description
Pin Name Type Pin Description
SDA I/O Serial Data Address: This is a bi-directional data pin for the two-wire interface. It
employs an open-drain output and is intended to be wire-OR’d with other devices on the
two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the
output driver includes slope control for falling edges. A pull-up resistor is required.
SCL Input Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on
the falling edge and clocked-in on the rising edge.
WP Input Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.
VDD Supply Supply Voltage
VSS Supply Ground
NC - No connect

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 FM24CL16B - 16Kb 3V I2C F-RAM

Overview Two-wire Interface

The FM24CL16B is a serial FRAM memory. The The FM24CL16B employs a bi-directional two-wire
memory array is logically organized as a 2,048 x 8 bus protocol using few pins and little board space.
memory array and is accessed using an industry Figure 2 illustrates a typical system configuration
standard two-wire interface. Functional operation of using the FM24CL16B in a microcontroller-based
the FRAM is similar to serial EEPROMs. The major system. The industry standard two-wire bus is
difference between the FM24CL16B and a serial familiar to many users but is described in this section.
EEPROM with the same pinout relates to its superior
write performance. By convention, any device that is sending data onto
the bus is the transmitter while the target device for
Memory Architecture this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
When accessing the FM24CL16B, the user addresses
generating the clock signal for all operations. Any
2,048 locations each with 8 data bits. These data bits
device on the bus that is being controlled is a slave.
are shifted serially. The 2,048 addresses are accessed
The FM24CL16B is always a slave device.
using the two-wire protocol, which includes a slave
address (to distinguish from other non-memory
The bus protocol is controlled by transition states in
devices), a row address, and a segment address. The
the SDA and SCL signals. There are four conditions
row address consists of 8-bits that specify one of 256
including Start, Stop, Data bit, and Acknowledge.
rows. The 3-bit segment address specifies one of 8
Figure 3 illustrates the signal conditions that define
segments within each row. The complete 11-bit
the four states. Detailed timing diagrams are in the
address specifies each byte uniquely.
electrical specifications.
Most functions of the FM24CL16B either are
controlled by the two-wire interface or handled VDD

automatically by on-board circuitry. The memory is

read or written at the speed of the two-wire bus. Rmin = 1.1 Kohm
Rmax = tR/Cbus
Unlike an EEPROM, it is not necessary to poll the Microcontroller

device for a ready condition since writes occur at bus

speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation is complete.
This is explained in more detail in the interface SDA SCL SDA SCL

section below. FM24CL16B Other Slave

Device

Note that the FM24CL16B contains no power

management circuits other than a simple internal
Figure 2. Typical System Configuration
power-on reset. It is the user’s responsibility to ensure
that VDD is within data sheet tolerances to prevent
incorrect operation.

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 FM24CL16B - 16Kb 3V I2C F-RAM

SCL

SDA 7 6 0

Stop Start Data bits Data bit Acknowledge

(Master) (Master) (Transmitter) (Transmitter) (Receiver)

Figure 3. Data Transfer Protocol

The receiver would fail to acknowledge for two

Stop Condition
distinct reasons. First is that a byte transfer fails. In
A stop condition is indicated when the bus master this case, the No-Acknowledge ends the current
drives SDA from low to high while the SCL signal is operation so that the part can be addressed again.
high. All operations using the FM24CL16B must end This allows the last byte to be recovered in the event
with a Stop condition. If an operation is pending of a communication error.
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory Second and most common, the receiver does not
read) in order to assert a Stop condition. acknowledge to deliberately end an operation. For
Start Condition example, during a read operation, the FM24CL16B
will continue to place data onto the bus as long as
A Start condition is indicated when the bus master
the receiver sends Acknowledges (and clocks).
drives SDA from high to low while the SCL signal is
When a read operation is complete and no more data
high. All read and write transactions begin with a
is needed, the receiver must not acknowledge the
Start condition. An operation in progress can be
last byte. If the receiver acknowledges the last byte,
aborted by asserting a Start condition at any time.
this will cause the FM24CL16B to attempt to drive
Aborting an operation using the Start condition will
the bus on the next clock while the master is sending
prepare the FM24CL16B for a new operation.
a new command such as a Stop.
If during operation the power supply drops below the Slave Address
specified VDD minimum, the system should issue a The first byte that the FM24CL16B expects after a
Start condition prior to performing another operation. Start condition is the slave address. As shown in
Data/Address Transfer Figure 4, the slave address contains the device type,
the page of memory to be accessed, and a bit that
All data transfers (including addresses) take place
specifies if the transaction is a read or a write.
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
Bits 7-4 are the device type and should be set to
not change while SCL is high. For system design
1010b for the FM24CL16B. The device type allows
considerations, keeping SCL in a low state while idle
other types of functions to reside on the 2-wire bus
improves robustness.
within an identical address range. Bits 3-1 are used
Acknowledge for page select. They specify the 256-byte block of
The Acknowledge takes place after the 8th data bit has memory that is targeted for the current operation. Bit
been transferred in any transaction. During this state, 0 is the read/write bit. R/W=1 indicates a read
the transmitter should release the SDA bus to allow operation and R/W=0 indicates a write operation.
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
No-Acknowledge and the operation is aborted.

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 FM24CL16B - 16Kb 3V I2C F-RAM

Page
Slave ID Select
Memory Operation
The FM24CL16B is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
1 0 1 0 A2 A1 A0 R/W higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24CL16B and a similar
Figure 4. Slave Address
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Word Address
After the FM24CL16B (as receiver) acknowledges Write Operation
the slave ID, the master will place the word address All writes begin with a slave ID then a word address
on the bus for a write operation. The word address is as previously mentioned. The bus master indicates a
the lower 8-bits of the address to be combined with write operation by setting the LSB of the Slave
the 3-bits of the page select to specify the exact byte Address to a 0. After addressing, the bus master
to be written. The complete 11-bit address is latched sends each byte of data to the memory and the
internally. memory generates an acknowledge condition. Any
number of sequential bytes may be written. If the
No word address occurs for a read operation, though end of the address range is reached internally, the
the 3-bit page select is latched internally. Reads address counter will wrap from 7FFh to 000h.
always use the lower 8-bits that are held internally in
the address latch. That is, reads always begin at the Unlike other nonvolatile memory technologies, there
address following the previous access. A random read is no write delay with FRAM. The entire memory
address can be loaded by doing a write operation as cycle occurs in less time than a single bus clock.
explained below. Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
After transmission of each data byte, just prior to the polling, a technique used with EEPROMs to
acknowledge, the FM24CL16B increments the determine if a write is complete is unnecessary and
internal address latch. This allows the next sequential will always return a ‘ready’ condition.
byte to be accessed with no additional addressing.
After the last address (7FFh) is reached, the address An actual memory array write occurs after the 8th
latch will roll over to 000h. There is no limit on the data bit is transferred. It will be complete before the
number of bytes that can be accessed with a single acknowledge is sent. Therefore, if the user desires to
read or write operation. abort a write without altering the memory contents,
this should be done using start or stop condition
Data Transfer
prior to the 8th data bit. The FM24CL16B needs no
After all address information has been transmitted, page buffering.
data transfer between the bus master and the
FM24CL16B can begin. For a read operation the The memory array can be write protected using the
device will place 8 data bits on the bus then wait for WP pin. Setting the WP pin to a high condition
an acknowledge. If the acknowledge occurs, the next (VDD) will write-protect all addresses. The
sequential byte will be transferred. If the FM24CL16B will not acknowledge data bytes that
acknowledge is not sent, the read operation is are written to protected addresses. In addition, the
concluded. For a write operation, the FM24CL16B address counter will not increment if writes are
will accept 8 data bits from the master then send an attempted to these addresses. Setting WP to a low
acknowledge. All data transfer occurs MSB (most state (VSS) will deactivate this feature.
significant bit) first.
Figure 5 and 6 below illustrates both a single-byte
and multiple-byte writes.

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 FM24CL16B - 16Kb 3V I2C F-RAM

By Master Start Address & Data Stop

S Slave Address 0 A Word Address A Data Byte A P

By FM24CL16
Acknowledge

Figure 5. Single Byte Write

By Master Start Address & Data Stop

S Slave Address 0 A Word Address A Data Byte A Data Byte A P

By FM24CL16
Acknowledge

Figure 6. Multiple Byte Write

There are four ways to properly terminate a read

Read Operation
operation. Failing to properly terminate the read will
There are two types of read operations. They are most likely create a bus contention as the
current address read and selective address read. In a FM24CL16B attempts to read out additional data
current address read, the FM24CL16B uses the onto the bus. The four valid methods are as follows.
internal address latch to supply the lower 8 address
bits. In a selective read, the user performs a procedure 1. The bus master issues a no-acknowledge in the
to set these lower address bits to a specific value. 9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
Current Address & Sequential Read the preferred method.
As mentioned above the FM24CL16B uses an 2. The bus master issues a no-acknowledge in the
internal latch to supply the lower 8 address bits for a 9th clock cycle and a start in the 10th.
read operation. A current address read uses the 3. The bus master issues a stop in the 9th clock
existing value in the address latch as a starting place cycle. Bus contention may result.
for the read operation. This is the address 4. The bus master issues a start in the 9th clock
immediately following that of the last operation. cycle. Bus contention may result.

To perform a current address read, the bus master If the internal address reaches 7FFh it will wrap
supplies a slave address with the LSB set to 1. This around to 000h on the next read cycle. Figures 7 and
indicates that a read operation is requested. The 3 8 show the proper operation for current address reads.
page select bits in the slave ID specify the block of
memory that is used for the read operation. On the Selective (Random) Read
next clock, the FM24CL16B will begin shifting out A simple technique allows a user to select a random
data from the current address. The current address is address location as the starting point for a read
the 3 bits from the slave ID combined with the 8 bits operation. It uses the first two bytes of a write
that were in the internal address latch. operation to set the internal address byte followed by
subsequent read operations.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read To perform a selective read, the bus master sends out
is simply a current address read with multiple byte the slave address with the LSB set to 0. This specifies
transfers. After each byte, the internal address counter a write operation. According to the write protocol, the
will be incremented. Each time the bus master bus master then sends the word address byte that is
acknowledges a byte this indicates that the loaded into the internal address latch. After the
FM24CL16B should read out the next sequential FM24CL16B acknowledges the word address, the
byte. bus master issues a start condition. This

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 FM24CL16B - 16Kb 3V I2C F-RAM

simultaneously aborts the write operation and allows set to 1. The operation is now a current address read.
the read command to be issued with the slave address This operation is illustrated in Figure 9.

No
By Master Start Address Acknowledge
Stop

S Slave Address 1 A Data Byte 1 P

By FM24CL16 Acknowledge Data

Figure 7. Current Address Read

No
Start Address Acknowledge Acknowledge
By Master
Stop

S Slave Address 1 A Data Byte A Data Byte 1 P

By FM24CL16 Acknowledge Data

Figure 8. Sequential Read

No
Start Address Start Address Acknowledge Acknowledge
By Master
Stop

S Slave Address 0 A Word Address A S Slave Address 1 A Data Byte A Data Byte 1 P

By FM24CL16 Acknowledge Data

Figure 9. Selective (Random) Read

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 FM24CL16B - 16Kb 3V I2C F-RAM

Electrical Specifications
Absolute Maximum Ratings
Symbol Description Ratings
VDD Power Supply Voltage with respect to VSS -1.0V to +5.0V
VIN Voltage on any pin with respect to VSS -1.0V to +5.0V
and VIN < VDD+1.0V *
TSTG Storage Temperature -55°C to + 125°C
TLEAD Lead temperature (Soldering, 10 seconds) 260° C
VESD Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E) 4kV
- Charged Device Model (AEC-Q100-011 Rev. B) 1.25kV
- Machine Model (AEC-Q100-003 Rev. E) 300V
Package Moisture Sensitivity Level MSL-1
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

DC Operating Conditions (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified)
Symbol Parameter Min Typ Max Units Notes
VDD Main Power Supply 2.7 3.3 3.65 V
IDD VDD Supply Current 1
@ SCL = 100 kHz 100 µA
@ SCL = 400 kHz 170 µA
@ SCL = 1 MHz 300 µA
ISB Standby Current 3 6 µA 2
ILI Input Leakage Current ±1 µA 3
ILO Output Leakage Current ±1 µA 3
VIH Input High Voltage 0.7 VDD VDD + 0.3 V
VIL Input Low Voltage -0.3 0.3 VDD V
VOL Output Low Voltage
@ IOL = 3.0 mA 0.4 V
RIN WP Input Resistance (WP)
For VIN = VIL (max) 40 KΩ 5
For VIN = VIH (min) 1 MΩ
VHYS Input Hysteresis (Does not apply to WP) 0.05 VDD V 4
Notes
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to the WP pin.
4. This parameter is characterized but not tested.
5. The input pull-down circuit is strong (40KΩ) when the input voltage is below VIL and much weaker (1MΩ)
when the input voltage is above VIH.

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 FM24CL16B - 16Kb 3V I2C F-RAM

AC Parameters (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified)
Symbol Parameter Min Max Min Max Min Max Units Notes
fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1
tLOW Clock Low Period 4.7 1.3 0.6 µs
tHIGH Clock High Period 4.0 0.6 0.4 µs
tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs
tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs
tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs
tSU:STA Start Condition Setup for Repeated 4.7 0.6 0.25 µs
Start
tHD:DAT Data In Hold Time 0 0 0 ns
tSU:DAT Data In Setup Time 250 100 100 ns
tR Input Rise Time 1000 300 300 ns 2
tF Input Fall Time 300 300 100 ns 2
tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs
tDH Data Output Hold 0 0 0 ns
(from SCL @ VIL)
tSP Noise Suppression Time Constant 50 50 50 ns
on SCL, SDA
Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.
1 The speed-related specifications are guaranteed characteristic points from DC to 1 MHz.
2 This parameter is periodically sampled and not 100% tested.

Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3V)

Symbol Parameter Max Units Notes
CI/O Input/Output Capacitance (SDA) 8 pF 1
CIN Input Capacitance 6 pF 1
Notes
1 This parameter is periodically sampled and not 100% tested.

Power Cycle Timing

Power Cycle Timing (TA = -40°C to +85°C, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol Parameter Min Max Units Notes
tPU Power Up (VDD min) to First Access (Start condition) 10 - ms
tPD Last Access (Stop condition) to Power Down (VDD min) 0 - µs
tVR VDD Rise Time 30 - µs/V 1
tVF VDD Fall Time 100 - µs/V 1
Notes
1. Slope measured at any point on VDD waveform.

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 FM24CL16B - 16Kb 3V I2C F-RAM

AC Test Conditions Equivalent AC Load Circuit

Input Pulse Levels 0.1 VDD to 0.9 VDD
Input rise and fall times 10 ns 3.6V
Input and output timing levels 0.5 VDD

1100 Ω

Diagram Notes Output

All start and stop timing parameters apply to both read and write cycles. 100 pF
Clock specifications are identical for read and write cycles. Write timing
parameters apply to slave address, word address, and write data bits.
Functional relationships are illustrated in the relevant data sheet
sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

t HIGH
tR tF t LOW t SP t SP
`
SCL
t SU:STA tBUF 1/fSCL t HD:DAT
t SU:DAT
SDA
tAA t DH
Start Stop Start Acknowledge

Write Bus Timing

t HD:DAT
SCL
t HD:STA t SU:DAT t AA
t SU:STO

SDA

Start Stop Start Acknowledge

Data Retention
Symbol Parameter Min Max Units Notes
TDR @ +85ºC 10 - Years
@ +80ºC 19 - Years
@ +75ºC 38 - Years

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 FM24CL16B - 16Kb 3V I2C F-RAM

Mechanical Drawing
8-pin SOIC (JEDEC MS-012 variation AA)

Refer to JEDEC MS-012 for complete dimensions and notes.

All dimensions in millimeters.

SOIC Package Marking Scheme

Legend:
XXXXXX= part number, P= package type (G=SOIC)
XXXXXXXP R=rev code, LLLLLLL= lot code
RLLLLLLL RIC=Ramtron Int’l Corp, YY=year, WW=work week
RICYYWW
Example: FM24CL16B, “Green” SOIC package, Year 2010, Work Week 49

FM24CL16BG
A00002G1
RIC1049

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 FM24CL16B - 16Kb 3V I2C F-RAM

8-pin TDFN (4.0mm x 4.5mm body, 0.95mm pitch)

Exposed metal pad
should be left floating.
4.50 ±0.1

4.00 ±0.1

2.60 ±0.10
3.60 ±0.10
Pin 1 ID

Pin 1

2.85 REF
0.30 ±0.1
0.0 - 0.05
0.75 ±0.05

0.20 REF. Recommended PCB Footprint

0.95 0.60
0.40 ±0.05
4.30

Silkscreen
Pin 1

0.50
0.95

Note: All dimensions in millimeters. The exposed pad should be left floating.

TDFN Package Marking Scheme for Body Size 4.0mm x 4.5mm

Legend:
R=Ramtron, XXXXX=base part number
RXXXXX LLLL= lot code,
LLLL YY=year, WW=work week
YYWW
Example: “Green” TDFN package, FM24CL16B, Lot 0003, Industrial temperature,
Year 2011, Work Week 07

R4L16B
0003
1107

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 FM24CL16B - 16Kb 3V I2C F-RAM

Revision History

Revision Date Summary

1.0 11/10/2010 Initial Release
1.1 12/20/2010 Added 4x4.5mm DFN package.
1.2 1/17/2011 Fixed DFN pinout. Modified DFN mechanical drawing and recommended pcb
footprint.
1.3 2/10/2011 Added ESD ratings. Updated DFN package marking.
1.4 2/15/2011 Changed tPU and tVF spec limits.

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