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1 ROCHESTER INSTITUTE OF TECHNOLOGY SPICE_Parameter_Calculator.xls

2 MICROELECTRONIC ENGINEERING 3/20/2010
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4 CALCULATION OF MOSFET SPICE PARAMETERS DR. LYNN FULLER
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6 To use this spreadsheet change the values in the white boxes. The rest of the sheet is protected and should not be changed unless
7 you are sure of the consequences. The calculated results are shown in the purple boxes.
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9 CONSTANTS
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11 T= 300 K Boron D0 0.76 cm2/s
12 KT/q = 0.026 volts Boron Ea 3.46 eV
13 ni = 1.45E+10 cm-3 Phosphorous D0 3.85 cm2/s
14 Eo = 8.85E-14 F/cm Phosphorous Ea 3.66 eV
15 Er si = 11.7
16 Er SiO2 = 3.9 Carrier Velocity Saturation occurs at ~ 5E6 to 2E7 cm/s, extracted values can be artificially 2 times higher
17 E affinity = 4.15 volts Critical value of electric field e c of ~8E3 to 3E4 V/cm for electrons, ~2E4 to 1E5 V/cm for holes
18 q = 1.60E-19 coul
19 Eg = 1.124 volts
20 INTRODUCTION
21 This spreadsheet calculates nmos or pmos level one, three and BSIM3 SPICE parameters from details known about the process parameters, device layout and
22 fabrication history. Level one spice parameters assume mobility is a function of total impurity concentration and temperature only. Level one uses the parameter
23 LAMBDA for channel length modulation. Different equations are used to calculate Ids in the saturation and non-saturation regions of operation.
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25 The level three SPICE model is derived from the level one model with some additional parameters to better account for the decrease in carrier mobility for
26 high vertical and lateral electric fields. The level three model also allows the user to account for narrow channel effects, drain induced barrier lowering (DIBL),
27 and gives better sub threshold characteristics. For example the parameter LAMBDA is replaced by a more complex model using the parameter VMAX and
28 KAPPA. The low field mobility value UO is modified for high gate electric fields with parameter THETA and modified for high lateral electric fields through
29 the VMAX parameter. Different equations are used to calculate Ids in the saturation, non-saturation and subthreshold regions of operation.
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31 The BSM3 SPICE parameters are derived from the level one and three parameters. BSIM models have hundreds of parameters used to fully describe DC and AC
32 deivce operation, temperature effects, noise, stress effects and more. Most of the parameters can only be determined from measured device performance. In
33 this spreadsheet the BSIM3 parameters are derived from level one and level three parameters. All other parameters are not specified and the default values are
34 invoked. The single equation for Ids is used that is valid in saturation, non-saturation and subthreshold regions of operation, making convergence during circuit
35 simulation more reliable.
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38 References: MOSFET Modeling with SPICE, Daniel Foty, 1997, Prentice Hall, ISBN-0-13-227935-5
39 Operation and Modeling of the MOS Transistor, 2nd Edition, Yannis Tsividis, 1999, McGraw-Hill, ISBN-0-07-065523-5
40 UTMOST III Modeling Manual-Vol.1. Ch. 5. From Silvaco International.
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42 LAYOUT PARAMETERS VALUES CALCULATED FROM PROCESS PARAMETERS
43 (assume source and drain are symmetrical)
44 L 2 um Diffusion Constant at Temp of Well Drive 1.43E-13 cm2/s
45 W 16 um Starting wafer doping = 1/(q umax Rho) 4.42E+14 cm-3
46 Area of Drain/Source 96 um2 Well Surface Concentration= Ns = Dose / (pi D t)^0.5 1.45E+17 cm-3
47 Perimeter of Drain/Source 44 um Well Depth = ((4DdTd/Dose) ln(Nsub(piDdTd)^0.5))^0.5 3.75 um
48 # squares between Contact and Channel 0.143 Well average doping, Nave = Dose/xj 5.33E+16 cm-3
49 # squares between LDD/N+ and Channel 0.025 Bulk Well Majority Carrier Mobility at N=Nave 394.32 cm2/v-s
50 Bulk Well Minority Carrier Mobility at N=Nave 1004.52 cm2/v-s
51 PROCESS PARAMETERS 1=yes, 0=No Well Sheet Resistance = 1/(q(µ(Nave))Dose) 792.50 ohms
52 Aluminum gate 0 Well surface mobility at Surface Doping Concentration 725.76 cm2/V-s
53 n+ Poly gate 1 select one Wdmax = (4 eoesi f s / q / Nave )^0.5 0.143 um
54 p+ Poly gate 0 Metal Work Function, fm 4.12 volts
55 N well (pMOSFET) 0 select one Magnitude of Semiconductor Potential (Fermi - Intrinsic), f s 0.419 volts
56 P well (nMOSFET) 1 Oxide Capacitance/cm2 = Cox' 2.30E-07 F/cm2
57 Vt adjust Dose (+ for Boron, - for Phos) 0.00E+00 cm-2 Metal Semi Work Function Diff, fms -0.170 volts
58 Gate Oxide Thickness 150 Å Flat Band Voltage, VFB = -0.379 volts
59 NSS 3.00E+11 cm-2 Threshold Voltage, VTO 1.33 volts
60 Starting Wafer Resistivity 10 ohm-cm Threshold Adjust, DV=q Dose/2/Cox' 0.00 volts
61 Well Dose 2.00E+13 cm-2 Ion Implanted Adjusted Threshold Voltage, VT 1.33 volts
62 Well Drive Time 710 min Diffusion Constant at Temp of D/S Anneal 1.17E-14 cm2/s
63 Well Drive Temperature 1100 C LDD D/S Junction Depth, XJ = 0.18 um
64 LDD D/S Dose 2.50E+13 cm-2 LDD D/S average doping, Nave = Dose/xj 1.36E+18 cm-3
65 LDD D/S Drive Time 30 min Bulk Mobility in LDD D/S at N=Nave 230.94 cm2/v-s
66 LDD D/S Drive Temperature 1000 C LDD D/S Sheet Resistance = 1/(q(µ(Nave))Dose) 1082.55 ohms
67 Field Oxide Thickness 6000 Å D/S Junction Depth, XJ = 0.27 um
68 Minority Carrier Lifetime in the well 1 µs D/S average doping, Nave = Dose/xj 7.52E+19 cm-3
69 D/S Dose (N+ or P+) 2.00E+15 cm-2 Bulk Mobility in D/S at N=Nave 92.51 cm2/v-s
70 D/S SILISIDE (1=YES, 0=NO) 0 D/S Sheet Resistance = 1/(q(µ(Nave))Dose) 33.78 ohms
71 Lateral Diffusion = LD = 0.8*Xj 0.15 µm
72 Capacitance/cm2 for Field Oxide 5.75E-09 F/cm2
73 D/S Width of Space Charge Layer at Zero Bias, Xdso = 0.152 µm
74 D/S Width of Space Charge Layer at Vdd, Bias Xds = 0.380 µm
75 Leff = Lmask - 2*LD - 2*Xdso 1.400 µm
76 MEASURED TRANSISTOR VALUES Built in Voltage for D/S pn junction 0.95 volts
77 Vdd 5 volts Junction reverse bias current density, JS 3.23E-08 A/m2
78 Magnitude of IDS at Vgs=Vds=Vdd 5.41 mAmps =I'ds Junction Capacitance for D/S at zero bias 6.80E-08 F/cm2
79 Magnitude of IDS at Vgs=Vdd, Vds=Vds 5.12 mAmps =Idsat Lambda, Calculated, ((Lmax/Lmin)-1)/Vdd 0.031 1/volt
80 VTO (+ for nmos and - for pmos)) 1.1 volts
81 Isub-min 0.001 nAmps CALCULATED SPICE PARAMETERS FROM MEASURED VALUES
82 D/S Sheet Resistance 39.2 ohms Ueff mobility to match IDS at Vgs=Vds=Vdd 286.44 cm2/v-s
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83 Lambda 0.03 1/volts LAMBDA measured 0.03 1/volts
84 VT0 measured 1.1 volts
85 JS = Isub-min/Area of Drain measured 1.04E-02 A/m2
86 RSH measured 39.2 ohms
87 SPICE PARAMETERS FOR LEVEL ONE MODEL
88 1 The parameters in the yellow boxes are calculated from the other parmaters and thus should not be entered in the SPICE model
89 2 If the SPICE parameters from measured values are different than the calculated SPICE parameters you might want to use them instead.
90 3 We assume the model definition has L, W, AD, AS, PD, PS, NRS, NRD specified for calculation of some of the parameters in the yellow boxes
91 4 Lambda is different for every different length transistor in the level one model, so a different model is needed for each different length mosfet
92
93 SPICE Name SPICE Parameters
94 Parameter Using Process Parameters note: most parameters use O not 0 at end of parameter name ("oh" not "zero")
95 1 Level 1 Schichman and Hodges Model
96 2 VTO 1.33 volts Zero Bias Threshold Voltage, enter value if threshold adjust implant is used
97 3 KP 2.50E-04 F/s-volt Transconductance Parameter, KP = U0 esi eo /Tox
98 4 GAMMA 9.52E-01 (volt)1/2 Bulk Threshold Parameter, GAMMA = [2q si eo NSUB/Cox2]1/2
99 5 PHI 0.419 volts PHI is the semiconductor potential, Intrinsic Level to Fermi Level difference
100 6 LAMBDA 0.031 1/volts Channel length modulation parameter
101 7 RD 27.06 ohms Series Drain Resistance
102 8 RS 27.06 ohms Series Source Resistance
103 9 CBD 7.08E-14 F CBD zero bias bulk to drain junction capacitance, CBD = CJ AD + CJSW PD
104 10 CBS 7.08E-14 F CBD zero bias bulk to source junction capacitance, CBD = CJ AD + CJSW PD
105 11 IS 3.10E-18 A D/S junction leakage current
106 12 PB 0.95 volts PB is the junction built in voltage, PB = (KT/q)ln (NSUB/ni) + 0.56
107 13 CGSO 3.40E-10 F/m G-to-S overlap C (per m channel width) CGSO=Cox’(mask overlap in L direction + LD)
108 14 CGDO 3.40E-10 F/m G-to-D overlap C (per m channel width) CGDO=Cox’(mask overlap in L direction + LD)
109 15 CGBO 5.75E-10 Fm G-to-well overlap C (per meter channel length) CGSO=Cox’(mask overlap in W direction)
110 16 RSH 33.78 ohms Sheet resistance of D/S
111 17 CJ 6.80E-04 F/m2 D/S Bottom junction capacitance/m2,
112 18 MJ 0.5 Junction Grading Coeficient for bottom of D/S Junction
113 19 CJSW 1.26E-10 F/m D/S side wall junction capacitance per meter of D/S permeter
114 20 MJSW 0.5 Junction Grading Coeficient for side of D/S Junction
115 21 JS 3.23E-08 A/m2 D/S junction leakage current
116 22 TOX 1.50E-08 m Gate Oxide Thickness
117 23 NSUB 1.45E+17 cm-3 Well Doping, Nave
118 24 NSS 3.00E+11 cm-2 Surface State Density as known from process knowledge
119 25 NFS 0 Fast Surface States, Always set to zero
120 26 TPG 1 +1 if gate doped opposite of channel, -1 if gate doped same as channel, 0 if gate is aluminum
121 27 XJ 0.18 um D/S Junction Depth
122 28 LD 0.15 um Lateral Diffusion of D/S into the channel arbitrarly set to 80% of XJ

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123 29 UO 363 cm2/v-s Well surface minority carrier mobility at well surface concentration divided by two
124 .MODEL RITSUBN1 NMOS (LEVEL=1 .MODEL RITSUBP1 PMOS (LEVEL=1
125 +VTO=1.0 LAMBDA= 0.031 PB=0.95 CGSO=3.4E-10 CGDO=3.4E-10 +VTO=1.0 LAMBDA= 0.05 PB=0.94 CGSO=5.08E-10 CGDO=5.08E-10
126 +CGBO=5.75E-10 RSH=33.8 CJ=6.8e-4 MJ=0.5 CJSW=1.26e-10 +CGBO=5.75E-10 RSH=33.7 CJ=5.01e-4 MJ=0.5 CJSW=1.38e-10
127 +MJSW=0.5 JS=3.23e-8 TOX=150E-10 NSUB=1.45e17 NSS=3E11 +MJSW=0.5 JS=6.43e-8 TOX=150E-10 NSUB=7.23e16 NSS=1E11
128 +TPG=+1 XJ=0.18U LD=0.15U UO=363) +TPG=+1 XJ=0.28U LD=0.22U UO=363)
129 SPICE PARAMETERS FOR LEVEL THREE MODEL
130 1 WD is estimated to be 1/2 the field oxide thickness for a LOCOS process
131 2 THETA is calculated from Ueff = UO/(1+THETA(Vgs-Vt)) and Ids=Ueff (Cox'/2) (W/L)(Vgs-Vt)^2(1+lVds) using measured Ids and Vt values
132 3 DELTA is calculated = q*Nave*(Xds)^2 / (eo esi (2 fs))
133 4 KAPPA is calculated = [(qNsub/(2eoer))((1-I/I')(L-2LD-Xdso-Xds))^2)/(Vds-Vdsat)]^0.5
134 5 VMAX is calculated from effective mobility times electric field at Vgs=Vds=Vdsat, where E=Vdsat/Leff
135 6 ETA is calculated from the ratio of charge in the channel at Vds=Vdd to charge in the channel at Vds=zero
136 note: Parameters in Red come directly from SPICE Level One
137 Parameter Name Value Units note: most parameters use O not 0 at end of parameter name ("oh" not "zero")
138 1 Level 3
139 2 TPG 1 Type of Gate Material
140 3 TOX 1.50E-08 m Gate Oxide Thickness
141 4 LD 2.95E-07 m Channel Length Reduction from Drawn Value
142 5 WD 3.00E-07 m Channel Width Reduction From Drawn Value
143 6 UO 726 cm2/V-s Zero Bias Low Field Mobility
144 7 VTO 1.33 V Measured threshold voltage for long wide devices with zero substrate bias
145 8 THETA 0.393 1/V Gate Field Induced Mobility Reduction Parameter
146 9 RS 27.06 ohm In level 3 only lumped resistance is available, each different width FET has a different model
147 10 RD 27.06 ohm In level 3 only lumped resistance is available, each different width FET has a different model
148 11 DELTA 2.27 Narrow Channel Effect on the Threshold Voltage
149 12 NSUB 1.45E+17 cm-3 Effective Substrate Doping
150 13 XJ 1.84E-07 m Drain/Source junction depth
151 14 VMAX 1.02E+07 m/s Maximum Carrier Velocity (extraction can gvie 1.2 to 2 times expected saturation velocity)
152 15 ETA 0.837 DIBL Coefficient
153 16 KAPPA 0.509 1/V Channel Length Modulation Effect on the Drain Current
154 17 NFS 3.00E+11 cm-2 Surface State Density
155 18 CGSO 3.40E-10 F/m Zero Bias Gate-Source Capacitance
156 19 CGDO 3.40E-10 F/m Zero Bias Gate-Drain Capacitance
157 20 CGBO 5.75E-10 F/m Zero Bias Gate-Substrate Capacitance
158 21 PB 0.95 V PB is the junction built in voltage, PB = (KT/q)ln (NSUB/ni) + 0.56
159 22 XQC 0.40 Charge Partitioning Parameter (from Ward and Dutton)
160 Adifferent model is needed for each transistor of different length or width. Example models shown below.
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162 *.MODEL RITSUBN3 NMOS (LEVEL=3 TPG=1 TOX=1.5E-8 LD=2.95E-7 WD=3.00E-7
163 *+U0= 726 VTO=0.5 THETA=0.393 RS=27 RD=27 DELTA=2.27 NSUB=1.45E17
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164 *+XJ=1.84E-7 VMAX=1.10E7 ETA=0.837 KAPPA=0.509 NFS=3E11
165 *+CGSO=3.4E-10 CGDO=3.48E-10 CGBO=5.75E-10 PB=0.95 XQC=0.4)
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167 *.MODEL RITSUBP3 PMOS (LEVEL=3 TPG=1 TOX=1.5E-8 LD=3.61E-7 WD=3E-7
168 +UO=377 VT0=-0.93 THETA=0.32 RS=33.7 RD=33.7 DELTA=2.35 NSUB=7.12E16
169 +XJ=2.26E-7 VMAX=3.84E6 ETA=0.897 KAPPA=4.481 NFS=3E11
170 +CGSO=4.15E-10 CGD0=4.15E-10 CGBO=5.75E-10 PB=0.94 XQC=0.40)
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172 SPICE PARAMETERS FOR BISIM3 VER 3.1, LEVEL 49
173 BSIM3V3 is the industry standard, physics-based, deep submicron MOSFET SPICE model for digital and analog circuit design from the Device Group at the
174 University of California at Berkeley. Level 8 is the origional Berkeley version, Level 81 is a slightly modified Silvaco version, Level 49 and 53 are Hspice versions.
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176 note: most parameters use 0 not O at end of parameter name ("zero" not "oh")
177 note: Parameters in Red come directly from SPICE Level One and/or Three
178 Parameter Name Value Units
179 Control Level 49 Level 8, 81, 49 or 53
180 Control VERSION 3.1 3.0, 3.1 or 3.2 versions, default is the newest version
181 Control MOBMOD 1 Mobility model selector (1,2,3,4… selects slightly different equations for calculation of Ueff)
182 Control CAPMOD 2 Capacitance model selector (1,2,3,4… selects slightly different equations for gate Ceff)
183 Process TOX 1.50E-08 m Gate oxide thickness
184 Process XJ 1.84E-07 m Junction Depth
185 Process NCH 1.45E+17 cm-3 Well surface doping concentration
186 Process NSUB 5.33E+16 cm-3 Well doping concentration below the surface
187 Process XT 1.43E-07 m Distance into well where surface concentration is valid, Default = 1.5E-7m
188 Process NSS 3.00E+11 cm-2 Surface State Density, Level 3 NFS or Level 1 NSS treated as equal
189 DC VTH0 1.33 V Threshold voltage, Long, Wide Device, Zero Substrate Bias = VTO in level 3
190 DC U0 725.76 cm2/v-s Low Field Mobility
191 DC WINT 2.0E-07 m Isolation Reduction of Channel Width (from process knowledge)
192 DC LINT 1.84E-07 m Source/Drain Underdiffusion of Gate (set equal to XJ)
193 DC PCLM 5.00 Channel Length Modulation Parameter, default = 1.3 (select to fit Ids vs. Vds family)
194 DC NGATE 5.00E+20 m-3 Gate Doping (5E20 if Diffusion Doped, Dose/Poly Thickness if Ion Implanted with D/S)
195 Diode/Resistor RSH 1082.55 ohm/sq Drain/Source sheet Resistance
196 Diode/Resistor JS 3.23E-08 A/m2 Bottom junction saturation current per unit area
197 Diode/Resistor JSW 3.23E-08 A/m side wall junction saturation current per unit length
198 Diode/Resistor CJ 6.80E-04 F/m2 Bottom Junction Capacitance per unit area at zero bias
199 Diode/Resistor MJ 0.5 Bottom Junction Capacitance Grading Coeficient
200 Diode/Resistor PB 0.95 V PB is the junction built in voltage, PB = (KT/q)ln (NSUB/ni) + 0.56
201 Diode/Resistor CJSW 1.26E-10 F/m Side Wall Junction Capacitance per meter of length at zero bias
202 Diode/Resistor MJSW 0.5 Side Wall Junction Capacitance Grading Coeficient
203 Diode/Resistor PBSW 0.95 V PBSW is the side wall junction built in voltage, PB = (KT/q)ln (NSUB/ni) + 0.56
204 AC CGS0 3.40E-10 F/m Zero Bias Gate-Source Capacitance per meter of gate width
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205 AC CGD0 3.40E-10 F/m Zero Bias Gate-Drain Capacitance per meter of gate width
206 AC CGB0 5.75E-10 F/m Zero Bias Gate-Substrate Capacitance per meter of gate length
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216 .MODEL RITSUBN49 NMOS (LEVEL=49 VERSION=3.1 CAPMOD=2 MOBMOD=1
217 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 NSS=3E11 PCLM=5
218 +VTH0=0.5 U0= 926 WINT=2.0E-7 LINT=1.84E-7 +NGATE=5E20
219 +RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
220 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95
221 +CGS0=3.4E-10 CGD0=3.4E-10 CGB0=5.75E-10) Measured
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228 LEVEL49
229 VT0=0.5
230 UO=1082
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242 LEVEL3
243 LEVEL 1 VTO=0.5
244 VTO=0.5 UO=725
245 UO=363
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258 Measured
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264 LEVEL 49
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277 LEVEL 1
278 LEVEL 3
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292 .MODEL RITSUBP49 PMOS (LEVEL=49 VERSION=3.1 CAPMOD=2 MOBMOD=1
293 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 NSS=3E11 PCLM=5
294 +XWREF= 2.0E-7 XLREF=3.61E-7 VTH0=-1.22 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20
295 +RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
296 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94
297 +CGS0=4.5E-10 CGD0=4.5E-10 CGB0=5.75E-10)
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