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    IEEE 3DIC Conference, Munich, November 18, 2010: Tutorial 1 3D-SIC Design and Test

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    bkv1409
    This document provides information about a 3-hour tutorial on 3D-SIC design and test taking place at the IEEE 3DIC conference in Munich, Germany. The tutorial will be presented by Paul Franzon from NC State University and Erik Jan Marinissen from IMEC and will cover challenges in 3D-SIC system design, CAD, thermal design, and testing. It will introduce 3DIC technology and focus on solving these challenges, including topics like 3D-SIC architecture opportunities, design flows, thermal and power integrity, and 3D test flows and methods. Brief biographies of the two speakers are also provided.

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    IEEE 3DIC Conference, Munich, November 18, 2010: Tutorial 1 3D-SIC Design and Test

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    This document provides information about a 3-hour tutorial on 3D-SIC design and test taking place at the IEEE 3DIC conference in Munich, Germany. The tutorial will be presented by Paul Franzon from NC State University and Erik Jan Marinissen from IMEC and will cover challenges in 3D-SIC system design, CAD, thermal design, and testing. It will introduce 3DIC technology and focus on solving these challenges, including topics like 3D-SIC architecture opportunities, design flows, thermal and power integrity, and 3D test flows and methods. Brief biographies of the two speakers are also provided.

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    This document provides information about a 3-hour tutorial on 3D-SIC design and test taking place at the IEEE 3DIC conference in Munich, Germany. The tutorial will be presented by Paul Franzon from NC State University and Erik Jan Marinissen from IMEC and will cover challenges in 3D-SIC system design, CAD, thermal design, and testing. It will introduce 3DIC technology and focus on solving these challenges, including topics like 3D-SIC architecture opportunities, design flows, thermal and power integrity, and 3D test flows and methods. Brief biographies of the two speakers are also provided.

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    40 views3 pages

    IEEE 3DIC Conference, Munich, November 18, 2010: Tutorial 1 3D-SIC Design and Test

    Uploaded by

    bkv1409
    This document provides information about a 3-hour tutorial on 3D-SIC design and test taking place at the IEEE 3DIC conference in Munich, Germany. The tutorial will be presented by Paul Franzon from NC State University and Erik Jan Marinissen from IMEC and will cover challenges in 3D-SIC system design, CAD, thermal design, and testing. It will introduce 3DIC technology and focus on solving these challenges, including topics like 3D-SIC architecture opportunities, design flows, thermal and power integrity, and 3D test flows and methods. Brief biographies of the two speakers are also provided.

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    IEEE 3DIC Conference, Munich, November 18, 2010

    Tutorial 1
    3D-SIC Design and Test

    Speakers and contact:

    Paul Franzon
    Department of Electrical and Computer Engineering,
    NC State University,
    Raleigh, NC 27695
    USA
    Phone: 919.515.7351
    E-Mail: paulf@ncsu.edu

    Erik Jan Marinissen


    IMEC vzw
    Kapeldreef 75, B-3001 Leuven
    BELGIUM
    Phone: +32 (16) 28-8755
    E-mail: erik.jan.marinissen@imec.be

    Content:
    3D stacking and integration with TSVs provide significant potential system advantages in terms of
    power, scale, cost, and performance. However, it also brings challenges in system design, CAD,
    thermal design, and test. This tutorial will briefly introduce 3DIC technology and then focus mainly
    on solving the challenges.

    Further details see next pages.

    Duration:
    3 hours
    Part 1 - Design of 3D-SICs

    1. Introduction

    2. 3D-SIC Technology
    Motivation
    Application drivers
    3D manufacturing steps (incl. TSV formation, wafer thinning, and bonding)
    Manufacturing options

    3. 3D-SIC System Drivers


    Design drivers
    Architectural opportunities
    Matching technology with application

    4. 3D-SIC Design
    Floorplanning and partitioning
    Usable CAD flows
    Thermal, power integrity and codesign
    Managing cost

    Part 2 - Test of 3D-SICs

    5. 3D Test Flows
    2D vs 3D test flows: wafer test and final test; pre-bond die testing and post-bond stack
    testing
    KGD and KGS testing
    Test flow cost modeling
    The value of pre-bond testing in W2W stacking

    6. 3D Test Contents
    Tests for new intra-die defects
    Tests for TSV-based interconnects

    7. 3D Test Access
    Wafer probing: from ATE to external I/Os and vice versa:
    pre-bond probing and post-bond probing
    Design-for-Test: from external I/Os to intra-die circuitry and vice versa:
    3D DfT architecture, standardization, EDA flow

    8. Conclusion
    Tutorial summary
    Evaluation with / by audience
    Biographies

    Paul D. Franzon is currently a Professor of Electrical and Computer Engineering at North Carolina
    State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia in 1988.
    He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and two companies
    he cofounded, Communica and LightSpin Technologies. His current interests center on the
    technology and design of complex systems incorporating VLSI, MEMS, advanced packaging and nano-
    electronics. He has led several major efforts and published over 180 papers in these areas. In 1993
    he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of
    Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, and in 2005 won the
    Alcoa award. He is a Fellow of the IEEE.

    Erik Jan Marinissen received the MSc degree in Computing Science and the PDEng degree in Software
    Technology from Eindhoven University of Technology in 1990 and 1992, respectively. He is currently
    a Principal Scientist at IMEC in Leuven, Belgium. Prior to IMEC, he was with NXP Semiconductors and
    Philips Research, both in Eindhoven, The Netherlands. Marinissen’s research interests include all
    topics in the domain of test and debug of integrated circuits. He is a co-author of more than 140
    journal and conference papers and a co-inventor of nine granted US and EU patent families. He is a
    recipient of Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability
    Workshop in 1995, the IEEE International Board Test Workshop in 2002, and the Most Significant
    Paper Award at the IEEE International Test Conference in 2008. Marinissen served as an Editor-in-
    Chief of IEEE Std. 1500. He serves on numerous conference committees, including ATS, ETS, DATE,
    ITC, and VTS. He is a founder of workshops on ‘Diagnostic Services in Network-on-Chips’ (DSNOC),
    ‘3D Integration’, and ‘Testing Three-Dimensional Stacked ICs’ (3D-TEST). Marinissen serves on the
    editorial boards of IEEE ‘Design & Test of Computers’, IET ‘Computers and Digital Techniques’ (IET-
    CDT), and Springer’s ‘Journal of Electronic Testing: Theory and Applications’ (JETTA). He is a Senior
    Member of IEEE and a Golden Core Member of Computer Society. Marinissen presented full-day
    tutorials at ATS, DATE, ETW, ITC, and VTS.

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