Microprocessors &

Microcontrollers
Somnath Dey
A microprocessor incorporates most or all of the functions
of a computer's central processing unit (CPU) on a single
integrated circuit (IC, or microchip). The first
microprocessors emerged in the early 1970s and were
used for electronic calculators, using binary-coded
decimal (BCD) arithmetic on 4-bit words. Other
embedded uses of 4-bit and 8-bit microprocessors, such
as terminals, printers, various kinds of automation etc.
followed soon after. Affordable 8-bit microprocessors
with 16-bit addressing also led to the first general-
Somnath Dey purpose microcomputers from the mid-1970s on.
ETCE/D/0027 [2010-11]

C e n t r a l C a l c u tt a P o l y t e c h n i c

+919836448851
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INTEL 8086 Microprocessor

Introduction:

The 8086 was the first 16-bit Microprocessor to be introduced by Intel Corporation. It is designed to be
upwardly compatible with the older 8080/8085 series of 8-bit microprocessors. The upward compatibility
allows programs written for the 8080/8085 to be easily converted to run on the 8086.

The word 16-bit means that its arithmetic logical unit, internal registers, and most of its instructions are
designed to work with 16-bit binary words. The 8086 has a 16-bit data bus, so it can read data form or
write data to memory and ports either 16-bits or 8- bits at a time. The 8086 has a 20-bit address bus, so it
can address any one of 220 or 1,048,576 memory locations. Each of the 1,048,576 memory addresses of
the 8086 represents a byte-wide location. Words will be stored in two consecutive memory locations. If the
first byte of a word is at an even address, the 8086 can read the entire word in one operation. If the first
byte of the word is at an odd address, the 8086 will read the first byte of the word in one operation, and
the second byte in another operation.

Maximum & Minimum Mode:

The 8086 has two modes of operation:

 The Minimum Mode

 The Maximum Mode

In single processor system, the 8086 operates in the minimum mode of operation. In a multiprocessor &
coprocessor configuration, the 8086 operates in the maximum mode of operation. The status of the pin
MN/MX (pin 33) decides the operating mode of 8086. When MN/MX =1, the 8086 operates in minimum
mode and when MN/MX=0, the 8086 operates in maximum mode. The 24 pin to 31 pin of 8086 have
alternate function.

Hardware Architecture:

The term architecture, as used in microprocessor circuits, describes the functional components that make
up the MPU and the interaction between them. These include the temporary storage devices known as
registers, which are used to hold data, instructions, and status information. There are also devices to
perform arithmetic and logical operations. Control devices are used to control the flow of information
through the MPU.

As shown by the block diagram in Fig.3, the 8086 MPU is divided into two independent functional parts
known as the Execution Unit (EU) and the Bus Interface Unit (BIU). The Bus Interface Unit consists of
segment registers, adder to generate 20 bit address and instruction prefetch queue.

Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and they
fill a First in First out 6 byte queue.

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Bus Interface Unit (BIU)

The BIU is made up of the address generation and bus-control unit, the instruction queue, and the
instruction pointer. It has the task of making sure that the bus is used to its fullest capacity in order to
speedup operations. This function is carried in two ways. First, by fetching the instructions before they
are needed by the execution unit and storing them in the instruction queue, the 8086 MPU is able to
increase computing speed. Second, by taking care of all bus-control functions, the EU is free to
concentrate on processing data and carrying out the instructions. The instruction pointer contains the
location or address of the next instruction to be executed.

Execution unit (EU):

The EU is where the actual processing of data takes place inside the 8086 MPU. It is here that the
arithmetic and logic unit (ALU) is located, along with the registers used to manipulate data and store
immediate results. The EU accepts instructions and data that have been fetched by the BIU and then
processes the information. Data processed by the EU can be transmitted to the memory or peripheral
devices through the BIU. EU has no direct connection with the outside world and relies solely on the
BIU to feed it with instructions and data as indicated in Fig.4.

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It unit consists of scratch pad registers such as 16-bit AX, BX, CX and DX and pointers like SP
(Stack Pointer), BP (Base Pointer) and finally index registers such as source index and destination
index registers. The 16-bit scratch pad registers can be split into two 8-bit registers. For example, AX
can be split into AH and AL registers. The segment registers and their default offsets are given
below.

The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The results of
these operations can affect the condition flags.

Different registers and their operations are listed below:

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Registers:

Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four
different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of
processor memory these 4 segments are located the 8086 microprocessor uses four segment
registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by instruction
pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated
during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By
default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment. SS register can be changed directly using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By
default, the processor assumes that all data referenced by general registers (AX, BX, CX, and DX) and
index register (SI, DI) is located in the data segment. DS register can be changed directly using POP
and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data.
By default, the processor assumes that the DI register references the ES segment in string
manipulation instructions. ES register can be changed directly using POP and LES instructions.

It is possible to change default segments used by general and index registers by prefixing instructions
with a CS, SS, DS or ES prefix.

All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The
general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which can be combined together and used
as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the
high-order byte. Accumulator can be used for I/O operations and string manipulation.

Base register consists of 2 8-bit registers BL and BH, which can be combined together and used as a
16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-
order byte. BX register usually contains a data pointer used for based, based indexed or register
indirect addressing.

Count register consists of 2 8-bit registers CL and CH, which can be combined together and used as a
16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH
contains the high-order byte. Count register can be used as a counter in string manipulation and
shift/rotate instructions.

Data register consists of 2 8-bit registers DL and DH, which can be combined together and used as a
16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH
contains the high-order byte. Data register can be used as a port number in I/O operations. In integer
32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting
number.

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General and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for
based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string manipulation instructions.

Other registers:

Instruction Pointer (IP) is a 16-bit register.

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8086 flag register format:

a) CARRY FLAG – SET BY CARRY OUT OF MSB

b) PARITY FLAG – SET IF RESULT HAS EVEN PARITY
c) AUXILIARY CARRY FLAG FOR BCD
d) ZERO FLAG – SET IF RESULT = 0
e) SIGN FLAG = MSB OF RESULT
f) SINGLE STEP TRAP FLAG
g) INTERRUPT ENABLE FLAG
h) STRING DIRECTION FLAG
i) OVERFLOW FLAG

Flag is a 16-bit register containing 9 1-bit flags:

 Overflow Flag (OF) - set if the result is too large positive number, or is too small negative
number to fit into destination operand.
 Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.
 Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
 Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.
 Sign Flag (SF) - set if the most significant bit of the result is set.
 Zero Flag (ZF) - set if the result is zero.
 Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.
 Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.
 Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last
result calculation.

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There are three internal buses, namely A bus, B bus and C bus, which interconnect the various blocks
inside 8086. The execution of instruction in 8086 is as follows:

The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetches the first
instruction of a program from the memory. Subsequent addresses are sent

Memory
Program, data and stack memories occupy the same memory space. The total addressable memory
size is 1MB. As the most of the processor instructions use 16-bit pointers the processor can effectively
address only 64 KB of memory. To access memory outside of 64 KB the CPU uses special segment
registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of
memory (see the "Registers" section above).

16-bit pointers and data are stored as:

address: low-order byte
address+1: high-order byte

32-bit addresses are stored in "segment: offset" format as:

address: low-order byte of segment

address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset

Physical memory address pointed by segment: offset pair is calculated as:

address = (<segment> * 16) + <offset>

Program memory - program can be located anywhere in memory. Jump and call instructions can be
used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere
within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127
- -127 bytes from current instruction.

Data memory - the 8086 processor can access data in any one out of 4 available segments, which
limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks).
Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing
instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or
SS segments instead of DS segment).

Word data can be located at odd or even byte boundaries. The processor uses two memory accesses
to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries
requires only one memory access.

Stack memory can be placed anywhere in memory. The stack can be located at odd memory
addresses, but it is not recommended for performance reasons (see "Data Memory" above).

Reserved locations:

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 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in
format segment: offset.

 FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h
address.

Interrupts
An interrupt is the method of accessing the MPU by a peripheral device. An interrupt is used to cause a
temporary halt in the execution of a program. The MPU responds to the interrupt with an interrupt
service routine, which is a short program or subroutine that instructs the MPU on how to handle the
interrupt.

When the 8086 is executing a program, it can get interrupted because of one of the following.

1. Due to an interrupt getting activated. This is called as hardware interrupt.

2. Due to an exceptional happening during an instruction execution, such as division of a
number by zero. This is generally termed as exceptions or Traps.
3. Due to the execution of an Interrupt instruction like "INT 21H". This is called a Software
interrupt.

The action taken by the 8086 is similar for all the three cases, except for minor differences.

There are two basic types of interrupts, maskable and non-maskable. A non-maskable interrupt
requires an immediate response by the MPU. It is usually used for serious circumstances like power
failure. A maskable interrupt is an interrupt that the MPU can ignore depending upon some
predetermined condition defined by the status register. Interrupts are also prioritized to allow for the
case when more than one interrupts needs to be serviced at the same time.

Hardware interrupts of 8086:

In a microcomputer system whenever an I/O port wants to communicate with the microprocessor
urgently, it interrupts the microprocessor. In such a case, the microprocessor completes the instruction
it is presently executing. Then, it saves the address of the next instruction on the stack top. Then it
branches to an Interrupt Service Subroutine (ISS), to service the interrupting I/O port. An ISS is also
commonly called as an Interrupt Handler. After completing the ISS, the processor returns to the original
program, making use of the return address that was saved on the stack top.

In 8086 there are two interrupt pins. They are NMI and INTR. NMI stands for non maskable interrupt.
Whenever an external device activates this pin, the microprocessor will be interrupted. This signal
cannot be masked. NMI is a vectored

In 8086 there are two interrupt pins. They are NMI and INTR

 INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of
the POPF instruction. When an interrupt occurs, the processor stores FLAGS register into
stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and

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jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>.
Interrupt processing routine should return with the IRET instruction.

 NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt.
Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location
0008h. This interrupt has higher priority than the maskable interrupt.

Software interrupts can be caused by:

 INT instruction - breakpoint interrupt. This is a type 3 interrupt.

 INT <interrupt number> instruction - any one interrupt from available 256 interrupts.

 INTO instruction - interrupt on overflow

 Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU
processes this interrupt it clears TF flag before calling the interrupt processing routine.

 Processor exceptions: divide error (type 0), unused opcode (type 6) and escape opcode (type
7).

Software interrupt processing is the same as for the hardware interrupts.

I/O ports
65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.

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Instruction Set
Instruction set of Intel 8086 processor consists of the following instructions:

 Data moving instructions.

 Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.
 Logic - AND, OR, exclusive OR, shift/rotate and test.
 String manipulation - load, store, move, compare and scan for byte/word.
 Control transfer - conditional, unconditional, call subroutine and return from subroutine.
 Input/output instructions.
 Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes:

Implied - the data value/data address is implicitly associated with the instruction.

Register - references the data in a register or in a register pair.

Immediate - the data is provided in the instruction.

Direct - the instruction operand specifies the memory address where data is located.

Register indirect - instruction specifies a register containing an address, where data is located. This
addressing mode works with SI, DI, BX and BP registers.

Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the
resulting value is a pointer to location where data resides.

Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the
resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register
(SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base
register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data
resides.

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INTEL 8051 Microcontroller

Introduction:

There are a wide range of devices available in the 8051 family, differing in terms of memory type and
capacity, number of counter/timers, types of serial inter-face, number of input/output ports, clock rates,
frequency range, etc. However, there is a commonality among all devices in that they have been
developed from the ‘core’ 8051 device with modifications to produce the particular attributes of a different
family member. Each member of the 8051 microcontroller family has been designed with improved device
specifications in mind and to provide the customer with a device to suit particular user requirements.

The 80c51 can be considered as the core device, and functions such as I/O ports, timer/counters, serial
interfacing and interrupts will be discussed. Any variations that exist for a particular family member will be
dealt with in the relevant appendix that covers a particular device.

The 80c51 is available in three different package types and is basically a 40-pin device (some packages
have 44 pins but only 40 are internally connected) with the following architecture:

 4KB 8 ROM;

 128 8RAM;

 Four 8-bit I/O ports.

 full-duplex enhanced UART with framing error detection and automatic address recognition;

 three 16-bit counter/timers;

 a six-source four-priority level nested interrupt structure;

 On-chip oscillator.

Block diagram:

The arrangement for the 80c51 device is shown in the block diagram of Fig.1. Variations exist according
to the family member, i.e. the on-chip program memory could be ROM or EPROM and the memory size
could vary (the 0C52 has 8KB ROM while the 87C52 has 8KB EPROM). Also the on-chip data memory
size could vary (both the 80C52 and 87C52 devices have 256 bytes of RAM).

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Fig. 1: 8051 Block diagram

Architecture of 8051 Microcontroller:

The 80C51 architecture is shown in Figure 1. The basic architecture is the same for all members of the
8051 family although there are differences for devices, which may have more, or less, ports,
comparators, ADC circuits, etc. Block diagrams for other relevant devices can be seen in those
appendices that cover their specification. Reference has already been made in general terms to the
80C51 ports, timer/counters, internal RAM and ROM/EPROM (where applicable).

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Specific features include:

 8-bit CPU with registers A (accumulator) and B

 16-bit program counter (PC)

 16-bit data pointer register (DPTR)

 8-bit program status word register (PSW)

 8-bit stack pointer (SP).

It is clear from the above that the 80C51 has a collection of 8-bit and 16-bit registers and 8-bit memory
locations.

Memory organization:

INTERNAL RAM:

The 80C51 has 128 bytes of on-chip RAM plus a number of SFRs. Including the SFR space gives 256
addressable locations but the addressing modes for internal RAM can accommodate 384 bytes by
splitting the memory space into three blocks viz. the lower 128, the upper 128 and the SFR space. The
lower 128 bytes use address locations 00H to 7FH and these can be accessed using direct and indirect
addressing. The upper 128 bytes use address locations 80H to FFH and may be accessed using direct
addressing only; locations in this space with addresses ending with 0H or 8H are also bit addressable.
Some members of the 80C51 family have 256 bytes of on-chip RAM and the upper 128 bytes in this
case would be accessible only using the indirect addressing mode.

For the 80C51 device, the internal RAM of 128 bytes is broken down into:

 Four register banks 0 to 3, each of which contains eight registers R0 to R7. The 32 bytes
occupy addresses from 00H to 1FH. Each register can be addressed specifically when its bank
is selected or an address can identify a particular register regardless of the bank, i.e. R2 of
bank 2 can be specified if bank 2 is selected or the same location can be specified as address
12H. The register banks not selected can be used as general-purpose RAM. Bits 3 and 4 of the
PSW register determine which bank is selected when a program is running. Reset will cause
bank 0 to be selected.

 Sixteen bytes that are bit addressable in the address range 20H to 2FH giving 128 addressable
bits. The bits have individual addresses ranging from 00H to 07H for byte address 20H, to 78H
to 7FH for byte address 2FH. Thus a bit may be addressed directly, say bit 78H, which is bit 7
of byte address 2F.

 A general-purpose memory range from 30H to 7FH, which is addressable as bytes.

In addition there are SFRs (special function registers) in the address range 80H to FFH. This address
range actually gives 128 addresses but only 32 are defined for the 80C51; the number defined varies
according to device, being much larger for some devices and less for others. Details of the SFRs for the
devices referred to in the main body of the text can be found in Appendices D, E and F. For the 80C51
the SFRs of the internal RAM are described in more detail as follows:

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Accumulator (ACC):

This 8-bit register, usually referred to as register A, is the major register for data operations such as
addition, subtraction, etc. and for Boolean bit manipulation. The register is also used for data transfers
between the device and external memory, where applicable. The accumulator is both bit and byte
addressable with the byte address at E0H and the bit addresses from E0H to E7H.

B Register:

This 8-bit register is used for multiplication and division operations. For other instructions it can be
considered another ‘scratch pad register. The B register is both bit and byte addressable with byte
address at F0H and bit addresses from F0H to F7H.

Program status word (PSW):

This 8-bit register at address D0H contains program status information as shown below:

With the bit functions defined in Table 1 stated below

Stack pointer (SP):

This 8-bit register at address 81H is incremented before data is stored during PUSH and CALL
executions. The SP is initialized to RAM address 07H after a reset, which causes the stack to
commence at location 08H.

Data pointer (DP):

This 16-bit register is intended to contain the two bytes that make a 16-bit address, with the high byte
(DPH) at address 83H and the low byte (DPL) at address 82H. It may also be used as two independent
8-bit registers.

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Ports 0 to 3:

P0, P1, P2 and P3 are the 8-bit SFR latches of ports 0, 1, 2 and 3 respectively. The addresses are
80H, 90H, A0H and B0H respectively. Writing a ‘1’ to any bit of any of the port SFRs causes the
corresponding port output pin to go high; writing a ‘0’ causes the corresponding port output pin to go
low. When used as an input, the external state of any port pin will be held in the port SFR.

Serial data buffer (SBUF):

This 8-bit register at address 99H is used for serial data in both transmit and receive modes. Moving
data to SBUF loads the data ready for transmission while moving data from SBUF allows access to
received data.

Timer registers:

The 80C51 contains three 16-bit timer/counters. Timer 0 has a low byte TL0 at address 8AH and a high
byte TH0 at address 8CH while timer 1 has a low byte at address 8BH and a high byte at address 8DH.
Timer 2 has a low byte at address CCH and a high byte at address CDH. Timer 2 can operate as an
event timer or event counter. An extra SFR register, the T2CON register, at address C8H, controls this
timer while a timer 2 mode control register T2MOD is at address C9H.

Control registers:

Certain control registers are required to provide control and status bits for the serial ports,
timer/counters and the interrupt system. The 8-bit control registers are:

TCON at address 88H

TMOD at address 89H

SCON at address 98H

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IE at address A8H

IP at address B8H

Timing & Control Unit:

This unit drives all the necessary timing & control signals required for the internal operation of the
circuit. It also drives control signals required for controlling the external system bus.

Oscillator:

It generates the basic timing clock signal for the operation of the circuit using crystal oscillator.

Instruction Register:

It decodes the opcode of an instruction to be executed & gives information to the timing & control unit to
generate necessary signals for the execution of the instruction.

EPROM & Program address register:

These blocks provide an ON-chip EPROM & a mechanism to internally address it.

RAM & Ram address register:

These blocks provide internal 128 bytes of RAM & a mechanism to address it internally.

Arithmetic & Logic Unit (ALU):

ALU performs 8-bit arithmetic & logical operation over the operand held by the temporary registers
TMP1 & TMP2. Users cannot access these temporary registers.

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Pin-out diagram of 80c51:

The 80C51 microcontroller is available in a 40-pin dual-in-line (DIL) package; the arrangement is shown
in Fig.2. Other packages are available and although the device pin functions are the same regardless of
package configuration, pin-out numbers vary. The pin-out numbers referred to in the description that
follows are valid only for the DIL package.

Figure 2: 80C51 pin-out layout (courtesy Philips Semiconductors)

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Supply voltage (VCC and VSS):

The device operates from a single þ5V supply connected to pin 40 (Vcc) while pin 20 (VSS) is
grounded.

Input/output (I/O) ports:

32 of the pins are arranged as four 8-bit I/O ports P0–P3. Twenty-four of these pins are dual purpose
(26 on the 80C52/80C58) with each capable of operating as a control line or part of the data/address
bus in addition to the I/O functions.

Details are as follows:

 Port 0: This is a dual-purpose port occupying pins 32 to 39 of the device. The port is an open-
drain bidirectional I/O port with Schmitt trigger inputs. Pins that have 1s written to them float
and can be used as high-impedance inputs. The port may be used with external memory to
provide a multiplexed address and data bus. In this application internal pull-ups are used when
emitting 1s. The port also outputs the code bytes during EPROM programming. External pull-
ups are necessary during program verification.

 Port 1: This is a dedicated I/O port occupying pins 1 to 8 of the device. The pins are connected
via internal pull-ups and Schmitt trigger input. Pins that have 1s written to them are pulled high
by the internal pull-ups and can be used as inputs; as inputs, pins that are externally pulled low
will source current via the internal pull-ups. The port also receives the low-order address byte
during program memory verification. Pins P1.0 and P1.1 could also function as external inputs
for the third timer/counter i.e.:

(P1.0) T2 Timer/counter 2 external count input/clock-out

(P1.1) T2EX Timer/counter 2 reload/capture/direction control

 Port 2: This is a dual-purpose port occupying pins 21 to 28 of the device. The specification is
similar to that of port 1. The port may be used to provide the high-order byte of the address bus
for external program memory or external data memory that uses 16-bit addresses. When
accessing external data memory that uses 8-bit addresses, the port emits the contents of the
P2 register. Some port 2 pins receive the high-order address bits during EPROM programming
and verification.

 Port 3: This is a dual-purpose port occupying pins 10 to 17 of the device. The specification is
similar to that of port 1. These pins, in addition to the I/O role, serve the special features of the
80C51 family; the alternate functions are summarized below:

 P3.0 RxD serial data input port

 P3.1 TxD serial data output port

 P3.2 INT0 external interrupt 0

 P3.3 INT1 external interrupt 1

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 P3.4 T0 timer/counter 0 external input

 P3.5 T1 timer/counter 1 external input

 P3.6 WR external data memory writes strobe

 P3.7 RD external data memory read strobe.

Reset (pin 9):

The 80C51 is reset by holding this input high for a minimum of two machine cycles before returning it
low for normal running. An internal resistance connects to pin 20 (V SS) allowing a power-on reset using
an external capacitor connected to pin 40 (V CC). The device internal registers are loaded with selected
values prior to normal operation.

XTAL1 and XTAL2 (pins 19 and 18 respectively):

The 80C51 on-chip oscillator is driven, usually, from an external crystal. The XTAL1 input also provides
an input to the internal clock generator circuits. PSEN (program store enable) (pin 29). This pin
provides an output read strobe to external program memory. The output is active low during the fetch
stage of an instruction. The signal is not activated during a fetch from internal memory.

ALE/PROG (address latch enable/program pulse) (pin 30):

The ALE signal is an output pulse used to latch the low byte of an address during access to external
memory. The signal rate is 1/6 the oscillator frequency and can be used as a general-purpose
clock/timing pulse for the external circuitry. The pin also provides the program pulse input (PROG)
during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set ALE will
be active only during a MOV X instruction

EA/VPP (external access/programming voltage) (pin 31):

This pin is either tied high or low according to circuit requirements. If tied high the device will execute
programs from internal memory provided the address is not higher than the last address in the internal
ROM/OTP. When the EA pin is tied low, thus disabling the internal ROM, program code is accessed
from external ROM. For a ROMless device the EA pin must be tied low permanently and the program
code accessed from external ROM could be as much as 64KB. EPROM versions of the device also use
this pin for the supply voltage (V PP) necessary for programming the internal EPROM. If security bit 1 is
programmed, EA will be internally latched on reset.

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Instruction Set
Data transfer Instruction.
 Move byte between accumulator (an SFR) and resistor at a resistor bank.
 Move byte from an SFR/Internal RAM to another direct.
 Move indirect.
 Move immediate, mode immediate DPTR.
 MOVC and MOVX indirect.
 Exchange or Push or Pop direct.

Bit Manipulation:
o Set, Complement, AND or OR or Move the bit.

Logic Instructions:
o AND, XOR, OR operation instructions

Byte Manipulation:
o Clear, Complement, or swap and rotate instructions.

Arithmetic Instructions:
o 8-bit ADD, Subtract, Multiply and Divide instructions.
o Increment –Decrement Instruction.

Program flow control Instructions:

o Branch Instructions
o Conditional Jumps
o Decrement and Jumps conditional
o Compare and then conditional jump
o Subroutine Call Instructions
o Nop
o Delay

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Interrupt flow control Instructions

o Interrupt flow control-mask bits, priority bits.
o RETI

INTEL 8086 Program

#P1: A block of data transfer from one set of #P2: 8-bit BCD addition or decimal addition of
memory location 136D: 0300 to another set of two data stored in 0300H and 0301H location.
memory location 136D: 0400.

C:\> DEBUG C:\> DEBUG

--A 0100 --A 0100

136D: 0100 MOV SI , 0300 136D: 0100 MOV SI , 0300

136D: 0103 MOV DI , 0400 136D: 0103 MOV AL , [ SI ]

136D: 0106 MOV CL , [ SI ] 136D: 0105 MOV BL , [SI+1]

136D: 0108 INC SI 136D: 0108 MOV AH , 00

136D: 0109 MOV AL ,[SI] 136D: 010A ADD AL , BL

136D: 010B MOV [DI ] , AL 136D: 010C DAA

136D: 010D INC SI 136D: 010D JNC 0111

136D: 010E INC DI 136D: 010F INC AH

136D: 010F LOOP 0109 136D: 0111 INT3

136D: 0111 INT3

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#P3: To find Factorial of a given data stored in the #P4: To find the largest no. in a series of 8-bit
location 0300H. data.

C:\> DEBUG C:\> DEBUG

--A 0100 --A 0100

136D: 0100 MOV AL , 01 136D: 0100 MOV SI , 0300

136D: 0103 MOV BL , 01 136D: 0103 MOV CL , [SI]

136D: 0106 MOV SI , 0300 136D: 0105 MOV AL , 00

136D: 0108 MOV CL,[SI] 136D: 0107 INC SI

136D: 0109 MUL BL 136D: 0108 CMP AL , [SI]

136D: 010B INC BL 136D: 010A INB 010E

136D: 010D LOOP 0109 136D: 010C MOV AL , [SI]

136D: 010E INT3 136D: 010E LOOP 0107

136D: 0110 MOV [0350] , AL

136D: 0113 INT3

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#P5: To find the largest no. in a series of 8-bit #P6: To find the smallest no. in a series of 8-bit
data. data.

C:\> DEBUG C:\> DEBUG

--A 0100 --A 0100

136D: 0100 MOV SI , 0300 136D: 0100 MOV SI , 0300

136D: 0103 MOV CL , [SI] 136D: 0103 MOV CL , [SI]

136D: 0105 MOV AL , 00 136D: 0105 MOV AL , FF

136D: 0107 INC SI 136D: 0107 INC SI

136D: 0108 CMP AL , [SI] 136D: 0108 CMP AL , [SI]

136D: 010A INB 010E 136D: 010A JB 010E

136D: 010C MOV AL , [SI] 136D: 010C MOV AL , [SI]

136D: 010E LOOP 0107 136D: 010E LOOP 0107

136D: 0110 MOV [0350] , AL 136D: 0110 MOV [0350] , AL

136D: 0113 INT3 136D: 0113 INT3

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Intel 8051 Program

#P1: Program to add 5(five) nos. Stored from #P2: Program to add 1+2+3....10 and to store the result in
memory locations 0030H to 0034H and to store the the resistor R5.
result in the resistor R5.

ORG 0000H; ORG 0000H;

MOV A, #00H; MOV A, #00H;

MOV R0, #05H; MOV R2, #0AH;

MOV R1, #30H AGAIN: ADD A, R2;

AGAIN: ADD A, @R1; DJNZ R2, AGAIN;

INC R1; MOV R2, A;

DJNZ R0, AGAIN; END;

MOV R5, A;

END;

#P3: Program to add 03 by 10 times and to store #P4: Program to move a block of data (5 nos.) from the
the result in the resistor R5. location of starting address 0300H to another location of
starting address 0050H.

ORG 0000H; ORG 0000H;

MOV A, #00H; MOV A, #00H;

MOV R2, #10; MOV R2, #05H;

AGAIN: ADD A, #03H; MOV R0, #30H;

DJNZ R2, AGAIN; MOV R1, #50H;

MOV R1, A; AGAIN: MOV A, @R0;

END; MOV @R1, A;

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INC R0;

INC R1;

DJNZ R2, AGAIN;

END;

#P5: Program to find the smallest data in a series #06. Program to find the largest data in a series (5
(5nos.) starting from the location 0040H. The result is nos.) starting from the location 0040H. The result is in
in ACC. ACC.

ORG 0000H; ORG 0000H;

MOV R0, #40H; MOV R0, #40H;

MOV R2, #05H; MOV R2, #05H;

MOV A, @R0; MOV A, @R0;

LOOP1: INC R0; LOOP1: NC R0;

MOV 50H, @R0; MOV 50H, @R0;

CJNE A, 50H, NEXT; CJNE A, 50H, NEXT;

SJMP LOOP2; SJMP LOOP2;

NEXT: JC LOOP2; NEXT: JNC LOOP2;

MOV A, 50H; MOV A, 50H;

LOOP2: DJNZ R2, LOOP1; LOOP2: DJNZ R2, LOOP1;

END; END;

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