16-Channel High Performance Differential Output, 192 KHZ, 24-Bit Dac

16-Channel High Performance
Differential Output, 192 kHz, 24-Bit DAC

Data Sheet ADAU1966
FEATURES GENERAL DESCRIPTION
118 dB DAC dynamic range and SNR The ADAU1966 is a high performance, single-chip DAC that
−98 dB THD + N provides 16 digital-to-analog converters (DACs) with differen-
Differential voltage DAC output tial output using the Analog Devices, Inc., patented multibit
2.5 V digital, 5 V analog and 3.3 V or 5 V I/O supplies sigma-delta (Σ-Δ) architecture. An SPI/I2C port is included,
521 mW total (32.6 mW/channel) quiescent power allowing a microcontroller to adjust volume and many other
PLL generated or direct MCLK master clock parameters. The ADAU1966 operates from 2.5 V digital, 5 V
Low EMI design analog and 3.3 V or 5 V input/output supplies. A linear regulator
Linear regulator driver to generate digital supply is included to generate the digital supply voltage from the analog
Supports 24-bit and 32 kHz to 192 kHz sample rates supply voltage. The ADAU1966 is available in an 80-lead LQFP
Low propagation 192 kHz sample rate mode package.
Log volume control with autoramp function The ADAU1966 is designed for low EMI. This consideration is
Temperature sensor with digital readout ±3°C accuracy apparent in both the system and circuit design architectures.
SPI and I2C controllable for flexibility By using the on-board PLL to derive the internal master clock
Software-controllable clickless mute from an external LRCLK, the ADAU1966 can eliminate the
Software power-down need for a separate high frequency master clock and can be
Right-justified, left-justified, I2S, and TDM modes used with or without a bit clock. The DACs are designed using
Master and slave modes with up to 16-channel input/output the latest Analog Devices continuous time architectures to
80-lead LQFP package further minimize EMI. By using 2.5 V digital supplies, power
Qualified for automotive applications consumption is minimized, and the digital waveforms are a
APPLICATIONS smaller amplitude, further reducing emissions.
Automotive audio systems

Home theater systems
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM

DIGITAL AUDIO
INPUT
ADAU1966
SERIAL DATA PORT
DAC DAC
DAC DAC
SDATA SDATA
DAC IN IN DAC
DIGITAL DIGITAL
DIFFERENTIAL DAC FILTER CLOCKS FILTER DAC DIFFERENTIAL
ANALOG AND AND ANALOG
AUDIO VOLUME VOLUME AUDIO
OUTPUTS DAC DAC OUTPUTS
CONTROL TIMING MANAGEMENT CONTROL
DAC AND CONTROL DAC
(CLOCK AND PLL)
DAC DAC
DAC DAC
SPI/I2C
PRECISION CONTROL PORT INTERNAL
VOLTAGE TEMP
REFERENCE SENSOR
09434-001
CONTROL DATA
INPUT/OUTPUT
Figure 1.
Rev. E Document Feedback

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ADAU1966 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Block Power-Down and Thermal Sensor Control 1 Register27
Applications ....................................................................................... 1 Power-Down Control 2 Register .............................................. 28
General Description ......................................................................... 1 Power-Down Control 3 Register .............................................. 29
Functional Block Diagram .............................................................. 1 Thermal Sensor Temperature Readout Register .................... 30
Revision History ............................................................................... 3 DAC Control 0 Register ............................................................ 31
Specifications..................................................................................... 4 DAC Control 1 Register ............................................................ 32
Analog Performance Specifications ........................................... 4 DAC Control 2 Register ............................................................ 33
Crystal Oscillator Specifications................................................. 5 DAC Individual Channel Mutes 1 Register ............................ 34
Digital Input/Output Specifications........................................... 5 DAC Individual Channel Mutes 2 Register ............................ 35
Power Supply Specifications........................................................ 6 Master Volume Control Register.............................................. 36
Digital Filters ................................................................................. 6 DAC 1 Volume Control Register .............................................. 36
Timing Specifications .................................................................. 7 DAC 2 Volume Control Register .............................................. 37
Absolute Maximum Ratings............................................................ 9 DAC 3 Volume Control Register .............................................. 37
Thermal Resistance ...................................................................... 9 DAC 4 Volume Control Register .............................................. 38
ESD Caution .................................................................................. 9 DAC 5 Volume Control Register .............................................. 38
Pin Configuration and Function Descriptions ........................... 10 DAC 6 Volume Control Register .............................................. 39
Typical Performance Characteristics ........................................... 13 DAC 7 Volume Control Register .............................................. 39
Application Circuits ....................................................................... 14 DAC 8 Volume Control Register .............................................. 40
Theory of Operation ...................................................................... 15 DAC 9 Volume Control Register .............................................. 40
Digital-to-Analog Converters (DACs) .................................... 15 DAC 10 Volume Control Register............................................ 41
Clock Signals ............................................................................... 15 DAC 11 Volume Control Register............................................ 41
Power-Up and RST ..................................................................... 16 DAC 12 Volume Control Register............................................ 42
Standalone Mode ........................................................................ 17 DAC 13 Volume Control Register............................................ 42
I2C Control Port .......................................................................... 17 DAC 14 Volume Control Register............................................ 43
Serial Control Port: SPI Control Mode ................................... 19 DAC 15 Volume Control Register............................................ 43
Power Supply and Voltage Reference ....................................... 20 DAC 16 Volume Control Register............................................ 44
Serial Data Ports—Data Format ............................................... 20 Common Mode and Pad Strength Register ............................ 44
Time-Division Multiplexed (TDM) Modes ............................ 20 DAC Power Adjust 1 Register ................................................... 45
Temperature Sensor ................................................................... 20 DAC Power Adjust 2 Register ................................................... 46
Additional Modes ....................................................................... 22 DAC Power Adjust 3 Register ................................................... 47
Register Summary .......................................................................... 24 DAC Power Adjust 4 Register ................................................... 48
Register Details ............................................................................... 25 Outline Dimensions ....................................................................... 52
PLL and Clock Control 0 Register ........................................... 25 Ordering Guide .......................................................................... 52
PLL and Clock Control 1 Register ........................................... 26 Automotive Products ................................................................. 52
Rev. E | Page 2 of 52
Data Sheet ADAU1966
REVISION HISTORY
3/16—Rev. D to Rev. E 3/13—Rev. B to Rev. C
Changes to Table 4 ............................................................................ 5 Changes to Table 2 and Table 3 ....................................................... 5
Changes to Table 4 ............................................................................ 6
12/13—Rev. C to Rev. D Changes to I2C Control Port Section ............................................ 18
Changes to Features Section ............................................................ 1 Changes to Figure 13, Table 19, Table 20, Table 21, and
Changes to General Description ..................................................... 1 Table 22 ............................................................................................. 19
Changes to Specifications Section................................................... 4 Changes to Serial Control Port: SPI Control Mode Section ..... 20
Deleted Table 3 and Table 4; Renumbered Sequentially .............. 5
Changes to Table 5 ............................................................................ 6 8/12—Rev. A to Rev. B
Changes to Theory of Operation Section ....................................15 Change to Table 10 .......................................................................... 10
Changes to Table 11 ........................................................................15
Changes to Table 13 ........................................................................17 7/12—Rev. 0 to Rev. A
Changes to Serial Control Port: SPI Control Mode Section......19 Changed Output Resistance at Each Pin Parameter from 100 Ω
Added Figure 14, Figure 15, and Figure 16; Renumbered to 33 Ω ................................................................................................ 4
Sequentially ......................................................................................19 Changes to Figure 13 ...................................................................... 19
Moved, Changes to Figure 17 ........................................................20 Added Figure 14 .............................................................................. 20
Changes to Power Supply and Voltage Reference Section and Updated Outline Dimensions........................................................ 52
Serial Data Ports—Data Format Section ......................................20
Changes to Figure 18 ......................................................................21 9/11—Revision 0: Initial Version
Change to Address 0x01C, Table 23 .............................................24
Changes to Table 52, Common Mode and Pad Strength
Register .............................................................................................44
ADAU1966 Data Sheet
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word
width = 24 bits, load capacitance (digital output) = 20 pF, load current (digital output) = ±1 mA or 1.5 kΩ to ½ DVDD supply, input
voltage high = 2.0 V, input voltage low = 0.8 V, analog audio output resistive load = 3100 Ω per pin, unless otherwise noted.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 25°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 25°C, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range 20 Hz to 20 kHz, −60 dB input
No Filter (RMS) 105 115.5 dB
With A-Weighted Filter (RMS) 108 118 dB
Total Harmonic Distortion + Noise 0 dBFS −90 dB
Two channels running, −1 dBFS −98 dB
16 channels running, −1 dBFS −98 −85 dB
Full-Scale Differential Output Voltage 3.00 (±8.49) V rms (V p-p)
Gain Error −10 +10 %
Offset Error −25 −6 +25 mV
Gain Drift −30 +30 ppm/°C
Interchannel Isolation 100 dB
Interchannel Phase Deviation 0 Degrees
Volume Control Step 0.375 dB
Volume Control Range 95.25 dB
De-emphasis Gain Error ±0.6 dB
Output Resistance at Each Pin 33 Ω
REFERENCE VOLTAGES
Temperature Sensor Reference Voltage TS_REF pin 1.50 V
Common-Mode Reference Output CM pin 2.14 2.25 2.29 V
External Reference Voltage Source CM pin 2.25 V
TEMPERATURE SENSOR
Temperature Accuracy −3 +3 °C
Temperature Readout Range −60 +140 °C
Temperature Readout Step Size 1 °C
Temperature Sample Rate 0.25 6 Hz
REGULATOR
Input Supply Voltage VSUPPLY pin 3.0 5 5.5 V
Regulated Output Voltage VSENSE pin 2.26 2.50 2.59 V
1
Functionally guaranteed at −40°C to +125°C case temperature.
Data Sheet ADAU1966
Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 105°C, unless otherwise noted.
Table 2.
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range 20 Hz to 20 kHz, −60 dB input
No Filter (RMS) 109 113.5 dB
With A-Weighted Filter (RMS) 110.5 116 dB
Total Harmonic Distortion + Noise 0 dBFS −85 dB
Two channels running −1 dBFS −92.5 dB
Eight channels running −1 dBFS −92.5 −85 dB
Full-Scale Differential Output Voltage 3.00 (±8.49) V rms (V p-p)
Gain Error −10 +10 %
Offset Error −25 −6 +25 mV
Gain Drift −30 +30 ppm/°C
Interchannel Isolation 100 dB
Interchannel Phase Deviation 0 Degrees
Volume Control Step 0.375 dB
Volume Control Range 95.25 dB
De-emphasis Gain Error ±0.6 dB
Output Resistance at Each Pin 33 Ω
REFERENCE
Temperature Sensor Reference Voltage TS_REF pin 1.50 V
Common-Mode Reference Output CM pin 2.14 2.25 2.29 V
External Reference Voltage Source CM pin 2.25 V
REGULATOR
Input Supply Voltage VSUPPLY pin 3.0 5 5.5 V
Regulated Output Voltage VSENSE pin 2.25 2.50 2.55 V
1
Functionally guaranteed at −40°C to +125°C case temperature.
CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.
Parameter Min Typ Max Unit
Transconductance, TA = 25°C 6.4 7 to 10 14 mmhos
Transconductance, TA = 105°C 5.2 7.5 to 8.5 12 mmhos
DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TA < +105°C, IOVDD = 5.0 V and 3.3 V ± 10%.
Table 4.
High Level Input Voltage (VIH) 0.7 × IOVDD V
Low Level Input Voltage (VIL) IOVDD = 5.0 V 0.3 × IOVDD V
Input Leakage IIH at VIH = 3.3 V 10 μA
IIL at VIL = 0 V 10 μA
High Level Output Voltage (VOH) IOH = 1 mA 0.8 × IOVDD V
Low Level Output Voltage (VOL) IOL = 1 mA 0.1 × IOVDD V
Input Capacitance 5 pF
ADAU1966 Data Sheet
POWER SUPPLY SPECIFICATIONS
Table 5.
SUPPLIES
Voltage AVDD 4.5 5.0 5.5 V
DVDD 2.25 2.5 3.6 V
PLLVDD 2.25 2.5 3.6 V
IOVDD 3.0 5.0 5.5 V
VSUPPLY 3.0 5.0 5.5 V
Analog Current—AVDD = 5.0 V
Normal Operation 84 mA
Power-Down 1 μA
Digital Current—DVDD = 2.5 V
Normal Operation fS = 48 kHz to 192 kHz 30 mA
Power-Down No MCLK or I2S 4 μA
PLL Current—PLLVDD = 2.5 V
Normal Operation fS = 48 kHz to 192 kHz 5 mA
Power-Down 1 μA
IO Current—IOVDD = 3.3 V
Normal Operation 4 mA
Power-Down 1 μA
QUIESCENT DISSIPATION—DITHER INPUT
Operation MCLK = 256 × fS, 48 kHz
All Supplies AVDDx = 5.0 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V 521 mW
Analog Supply AVDDx = 5.0 V 420 mW
Digital Supply DVDD = 2.5 V 75 mW
PLL Supply PLLVDD= 2.5 V 13 mW
I/O Supply IOVDD = 3.3 V 13 mW
Power-Down, All Supplies 0 mW
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins 1 kHz, 200 mV p-p 85 dB
20 kHz, 200 mV p-p 85 dB
DIGITAL FILTERS
Table 6.
Parameter Mode Factor Min Typ Max Unit
DAC INTERPOLATION FILTER
Pass Band 48 kHz mode, typical at 48 kHz 0.4535 × fS 22 kHz
96 kHz mode, typical at 96 kHz 0.3646 × fS 35 kHz
Pass-Band Ripple 48 kHz mode, typical at 48 kHz ±0.01 dB
96 kHz mode, typical at 96 kHz ±0.05 dB
192 kHz mode, typical at 192 kHz ±0.1 dB
Transition Band 48 kHz mode, typical at 48 kHz 0.5 × fS 24 kHz
Stop Band 48 kHz mode, typical at 48 kHz 0.5465 × fS 26 kHz
Stop-Band Attenuation 48 kHz mode, typical at 48 kHz 68 dB
96 kHz mode, typical at 96 kHz 68 dB
192 kHz mode, typical at 192 kHz 68 dB
Data Sheet ADAU1966
Parameter Mode Factor Min Typ Max Unit
Propagation Delay 48 kHz mode, typical at 48 kHz 25/fS 521 μs
96 kHz mode, typical at 96 kHz 11/fS 115 μs
192 kHz mode, typical at 192 kHz 8/fS 42 μs
192 kHz low delay mode, typical at 192 kHz 2/fS 10 μs
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 2.5 V ± 10%.
Table 7.
Parameter Description Min Typ Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET
tMH MCLK duty cycle, DAC clock source = PLL clock at 40 60 %
256 × fS, 384 × fS, 512 × fS, and 768 × fS
tMH DAC clock source = direct MCLK at 512 × fS (bypass 40 60 %
on-chip PLL)
fMCLK MCLKI frequency, PLL mode 6.9 40.5 MHz
fMCLK Direct MCLK 512 × fS mode 27.1 MHz
fBCLK DBCLK frequency, PLL mode 27.0 MHz
tPDR Low 15 ns
tPDRR Recovery, reset to active output 300 ms
PLL
Lock Time MCLK input 10 ms
Lock Time DLRCLK input 50 ms
256 × fS VCO Clock, Output Duty Cycle, MCLKO Pin 40 60 %
SPI PORT See Figure 17
tCCH CCLK high 35 ns
tCCL CCLK low 35 ns
fCCLK CCLK frequency, fCCLK = 1/tCCP; only tCCP shown in Figure 17 10 MHz
tCDS CDATA setup, time to CCLK rising 10 ns
tCDH CDATA hold, time from CCLK rising 10 ns
tCLS CLATCH setup, time to CCLK rising 10 ns
tCLH CLATCH hold, time from CCLK falling 10 ns
tCLHIGH CLATCH high, not shown in Figure 17 10 ns
tCOE COUT enable from CCLK falling 30 ns
tCOD COUT delay from CCLK falling 30 ns
tCOH COUT hold from CCLK falling, not shown in Figure 17 30 ns
tCOTS COUT tristate from CCLK falling 30 ns
I2C See Figure 2 and Figure 13
fSCL SCL clock frequency 400 kHz
tSCLL SCL low 1.3 μs
tSCLH SCL high 0.6 μs
tSCS Setup time (start condition), relevant for repeated start 0.6 μs
condition
tSCH Hold time (start condition), first clock generated after 0.6 μs
this period
tSSH Setup time (stop condition) 0.6 μs
tDS Data setup time 100 ns
tSR SDA and SCL rise time 300 ns
tSF SDA and SCL fall time 300 ns
tBFT Bus-free time between stop and start 1.3 μs
ADAU1966 Data Sheet
Parameter Description Min Typ Max Unit
DAC SERIAL PORT See Figure 19
tDBH DBCLK high, slave mode 10 ns
tDBL DBCLK low, slave mode 10 ns
tDLS DLRCLK setup, time to DBCLK rising, slave mode 10 ns
tDLH DLRCLK hold from DBCLK rising, slave mode 5 ns
tDLS DLRCLK skew from DBCLK falling, master mode −8 +8 ns
tDDS DSDATAx setup to DBCLK rising 10 ns
tDDH DSDATAx hold from DBCLK rising 5 ns
tSCH tDS tSCH

SDA
tSR tSCLH
tBFT
09434-002
SCL
tSCLL tSF tSCS tSSH
Figure 2. I2C Timing Diagram
Data Sheet ADAU1966
ABSOLUTE MAXIMUM RATINGS

Table 8. THERMAL RESISTANCE
Parameter Rating θJA represents junction-to-ambient thermal resistance; θJC repre-
Analog (AVDD) −0.3 V to +5.5 V sents the junction-to-case thermal resistance. All characteristics
Input/Output (IOVDD) −0.3 V to +5.5 V are for a 4-layer board with a solid ground plane.
Digital (DVDD) −0.3 V to +3.6 V
Table 9. Thermal Resistance
PLL (PLLVDD) −0.3 V to +3.6 V
VSUPPLY −0.3 V to +6.0 V Package Type θJA θJC Unit
Input Current (Except Supply Pins) ±20 mA 80-Lead LQFP 42.3 10.0 °C/W
Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins) −0.3 V to IOVDD + 0.3 V ESD CAUTION
Operating Temperature Range (Case) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ADAU1966 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DAC12N
DAC11N
DAC10N
DAC12P
DAC11P
DAC10P
TS_REF
AGND3
AGND2
DAC9N
DAC8N
DAC7N
DAC6N
DAC5N
DAC9P
DAC8P
DAC7P
DAC6P
DAC5P
CM
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DAC_BIAS3 1 60 DAC_BIAS2
PIN 1
DAC_BIAS4 2 INDICATOR 59 DAC_BIAS1
AVDD3 3 58 AVDD2
DAC13P 4 57 DAC4N
DAC13N 5 56 DAC4P
DAC14P 6 55 DAC3N
DAC14N 7 54 DAC3P
DAC15P 8 53 DAC2N
DAC15N 9 52 DAC2P
DAC16P 10 ADAU1966A 51 DAC1N
TOP VIEW
DAC16N 11 (Not to Scale) 50 DAC1P
AVDD4 12 49 AVDD1
AGND4 13 48 AGND1
PLLGND 14 47 PU/RST
LF 15 46 SA_MODE
PLLVDD 16 45 SS/ADDR0/SA
MCLKI/XTALI 17 44 SCLK/SCL
XTALO 18 43 MISO/SDA/SA
MCLKO 19 42 MOSI/ADDR1/SA
DVDD 20 41 DVDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
IOVDD
IOVDD
VSUPPLY
VSENSE
VDRIVE
SA1
SA2
DGND
DGND
DLRCLK
DGND
DGND
DBCLK
DVDD
DSDATA6
DSDATA5
DSDATA4
DSDATA3
DSDATA2
DSDATA1
NOTES
11298-003
1. SEE THE STANDALONE MODE SECTION (TABLE 13 AND TABLE 14) FOR THE SA_MODE SETTINGS
FOR PIN 31, PIN 32, PIN 42, PIN 43, AND PIN 45.
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions

Pin No. Type1 Mnemonic Description
1 I DAC_BIAS3 DAC Bias 3. AC couple with 470 nF to AGND3.
2 I DAC_BIAS4 DAC Bias 4. AC couple with 470 nF to AVDD3.
3 PWR AVDD3 Analog Power.
4 O DAC13P DAC13 Positive Output.
5 O DAC13N DAC13 Negative Output.
13 GND AGND4 Analog Ground.
14 GND PLLGND PLL Ground.
15 O LF PLL Loop Filter, Reference to PLLVDD.
16 PWR PLLVDD Apply 2.5 V to Power PLL.
17 I MCLKI/XTALI Master Clock Input, Input to Crystal Inverter.
18 O XTALO Output from Crystal Inverter.
19 O MCLKO Master Clock Output.
Data Sheet ADAU1966
20, 29, 41 PWR DVDD Digital Power, 2.5 V.
21, 26, 30, 40 GND DGND Digital Ground.
22, 39 PWR IOVDD Power for Digital Input and Output Pins, 3.3 V to 5 V.
23 I VSENSE 2.5 V Output of Regulator, Collector of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
24 O VDRIVE Drive for Base of Pass Transistor.
25 I VSUPPLY 5 V Input to Voltage Regulator, Emitter of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
27 I/O DBCLK Bit Clock for DACs.
28 I/O DLRCLK Frame Clock for DACs.
31 I DSDATA8/SA DAC15 and DAC 16 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 13, and Table 14).
32 I DSDATA7/SA DAC13 and DAC 14 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 13, and Table 14).
33 I DSDATA6 DAC11 and DAC 12 Serial Data Input.
42 I CDATA/ADDR1/SA Control Data Input (SPI)/Address 1 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 13).
43 I/O COUT/SDA/SA Control Data Output (SPI)/Control Data Input (I2C)/SA_MODE State (see the
Standalone Mode section and Table 13).
44 I CCLK/SCL/SA Control Clock Input (SPI)/Control Clock Input (I2C)/SA_MODE State (see the Standalone
Mode section and Table 13).
45 I CLATCH/ADDR0/SA Control Chip Select (SPI) (Low Active)/Address 0 (I2C)/SA_MODE State (see the
Standalone Mode section and Table 13).
46 I SA_MODE Standalone Mode. This pin allows mode control of ADAU1966 using Pin 42 to Pin 45,
Pin 31, and Pin 32 (high active, see Table 13 and Table 14).
47 I PU/RST Power-Up/Reset (Low Active).
59 I DAC_BIAS1 DAC Bias 1. AC couple with 470 nF to AVDD2.
60 I DAC_BIAS2 DAC Bias 2. AC couple with 470 nF to AGND2.
62 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 10 μF in parallel
with 100 nF to AGND2. This reference can be shut off in the PLL_CLK_CTRL1 register
and the pin can be driven with an outside voltage source.
63 O TS_REF Voltage Reference Filter Capacitor Connection. Bypass with 10 μF in parallel with
100 nF to AGND2.
ADAU1966 Data Sheet
1
I = input, O = output, I/O = input/output, PWR = power, GND = ground.
Data Sheet ADAU1966
TYPICAL PERFORMANCE CHARACTERISTICS

0.05 0.20
0.04
0.15
0.03
0.10
0.02
MAGNITUDE (dB)
MAGNITUDE (dB)
0.05
0.01
0 0
–0.01
–0.05
–0.02
–0.10
–0.03
–0.15
–0.04
–0.05 –0.20
09434-004
09434-006
0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
FREQUENCY (FACTORED TO fS) FREQUENCY (FACTORED TO fS)
Figure 4. DAC Pass-Band Filter Response, 48 kHz Figure 6. DAC Pass-Band Filter Response, 96 kHz
0 0
–10 –10
–20 –20
–30 –30
MAGNITUDE (dB)
MAGNITUDE (dB)
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
09434-005
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
09434-007
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FREQUENCY (FACTORED TO fS) FREQUENCY (FACTORED TO fS)
Figure 5. DAC Stop-Band Filter Response, 48 kHz Figure 7. DAC Stop-Band Filter Response, 96 kHz
ADAU1966 Data Sheet
APPLICATION CIRCUITS
Typical application circuits are shown in Figure 8 to Figure 11. Recommended loop filters for DLRCLK and MCLKI/XTALI modes of the
PLL reference are shown in Figure 8. Output filters for the DAC outputs are shown in Figure 9 and Figure 10, and an external regulator
circuit is shown in Figure 11.
DLRCLK MCLKI/XTALI
LF LF
39nF 5.6nF
2.2nF 390pF
3.32kΩ 562Ω
09434-008
PLLVDD PLLVDD
Figure 8. Recommended Loop Filters for DLRCLK or MCLKI/XTALI PLL Reference Modes
10µF
237Ω +
DACP OUTP
2.7nF
10µF
237Ω +
DACN OUTN
49.9kΩ 49.9kΩ
09434-009
Figure 9. Typical DAC Output Passive Filter Circuit (Differential)
1.1nF
AD8672ARZ
1.50kΩ 1.54kΩ 5
DAC1P 100Ω 4.7µF
7 + OUTPUT1P
6
+12V DC 422Ω
2.49kΩ
100kΩ
+ +
0.1µF 4.7µF 1nF 4.7µF
8
V+
V–
4 + +
0.1µF 4.7µF 1nF 4.7µF
100kΩ
2.49kΩ
–12V DC 2 422Ω
4.7µF
1 100Ω
+ OUTPUT1N
1.50kΩ 1.54kΩ 3
DAC1N
AD8672ARZ
09434-010
1.1nF
Figure 10. Typical DAC Output Active Filter Circuit (Differential)
100nF 10µF
+
VSUPPLY 5V
1kΩ E
B
VDRIVE FZT953
C
VSENSE 2.5V
+
100nF 10µF
09434-011
Figure 11. Recommended 2.5 V Regulator Circuit
Data Sheet ADAU1966
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTERS (DACS) The ADAU1966 offers control over the analog performance
The 16 ADAU1966 digital-to-analog converter (DAC) channels of the DACs; it is possible to program the registers to reduce
are differential for improved noise and distortion performance the power consumption with the trade-off of lower SNR and
and are voltage output for simplified connection. The DACs THD + N. The reduced power consumption is the result of
include on-chip digital interpolation filters with 68 dB stop-band changing the internal bias current to the analog output
attenuation and linear phase response, operating at an over- amplifiers.
sampling ratio of 256× (48 kHz range), 128× (96 kHz range), or Register DAC_POWER1 to Register DAC_POWER4 present
64× (192 kHz range). Each channel has its own independently four basic settings for the DAC power vs. performance in each
programmable attenuator, adjustable in 255 steps in increments of the 16 channels: best performance, good performance, low
of 0.375 dB. Digital inputs are supplied through eight serial data power, and lowest power. Alternatively, in Register PLL_CLK_
input pins (two channels on each pin), a common frame clock CTRL1[7:6], the LOPWR_MODE bits offer global control over
(DLRCLK), and a bit clock (DBCLK). Alternatively, any one of the the power and performance for all 16 channels. The default
TDM modes can be used to access up to 16 channels on a single setting is b00. This setting allows the channels to be controlled
TDM data line. individually using the DAC_POWERx registers. Setting b10
The ADAU1966 has a low propagation delay mode; this mode and Setting b11 select the low power and lowest power settings.
is an option for an fS of 192 kHz and is enabled in Register DAC_ The data presented in Table 11 shows the result of setting all
CTRL0[2:1]. By setting these bits to b11, the propagation delay 16 channels to each of the four settings. The SNR and THD + N
is reduced by the amount shown in Table 6. The shorter delay is specifications are shown in relation to the measured perfor-
achieved by reducing the amount of digital filtering; the negative mance of a device at the best performance setting.
impact of selecting this mode is reduced audio frequency response The voltage at CM, the common-mode reference pin, can be
and increased out-of-band energy. used to bias the external op amps that buffer the output signals
When AVDD is supplied with 5 V, each analog output pin has a (see the Power Supply and Voltage Reference section).
nominal common-mode (CM) dc level of 2.25 V and swings CLOCK SIGNALS
±2.12 V above and below the 2.25 V for a for a 1.5 V rms signal Upon powering the ADAU1966 and asserting the PU/RST pin
on each pin. Differentially, the signal is 3 V rms, 8.48 V p-p,
high, the device starts in either standalone mode (SA_MODE)
from a 0 dBFS digital input signal.
or program mode, depending on the state of SA_MODE (Pin 46).
The differential analog outputs require only a single-order The clock functionality of SA_MODE is described in the
passive differential RC filter to provide the specified DNR Standalone Mode section. In program mode, the default for the
performance; see Figure 9 for an example filter. The outputs can ADAU1966 is for the MCLKO pin to feed a buffered output of
easily drive differential inputs on a separate PCB through the MCLKI signal. The default for the DLRCLK and DBCLK
cabling as well as differential inputs on the same PCB. ports is slave mode; the DAC must be driven with a coherent set
If more signal level is required or if a more robust filter is needed, a of MCLK, LRCLK, and BCLK signals to function.
single op amp gain stage designed as a second-order, low-pass The MCLKO pin can be programmed to provide different clock
Bessel filter can be used to remove the high frequency out-of- signals using Register Bits PLL_CLK_CTRL1[5:4]. The default,
band noise present on each pin of the differential outputs. The b10, provides a buffered copy of the clock signal that is driving
choice of components and design of this circuit is critical to yield the MCLKI pin. Two modes, b00 and b01, provide low jitter
the full DNR of the DACs (see the recommended passive and clock signals. The b00 setting yields a clock rate between 4 MHz
active circuits in Figure 9 and Figure 10). This filter can be built and 6 MHz, and b01 yields a clock rate between 8 MHz and
into an active difference amplifier to provide a single-ended output 12 MHz. Both of these clock frequencies are scaled as ratios of
with gain, if necessary. Note that the use of op amps with low MCLK automatically inside the ADAU1966. As an example, an
slew rate or low bandwidth can cause high frequency noise and MCLK of 8.192 MHz and a setting of b00 yield an MCLKO of
tones to fold down into the audio band; exercise care when (8.192/2) = 4.096 MHz. Alternatively, an MCLK of 36.864 MHz
selecting these components. and a setting of b01 yield an MCLKO frequency of (36.864/3) =
12.288 MHz. The setting b11 shuts off the MCLKO pin.
Table 11. DAC Power vs. Performance

Register Setting Best Performance Good Performance Low Power Lowest Power
Total AVDD Current 84 mA 75 mA 66 mA 56 mA
SNR Reference −0.2 dB −1.5 dB −14.2 dB
THD + N (−1 dBFS signal) Reference −1.8 dB −3.0 dB −5.8 dB
ADAU1966 Data Sheet
After the PU/RST pin has been asserted high, the PLL_CLK_ bit in the DAC_CTRL1 register. With the BCLK_GEN bit set to
CTRLx registers (Register 0x00 and Register 0x01) can be b1 (internal) and the SAI_MS bit set to b0 (slave), the ADAU1966
programmed. The on-chip phase-locked loop (PLL) can be generate its own DBCLK; this works with the PLL input set to
selected to use the clock appearing at the MCLKI/XTALI pin at either MCLKI/XTALI or DLRCLK. DLRCLK is the only required
a frequency of 256, 384, 512, or 768 times the sample rate (fS), clock in DLRCLK PLL mode.
referenced to the 48 kHz mode from the master clock select POWER-UP AND RST
(MCS) setting, as described in Table 12. In 96 kHz mode, the
master clock frequency stays at the same absolute frequency; Power sequencing for the ADAU1966 starts with AVDD and
therefore, the actual multiplication rate is divided by 2. In IOVDD, followed by DVDD. It is very important that AVDD be
192 kHz mode, the actual multiplication rate is divided by 4. settled at a regulated voltage and that IOVDD be within 10% of
For example, if the ADAU1966 is programmed in 256 × fS mode, regulated voltage before applying DVDD. When using the
the frequency of the master clock input is 256 × 48 kHz = ADAU1966 internal regulator, this timing occurs by default.
12.288 MHz. If the ADAU1966 is then switched to 96 kHz To guarantee proper startup, the PU/RST pin must be pulled
operation (by writing to DAC_CTRL0 [2:1]), the frequency of low by an external resistor and then driven high after the power
the master clock remains at 12.288 MHz, which is 128 × fS in this supplies stabilize. The PU/RST can also be pulled high using a
example. In 192 kHz mode, MCS becomes 64 × fS. simple RC network.
The internal clock for the digital core varies by mode: 512 × fS Driving the PU/RST pin low puts the device into a very low power
(48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz state (<3 μA). All functionality of the ADAU1966 is disabled until
mode). By default, the on-board PLL generates this internal the PU/RST pin is asserted high. Once this pin is asserted high,
master clock from an external clock. the ADAU1966 requires 300 ms to stabilize. The MMUTE bit in
The PLL must be powered and stable before the ADAU1966 is the DAC_CTRL0 register must be toggled for operation.
used as a source for quality audio. The PLL is enabled by reset The PUP bit in the PLL_CLK_CTRL0 register can be used to
and does not require writing to the I2C or SPI port for normal power down the ADAU1966. Engaging the master power-down
operation. puts the ADAU1966 in an idle state while maintaining the set-
With the PLL enabled, the performance of the ADAU1966 is not tings of all registers. Additionally, the power-down bits in the
affected by jitter as high as a 300 ps rms time interval error PDN_THRMSENS_CTRL1 register (TS_PDN, PLL_PDN, and
(TIE). If the internal PLL is not used, it is best to use an independ- VREG_PDN) can be used to power down individual sections of
ent crystal oscillator to generate the master clock. the ADAU1966.
If the ADAU1966 is to be used in direct MCLK mode, the PLL can The SOFT_RST bit in the PLL_CLK_CTRL0 register sets all of
be powered down in the PDN_THRMSENS_CTRL_1 register. the control registers to their default settings while maintaining
For direct MCLK mode, a 512 × fS (referenced to 48 kHz mode) the internal clocks in default mode. The SOFT_RST bit does
master clock must be used as MCLK, and the CLK_SEL bit in not power down the analog outputs; toggling this bit does not
the PLL_CLK_CTRL1 register must be set to b1. cause audible popping sounds at the differential analog outputs.
The ADAU1966 PLL can also be programmed to run from an Proper startup of the ADAU1966 proceeds as follows:
external LRCLK. When the PLLIN bits in the PLL_CLK_CTRL0 1. Apply power to the ADAU1966 as described previously.
register are set to 01 and the appropriate loop filter is connected
2. Assert the PU/RST pin high after power supplies have
to the LF pin (see Figure 8), the ADAU1966 PLL generates all
stabilized.
of the necessary internal clocks for operation with no external
3. Set the PUP bit to b1.
MCLK. This mode reduces the number of high frequency
4. Program all necessary registers for the desired settings.
signals in the design, reducing EMI emissions.
5. Set the MMUTE bit to b0 to unmute all channels.
It is possible to further reduce EMI emissions of the circuit by
using the internal DBCLK generation setting of the BCLK_GEN
Data Sheet ADAU1966
Table 12. MCS and fS Modes
Master Clock Select (MCS), PLL_CLK_CTRL0[2:1]
Sample Rate Select (FS) Setting 0, b00 Setting 1, b01 Setting 2, b10 Setting 3, b11
DAC_CTRL0[2:1] Ratio MCLK (MHz) Ratio MCLK Ratio MCLK Ratio MCLK
32 kHz, b00 256 × fS 8.192 384 × fS 12.288 512 × fS 16.384 768 × fS 24.576
44.1 kHz, b00 256 × fS 11.2896 384 × fS 16.9344 512 × fS 22.5792 768 × fS 33.8688
48 kHz, b00 256 × fS 12.288 384 × fS 18.432 512 × fS 24.576 768 × fS 36.864
64 kHz, b01 128 × fS 8.192 192 × fS 12.288 256 × fS 16.384 384 × fS 24.576
88.2 kHz, b01 128 × fS 11.2896 192 × fS 16.9344 256 × fS 22.5792 384 × fS 33.8688
96 kHz, b01 128 × fS 12.288 192 × fS 18.432 256 × fS 24.576 384 × fS 36.864
128 kHz, b10 or b11 64 × fS 8.192 96 × fS 12.288 128 × fS 16.384 192 × fS 24.576
176.4 kHz, b10 or b11 64 × fS 11.2896 96 × fS 16.9344 128 × fS 22.5792 192 × fS 33.8688
192 kHz, b10 or b11 64 × fS 12.288 96 × fS 18.432 128 × fS 24.576 192 × fS 36.864
STANDALONE MODE either to acknowledge the master (ACK) or to send data during
2
The ADAU1966 can operate without a typical I C or SPI a read operation. The SDA pin for the I2C port is an open-drain
connection to a microcontroller. This standalone mode is collector and requires a 2 kΩ pull-up resistor. A write or read
made available by setting the SA_MODE (Pin 46) to high access occurs when the SDA line is pulled low while the SCL
(IOVDD). All registers are set to default except the options line is high, indicated by a start in Figure 12 and Figure 13. SDA
shown in Table 13. is only allowed to change when SCL is low except when a start or
stop condition occurs, as shown in Figure 12 and Figure 13. The
Table 13. SA_MODE Settings first eight bits of the data-word consist of the device address and
Pin No. Setting Function the R/W bit. The device address consists of an internal built-in
42 0 Master mode serial audio interface (SAI) address (0x04) and two address pins, ADDR1 and ADDR0. The
1 Slave mode SAI two address bits allow four ADAU1966 devices to be used in a
43 0 MCLK = 256 × fS, PLL on system. Initiating a write operation to the ADAU1966 involves
1 MCLK = 384 × fS, PLL on sending a start condition and then sending the device address
44 0 Must be set to 0 with the R/W bit set low. The ADAU1966 responds by issuing
45 0 I2S SAI format an acknowledge to indicate that it has been addressed. The user
1 TDM modes, determined by Pin 31 and Pin 32 then sends a second frame telling the ADAU1966 which register
is required to be written. Another acknowledge is issued by the
When both SA_MODE and Pin 45 are set high, TDM mode is
ADAU1966. Finally, the user can send another frame with the
selected. Table 14 shows the available TDM modes; these modes
eight data bits required to be written to the register. A third
are set by connecting Pin 31 (DSDATA8) and Pin 32 (DSDATA7)
acknowledge is issued by the ADAU1966 after which the user
to GND or IOVDD.
can send a stop condition to complete the data transfer.
Table 14. TDM Modes A read operation requires that the user first write to the
Pin No. Setting Function ADAU1966 to point to the correct register and then read the
32:31 00 TDM4—DLRCLK pulse data. This is achieved by sending a start condition followed by
01 TDM8—DLRCLK pulse the device address frame, with the R/W bit low, and then the
10 TDM16—DLRCLK pulse register address frame. Following the acknowledge from the
11 TDM8—DLRCLK 50% duty cycle ADAU1966, the user must issue a repeated start condition. The
When the ADAU1966 is powered up in SA_MODE and the next frame is the device address with the R/W bit set high. On
PU/RST pin is asserted high, the MCLKO pin provides a buff- the next frame, the ADAU1966 outputs the register data on the
ered version of the MCLKI pin, whether the source is a crystal SDA line. A stop condition completes the read operation.
or an active oscillator.
Table 15. I2C Addresses
2
I C CONTROL PORT ADDR1 ADDR0 Slave Address
2
The ADAU1966 has an I C-compatible control port that permits 0 0 0x04
programming and reading back of the internal control registers for 0 1 0x24
the DACs and clock system. The I2C interface of the ADAU1966 is 1 0 0x44
a 2-wire interface consisting of a clock line, SCL, and a data line, 1 1 0x64
SDA. SDA is bidirectional, and the ADAU1966 drives SDA
ADAU1966 Data Sheet
SCL
SDA AD1 AD0 0 0 1 0 0 R/W 0 0 0 0 0 1 1 0
START BY ACK. BY ACK. BY

MASTER (S) ADAU1966 (AS) ADAU1966 (AS)
FRAME 1 FRAME 2
CHIP ADDRESS BYTE REGISTER ADDRESS BYTE
SCL
(CONTINUED)
SDA D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY STOP BY
09434-012
ADAU1966 (AS) MASTER (P)
FRAME 3
DATA BYTE TO ADAU1966
Figure 12. I2C Write Format
SCL
SDA AD1 AD0 0 0 1 0 0 R/W 0 0 0 0 0 1 1 0
START BY ACK. BY ACK. BY

MASTER (S) ADAU1966 (AS) ADAU1966 (AS)
FRAME 1 FRAME 2
CHIP ADDRESS BYTE REGISTER ADDRESS BYTE
SCL
(CONTINUED)
SDA AD1 AD0 0 0 1 0 0 R/W D7 D6 D5 D4 D3 D2 D1 D0

(CONTINUED)
REPEATED START ACK. BY ACK. BY STOP BY
09434-013
BY MASTER (S) ADAU1966 (AS) MASTER (AM) MASTER (P)
FRAME 3 FRAME 4
CHIP ADDRESS BYTE REGISTER DATA
Figure 13. I2C Read Format
Table 16. I2C Abbreviations

Abbreviation Condition
S Start bit
P Stop bit
AM Acknowledge by master
AS Acknowledge by slave
Table 17. Single Word I2C Write

S Chip Address, R/W = 0 AS Register Address AS Data-Word AS P
Table 18. Burst Mode I2C Write

S Chip Address, R/W = 0 AS Register Address AS Data-Word 1 AS Data-Word 2 AS Data-Word N AS P
Table 19. Single Word I2C Read

S Chip Address, R/W = 0 AS Register Address AS S Chip Address, R/W = 1 AS Data-Word AM P
Table 20. Burst Mode I2C Read

S Chip Address, AS Register AS S Chip Address, AS Data- AM Data- AM Data- AM P
R/W = 0 Address R/W = 1 Word 1 Word 2 Word N
Data Sheet ADAU1966
SERIAL CONTROL PORT: SPI CONTROL MODE Table 21. SPI Address and R/W Byte Format
The ADAU1966 has an SPI control port that permits program- Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ming and readback of the internal control registers for the 0 0 0 0 1 1 0 R/W
DACs and clock system. A standalone mode is also available for When reading data from the ADAU1966, the COUT pin is
operation without serial control; it is configured at reset using the tristated until the third byte, at which point it drives the data
SA_MODE pin. See the Standalone Mode section for details out (see Figure 16). The COUT pin is tristated at all other times,
about SA_MODE. allowing the pin to be bussed with other devices, see Figure 17
By default, the ADAU1966 is in I2C mode; however, SPI control for the timing requirements.
mode can be entered by pulling CLATCH low three times. To Chip Address R/W
enter SPI control mode, perform three dummy writes to the SPI
The LSB of the first byte of a SPI transaction is an R/W bit. This
port (the ADAU1966 does not acknowledge these three writes).
Beginning with the fourth SPI write, data can be written to or bit determines whether the communication is a read (Logic
read from the IC. The ADAU1966 can exit SPI control mode Level 1) or a write (Logic Level 0); see Table 21 for this format.
only by a full reset initiated by power cycling the device. SPI Burst Read/Write
The SPI control port of the ADAU1966 is a 4-wire serial control The SPI port is capable of performing burst reads or writes.
port. The format is a 24-bit wide data-word. The serial bit clock This is accomplished by sending the chip address byte with the
and latch can be completely asynchronous to the sample rate of R/W bit, followed by the first register address that needs to be
the DACs. Table 21 shows the format of the SPI address byte. read or written to. Then, as long as the CLATCH pin is held
The first byte is the global address with a read/write bit. For the low, registers can be sequentially read or written by continuing
ADAU1966, the address is Address 0x06, shifted left one bit due to send out clock pulses into the CCLK pin. A very efficient
to the R/W bit. The second byte is the ADAU1966 register procedure to initialize the ADAU1966 is accomplished by
address, and the third byte is the data, as shown in Figure 15 1. Sending out the address byte with the R/W bit low (write).
and Figure 16.
2. Sending out the address of the first register.
3. Sending out all the register byte values.
4. Toggling the CLATCH pin.
5. Performing a burst read to verify the register writes.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
CLATCH
CCLK
09434-114
CDATA
Figure 14. SPI Mode Initial Sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CLATCH
CCLK
09434-115
DEVICE ADDRESS (7 BITS) R/W

REGISTER ADDRESS BYTE DATA BYTE
CDATA
Figure 15. SPI Write to ADAU1966 Clocking
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CCLK
CLATCH
DEVICE ADDRESS (7 BITS)

REGISTER ADDRESS BYTE DATA BYTE
CDATA
R/W
09434-116
COUT DATA BYTE FROM ADAU1966
Figure 16. SPI Read from the ADAU1966 Clocking
ADAU1966 Data Sheet
tCLS
tCLH
tCCH tCCL
tCCP
CLATCH
tCOTS
CCLK
tCDS tCDH
CDATA D23 D22 D9 D8 D0
COUT
tCOE D9 D8 D0
09434-117
tCOD
Figure 17. Format of the SPI Signal
POWER SUPPLY AND VOLTAGE REFERENCE SERIAL DATA PORTS—DATA FORMAT

The ADAU1966 is designed for 5 V analog and 2.5 V digital The 16 DAC channels use a common serial bit clock (DBCLK)
supplies. To minimize noise pickup, bypass the power supply and a common left-right framing clock (DLRCLK) in the serial
pins with 100 nF ceramic chip capacitors placed as close to the data port. The clock signals are all synchronous with the sample
pins as possible. Also, provide a bulk aluminum electrolytic rate. The normal stereo serial modes are shown in Figure 18.
capacitor of at least 22 μF for each rail on the same PC board as The DAC serial data mode defaults to I2S (1 BCLK delay) upon
the codec. It is important that the analog supply be as clean as power-up and reset. The ports can also be programmed for left-
possible. justified and right-justified (24-bit and 16-bit) operation using
The ADAU1966 includes a 2.5 V regulator driver that requires DAC_CTRL0[7:6]. Stereo and TDM modes can be selected using
only an external pass transistor and bypass capacitors to make a DAC_CTRL0[5:3]. The polarity of the DLRCLK pin is pro-
2.5 V regulator from a 5 V supply. The VSUPPLY and VSENSE grammable according to the DAC_CTRL1[5] bit, allowing
pins must be decoupled with no more than 10 μF, in parallel for easy channel swapping.
with 100 nF high frequency bypassing. If the regulator driver is The DBCLK pin can latch on the rising or falling edge of the
not used, connect VSUPPLY and VDRIVE to GND and leave clock signal. DAC_CTRL1[1] selects the active edge.
VSENSE unconnected.
The serial ports are programmable as the clock masters according
All digital inputs are compatible with TTL and CMOS levels. to the DAC_CTRL1[0] bit. By default, the serial port is in slave
All outputs are driven from the 3.3 V or 5 V IOVDD supply and mode.
are compatible with TTL and 3.3 V CMOS levels.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The temperature sensor internal voltage reference (VTS_REF) is
brought out on the TS_REF pin and must be bypassed as close The ADAU1966 serial ports also have several different TDM
as possible to the chip with a parallel combination of 10 μF and serial data modes. The ADAU1966 can support a single data line
100 nF. TDM16, a dual data line (TDM8), a quad data line (TDM4), or
eight data lines (TDM2). The DLRCLK can be operated in both
The internal band gap reference can be disabled in the single-cycle pulse mode and a 50% duty cycle mode. Both
PLL_CLK_CTRL1 register by setting VREF_EN to 0; the CM 16 DBCLKs or 32 DBCLKs per channel are selectable for
pin can be then be driven from an external source. This can be each mode.
used to scale the DAC output to the clipping level of a power
amplifier based on its power supply voltage. The I/O pins of the serial ports are defined according to the
serial mode that is selected. For a detailed description of the
The CM pin is the internal common-mode reference. It must function of each pin in TDM and stereo modes, see Table 22.
be bypassed as close as possible to the chip, with a parallel
combination of 10 μF and 100 nF. This voltage can be used to TEMPERATURE SENSOR
bias external op amps to the common-mode voltage of the analog The ADAU1966 has an on-board temperature sensor that allows
input and output signal pins. It is recommended that the CM the user to read the temperature of the silicon inside the device.
pin be isolated from the external circuitry by using a high quality The temperature sensor readout has a range of −60°C to +140°C
buffer to provide a quiet, low impedance source for the external in 1°C steps. The PDN_THRMSENS_CTRL_1 register controls
circuitry. Use of a quiet op amp is critical, because any noise the settings of the sensor. The temperature sensor is powered on
added to the reference voltage is injected into the signal path. by default and can be shut off by setting the TS_PDN[2] bit to
b1 in PDN_THRMSENS_CTRL_1. The temperature sensor can
be run in either continuous operation or one-shot mode. The
temperature sensor conversion mode is modified using Bit 5,
THRM_MODE; the default is THRM_MODE = 1, one-shot
Data Sheet ADAU1966
mode. In one-shot mode, writing a 0 followed by writing a 1 to Once a temperature conversion is placed in the
Bit 4, THRM_GO, results in a single reset and temperature THRM_TEMP_STAT register, the data can be translated into
conversion, placing the resulting temperature data in the degrees Celsius (°C) using the following steps:
THRM_TEMP_STAT register. In continuous operation mode, 1. Convert the binary or hexadecimal data read from
the data conversion takes place at a rate set by Bits[7:6], THRM_ THRM_TEMP_STAT into decimal form.
RATE, with a range of 0.5 sec to 4 sec between samples. Faster 2. Subtract 60 from the converted THRM_TEMP_STAT data;
rates are possible using the one-shot mode. this is the temperature of the silicon in °C.
DLRCLK LEFT CHANNEL RIGHT CHANNEL
BCLK
DSDATAx MSB LSB MSB LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 1
DBCLK
I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 0
DBCLK
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL: SAI = 0, SDATA_FMT = 2 OR 3
DLRCLK
DBCLK
09434-118
TDM MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 1, 2, 3, OR 4
1/fS
Figure 18. Stereo and TDM Serial Audio Modes

tDBH
DBCLK
tDBL
tDLS tDLH
DLRCLK
tDDS
DSDATAx
LEFT-JUSTIFIED MSB MSB – 1
MODE
tDDH
tDDS
DSDATAx
I2S-JUSTIFIED MSB
MODE
tDDH
tDDS tDDS
DSDATAx
RIGHT-JUSTIFIED MSB LSB
09434-016
MODE
tDDH tDDH
Figure 19. DAC Serial Timing
ADAU1966 Data Sheet
Table 22. Pin Function Changes in Different Serial Audio Interface Modes
Stereo Modes TDM4 Mode TDM8 Mode TDM16 Mode
Signal (SAI = 0 or 1) (SAI = 2) (SAI = 3) (SAI = 4)
DSDATA1 Channel 1/Channel 2 Channel 1 to Channel 4 Channel 1 to Channel 8 Channel 1 to Channel 16
data in data in data in data in
DSDATA2 Channel 3/Channel 4 Channel 5 to Channel 8 Channel 9 to Channel 16 Not used
data in data in data in
DSDATA3 Channel 5/Channel 6 Channel 9 to Channel 12 Not used Not used
data in data in
DSDATA4 Channel 7/Channel 8 Channel 13 to Channel 16 Not used Not used
data in data in
DSDATA5 Channel 9/Channel 10 Not used Not used Not used
data in
DSDATA6 Channel 11/Channel 12 Not used Not Used Not used
data in
data in
data in
DLRCLK DLRCLK in/DLRCLK out TDM frame sync in/ TDM frame sync in/ TDM frame sync in/
TDM frame sync out TDM frame sync out TDM frame sync out
DBCLK DBCLK in/DBCLK out TDM DBCLK in/TDM TDM DBCLK in/TDM TDM DBCLK in/
DBCLK out DBCLK out TDM DBCLK out
Maximum Sample Rate 192 kHz 192 kHz 96 kHz 48 kHz
ADDITIONAL MODES To relax the requirement for the setup time of the ADAU1966 in
The ADAU1966 offers several additional modes for board level cases of high speed TDM data transmission, the ADAU1966 can
design enhancements. To reduce the EMI in board level design, latch in the data using the falling edge of DBCLK; see the
serial data can be transmitted without an explicit DBCLK. See BCLK_EDGE bit in the DAC_CTRL1 register. This effectively
Figure 20 for an example of a DAC TDM data transmission mode dedicates the entire BCLK period to the setup time. This mode
that does not require a high speed DBCLK or an external MCLK. is useful in cases where the source has a large delay time in the
This configuration is applicable when the ADAU1966 master serial data driver. Figure 21 shows this inverted DBCLK mode
clock is generated by the PLL with the DLRCLK as the PLL of data transmission.
reference frequency.
Data Sheet ADAU1966
DLRCLK
32 BITS
INTERNAL
DBCLK
DSDATAx
DLRCLK
INTERNAL
DBCLK
09434-017
TDM-DSDATAx
Figure 20. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK)
DLRCLK
DBCLK
DATA MUST BE VALID

AT THIS BCLK EDGE
09434-018
DSDATAx MSB
Figure 21. Inverted DBCLK Mode in DAC Serial Data Transmission

(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission)
ADAU1966 Data Sheet
REGISTER SUMMARY
Table 23. ADAU1966 Register Summary
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x00 PLL_CLK_CTRL0 [7:0] PLLIN XTAL_SET SOFT_RST MCS PUP 0x00 RW
0x01 PLL_CLK_CTRL1 [7:0] LOPWR_MODE MCLKO_SEL PLL_MUTE PLL_LOCK VREF_EN CLK_SEL
0x2A RW
0x02 PDN_THRMSENS_CTRL_1 [7:0] THRM_RATE THRM_MODE THRM_GO RESERVED TS_PDN PLL_PDN VREG_PDN
0xA0 RW
0x03 PDN_CTRL2 [7:0] DAC08_PDN DAC07_PDN DAC06_PDN DAC05_PDN DAC04_PDN DAC03_PDN DAC02_PDN DAC01_PDN
0x00 RW
0x04 PDN_CTRL3 [7:0] DAC16_PDN DAC15_PDN DAC14_PDN DAC13_PDN DAC12_PDN DAC11_PDN DAC10_PDN DAC09_PDN
0x00 RW
0x05 THRM_TEMP_STAT [7:0] TEMP 0x00 R
0x06 DAC_CTRL0 [7:0] SDATA_FMT SAI FS MMUTE 0x01 RW
0x07 DAC_CTRL1 [7:0] BCLK_GEN LRCLK_MODE LRCLK_POL SAI_MSB RESERVED BCLK_RATE BCLK_EDGE SAI_MS 0x00 RW
0x08 DAC_CTRL2 [7:0] RESERVED VREG_CTRL BCLK_TDMC DAC_POL AUTO_MUTE_EN DAC_OSR DE_EMP_EN 0x06 RW
0x09 DAC_MUTE1 [7:0] DAC08_MUTE DAC07_MUTE DAC06_MUTE DAC05_MUTE DAC04_MUTE DAC03_MUTE DAC02_MUTE DAC01_MUTE 0x00 RW
0x0A DAC_MUTE2 [7:0] DAC16_MUTE DAC15_MUTE DAC14_MUTE DAC13_MUTE DAC12_MUTE DAC11_MUTE DAC10_MUTE DAC09_MUTE 0x00 RW
0x0B DACMSTR_VOL [7:0] DACMSTR_VOL 0x00 RW
0x0C DAC01_VOL [7:0] DAC01_VOL 0x00 RW
0x0D DAC02_VOL [7:0] DAC02_VOL 0x00 RW
0x0E DAC03_VOL [7:0] DAC03_VOL 0x00 RW
0x0F DAC04_VOL [7:0] DAC04_VOL 0x00 RW
0x10 DAC05_VOL [7:0] DAC05_VOL 0x00 RW
0x1A DAC15_VOL [7:0] DAC15_VOL 0x00 RW
0x1B DAC16_VOL [7:0] DAC16_VOL 0x00 RW
0x1C CM_SEL_PAD_STRGTH [7:0] RESERVED RESERVED PAD_DRV RESERVED RESERVED RESERVED RESERVED RESERVED 0x02 RW
0x1D DAC_POWER1 [7:0] DAC04_POWER DAC03_POWER DAC02_POWER DAC01_POWER 0xAA RW
0x1E DAC_POWER2 [7:0] DAC08_POWER DAC07_POWER DAC06_POWER DAC05_POWER 0xAA RW
0x1F DAC_POWER3 [7:0] DAC12_POWER DAC11_POWER DAC10_POWER DAC09_POWER 0xAA RW
0x20 DAC_POWER4 [7:0] DAC16_POWER DAC15_POWER DAC14_POWER DAC13_POWER 0xAA RW
Data Sheet ADAU1966
REGISTER DETAILS
PLL AND CLOCK CONTROL 0 REGISTER
Address: 0x00, Reset: 0x00, Name: PLL_CLK_CTRL0
Table 24. Bit Descriptions for PLL_CLK_CTRL0

Bits Bit Name Settings Description Reset Access
[7:6] PLLIN PLL Input Select. Selects between MCLKI/XTALI or DLRCLK as the input to 0x0 RW
the PLL.
00 MCLKI or XTALI
01 DLRCLK
10 Reserved
11 Reserved
[5:4] XTAL_SET XTAL Oscillator Setting. XTALO pin status. 0x0 RW
00 XTAL Oscillator Enabled
01 Reserved
10 Reserved
11 XTALO Off
3 SOFT_RST Software Reset Control. This bit resets all circuitry inside the IC, except 0x0 RW
I2C/SPI communications. All control registers are reset to default values,
except Register 0x00 and Register 0x01. The PLL_CLK_CTRLx registers do
not change state.
0 Normal Operation
1 Device in Reset
[2:1] MCS Master Clock Select. MCLKI/XTALI pin functionality (PLL active), master 0x0 RW
clock rate setting. The following values are for the fS rate window from
32 kHz to 48 kHz. See Table 12 for details when using other fS selections.
00 256 × fS MCLK (44.1 kHz or 48 kHz)
01 384 × fS MCLK (44.1 kHz or 48 kHz)
10 512 × fS MCLK (44.1 kHz or 48 kHz)
11 768 × fS MCLK (44.1 kHz or 48 kHz)
0 PUP Master Power-Up Control. This bit must be set to 1 as the first register 0x0 RW
write to power up the IC.
0 Master Power-Down
1 Master Power-Up
ADAU1966 Data Sheet
PLL AND CLOCK CONTROL 1 REGISTER
Address: 0x01, Reset: 0x2A, Name: PLL_CLK_CTRL1
B7 B6 B5 B4 B3 B2 B1 B0
0 0 1 0 1 0 1 0
[7:6] LOPWR_MODE [0] CLK_SEL

Global Power/Performance Adjust DAC Clock Select
00: I2C Register Settings 0: MCLK from PLL
01: Reserved 1: MCLK from MCLKI or XTALI
10: Lower Power
11: Lowest Power
[1] VREF_EN
Internal Voltage Reference Enable
0: Disabled
[5:4] MCLKO_SEL
1: Enabled
MCLK Output Frequency
00: MCLKO = 4 MHz to 6 MHz scaled by fs
01: MCLKO = 8 MHz to 12 MHz scaled by fs [2] PLL_LOCK
10: MCLKO = Buffered MCLKI PLL Lock Indicator
11: MCLKO Pin Disabled 0: PLL Not Locked
1: PLL Locked
[3] PLL_MUTE
PLL Automute Enable/Lock
0: No DAC Automute
1: DAC Automute on PLL Unlock
Table 25. Bit Descriptions for PLL_CLK_CTRL1

[7:6] LOPWR_MODE Global Power/Performance Adjust. These bits adjust the power 0x0 RW
consumption and performance level for all 16 DAC channels at once. See
the Digital-to-Analog Converters (DACs) section for more details.
00 I2C Register Settings
01 Reserved
10 Low Power
11 Lowest Power
[5:4] MCLKO_SEL MCLK Output Frequency. Frequency selection for MCLKO pin. See the 0x2 RW
Clock Signals section for more details.
00 MCLKO = 4 MHz to 6 MHz scaled by fS
01 MCLKO = 8 MHz to 12 MHz scaled by fS
10 MCLKO = Buffered MCLKI
11 MCLKO Pin Disabled
3 PLL_MUTE PLL Automute Enable/Lock. This bit enables the PLL lock automute 0x1 RW
function.
0 No DAC Automute
1 DAC Automute on PLL Unlock
2 PLL_LOCK PLL Lock Indicator. 0x0 R
0 PLL Not Locked
1 PLL Locked
1 VREF_EN Internal Voltage Reference Enable. The internal voltage reference powers 0x1 RW
the common mode for the ADAU1966. Disabling this bit allows the user to
drive the CM pin with an outside voltage source.
0 Disabled
1 Enabled
0 CLK_SEL DAC Clock Select. Selects between PLL or Direct MCLK mode. 0x0 RW
0 MCLK from PLL
1 MCLK from MCLKI or XTALI
Data Sheet ADAU1966
BLOCK POWER-DOWN AND THERMAL SENSOR CONTROL 1 REGISTER
Address: 0x02, Reset: 0xA0, Name: PDN_THRMSENS_CTRL_1
Table 26. Bit Descriptions for PDN_THRMSENS_CTRL_1

[7:6] THRM_RATE Conversion Time Interval. When THERM_MODE = 0, the THERM_RATE bits 0x2 RW
control the time interval between temperature conversions.
00 4 sec/Conversion
01 0.5 sec/Conversion
10 1 sec/Conversion
11 2 sec/Conversion
5 THRM_MODE Continuous vs. One-Shot. Determines whether the temperature 0x1 RW
conversions occur continuously or only when commanded. To perform
one-shot temperature conversions, set this bit to 1.
0 Continuous Operation
1 One-Shot Mode
4 THRM_GO One-Shot Conversion Mode. When in one-shot conversion mode, 0x0 RW
THERM_MODE = 1, the THERM_GO bit must be set to 0 followed by a
write of 1. This sequence results in a single temperature conversion. The
temperature data is available 120 ms after writing a 1 to this bit.
0 Reset
1 Convert temperature
2 TS_PDN Temperature Sensor Power-Down. 0x0 RW
0 Temperature Sensor On
1 Temperature Sensor Power-Down
1 PLL_PDN PLL Power-Down. 0x0 RW
0 PLL Normal Operation
1 PLL Power-Down
0 VREG_PDN Voltage Regulator Power-Down. 0x0 RW
0 Voltage Regulator Normal Operation
1 Voltage Regulator Power-Down
ADAU1966 Data Sheet
POWER-DOWN CONTROL 2 REGISTER
Address: 0x03, Reset: 0x00, Name: PDN_CTRL2
Table 27. Bit Descriptions for PDN_CTRL2

7 DAC08_PDN Channel 8 Power-Down. 0x0 RW
0 Normal Operation
1 Power-Down Channel 8
0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
Data Sheet ADAU1966
POWER-DOWN CONTROL 3 REGISTER
Address: 0x04, Reset: 0x00, Name: PDN_CTRL3
Table 28. Bit Descriptions for PDN_CTRL3

0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
0 Normal Operation
ADAU1966 Data Sheet
THERMAL SENSOR TEMPERATURE READOUT REGISTER
Address: 0x05, Reset: 0x00, Name: THRM_TEMP_STAT
Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step size. Read this register and convert the hexadecimal or binary
TEMP value into decimal form; then subtract 60 from this decimal conversion. The result is the temperature in degrees Celsius.
Table 29. Bit Descriptions for THRM_TEMP_STAT

[7:0] TEMP Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step 0x00 R
size. To convert TEMP code to temperature, use the equation (TEMP − 60).
Data Sheet ADAU1966
DAC CONTROL 0 REGISTER
Address: 0x06, Reset: 0x01, Name: DAC_CTRL0
B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 1
[7:6] SDATA_FMT [0] MMUTE

SDATA Format DAC Master Mute
00: I2S—1-BCLK Cycle Delay 0: Normal Operation
01: Left-Justified—0-BCLK Cycle Delay 1: All Channels Muted
10: Right-Justified 24-bit Data—
8-BCLK Cycle Delay
11: Right-Justified 16-bit Data— [2:1] FS
16-BCLK Cycle Delay Sample Rate Select
[5:3] SAI 00: 32 kHz/44.1kHz/48kHz
Serial Audio Interface 01: 64 kHz/88.2kHz/96kHz
000: Stereo (I 2S, LJ, RJ) 10: 128 kHz/176.4kHz/192kHz
001: TDM2—Octal Line 11: 128 kHz/176.4kHz/192kHz Low Propagation Delay
010: TDM4—Quad Line
011: TDM8—Dual Line
100: TDM16—Single Line (48 kHz)
101: Reserved
110: Reserved
111: Reserved
Table 30. Bit Descriptions for DAC_CTRL0

[7:6] SDATA_FMT SDATA Format. Only used when SAI = 000. 0x0 RW
00 I2S—1-BCLK Cycle Delay
01 Left-Justified—0-BCLK Cycle Delay
10 Right-Justified 24-bit Data—8-BCLK Cycle Delay
11 Right-Justified 16-bit Data—16-BCLK Cycle Delay
[5:3] SAI Serial Audio Interface. When SAI = 000, the SDATA_FMT bits control stereo 0x0 RW
SDATA format.
000 Stereo (I2S, LJ, RJ)
001 TDM2—Octal Line
010 TDM4—Quad Line
011 TDM8—Dual Line
100 TDM16—Single Line (48 kHz)
101 Reserved
110 Reserved
111 Reserved
[2:1] FS Sample Rate Select. 0x0 RW
00 32 kHz/44.1 kHz/48 kHz
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 128 kHz/176.4 kHz/192 kHz Low Propagation Delay
0 MMUTE DAC Master Mute. 0x1 RW
0 Normal Operation
1 All Channels Muted
ADAU1966 Data Sheet

7 BCLK_GEN DBCLK Generation. When the PLL is locked to DLRCLK, it is possible to run 0x0 RW
the ADAU1966 without an external DBCLK.
0 Normal Operation—DBCLK
1 Internal DBCLK Generation
6 LRCLK_MODE DLRCLK Mode Select. Only Valid for TDM modes. 0x0 RW
0 50% Duty Cycle DLRCLK
1 Pulse Mode
5 LRCLK_POL DLRCLK Polarity. Allows the swapping of data between channels. 0x0 RW
0 Left/Odd channels are DLRCLK Low (Normal)
1 Left/Odd channels are DLRCLK High (Inverted)
4 SAI_MSB MSB Position. 0x0 RW
0 MSB First DSDATA
1 LSB First DSDATA
2 BCLK_RATE DBCLK Rate. Number of DBCLK cycles per DLRCLK Frame. Used only for 0x0 RW
generating DBCLK in Master Mode operation (SAI_MS = 1).
0 32 Cycles per Frame
1 16 Cycles per Frame
1 BCLK_EDGE DBCLK Active Edge. Adjust the polarity of the DBCLK leading edge. 0x0 RW
0 Latch in Rising Edge
1 Latch in Falling Edge
0 SAI_MS Serial Interface Master. Both DLRCLK and DBCLK become master when 0x0 RW
enabled.
0 DLRCLK/DBCLK Slave
1 DLRCLK/DBCLK Master
Data Sheet ADAU1966

[6:5] VREG_CTRL Voltage Regulator Control. Select the Regulator Output Voltage. 0x0 RW
00 Regulator Out = 2.5 V
4 BCLK_TDMC DBCLK Rate in TDM Mode. Number of DBCLK cycles per channel slot when 0x0 RW
in TDM mode.
0 32 BCLK cycles/channel slot
1 16 BCLK cycles/channel slot
3 DAC_POL DAC Output Polarity. This is a global switch of DAC polarity. 0x0 RW
0 Noninverted DAC Output
1 Inverted DAC Output
2 AUTO_MUTE_EN Automute Enable. Automatically mutes the DACs when 1024 consecutive 0x1 RW
zero input samples are received. This is independent per channel.
0 Auto-Zero Input Mute Disabled
1 Auto-Zero Input Mute Enabled
1 DAC_OSR DAC Oversampling Rate. OSR Selection. 0x1 RW
0 256 × fS DAC Oversampling
1 128 × fS DAC Oversampling
0 DE_EMP_EN De-Emphasis Enable. 0x0 RW
0 No De-Emphasis/Flat
1 De-Emphasis Enabled
ADAU1966 Data Sheet
DAC INDIVIDUAL CHANNEL MUTES 1 REGISTER
Address: 0x09, Reset: 0x00, Name: DAC_MUTE1
Table 33. Bit Descriptions for DAC_MUTE1

7 DAC08_MUTE DAC8 Soft Mute. 0x0 RW
0 DAC8 Normal Operation
1 DAC8 Mute
1 DAC7 Mute
1 DAC6 Mute
1 DAC5 Mute
1 DAC4 Mute
1 DAC3 Mute
1 DAC2 Mute
1 DAC1 Mute
Data Sheet ADAU1966
DAC INDIVIDUAL CHANNEL MUTES 2 REGISTER
Address: 0x0A, Reset: 0x00, Name: DAC_MUTE2
Table 34. Bit Descriptions for DAC_MUTE2

1 DAC16 Mute
1 DAC15 Mute
1 DAC14 Mute
1 DAC13 Mute
1 DAC12 Mute
1 DAC11 Mute
1 DAC10 Mute
1 DAC9 Mute
ADAU1966 Data Sheet
MASTER VOLUME CONTROL REGISTER
Address: 0x0B, Reset: 0x00, Name: DACMSTR_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 57 for a complete list of the volume settings.
Table 35. Bit Descriptions for DACMSTR_VOL

[7:0] DACMSTR_VOL Master Volume Control. 0x00 RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 1 VOLUME CONTROL REGISTER

Address: 0x0C, Reset: 0x00, Name: DAC01_VOL
Table 36. Bit Descriptions for DAC01_VOL

[7:0] DAC01_VOL DAC Volume Control Channel 1. 0x00 RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Data Sheet ADAU1966
Address: 0x0D, Reset: 0x00, Name: DAC02_VOL

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB

Address: 0x0E, Reset: 0x00, Name: DAC03_VOL

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
ADAU1966 Data Sheet
Address: 0x0F, Reset: 0x00, Name: DAC04_VOL

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB

Address: 0x10, Reset: 0x00, Name: DAC05_VOL

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Data Sheet ADAU1966

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB


00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
ADAU1966 Data Sheet

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB


00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Data Sheet ADAU1966

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB


00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
ADAU1966 Data Sheet

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB


00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Data Sheet ADAU1966

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB

Address: 0x1A, Reset: 0x00, Name: DAC15_VOL

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
ADAU1966 Data Sheet
Address: 0x1B, Reset: 0x00, Name: DAC16_VOL

00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
COMMON MODE AND PAD STRENGTH REGISTER

Address: 0x1C, Reset: 0x02, Name: CM_SEL_PAD_STRGTH
Table 52. Bit Descriptions for CM_SEL_PAD_STRGTH

5 PAD_DRV Output Pad Drive Strength Control. Pad strength is stated for IOVDD = 5 V. 0x0 RW
0 4 mA Drive for All Pads
1 8 mA Drive for All Pads
Data Sheet ADAU1966
DAC POWER ADJUST 1 REGISTER
Address: 0x1D, Reset: 0xAA, Name: DAC_POWER1
Table 53. Bit Descriptions for DAC_POWER1

[7:6] DAC04_POWER DAC Power Control Channel 4. 0x2 RW
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
ADAU1966 Data Sheet
Address: 0x1E, Reset: 0xAA, Name: DAC_POWER2

00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
Data Sheet ADAU1966
Address: 0x1F, Reset: 0xAA, Name: DAC_POWER3

00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
ADAU1966 Data Sheet
Address: 0x20, Reset: 0xAA, Name: DAC_POWER4

00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
Data Sheet ADAU1966
Table 57. Volume Table
Binary Value Volume Attenuation (dB) Binary Value Volume Attenuation (dB)
00000000 0 00101110 −17.25
00000001 −0.375 00101111 −17.625
00000010 −0.75 00110000 −18
00000011 −1.125 00110001 −18.375
00000100 −1.5 00110010 −18.75
00000101 −1.875 00110011 −19.125
00000110 −2.25 00110100 −19.5
00000111 −2.625 00110101 −19.875
00001000 −3 00110110 −20.25
00001001 −3.375 00110111 −20.625
00001010 −3.75 00111000 −21
00001011 −4.125 00111001 −21.375
00001100 −4.5 00111010 −21.75
00001101 −4.875 00111011 −22.125
00001110 −5.25 00111100 −22.5
00001111 −5.625 00111101 −22.875
00010000 −6 00111110 −23.25
00010001 −6.375 00111111 −23.625
00010010 −6.75 01000000 −24
00010011 −7.125 01000001 −24.375
00010100 −7.5 01000010 −24.75
00010101 −7.875 01000011 −25.125
00010110 −8.25 01000100 −25.5
00010111 −8.625 01000101 −25.875
00011000 −9 01000110 −26.25
00011001 −9.375 01000111 −26.625
00011010 −9.75 01001000 −27
00011011 −10.125 01001001 −27.375
00011100 −10.5 01001010 −27.75
00011101 −10.875 01001011 −28.125
00011110 −11.25 01001100 −28.5
00011111 −11.625 01001101 −28.875
00100000 −12 01001110 −29.25
00100001 −12.375 01001111 −29.625
00100010 −12.75 01010000 −30
00100011 −13.125 01010001 −30.375
00100100 −13.5 01010010 −30.75
00100101 −13.875 01010011 −31.125
00100110 −14.25 01010100 −31.5
00100111 −14.625 01010101 −31.875
00101000 −15 01010110 −32.25
00101001 −15.375 01010111 −32.625
00101010 −15.75 01011000 −33
00101011 −16.125 01011001 −33.375
00101100 −16.5 01011010 −33.75
00101101 −16.875 01011011 −34.125
ADAU1966 Data Sheet
01011100 −34.5 10001011 −52.125
01011101 −34.875 10001100 −52.5
01011110 −35.25 10001101 −52.875
01011111 −35.625 10001110 −53.25
01100000 −36 10001111 −53.625
01100001 −36.375 10010000 −54
01100010 −36.75 10010001 −54.375
01100011 −37.125 10010010 −54.75
01100100 −37.5 10010011 −55.125
01100101 −37.875 10010100 −55.5
01100110 −38.25 10010101 −55.875
01100111 −38.625 10010110 −56.25
01101000 −39 10010111 −56.625
01101001 −39.375 10011000 −57
01101010 −39.75 10011001 −57.375
01101011 −40.125 10011010 −57.75
01101100 −40.5 10011011 −58.125
01101101 −40.875 10011100 −58.5
01101110 −41.25 10011101 −58.875
01101111 −41.625 10011110 −59.25
01110000 −42 10011111 −59.625
01110001 −42.375 10100000 −60
01110010 −42.75 10100001 −60.375
01110011 −43.125 10100010 −60.75
01110100 −43.5 10100011 −61.125
01110101 −43.875 10100100 −61.5
01110110 −44.25 10100101 −61.875
01110111 −44.625 10100110 −62.25
01111000 −45 10100111 −62.625
01111001 −45.375 10101000 −63
01111010 −45.75 10101001 −63.375
01111011 −46.125 10101010 −63.75
01111100 −46.5 10101011 −64.125
01111101 −46.875 10101100 −64.5
01111110 −47.25 10101101 −64.875
01111111 −47.625 10101110 −65.25
10000000 −48 10101111 −65.625
10000001 −48.375 10110000 −66
10000010 −48.75 10110001 −66.375
10000011 −49.125 10110010 −66.75
10000100 −49.5 10110011 −67.125
10000101 −49.875 10110100 −67.5
10000110 −50.25 10110101 −67.875
10000111 −50.625 10110110 −68.25
10001000 −51 10110111 −68.625
10001001 −51.375 10111000 −69
10001010 −51.75 10111001 −69.375
Data Sheet ADAU1966
10111010 −69.75 11011101 −82.875
10111011 −70.125 11011110 −83.25
10111100 −70.5 11011111 −83.625
10111101 −70.875 11100000 −84
10111110 −71.25 11100001 −84.375
10111111 −71.625 11100010 −84.75
11000000 −72 11100011 −85.125
11000001 −72.375 11100100 −85.5
11000010 −72.75 11100101 −85.875
11000011 −73.125 11100110 −86.25
11000100 −73.5 11100111 −86.625
11000101 −73.875 11101000 −87
11000110 −74.25 11101001 −87.375
11000111 −74.625 11101010 −87.75
11001000 −75 11101011 −88.125
11001001 −75.375 11101100 −88.5
11001010 −75.75 11101101 −88.875
11001011 −76.125 11101110 −89.25
11001100 −76.5 11101111 −89.625
11001101 −76.875 11110000 −90
11001110 −77.25 11110001 −90.375
11001111 −77.625 11110010 −90.75
11010000 −78 11110011 −91.125
11010001 −78.375 11110100 −91.5
11010010 −78.75 11110101 −91.875
11010011 −79.125 11110110 −92.25
11010100 −79.5 11110111 −92.625
11010101 −79.875 11111000 −93
11010110 −80.25 11111001 −93.375
11010111 −80.625 11111010 −93.75
11011000 −81 11111011 −94.125
11011001 −81.375 11111100 −94.5
11011010 −81.75 11111101 −94.875
11011011 −82.125 11111110 −95.25
11011100 −82.5 11111111 −95.625
ADAU1966 Data Sheet
OUTLINE DIMENSIONS
16.20
0.75 16.00 SQ
1.60 15.80
0.60 MAX
0.45 80 61
1 60
PIN 1
14.20
TOP VIEW
(PINS DOWN) 14.00 SQ
13.80
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 0° 20 41
0.05 SEATING 0.10 21 40
PLANE COPLANARITY
VIEW A 0.65 0.38
BSC 0.32
VIEW A LEAD PITCH
ROTATED 90° CCW 0.22
051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 22. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
ADAU1966WBSTZ −40°C to +105°C 80-Lead LQFP ST-80-2
ADAU1966WBSTZRL −40°C to +105°C 80-Lead LQFP, 13” Tape and Reel ST-80-2
EVAL-ADAU1966Z Evaluation Board
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADAU1966W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09434-0-3/16(E)

16-Channel High Performance Differential Output, 192 KHZ, 24-Bit Dac

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16-Channel High Performance Differential Output, 192 KHZ, 24-Bit Dac

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16-Channel High Performance

Differential Output, 192 kHz, 24-Bit DAC

Automotive audio systems

FUNCTIONAL BLOCK DIAGRAM

Rev. E Document Feedback

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS

tSCH tDS tSCH

Figure 2. I2C Timing Diagram

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 10. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 10. Typical DAC Output Active Filter Circuit (Differential)

Figure 11. Recommended 2.5 V Regulator Circuit

Table 11. DAC Power vs. Performance

SDA AD1 AD0 0 0 1 0 0 R/W 0 0 0 0 0 1 1 0

START BY ACK. BY ACK. BY

Figure 12. I2C Write Format

SDA AD1 AD0 0 0 1 0 0 R/W 0 0 0 0 0 1 1 0

START BY ACK. BY ACK. BY

SDA AD1 AD0 0 0 1 0 0 R/W D7 D6 D5 D4 D3 D2 D1 D0

Figure 13. I2C Read Format

Table 16. I2C Abbreviations

Table 17. Single Word I2C Write

Table 18. Burst Mode I2C Write

Table 19. Single Word I2C Read

Table 20. Burst Mode I2C Read

Figure 14. SPI Mode Initial Sequence

DEVICE ADDRESS (7 BITS) R/W

Figure 15. SPI Write to ADAU1966 Clocking

DEVICE ADDRESS (7 BITS)

COUT DATA BYTE FROM ADAU1966

Figure 16. SPI Read from the ADAU1966 Clocking

CDATA D23 D22 D9 D8 D0

Figure 17. Format of the SPI Signal

POWER SUPPLY AND VOLTAGE REFERENCE SERIAL DATA PORTS—DATA FORMAT

DLRCLK LEFT CHANNEL RIGHT CHANNEL

DSDATAx MSB LSB MSB LSB

LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 1

DLRCLK LEFT CHANNEL RIGHT CHANNEL

DSDATAx MSB LSB MSB LSB

I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 0

DLRCLK LEFT CHANNEL RIGHT CHANNEL

DSDATAx MSB LSB MSB LSB

RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL: SAI = 0, SDATA_FMT = 2 OR 3

DSDATAx MSB LSB MSB LSB

Figure 18. Stereo and TDM Serial Audio Modes

Figure 19. DAC Serial Timing

DATA MUST BE VALID

Figure 21. Inverted DBCLK Mode in DAC Serial Data Transmission

Table 24. Bit Descriptions for PLL_CLK_CTRL0

[7:6] LOPWR_MODE [0] CLK_SEL

Table 25. Bit Descriptions for PLL_CLK_CTRL1

Table 26. Bit Descriptions for PDN_THRMSENS_CTRL_1

Table 27. Bit Descriptions for PDN_CTRL2

Table 28. Bit Descriptions for PDN_CTRL3

Table 29. Bit Descriptions for THRM_TEMP_STAT