CS4222

20-Bit Stereo Audio Codec with Volume Control

Features Description
l 99 dB 20-bit A/D Converters The CS4222 is a highly integrated, high performance,
l 99 dB 20-bit D/A Converters 20-bit, audio codec providing stereo analog-to-digital
and stereo digital-to-analog converters using delta-sig-
l 110 dB DAC Signal-to-Noise Ratio (EIAJ) ma conversion techniques. The device operates from a
l Analog Volume Control single +5 V power supply, and features low power con-
- 0.5 dB Step Resolution sumption. Selectable de-emphasis filter for 32, 44.1, and
48 kHz sample rates is also included.
- 113.5 dB Attenuation
l Soft Mute Capability The CS4222 also includes an analog volume control ca-
l Differential Inputs/Outputs pable of 113.5 dB attenuation in 0.5 dB resolution. The
analog volume control architecture preserves dynamic
l On-chip Anti-aliasing and Output Smoothing range during attenuation. Volume control changes are
Filters implemented using a "soft" ramping or zero crossing
l De-emphasis for 32, 44.1 and 48 kHz technique.
l Stand-Alone or Control Port Mode Applications include reverb processors, musical instru-
l Single +5 V power supply ments, DAT, and multitrack recorders.
The CS4222 is packaged in a 28-pin plastic SSOP.

ORDERING INFORMATION
CS4222-KS -10° to +70° C 28-pin SSOP
CDB4222 Evaluation Board
I

SCL/CCLK SDA/CDIN AD0/CS SMUTE MCLK VD VA

RST Control Port

DEM1
DEM0
with De-Emphasis

Left Volume AOUTL+

Output Stage
Digital Filters

Analog Low
Pass and

DAC Control
Serial Audio Data Interface

AOUTL-

LRCK AOUTR+
Right Volume
SCLK DAC Control AOUTR-
SDIN
Left AINL-
Digital Filters

SDOUT ADC AINL+

AINR-
Right
ADC AINR+

DGND AGND

This document contains information for a new product.

Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1997 JAN ‘97
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS236PP3
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 1
 CS4222

ANALOG CHARACTERISTICS ( TA = 25°C; VA, VD = +5V; Full Scale Input Sine wave,
997 Hz; Fs = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in "Recom-
mended Connection Diagram"; SPI mode, Format 0, unless otherwise specified.)
Parameter Symbol Min Typ Max Units
Analog Input Characteristics
ADC Resolution - - 20 Bits
Total Harmonic Distortion THD 0.003 - %
Dynamic Range (A-weighted): TBD 99 - dB
(unweighted): TBD 96 - dB
Total Harmonic Distortion + Noise -1 dB (Note 1) THD+N - -90 TBD dB
Interchannel Isolation (1 kHz) - 90 - dB
Interchannel Gain Mismatch - 0.1 - dB
Offset Error (with High Pass Filter) - - 0 LSB
(HPF defeated with CAL) - TBD - LSB
Full Scale Input Voltage (Differential) 1.9 2.0 2.1 Vrms
Gain Drift - 100 - ppm/°C
Input Resistance 10 - - kΩ
Input Capacitance - - 15 pF
Common Mode Input Voltage - 2.3 - V
A/D Decimation Filter Characteristics
Passband (Note 2) 0 - 21.8 kHz
Passband Ripple - - ±0.01 dB
Stopband (Note 2) 30 - 6114 kHz
Stopband Attenuation (Note 3) 80 - - dB
Group Delay (Fs = Output Sample Rate) (Note 4) tgd - 15/Fs - s
Group Delay Variation vs. Frequency ∆ tgd - - 0 µs
High Pass Filter Characteristics
Frequency Response: -3 dB (Note 2) - 3.7 - Hz
-0.1 dB - 20 - Hz
Phase Deviation @ 20 Hz (Note 2) - 10 - Degree
Passband Ripple - - 0 dB
Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms)
2. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz,
the 0.01 dB passband edge is 0.4535xFs and the stopband edge is 0.625xFs.
3. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is
no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.8 kHz
where n = 0,1,2,3...).
4. Group delay for Fs = 48 kHz, tgd = 15/48 kHz = 312µs

* Parameter definitions are given at the end of this data sheet.

Specifications are subject to change without notice.

2 DS236PP3
 CS4222

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Units
Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified.
DAC Resolution - - 20 Bits
Signal-to-Noise, Idle-Channel Noise (DAC muted, A-weighted) TBD 110 - dB
Dynamic Range (DAC not muted, A-weighted) TBD 99 - dB
(DAC not muted, unweighted) TBD 96 - dB
Total Harmonic Distortion THD - 0.003 - %
Total Harmonic Distortion + Noise THD+N - -88 TBD dB
Interchannel Isolation (1kHz) - 90 - dB
Interchannel Gain Mismatch - 0.1 - dB
Attenuation Step Size (All Outputs) 0.35 0.5 0.65 dB
Programmable Output Attenuation Span 110 113.5 - dB
Differential Offset Voltage - ±10 - mV
Common Mode Output Voltage - 2.3 - V
Full Scale Output Voltage 1.9 2.0 2.1 Vrms
Gain Drift - 100 - ppm/°C
Out-of-Band Energy (Fs/2 to 2Fs) - -60 - dBFS
Analog Output Load Resistance: 10 - - kΩ
Capacitance: - - 100 pF
Combined Digital and Analog Filter Characteristics
Frequency Response 10 Hz to 20 kHz - ±0.1 - dB
Deviation from Linear Phase - ±0.5 - Degrees
Passband: to 0.01 dB corner (Notes 5,6) 0 - 21.8 kHz
Passband Ripple (Note 6) - - ±0.01 dB
Stopband (Notes 5,6) 26.2 - - kHz
Stopband Attenuation (Notes 7) 70 - - dB
Group Delay (Fs = Input Word Rate) tgd - 16 / Fs - s
Power Supply
Power Supply Current VA - 30 TBD mA
VD - 20 TBD mA
Total Power Down - 0.2 - mA
Power Supply Rejection Ratio (1 kHz, 10 mVrms) - 50 - dB
Notes: 5. The passband and stopband edges scale with frequency. For input word rates, Fs, other than
48 kHz, the 0.01 dB passband edge is 0.4535xFs and the stopband edge is 0.5465xFs.
6. Digital filter characteristics.
7. Measurement bandwidth is 10Hz to 3Fs.

Specifications are subject to change without notice

DS236PP3 3
 CS4222

SWITCHING CHARACTERISTICS (TA = 25°C; VA, VD = +5V ±5%, outputs loaded with 30pF)
Parameter Symbol Min Typ Max Units
Audio ADC’s & DAC’s Sample Rate Fs 4 - 50 kHz
MCLK Frequency (MCLK = 256, 384, or 512 Fs) 1.024 - 26 MHz
MCLK Pulse Width High MCLK = 512 Fs 10 - - ns
MCLK = 384 Fs 21 - - ns
MCLK = 256 Fs 31 - - ns
MCLK Pulse Width Low MCLK = 512 Fs 10 - - ns
MCLK = 384 Fs 21 - - ns
MCLK = 256 Fs 31 - - ns
MCLK Jitter Tolerance - 500 - ps RMS
RST Low Time (Note 8) 10 - - ms
1
SCLK Falling edge to SDOUT output valid (DSCK=0) tdpd - - (384)Fs
+ 20 ns

LRCK edge to MSB valid tlrpd - - 25 ns

SDIN Setup Time Before SCLK Rising Edge (DSCK=0) tds - - 25 ns
SDIN Hold Time After SCLK Rising Edge (DSCK=0) tdh - - 25 ns
SCLK Period tsckw 1 - - ns
(128) Fs

SCLK High Time tsckh 40 - - ns

SCLK Low Time tsckl 40 - - ns
SCLK Rising to LRCK Edge (DSCK=0) tlrckd 20 - - ns
LRCK Edge to SCLK Rising (DSCK=0) tlrcks 40 - - ns
Notes: 8. After powering up the CS4222, PDN should be held low for 10 ms to allow the power supply
to settle.

LRCK

t lrckd t lrcks t sckh t sckl

SCLK*

t sckw

SDIN

t lrpd t ds t dh t dpd

SDOUT MSB MSB-1

*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.

Serial Audio Port Data I/O timing

4 DS236PP3
 CS4222

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25°C VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30pF)
Parameter Symbol Min Max Units
2
SPI Mode (SPI/I C = 0)
CCLK Clock Frequency fsck - 6 MHz
RST rising edge to CS falling tsrs 500 - ns
CCLK edge to CS falling (Note 9) tspi 500 - ns
CS High Time Between Transmissions tcsh 1.0 - µs
CS Falling to CCLK Edge tcss 20 - ns
CCLK Low Time tscl 66 - ns
CCLK High Time tsch 66 - ns
CDIN to CCLK Rising Setup Time tdsu 40 - ns
CCLK Rising to DATA Hold Time (Note 10) tdh 15 - ns
Rise Time of CCLK and CDIN (Note 11) tr2 - 100 ns
Fall Time of CCLK and CDIN (Note 11) tf2 - 100 ns
Notes: 9. tspi only needed before first falling edge of CS after RST rising edge.
tspi = 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For FSCK < 1 MHz

RST t srs

CS
t spi t css t scl t sch t csh

CCLK

t r2 t f2

CDIN

t dsu t
dh

DS236PP3 5
 CS4222

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25°C; VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30pF)
Parameter Symbol Min Max Units
2 ® 2
I C Mode (SPI/I C = 1) (Note 12)
SCL Clock Frequency fscl - 100 kHz
RST Rising Edge to Start tirs 500 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low Time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 13) thdd 0 - µs
SDA Setup Time to SCL Rising tsud 250 - ns
Rise Time of Both SDA and SCL Lines tr - 1 µs
Fall Time of Both SDA and SCL Lines tf - 300 ns
Setup Time for Stop Condition tsusp 4.7 µs

Notes: 12. Use of the I2C® bus interface requires a license from Philips.
I2C® is a registered trademark of Philips Semiconductors.
13. Data must be held for sufficient time to bridge the 300ns transition time of SCL.

RST
t irs
Repeated
Stop Start Start Stop

SDA
t buf t hdst t high t tf
hdst t susp

SCL

t t t sud t sust tr
low hdd

6 DS236PP3
 CS4222

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.)
Parameter Symbol Min Typ Max Units
Power Supplies Digital VD -0.3 - 6.0 V
Analog VA -0.3 - 6.0 V
Input Current (Note 14) - - ±10 mA
Analog Input Voltage (Note 15) -0.7 - VA+0.7 V
Digital Input Voltage (Note 15) -0.7 - VD+0.7 V
Ambient Temperature (Power Applied) -55 - +125 °C
Storage Temperature -65 - +150 °C
Warning: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

Note: 14. Any pin except supplies. Transient currents of up to ±100mA on the analog input pins will
not cause SCR latch-up.
15. The maximum over or under voltage is limited by the input current.

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with respect
to 0V.)

Parameter Symbol Min Typ Max Units

Power Supplies Digital VD 4.75 5.0 5.25 V
Analog VA 4.75 5.0 5.25 V
VA - VD - - 0.4 V
Operating Ambient Temperature TA -10 25 70 °C

DIGITAL CHARACTERISTICS (TA = 25 °C; VA, VD = 5V ± 5%)

Parameter Symbol Min Typ Max Units
High-level Input Voltage VIH 2.8 - VD+0.3 V
Low-level Input Voltage VIL -0.3 - 1.0 V
High-level Output Voltage at I0 = -2.0 mA VOH VD-1.0 - - V
Low-level Output Voltage at I0 = 2.0 mA VOL - - 0.4 V
Input Leakage Current (Digital Inputs) - - 10 µA
Output Leakage Current (High Impedance Digital Outputs) - - 10 µA

DS236PP3 7
 CS4222

Ferrite Bead
2Ω
+5V
Supply + 1 µF 0.1 µF 0.1 µF + 1 µF

21 6
150Ω VA VD
20 25
AINL+ AOUTL+ Analog
2.2 nF 26 Filter
AOUTL-
150Ω
19
AINL-
24
150Ω AOUTR+
23
Analog
17 AOUTR- Filter
AINR+
2.2 nF
150Ω
CS4222
16 18 Digital
AINR- DEM1
13 Audio
DEM0 Source

10
SCL/CCLK
11
SDA/CDIN
12
Microcontroller AD0/CS
27 Rs
RST 8
2 SDOUT
SMUTE
9 Rs
1 SDIN
NC
4 Rs Audio
14 LRCK
NC DSP
5 Rs
15 SCLK
NC
3 Rs 1
Note: Pins 10,11, and 12 28 MCLK
should be tied to DGND NC
in stand-alone mode. AGND DGND
22 7 Rs = 500 Ω
Rs 1 = 50 Ω

Figure 1. Recommended Connection Diagram

(Also see recommended layout diagram, Figure 10)

8 DS236PP3
 CS4222

FUNCTIONAL DESCRIPTION Control Port Stand-alone

Volume control -
Overview Adjustable Mute ramp rate Fixed Mute ramp rate
Enable zero crossing detect Disabled
The CS4222 has 2 channels of 20-bit analog-to- Disable mute on zero input Enabled
digital conversion and 2 channels of 20-bit De-emphasis De-emphasis
digital-to-analog conversion. All ADCs and Mute DAC outputs Mute DAC outputs
DACs are delta-sigma converters. The DAC out- ADC Input Peak Level -
puts have adjustable output attenuation Detect
implemented in 0.5 dB step resolution. The de- 16, 18, 20 bit Interface 20 bit I2S Interface
vice also includes a soft mute function and Individual ADC/DAC power Codec power down
digital de-emphasis for 32, 44.1, and 48 kHz. down
Cal on command Cal on power-up
Digital audio data for the DACs and from the High pass enable/disable High pass enabled
ADCs is communicated over separate serial Table 1. Control Port vs. Stand-alone
ports. This allows concurrent writing to and
reading from the device. Control for the func-
tions available on the CS4222 are communicated Analog Inputs
over a serial microcontroller interface. Figure 1
shows the recommended connection diagram for Line Level Inputs
the CS4222.
AINR-, AINR+, AINL-, and AINL+ are the dif-
The device can be operated with or without the ferential line level input pins (See Figure 1).
control port interface. Additional functions are Figure 2 shows an AC coupled optional input
available when the control port interface is used buffer which combines level shifting with single-
as outlined in Table 1. ended to differential conversion. Analog inputs
must be DC coupled into the CS4222 with a
2.3V common mode input voltage. Any DC off-

Figure 2. Optional Line Input Buffer

DS236PP3 9
 CS4222

set at the input to the CS4222 will be removed Analog Outputs

by the internal high-pass filters. See Figure 3 for
the differential input signal description. The Line Level Outputs
ADC outputs may be muted (set to zero) by
writing the ADMR and ADML bits, and the The CS4222 contains an on-chip buffer amplifier
ADC can be independently powered down using producing differential outputs capable of driving
the PDAD bit. ADMR, ADML, and PDAD are 10 kΩ loads. Each output (AOUTL+, AOUTL-,
all located in the ADC control byte (#1). AOUTR+, AOUTR-) will produce a nominal
2.83 Vpp (1 Vrms) output with a 2.3 volt com-
Input Level Monitoring mon mode for a full scale digital input. This is
equivalent to a 5.66 Vpp (2 Vrms) differential
The CS4222 includes independent Peak Input signal as shown in Figure 3. The recommended
Level Monitoring for each channel. The analog- off-chip analog filter is either a 2nd order Butter-
to-digital converter continually monitors the peak worth or a 3rd order Butterworth, if greater
digital signal for both channels, prior to the digi- out-of-band noise filtering is desired. The
tal limiter, and records these values in the CS4222 DAC interpolation filter has been pre-
LVL2-0 (left channel) and LVR2-0 (right chan- compensated for an external 2nd or der
nel) bits in the Converter Status Report Byte Butterworth filter with a 3dB corner at Fs, or a
(#6). These bits indicate whether the input level 3rd order Butterworth filter with a 3dB corner at
is clipping, -1 to -6 dB from full scale in 1 dB 0.75 Fs to provide a flat frequency response and
resolution, or below -6 dB from full scale. The linear phase over the passband (see Figure 4 for
LVL/LVR bits are "sticky" bits and are reset to Fs = 48 kHz). If the recommended filter is not
zero when read. used, small frequency response magnitude and
phase errors will occur. In addition to providing
High Pass Filter out-of-band noise attenuation, the output filters
shown in Figure 4 provide differential to single-
The operational amplifiers in the input circuitry ended conversion.
driving the CS4222 may generate a small DC
offset into the A/D converter. The CS4222 in- The DACs can be powered down using the
cludes a high pass filter after the decimator to PDDA bit in the DAC control register (#2).
remove any DC offset which could result in re-
cording a DC level, possibly yielding "clicks"
when switching between devices in a multichan- CS4222
(2.3 + 1.4)V
nel system. The characteristics of this first-order
AIN+/AOUT+ 2.3V
high pass filter are outlined below for Fs equal
(2.3 - 1.4)V
to 48 kHz. The filter response scales linearly
(2.3 + 1.4)V
with sample rate. The high pass filter may be de-
AIN+/AOUT- 2.3V
feated independently for the left and right
(2.3 - 1.4)V
channels by writing HPDR and HPDL in the
ADC control byte (#1).
Full Scale Input level = (AIN+) - (AIN-)= 5.66 Vpp
Full Scale Output level = (AOUT+) - (AOUT-)= 5.66 Vpp
Frequency Response -3dB @ 3.7 Hz
-0.1 dB @ 20 Hz Figure 3. Full Scale Input/Output Voltage
Phase Deviation 10 degrees @ 20 Hz
Passband Ripple None
Table 2. High Pass Filter Characteristics

10 DS236PP3
 CS4222

Figure 4.

Analog/Digital Volume Control - Control Port 0 Analog Digital

Mode Only
Signal
Amplitude (dB)

The DAC outputs are each routed through an at-

tenuator which is adjustable in 0.5 dB steps.
Output attenuation is available through the Out- Noise
put Attenuator Data Bytes (#3 & #4). Level
changes are implemented with an analog volume
control until the residual output noise is equal to
the noise floor in the mute state at which point
volume changes are performed digitally. This 0 Attenuation (dB) -113.5
technique is superior to purely digital volume Figure 5. Hybrid Analog/Digital Attenuation
control techniques as the noise is attenuated by
the same amount as the signal, thus preserving from the current level to the new level in 0.5 dB
dynamic range (see Figure 5). steps. The default rate of volume change is 8
LRCK cycles for each 0.5 dB step (equivalent to
The CS4222 implements a "soft" volume control 647 µs at Fs = 48 kHz). The rate of volume
whereby level changes are achieved by ramping
DS236PP3 11
 CS4222

change is adjustable to 4, 16, or 32 LRCK cycles they receive between 512 and 1024 consecutive
with the RMP1/0 bits in the DAC control byte zeros (or -1 code). Detection and muting is done
(#2). independently for left and right channels. A sin-
gle non-zero value will immediately unmute the
"Soft" volume control may be disabled through DAC output. This feature is enabled on power-
the SOFT bit in the DAC bit Control Byte (#2). up, and it may be disabled with the MUTC bit in
When "soft" volume control is defeated, level the DAC Control Byte (#2).
changes step from the current level to the new
level in a single step. The volume change takes Master Clock Generation
effect on a zero crossing to minimize audible ar-
tifacts. If there is no zero crossing, then the The Master Clock, MCLK, is used to operate the
requested level change will occur after a time- digital filters and the delta-sigma modulator.
out period between 512 and 1024 sample periods MCLK must be either 256x, 384x, or 512x the
(10.7 ms to 21.3 ms at 48 kHz sample rate). desired Input Sample Rate, Fs. Fs is the fre-
There is a separate zero crossing detector for quency at which digital audio samples for each
each channel. ACCR and ACCL bits in the Con- channel are input to the DAC or output from the
verter Status Report Byte (#6) give feedback on ADC and is equal to the LRCK frequency. The
when a volume control change has taken effect MCLK to LRCK frequency ratio is detected
for the right and left channel. This bit goes high automatically during the initialization sequence by
when a new setting is loaded and returns low counting the number of MCLK transitions during
when it has taken effect. a single LRCK period. Internal dividers are then
set to generate the proper clocks for the digital
Soft Mute/Mute on Zero Input Data filters, delta-sigma modulators and switched-ca-
pacitor filter. Table 3 illustrates the standard
Muting can be achieved via hardware or soft- audio sample rates and the required MCLK fre-
ware control. Soft mute can be achieved by quencies. If MCLK stops for 10µs, the CS4222
lowering the SMUTE pin at which point the out- will enter a power down state until the clock re-
put level will ramp down in 0.5 dB steps to a turns. The control port registers will maintain
muted state. Upon returning the SMUTE pin their current settings. It is required to have
high, the output will ramp up to the volume con- SCLK and LRCK derived from the master clock.
trol setting in the Output Attenuator Data Bytes
(#3 & #4). "Soft" mute may be disabled through
the SOFT bit in the DAC Control Byte (#2). Fs (kHz) MCLK (MHz)
When "soft" mute is defeated, muting occurs on 256x 384x 512x
zero crossings or after a time-out period, similar 32 8.1920 12.2880 16.3840
to the volume control changes. 44.1 11.2896 16.9344 22.5792
48 12.2880 18.4320 24.5760
Under software control, each output can be inde- Table 3. Common Clock Frequencies
pendently muted via mute control bits, MUTR
and MUTL, in the DAC Control Byte (#2). Soft
mute or zero crossing mute will be implemented
depending on the state of the SOFT bit in the
DAC Control Byte (#2).

Muting on consecutive zero input data is also

provided where all DAC outputs will mute if
12 DS236PP3
 CS4222

FORMAT 0: LRCK Left Right

(Stand-Alone and SCLK
Control Port Mode)
SDIN MSB LSB MSB LSB

FORMAT 1: LRCK Left Right

(Control Port SCLK
Mode only)
SDIN MSB LSB MSB LSB MSB

FORMAT 2, 3, 4: LRCK Left Right

Format 2: M = 20
SCLK
Format 3: M = 18
Format 4: M = 16 SDIN LSB MSB LSB MSB LSB
(Control Port
Mode only) M SCLKs M SCLKs

Note: SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1.

Figure 6. Audio DSP Data Input Formats.

FORMAT 0: LRCK Left Right

(Stand-Alone and
SCLK
Control Port Mode)
SDIN MSB LSB MSB LSB

FORMAT 1: LRCK Left Right

(Control Port
Mode only) SCLK
SDIN MSB LSB MSB LSB MSB

Note: SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1.

Figure 7. Audio DSP Port Data Output Formats.

DS236PP3 13
 CS4222

Serial Audio Data Interface CS4222 may be set via the DSCK bit in the DSP
Port Mode Byte (#5). The default input and out-
Serial Audio Interface Signals put format is I2S compatible.

The serial interface clock, SCLK, is used for Control Port Interface
transmitting and receiving audio data. The active
edge of SCLK is chosen by setting the DSCK bit The control port is used to load all the internal
in the DSP Port Mode Byte (#6); the default settings. The operation of the control port may
upon power-up is that data is valid on the rising be completely asynchronous with the audio sam-
edge for both input and output. SCLK is an in- ple rate. However, to avoid potential interference
put from an external source and at least 20 problems, the control port pins should remain
SCLK’s per half period of LRCK are required static if no operation is required.
for proper operation.
The control port has 2 modes: SPI and I2C®,
The Left/Right clock (LRCK) is used to indicate with the CS4222 operating as a slave device. If
left and right data and the start of a new sample I2C operation is desired, AD0/CS should be tied
period. The frequency of LRCK must be equal to VD or DGND. If the CS4222 ever detects a
to the system sample rate, Fs. negative transition on AD0/CS after power-up,
SPI mode will be selected.
SDIN is the data input pin which drives a pair of
DACs. SDOUT is the output data pin from the SPI Mode
ADC’s.
In SPI mode, CS is the CS4222 chip select sig-
Serial Audio Interface Formats nal, CCLK is the control port bit clock, CDIN is
the input data line from the microcontroller and
The serial audio port supports 5 input and 2 out- the chip address is 0010000. All signals are in-
put formats, shown in Figures 6 and 7. These puts and data is clocked in on the rising edge of
formats are chosen through the DSP Port Mode CCLK.
Byte (#5) with the DDO and DDI2/1/0 bits. The
data output format is 20 bits and may be left jus- Figure 8 shows the operation of the control port
tified or I2S compatible depending on the state in SPI mode. To write to a register, bring CS
of the DDO bit. The input data format is set low. The first 7 bits on CDIN form the chip ad-
with the DDI bits to be left or right justified or dress, and must be 0010000. The eighth bit is a
I2S compatible. In addition, the polarity of the read/write indicator (R/W), which must be low
SCLK edge used to clock in/out data from the to write. Register reading from the CS4222 is
CS

CCLK
CHIP
ADDRESS MAP DATA
CDIN 0010000 R/W MSB LSB

byte 1 byte n
MAP = Memory Address Pointer
Figure 8. Control Port Timing, SPI mode

14 DS236PP3
 CS4222

Note 1
ADDR DATA DATA
SDA 001000
AD0
R/W ACK
1-8
ACK
1-8
ACK

SCL

Start Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Figure 9. Control Port Timing, I2C® Mode

not supported in the SPI mode. The next 8 bits reads or writes of consecutive registers. Each
form the Memory Address Pointer (MAP), which byte is separated by an acknowledge bit. Use of
is set to the address of the register that is to be the I2C bus®compatible interface requires a li-
updated. The next 8 bits are the data which will cense from Philips. I2C bus® is a registered
be placed into register designated by the MAP. trademark of Philips Semiconductor.

The CS4222 has a MAP auto increment capabil- Control Port Bit Definitions
ity, enabled by the INCR bit in the MAP register.
If INCR is a zero, then the MAP will stay con- All registers can be written and read in I2C
stant for successive writes. If INCR is set to a 1, mode, except the Converter Status Report Byte
then MAP will auto increment after each byte is (#6) and the CLKE and CALP bits in the ADC
written, allowing block writes of successive reg- control byte (#1) which are read only. SPI mode
isters. Register reading from the CS4222 is not only allows for register writing. See the follow-
supported in the SPI mode. ing bit definition tables for bit assignment
information.
I2C ®Mode

In I2C® mode, SDA is a bidirectional data line.

Data is clocked into and out of the part by the
clock, SCL, with the clock to data relationship as
shown in Figure 9. There is no CS pin. Pin AD0
forms the partial chip address and should be tied
to VD or DGND as desired. The upper 6 bits of
the 7 bit address field must be 001000. To com-
municate with the CS4222 the LSB of the chip
address field, which is the first byte sent to the
CS4222, should match the setting of the AD0
pin. The eighth bit of the address byte is the
R/W bit (high for a read, low for a write). If the
operation is a write, the next byte is the Memory
Address Pointer which selects the register to be
read or written. If the operation is a read, the
contents of the register pointed to by the Mem-
ory Address Pointer will be output. Setting the
auto increment bit in MAP, allows successive

DS236PP3 15
 CS4222

De-Emphasis Power-up/Reset/Power Down/Calibration

The CS4222 is capable of digital de-emphasis Upon power up, the user should hold RST=0 for
for 32, 44.1, or 48 kHz sample rates. Imple- approximately 10 ms. In this state, the control
mentation of digital de-emphasis requires port is reset to its default settings and the part
reconfiguration of the digital filter to maintain remains in the power down mode. At the end of
the filter response shown in Figure 10 at multi- RST, the device performs an offset calibration
ple sample rates. which lasts approximately 50 ms after which the
device enters normal operation. A calibration
De-emphasis control is achieved with the may also be initiated via the CAL bit in the
DEM1/0 pins or through the DEM2-0 bits in the ADC Control Byte (#1). The CALP bit in the
DAC Control Byte (#2). The default state on ADC Control Byte is a read only bit indicating
power-up is de-emphasis controlled via the the status of the calibration.
DEM1/0 pins (DEM2-0 bits=0). DEM1/0 pin
control is defined in Table 4. Reset/Power Down is achieved by lowering the
RST pin causing the part to enter power down.
Once RST goes high, the control port is func-
DEM 1 DEM 0 De-emphasis tional and the desired settings should be loaded.
0 0 32 kHz
0 1 44.1 kHz The CS4222 will also enter power down mode if
1 0 48 kHz the master clock source stops for approximately
1 1 OFF 10 µs or if the LRCK is not synchronous to the
master clock. The control port will retain its
Table 4. De-Emphasis filter control
current settings.

Additionally, the PDAD (ADC Control Byte #1)

and PDDA (DAC Control Byte #2) bits can be
used to power down the ADC’s and DAC’s inde-
Gain pendently. If both are set to 1, the CS4222 will
dB power down the entire chip. The control port
will retain its current settings.
T1=50µs
0dB The CS4222 will mute the analog outputs and
enter the power down mode if the supply drops
below approximately 4 volts.
T2 = 15µs
-10dB Power Supply, Layout and Grounding

The CS4222 should be located on the analog

F1 F2 Frequency
ground plane along with associated analog cir-
cuitry and should be positioned near the split
between ground planes (see Figure 11). Prefer-
ably, the device should also have its own power
Figure 10. De-emphasis Curve. plane. The +5V supply should be connected to
the CS4222 via a ferrite bead, positioned closer
than 1" to the device. A single connection be-

16 DS236PP3
 CS4222

tween the CS4222 ground and the board ground

should be positioned as shown in Figure 11. See
the CDB4222 evaluation board data sheet for
recommended layout of the decoupling compo-
nents.

ADC and DAC Filter Response Plots

Figures 12 through 17 show the overall fre-

quency response, passband ripple and transition
band for the CS4222 ADC’s and DAC’s.

> 1/8"

Digital Analog Note that the CS4222

+5V
Ground Ground is oriented with its
Ferrite
Plane Plane digital pins towards the
Bead
digital end of the board.
CS4222

Ground
Connection

CPU & Digital Codec Codec

Logic digital analog
signals signals &
components

Figure 11. Suggested Layout Guideline (See CDB4222 Data Sheet)

DS236PP3 17
 CS4222

Figure 12. ADC Filter Response. Figure 15. DAC Frequency Response.

Figure 13. ADC Passband Ripple. Figure 16. DAC Passband Ripple.

Figure 14. ADC Transition Band. Figure 17. DAC Transition Band.

18 DS236PP3
 CS4222

Memory Address Pointer (MAP) DAC Control Byte (2)

B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
INCR 0 0 0 0 MAP2 MAP1 MAP0 PDDA MUTC MUTR MUTL SOFT 0 RMP1 RMP0
MAP2-MAP0 Register Pointer PDDA Power Down DAC
INCR Auto Increment Control Bit 0 - Normal
1 - Power down
0 - No auto increment
1 - Auto increment on MUTC Controls mute on consecutive zeros
This register defaults to 00h. function
0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros.
Reserved Byte (0)
MUTR-MUTL Mute control bits
0 - Normal output level
This byte is reserved for internal use and must 1 - Selected DAC output muted
be set to 00h for normal operation. SOFT Soft Mute Control
This register defaults to 00h. 0 - Volume control changes, muting and
mute-on-zeros occur with "ramp"
1 - Volume control changes, muting and
ADC Control Byte (1) mute-on-zeros occur on zero crossings
B7 B6 B5 B4 B3 B2 B1 B0
PDAD HPDR HPDL ADMR ADML CAL CALP CLKE
RMP1-0 Soft Volume 0.5 dB step rate
0 - 1 step per 8 LRCK’s
PDAD Power Down ADC 1 - 1 step per 4 LRCK’s
0 - Normal 2 - 1 step per 16 LRCK’s
1 - Power down 3 - 1 step per 32 LRCK’s
HPDR-HPDL High pass filter defeat, right and left This register defaults to 00h.
0 - High pass filters active
1 - High pass filters defeated
ADMR-ADML ADC Muting, right and left
0 - Normal
1 - Output muted
CAL Calibration control bit
0 - Normal operation
1 - Rising edge initiates calibration
The following bits are read only:
CALP Calibration status
0 - Calibration done
1 - Calibration in progress
CLKE Clocking Error
0 - No error
1 - error

This register defaults to 00h.

DS236PP3 19
 CS4222

Output Attenuator Data Byte (3, 4) Converter Status Report Byte (Read Only) (6)
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ACCR ACCL LVR2 LVR1 LVR0 LVL2 LVL2 LVL0
ATT7-ATT0 Sets attenuator level ACCR-ACCL Acceptance bit
0 - No attenuation 0 - ATT7-0 has been accepted
227 - 113.5 dB attenuation 1 - New setting waiting for zero crossing
>227 - DAC muted LVL2-0,LVR2-0 Left and Right ADC output level
ATT0 represents 0.5 dB of attenuation 0 - Normal output levels
1 - -6 dB level
This register defaults to 00h. 2 - -5 dB level
3 - -4 dB level
4 - -3 dB level
5 - -2 dB level
DSP Port Mode Byte (5) 6 - -1 dB level
B7 B6 B5 B4 B3 B2 B1 B0 7 - Clipping
DEM2 DEM1 DEM0 DSCK DDO DDF2 DDF1 DDF0
DEM2-0 Selects de-emphasis control source LVL2-0 and LVR2-0 bits are ’sticky’. They constantly
0 - De-emphasis controlled by pins monitor the ADC output for the peak levels and hold
1 - 44.1 kHz de-emphasis setting the maximum output. They are reset to 0 when read.
2 - 48 kHz de-emphasis setting
This register is read only.
3 - 32 kHz de-emphasis setting
4 - De-emphasis disabled
5 - Not used
6 - Not used
7 - Not used
DSCK Set the polarity of clocking data
0 - Data valid on rising edge of SCLK
1 - Data valid on falling edge of SCLK
DDO Data output format
0 - I2S compatible
1 - Left justified
DDI2-DDI0 Data input format
0 - I2S compatible
1 - Left justified
2 - Right justified, 20-bit
3 - Right justified, 18-bit
4 - Right justified, 16-bit
5 - Not used
6 - Not used
7 - Not used

This register defaults to 00h.

20 DS236PP3
 CS4222

PIN DESCRIPTIONS

NC 1 28 NC
SMUTE 2 27 RST
MCLK 3 26 AOUTL-
LRCK 4 25 AOUTL+
SCLK 5 24 AOUTR+
VD 6 23 AOUTR-
DGND 7 22 AGND
SDOUT 8 21 VA
SDIN 9 20 AINL+
SCL/CCLK 10 19 AINL-
SDA/CDIN 11 18 DEM1
AD0/CS 12 17 AINR+
DEM0 13 16 AINR-
NC 14 15 NC

Power Supply
VA - Positive Analog Power, Pin 21.
Positive analog supply. Nominally +5 volts.

VD - Positive Digital Power, Pin 6.

Positive supply for the digital section. Nominally +5 volts.

AGND - Analog Ground, Pin 22.

Analog ground reference.

DGND - Digital Ground, Pin 7.

Digital ground for the digital section.

Analog Inputs
AINR-, AINR+ - Differential Right Channel Analog Input, Pins 16 and 17.
Analog input connections of the right channel differential inputs. Typically 2 Vrms differential
(1 Vrms for each input pin) for a full-scale analog input signal.

AINL-, AINL+ - Differential Left Channel Analog Input, Pins 19 and 20.
Analog input connections of the left channel differential inputs. Typically 2 Vrms differential
(1 Vrms for each input pin) for a full-scale analog input signal.

DS236PP3 21
 CS4222

Analog Outputs
AOUTR-, AOUTR+ - Differential Right Channel Analog Outputs, Pins 23 and 24.
Analog output connections for the Right channel differential outputs. Nominally 2 Vrms
(differential) for full-scale digital input signal.

AOUTL-, AOUTL+ - Differential Left Channel Analog Outputs, Pins 25 and 26.
Analog output connections for the Left channel differential outputs. Nominally 2 Vrms
(differential) for full-scale digital input signal.

Digital Inputs
MCLK - Master Clock, Pin 3.
Clock source for the delta-sigma modulator sampling and digital filters. The frequency of this
clock must be either 256x, 384x, or 512x Fs.

LRCK - Left/Right Clock, Pin 4.

LRCK determines which channel, left or right, is to be input/output on SDIN/SDOUT.
Although the outputs for each ADC channel are transmitted at different times, Left/Right pairs
represent simultaneously sampled analog inputs. LRCK is an input clock whose frequency
must be equal to Fs.

SCLK - Serial Data Clock, Pin 5.

Clocks the individual bits of the serial data out from SDOUT and in from SDIN.

SDIN - Serial Data Input, Pin 9.

Two’s complement MSB-first serial data of either 16, 18, or 20 bits is input on this pin. The
data is clocked into the CS4222 via the SCLK clock and the channel is determined by the
LRCK clock. The default interface format on power-up is an I2S compatible 20-bit interface.
This may be changed by writing the control port (DSP Port Mode Byte #5).

DEM1, DEM0 - De-Emphasis Select, Pins 18 and 13.

Controls the activation of the standard 50/15 µs de-emphasis filter. 32, 44.1, or 48 kHz sample
rate selection defined in Table 4.

SMUTE - Soft Mute, Pin 2.

SMUTE low activates a muting function for both the left and right channel D/A converter
outputs. Soft muting is achieved by ramping down the volume in 0.5 dB steps until achieving
mute if SOFT bit (DAC Control Byte #2) is set to 0 (default).

Digital Outputs
SDOUT - Serial Data Output, Pin 8.
Two’s complement MSB-first serial data of 20 bits is output on this pin. The data is clocked
out via the SCLK clock and the channel is determined by LRCK.

22 DS236PP3
 CS4222

Control Port Signals

SCL/CCLK - Serial Control Interface Clock, Pin 10.
SCL/CCLK is the serial control interface clock and is used to clock control bits into and out of
the CS4222 This pin should be tied to DGND in stand-alone mode.

AD0/CS - Address Bit/Control Port Chip Select, Pin 12.

In I2C® mode, AD0 is a chip address bit. In SPI mode, CS is used to enable the control port
interface on the CS4222. The CS4222 will enter SPI mode if a negative transition is ever seen
on this pin after power up. This pin should be tied to DGND in stand-alone mode.

SDA/CDIN - Serial Control Data In, Pin 11.

SDA/CDIN is the input data line for the control port interface. This pin should be tied to
DGND in stand-alone mode.

Miscellaneous Pins
RST - Reset, Pin 27.
When low, the CS4222 enters a low power mode and all internal states are reset, including the
control port. When high, the control port becomes operational and normal operation will occur.

NC - No Connect, Pins 1, 14, 15 and 28

These pins are not connected internally and should be tied to DGND to minimize noise
coupling.

PARAMETER DEFINITIONS

Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral
components over the specified bandwidth. Dynamic range is a signal-to-noise measurement
over the specified bandwidth made with a -60dBFS signal. 60dB is then added to the resulting
measurement to refer the measurement to full scale. This technique ensures that the distortion
components are below the noise level and do not affect the measurement. This measurement
technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic
Industries Association of Japan, EIAJ CP-307.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over
the specified bandwidth (typically 20Hz to 20kHz), including distortion components. Expressed
in decibels. ADCs are measured at -1 dBFS as suggested in AES17-1991 Annex A and DACs
are measured at 0 dBFS.

DS236PP3 23
 CS4222

Idle Channel Noise / Signal-to-Noise-Ratio

The ratio of the rms analog output level with 1kHz full scale digital input to the rms analog
output level with all zeros into the digital input. Measured A-weighted over a 10Hz to 20kHz
bandwidth. Units in decibels. This specification has been standardized by the Audio
Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has
also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and
referred to as Signal-to-Noise-Ratio.

Total Harmonic Distortion (THD)

THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the
test signal. Units in decibels.

Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the converter’s output
with no signal to the input under test and a full-scale signal applied to the other channel. Units
in decibels.

Frequency Response
A measure of the amplitude response variation from 20Hz to 20kHz relative to the amplitude
response at 1kHz. Units in decibels.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units are in decibels.

Gain Error
The deviation from the nominal full scale output for a full scale input.

Gain Drift
The change in gain value with temperature. Units in ppm/°C.

Offset Error
For the ADCs, the deviation in LSB’s of the output from mid-scale with the selected inputs tied
to a common potential. For the DAC’s, the differential output voltage with mid-scale input
code. Units are in volts.

24 DS236PP3
 CS4222

PACKAGE DIMENSIONS

E SSOP Package
Dimensions

1 2 3

TOP VIEW

D1 E 11

A2 A

A1
e L
Seating END VIEW
b2
Plane
SIDE VIEW
MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX Note
Notes: A - - 2.13 - - 0.084
1. "D" and "E 1 " are reference datums A1 0.05 0.15 0.25 0.002 0.006 0.010
and do not include mold flash or A2 1.62 1.75 1.88 0.064 0.070 0.074
protrusions, but do include mold
b 0.22 0.30 0.38 0.009 0.012 0.015 2, 3
mismatch and are measured at the
parting line, mold flash or protrusions D see other table see other table 1
shall not exceed 0.20mm per side. E 7.40 7.80 8.20 0.291 0.307 0.323
2. Dimension b does not include E1 5.00 5.30 5.60 0.197 0.209 0.220 1
dambar protrusion/intrusion. e 0.61 0.65 0.69 0.024 0.026 0.027
Allowable dambar protrusion shall L 0.63 0.90 1.03 0.025 0.035 0.040
be 0.13mm total in excess of b N see other table see other table
∝
dimension at maximum material
0° 4° 8° 0° 4° 8°
condition. Dambar intrusion shall
not reduce dimension b by more than
0.07mm at least material condition. D
3. These dimensions apply to the flat MILLIMETERS INCHES
section of the lead between 0.10 and N MIN NOM MAX MIN NOM MAX Note
0.25mm from lead tips. 20 6.90 7.20 7.50 0.272 0.283 0.295 1
28 9.90 10.20 10.50 0.390 0.402 0.413 1

DS236PP3 25