DELAY

3.1 Introduction
The two most common metrics for a good chip are speed and power. Delay and power are
influenced as much by the wires as by the transistors.
Definitions
Propagation delay time, tpd = maximum time from the input crossing 50% to the output crossing
50%
Contamination delay time, tcd = minimum time from the input crossing 50% to the output
crossing 50%
Rise time, tr = time for a waveform to rise from 20% to 80% of its steady-state value
Fall time, tf = time for a waveform to fall from 80% to 20% of its steady-state value
Edge rate, trf = (tr + tf)/2

Figure 3.1 Propagation delay and rise/fall times

Rise/fall times are also sometimes called slopes or edge rates. Propagation and contamination
delay times are also called max-time and min-time, respectively. The gate that charges or
discharges a node is called the driver and the gates and wires being driven are called the load.
Propagation delay is usually the most relevant value of interest, and is often simply called delay.
Timing analyzer
A timing analyzer computes the arrival times, i.e., the latest time at which each node in a block
of logic will switch. The nodes are classified as inputs, outputs, and internal nodes. The user
must specify the arrival time of inputs and the time data is required at the outputs. The arrival
time ai at internal node i depend on the propagation delay of the gate driving i and the arrival
times of the inputs to the gate:

The timing analyzer computes the arrival times at each node and checks that the outputs arrive
by their required time. The slack is the difference between the required and arrival times.
Positive slack means that the circuit meets timing. Negative slack means that the circuit is not
fast enough. Figure 3.2 shows nodes annotated with arrival times. If the outputs are all required
at 200ps, the circuit has 60 ps of slack.

Figure 3.2 Arrival time example

Timing Optimization
In most designs there will be many logic paths that do not require any conscious effort when it
comes to speed. These paths are already fast enough for the timing goals of the system.
However, there will be a number of critical paths that limit the operating speed of the system and
require attention to timing details. The critical paths can be affected at four main levels:
 The architectural/micro architectural level
 The logic level
 The circuit level
 The layout level
Transient Response:
The most fundamental way to compute delay is to develop a physical model of the circuit of
interest, write a differential equation describing the output voltage as a function of input voltage
and time, and solve the equation. The solution of the differential equation is called the transient
response, and the delay is the time when the output reaches VDD /2. The differential equation is
based on charging or discharging of the capacitances in the circuit. The circuit takes time to
switch because the capacitance cannot change its voltage instantaneously. If capacitance C is
charged with a current I, the voltage on the capacitor varies as:

Every real circuit has some capacitance. In an integrated circuit, it typically consists of the gate
capacitance of the load along with the diffusion capacitance of the driver’s own transistors wires
that connect transistors together often contribute the majority of the capacitance. The transistor
current depends on the input (gate) and output (source/drain) voltages.
Figure 3.3(a) shows an inverter X1 driving another inverter X2 at the end of a wire. Suppose a
voltage step from 0 to VDD is applied to node A and we wish to compute the propagation delay,
tpdf , through X1, i.e., the delay from the input step until node B crosses VDD/2.
These capacitances are annotated on Figure 3.3(b). There are diffusion capacitances between the
drain and body of each transistor and between the source and body of each transistor: Cdb and
Csb . The gate capacitance Cgs of the transistors in X2 are part of the load. The wire capacitance
is also part of the load. The gate capacitance of the transistors in X1 and the diffusion
capacitance of the transistors in X2 do not matter because they do not connect to node B. The
source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and
thus do not contribute to the switching capacitance. It is also irrelevant whether the second
terminal of each capacitor connects to ground or power because both are constant supplies, so for
the sake of simplicity, we can draw all of the capacitors as if they are connected to ground.
Figure 3.3(c) shows the equivalent circuit diagram in which all the capacitances are lumped into
a single Cout
 Figure 3.3 Capacitances for inverter delay calculations
Before the voltage step is applied, A = 0. N1 is OFF, P1 is ON, and B = VDD. After the step, A
= 1. N1 turns ON and P1 turns OFF and B drops toward 0. The rate of change of the voltage VB
at node B depends on the output capacitance and on the current through N1:

Suppose the transistors obey the long-channel models. The current depends on whether N1 is in
the linear or saturation region. The gate is at VDD, the source is at 0, and the drain is at VB.
Thus, Vgs = VDD and Vds = VB. Initially, Vds = VDD > Vgs – Vt , so N1 is in saturation. As
VB falls below VDD – Vt , N1 enters the linear region. Substituting EQ (2.10) and rearranging,
we find the differential equation governing VB. During saturation, the current is constant and VB
drops linearly until it reaches VDD Vt . Thereafter, the differential equation becomes nonlinear.

In a real circuit, the input comes from another gate with a nonzero rise/fall time. This input can
be approximated as a ramp with the same rise/fall time. Let us consider a rising ramp and a
falling output and examine how the nonzero rise time affects the propagation delay. Assuming
Vtn + |Vtp| < VDD, the ramp response includes three phases, as shown in Table 4.1. When A
starts to rise, N1 remains OFF and B remains at VDD. When A reaches Vtn, N1 turns ON. It
fights P1 and starts to gradually pull B down toward an intermediate. When A gets close enough
to VDD, P1 turns OFF and B falls to 0 unopposed. Thus, we can write the differential equations
for VB in each phase:

Table 3.1 Phases of inverter ramp response

RC Delay Model
RC delay model should be developed to estimate the delay of logic gates. The RC delay model
treats a transistor as a switch in series with a resistor.
Effective Resistance
A unit nMOS transistor is defined to have effective resistance R. An nMOS transistor of k times
unit width has resistance R/k because it delivers k times as much current. A unit pMOS transistor
has greater resistance, generally in the range of 2R–3R, because of its lower mobility. An pMOS
transistor of k times unit width has resistance 2R/k because it delivers k times as much current.
Gate and Diffusion Capacitance
Each transistor also has gate and diffusion capacitance. A transistor of k times unit width has
capacitance kC. Diffusion capacitance depends on the size of the source/drain region.
Equivalent RC circuits

Figure 3.5 Equivalent circuits for transistors

 Figure 3.6 Equivalent circuits for an inverter
Example: Sketch a 3-input NAND gate with transistor widths chosen to achieve effective rise
and fall resistance equal to that of a unit inverter (R). Annotate the gate with its gate and
diffusion capacitances. Assume all diffusion nodes are contacted. Then sketch equivalent circuits
for the falling output transition and for the worst-case rising output transition
 Figure 3.7 Equivalent circuits for a 3-input NAND gate
Elmore Delay
The Elmore delay model estimates the delay from a source switching to one of the leaf nodes
changing as the sum over each node i of the capacitance Ci on the node, multiplied by the
effective resistance Ris on the shared path from the source to the node and the leaf.

1. Compute the Elmore delay for Vout in the 2nd order RC system

Solution:
The Elmore delay, tpd = R1C1 + (R1 + R2)C2
2. Estimate tpd for a unit inverter driving m identical unit inverters.
Solution:
The Elmore delay is tpd = (3 + 3m)RC.
3. Repeat Example 2 if the driver is w times unit size.

Solution:
The Elmore delay is tpd = ((3w + 3m)C)(R/w) = (3 + 3m/w)RC
Let h = m/w
Where h represents fanout of the gate, which is defined as the ratio of the load capacitance to the
input capacitance.
Therefore Elmore delay is tpd (3 + 3h)RC.
4. If a unit transistor has R = 10 kΩ and C = 0.1 fF in a 65 nm process, compute the delay, in
picoseconds, of the inverter in Figure with a fanout of h = 4.

Solution:
The RC product in the 65 nm process is (10 kΩ) (0.1 fF).For h=4 the delay is (3 + 3h)(1 ps) = 15
ps.
5. Estimate tpdf and tpdr for the 3-input NAND gate if the output is loaded with h identical
NAND gates.
Solution:
a)The Elmore delay for the falling output is the sum of these RC products, tpdf = (3C)(R/3) +
(3C)(R/3 + R/3) + ((9 + 5h)C)(R/3 + R/3 + R/3) = (12 + 5h)RC.
b)The Elmore delay for the rising output is tpdr = (15 + 5h)RC
Note: The relevant resistance is only R, not (R + R/3), because the output is being charged only
through R.

Linear delay Model

Delay of a gate can be expressed as two components
d=f+p
p is the parasitic delay inherent to the gate when no load is attached.
f is the effort delay or stage effort that depends on the complexity and fanout of the gate
f = gh
where g=logical effort
h=electrical effort or fan-out
Logical effort(g) of a gate is defined as the ratio of the input capacitance of the gate to the input
capacitance of an inverter that can deliver the same output current.
Electrical effort or fanout(h) is defined as the ratio of the output capacitance of the gate to the
input capacitance.
h=cout/cin
The parasitic delay(p) of a gate is the delay of the gate when it drives zero load.
 Table 3.2 Logical effort of common gates
Gate Type Number of Inputs
inverter 1 2 3 4 n
NAND 4/3 5/3 6/3 (n + 2)/3
NOR 5/3 7/3 9/3 (2n + 1)/3

Table 3.3 parasitic delay of common gates

Gate Type Number of Inputs
inverter 1 2 3 4 n
NAND 2 3 4 n
NOR 2 3 4 n

Example. Use the linear delay model to estimate the delay of the fanout-of-4 (FO4) inverter
Solution: The logical effort of the inverter is g = 1. The electrical effort is 4 because the load is
four gates of equal size. The parasitic delay of an inverter is p=1.
The total delay is d = gh + p = 1 × 4 + 1 = 5
Linear delay in multistage logic networks
Figure 4.29 shows the logical and electrical efforts of each stage in a multistage path as a
function of the sizes of each stage. The path of interest is marked with the dashed blue line. From
figure it is observed that logical effort is independent of size, while electrical effort depends on
sizes.

Figure 3.8 Multistage logic network

The path logical effort G can be expressed as the products of the logical efforts of each stage
along the path.

The path electrical effort H can be given as the ratio of the output capacitance the path must
drive divided by the input capacitance presented by the path.
The path effort F is the product of the stage efforts of each stage.