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DAC Analysis
DAC Analysis
Applications
-
Multistep ADCs
High-Resolution Displays
Waveform Synthesis
Complex Modulation Formats
Instrumentation
Storage of Analog Info in Digital Form
Basics
D
(m bits)
DA
C
A=D
D is dimensionless sets both the full scale and the dimension of A.
Example: = IREF A = IREF D
= VREF A = VREF D
For voltages, its easier to generate fractions of VREF rather than its
multiples:
A = (VREF/2m)* D
D/A conversion can be viewed as a reference division or multiplication function. The precision is determined by how accurately the
reference is multiplied or subdivided, and the speed depends on how
fast each level can be selected and established at the output.
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Digital Codes
Four types of digital codes are frequently used in D/A and A/D
converters
The difference between the characteristic and the straight line is called
the INL profile.
- Settling Time is the time required for the output to experience a fullscale transition and settle within a specified error band around its final
value.
- Glitch Impulse Area is the maximum area under any extraneous glitch
that appears at the output after the input code changes.
- SNDR is the ratio of the signal power to the total noise and harmonic
distortion at the output when the input is a digital sinusoid.
DAC Analysis Procedure:
1. Understand how a voltage, current, or charge reference can be
divided or multiplied.
2. Analyze the sources of nonlinearity (gradients, mismatches, ...).
3. Analyze speed limitations.
R
m
2 R/4
Vout
R
Vref/2
R
m bits
1-of-n code
silicide
Binary
Iout
Iref
I1
Current-steering
DAC
Binary
I2
That is,
8C
Vout
4C
2C
Segmented Array:
Vout
C
C
Reset switch
Vref
Vref
Vref
Vref
Thermometer Code
- DNL is small; only one cap is added from one code to next.
- Unconditionally monotonic
Sources of Nonlinearity
Capacitor Mismatch
Capacitor Nonlinearity
Nonlinearity of Junction Cap. of Reset switch
1. Capacitor Mismatch
W
L
tox
C = W*L*/tox
C/C = W/W + L/L - tox/tox
How to choose W and L?
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Important Note:
Q(V) C(V) V for a nonlinear cap.
Rather:
Vout
Reset
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DAC Architectures
Ladder with Switched Subdivider
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Current-Steering Architectures
1. Fully-Segmented Architecture
Issues:
o How to perform binary-thermometer code conversion to
minimize routing and capacitance on output node?
o How to partition into segmented and binary? <= 4 bits
Matrix Architecture
Matching Considerations
Required Matching for DACs: [Bastos, JSSC, Dec. 98]
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