CPE 169 EXPERIMENT NINE

TITLE: FINITE STATE MACHINE DESIGN USING VHDL

TIME: 180 MINUTES
AUTHOR: B. Mealy, A. Liddicoat
UPDATE: September 12, 2003

HARDWARE: Pentium 4 Computer

SOFTWARE: Xilinx ISE Foundation Series Software
COMPONENTS: Digilab XCR Plus Development Board

Purpose

To use the Xilinx ISE Foundation Series Software to design and implement finite state machines
(FSMs).To introduce the Xilinx StateCAD software for use in implementing FSMs. To introduce
the dependent PS/NS style for describing FSMs using VHDL behavioral modeling.

Introduction

Experiment 8 used VHDL behavioral modeling to implement single-bit storage elements. These simple
sequential circuits were used in the construction of a 4-bit loadable shift register. This experiment shows
how similar storage elements are used to store state variables in finite state machines (FSMs). This
experiment introduces two different approaches to designing FSMs.

The first FSM design technique uses the Xilinx StateCAD software. In this approach, the software allows
the state diagram to be entered graphically onto the workspace. The software allows for pertinent options
such as asynchronous inputs, parallel loading, state variable encoding techniques etc. VHDL code is
generated from the graphical representation of the FSM. This VHDL code can be synthesized in a process
similar to the design methodologies presented in previous experiments.

The second FSM design technique essentially extends the basic storage cell presented in Experiment 8. In
this approach, VHDL behavioral modeling is used to implement a FSM using a dependent PS/NS style. The
resulting VHDL code is then processed similar to previous design methodologies.

Both of the two FSMs designed in this experiment are simple counter circuits. The inputs are limited to
asynchronous state variable clearing and counting enables. The outputs are comprised of terminal count
signals and the state variables. A short explanation of the StateCAD software is presented as well as a
description of VHDL behavioral modeling using the dependent PS/NS style of FSM design.

FSM Design using VHDL Behavioral Modeling

This section provides an introduction to implementing FSMs using VHDL behavioral models. Although
there are several styles for implementing FSMs using VHDL, this introduction only covers the dependent
PS/NS style. The focused is further narrowed by only discussing FSMs with Moore-type outputs. Further
information describing FSM implementation is found in the class text.
The design of FSMs begins where the design of sequential circuit elements from Experiment 8 leaves off.
Relatively complex FSMs can be designed by adding a few concepts with the description of the basic
storage element of the previous experiment. The first concept to explore is the relation between the standard
block diagram of a Moore-type FSM and its VHDL equivalent.

A block diagram for a standard Moore-type FSM is shown in Figure 1. The next state decoder is a block of
combinatorial logic that uses the current external inputs and the current state of the FSM to choose the next
state of the FSM. In other words, the inputs to this block are decoded and to produce an output that
represents the next state of the FSM. The next state becomes the present state of the FSM when the clock
input to the state registers block becomes active. The state registers block contains storage elements that
store the present state of the machine. The inputs to the output decoder are are decoded via combinatorial
logic to produce the external outputs. Because the external outputs are only dependent upon the current
state of the machine, this FSM is classified as a Moore FSM.

Figure 1: Diagram of a Moore-type FSM.

Although it does not look much clearer, you’ll soon find the FSM model shown in Figure 2 to be a straight-
forward method to implement FSMs. The approach we will use divides the FSM into two VHDL processes.
One process, the Synchronous Process, handles all the matters regarding clocking and other controls
associated with the storage element. The other process, the Combinatorial Process, handles all the matters
associated with the Next State Decoder and the Output Decoder of Figure 1. Note that these two blocks in
Figure 1 are both comprised of combinatorial logic.

There is some new lingo used in the description of signals used in Figure 2. The inputs labeled Parallel
Control are used to signify inputs that act in parallel to each of the storage elements. These inputs would
include enables, presets, clears, etc. The inputs labeled State Transition Control include external inputs that
control state transitions. The other inputs and outputs shown in Figure 2 are self-explanatory in nature.

Figure 2: Diagram for the dependent PS/NS FSM style.

The best approach to learning how to design FSMs using the PS/NS style is by examining an exa mple. The
example used for this purpose is shown in Figure 3. The state diagram is shown in Figure 3(a) and the
associated black box is shown in Figure 3(b). The VHDL code that implements this FSM is shown in Figure
4.

(a) (b)

Figure 3: State diagram and black box diagram of learning exampl e.

entity fsm_ex1 is
port ( TOG_EN : in std_logic;
CLK : in std_logic;
RESET : in std_logic;
Y : out std_logic;
Z1 : out std_logic);
end fsm_ex1;
architecture fsm_ex1 of my_fsm_ex1 is
type state_type is (ST0,ST1);
signal PS,NS : state_type;
begin
sync_proc: process(CLK,NS,CLR)
begin
-- asynchronous input
if (RESET = ‘1’) then PS <= ST0;

-- the synchrous input

elsif (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_proc;

comb_proc: process(PS,TOG_EN)
begin
case PS is
when ST0 => -- items regarding state ST0
Z1 <= ‘1’; -- Moore output
if (TOG_EN = ‘1’) then NS <= ST1; -- transition control
else NS <= ST0;
end if;
when ST1 => -- items regarding state ST1
Z1 <= ‘0’; -- Moore output
if (TOG_EN = ‘1’) then NS <= ST0; -- transition control
else NS <= ST1;
end if;
end case;
end process comb_proc;

-- external state assignment

with PS select
Y <= ‘0’ when ST0,
‘1’ when ST1,
‘0’ when others;

end fsm_ex1;

Figure 4: The VHDL code for the learning example.

There are many things worth noting in the VHDL code shown in Figure 4. Some of the more interesting
things are listed below.

• A special VHDL type is used to represent the states. This is an example of how VHDL handles
enumeration types found in standard programming languages. There is an internal numerical
representation for the listed state types but we only deal with the more expressive textual
equivalent.

• The synchronous process is equal in form and function to the simple D flip-flops used in
Experiment 8. The only difference is that PS and NS is substituted for D and Q, respectively.
 • Even though this is about the simplest FSM you could hope for, the code looks somewhat
complicated. But if you examine it closely, you can see that everything is nicely compartmentalized
in the solution. The synchronous process handles the asynchronous reset and the assignment of a
new state upon the arrival of the system clock. The combinatorial process handles the outputs not
handled in the synchronous process, the outputs, and the generation of the next state of the FSM.

• Because the two processes operate concurrently, they can be considered as working in a lock-step
manner. Changes to the NS signal that are generated in the combinatorial process forces an
evaluation of the synchronous process. When the changes are actually instituted in the
synchronous process on the next clock edge, the changes in the PS signal causes the
combinatorial process to be evaluated.

• The case statement in the combinatorial process provides a when clause for each state of the FSM.
This is the standard approach for the dependent PS/NS coding style.

• The Moore output is a function of only the present state. This is expressed by the fact that the
assignment of the Z1 output is unconditionally evaluated in each when clause of the case
statement in the combinatorial process.

• A selective signal assignment statement is used to assign a value to the state variable output Y
based on the condition of the state variable. The selective signal assignment statement is
evaluated each time a change in signal PS is detected.

Remember, there are three concurrent statements in the VHDL code shown in Figure 4: two process
statements and a selective signal assignment statement. These three statements execute concurrently.
Execution is initiated based a changes in the signals in the sensitivity list for the processes or a changes in
the argument for the selective signal assignment statement.

Procedures

The procedures in this experiment involve designing, implementing, and testing two FSMs using two
different approaches. In the first procedure, the Xilinx StateCAD program is used as a tool to generated
VHDL code for a simple counter. In the second procedure, the VHDL code is written directly using a
dependent PS/NS style. The methodology used to test and implement these FSMs are is similar to previous
experiments.

P1 FSM Design with StateCAD

1. Figure 5(a) provides an abbreviated state stable description of a 2-bit upcounter. On a separate
sheet of paper, draw a state diagram of this FSM and include it with your final report. The CLR
signal is an asynchronous reset and RCO is a Moore-type output that indicates when the counter
has reached its maximum count.

2. Use StateCAD to design the 2-bit binary counter described in Figure 5. Signals Y1 and Y0 are the
state variables and reflect the present state of the FSM. Use the state assignments A=00, B=01,
C=10, and D=11 in your design. The StateCAD software is user-friendly and basically involves
graphical entry of a state diagram. A general set of StateCAD software highlights and possible
 sticking points are described in the following rough set of instructions. Include a printout your
FSM from the StateCAD program in your lab report.

• Use the Add State icon to add required states to the StateCAD working area.
• Use the Add Transition icon to add appropriate transitions between states.

• Use the Add Reset icon to add reset conditions where required.

• Conditions directing the state transitions are entered by double-clicking on the transition lines
and entering the correct information into the Edit Conditions dialog box.

• State name and outputs associated with states are added by right-clicking on the states and
entering the appropriate information in to the Edit State pop-up window under the State Name
and Outputs fields. The FSM described in the procedure is a Moore-type FSM. Assign the
state names as A, B, C, and D. Provide the associated outputs as !Y1 !Y0, !Y1 Y0, etc.

• The RCO condition is provided in the final state only. Not including the RCO variable in the
other states causes the RCO output to default to 0.

• Select OptionsàConfiguration and select the Binary Encoded radio button in the State
Assignment portion of the Configuration pop-up window.

• Compile your schematic by clicking on the Generate HDL menu option.

3. Use the TestBencher to generate test vectors for the FSM and verify proper operation with the
ModelSim XE simulator.

4. Create a constraints file according to the pin assignments shown in Table 1.

5. Download your design to the Digilab XCR Plus development board. Demonstrate your working
design to the lab instructor.

CLR CNT PS NS RCO

1 - - A 0
0 0 A A 0
0 1 A B 0
0 0 B B 0
0 1 B C 0
0 0 C C 0
0 1 C D 0
0 0 D D 1
0 1 D A 1

(a) (b)
 Figure 5: State table and black box diagram for FSM of P1.

Inputs Outputs
FSM Signal CLR CNT CLK Y1 Y0 RCO
Digilab XCR BTN1 BTN2 CLK LD1 LD2 LD8

Table 1: Input and output assignments for the Digilab XCR Plus development board.

P2 FSM Design Using VHDL Behavioral Modeling

1. Using VHDL behavioral modeling and the dependent PS/NS style, design the FSM described in
Figure 6. This FSM is a 2-bit down-counter with the count represented by the state variables Y2
and Y1. The START signal is an asynchronous set and TC is a Moore-type output that indicates
when the counter has reached its minimum count.

2. Use the TestBencher to generate test vectors for the FSM and verify proper operation with the
ModelSim XE simulator.

3. Create a constraints file according to the pin assignments shown in Table 2.

4. Download your design to the Digilab XCR Plus development board. Demonstrate your working
design to the lab instructor.

(a) (b)
 Figure 6: State diagram and black box diagram for FSM of P2.

Inputs Outputs
FSM Signal CLR dcnt CLK Y2 Y1 TC
Digilab XCR BTN1 BTN2 CLK LD1 LD2 LD8

Table 2: Input and output assignments for the Digilab XCR Plus development board.

P3 Conclusions

Each group member should provided a summary and conclusion of the topics presented in this experiment.