ECE 621

Signaling & Synchronization

Fall 2017
Topic 4
RX Circuitry
Sameh A. Ibrahim
Ain Shams University
ICL
(Courtesy of S. Pamarti – UCLA, S. Palermo – TAMU,
E. Alon – UCB, and D. Allstot – UW)
 Outline

 RX Overview
▪ Parameters
▪ Architecture choices
 RX Amplifiers
▪ Pre-amplifiers
▪ Bandwidth extension techniques
 Clocked Comparators
▪ Circuits
▪ Characterization techniques
 Demultiplexing
 RX Sensitivity
▪ Offset
▪ Noise

RX Circuitry 2
 Receiver Block Diagram

 Goals
▪ High bit rate
▪ Low power consumption
▪ Low BER
• Good voltage/current and timing margins

RX Circuitry 3
 Receiver Components
 Pre-amplifier
▪ Compensates for average channel loss (not equalization).
▪ Can be used also for equalization, offset correction, and fix
sampler common-mode.
▪ Must provide gain at high-bandwidth corresponding to full
data rate.
 Sampler / Slicer
▪ Extracts the data from the received signal.
▪ Can be implemented with static amplifiers or clocked-
regenerative amplifiers
• Clock regenerative amplifiers are more power efficient.
 De-multiplexer
▪ Separate data to supply multiple, slower, data destinations.
RX Circuitry 4
 Receiver Parameters
 RX sensitivity, offsets in voltage and time domain, and
aperture time are important parameters
 Minimum eye width is determined by aperture time plus
peak-to-peak timing jitter.
 Minimum eye height is determined by sensitivity plus
peak-to-peak voltage offset.

RX Circuitry 5
 Receiver Architecture Choices

 Option 1
▪ If wide bandwidth, high gain pre-amplifier is available.
 Option 2
▪ If received signal is large, or
▪ If wide bandwidth, high gain pre-amplifier is unavailable.
 Option 3
▪ Very low received signal
▪ Wide bandwidth, but low gain pre-amplifier
RX Circuitry 6
 Outline

 RX Overview
▪ Parameters
▪ Architecture choices
 RX Amplifiers
▪ Pre-amplifiers
▪ Bandwidth extension techniques
 Clocked Comparators
▪ Circuits
▪ Characterization techniques
 Demultiplexing
 RX Sensitivity
▪ Offset
▪ Noise

RX Circuitry 7
 Pre-Amplifier Goals

 Provide a large swing input to the sampler/slicer.

 Filter noise outside the received signal bandwidth.
 Issues
▪ Power consumption
▪ Input offset and its variability
▪ High frequency operation

RX Circuitry 8
 A Simple Single-Ended Pre-Amplifier

 CMOS inverter is one of the simplest RX pre-amplifiers.

 Termination voltage, VTT, should be placed near
inverter trip point.
 Issues
▪ Limited gain (<20)
▪ High PVT variation results in large input referred offset.
▪ Single-ended operation makes it both sensitive to and
generate supply noise.

RX Circuitry 9
Schmitt Trigger Single-Ended Pre-Amplifier

 Different thresholds for pull-down and pull-up

▪ Better noise margin than the inverter
 Reduced sensitivity to high frequency input noise
▪ Due to hysteresis of the Schmitt trigger
 Still difficult to operate at high data rates
▪ The switching thresholds still vary with process, voltage,
and temperature
RX Circuitry 10
 Differential Pre-Amplifiers
 Differential input amplifiers often used
as input stage in high performance
serial links.
▪ Rejects common-mode noise.
▪ Sets input common-mode for the
comparator.
 Input stage type (n or p) often set by
termination scheme
 High gain-bandwidth product necessary
to amplify full data rate signal
 Offset correction and equalization can
be merged into the input amplifier.
 Can be used for single-ended RX.
 Output is not fully rail-to-rail.
▪ Can cascade stages for more gain.
 Sensitive to supply noise variations
RX Circuitry 11
 Current Mode Diff. Pre-Amps

[Ishibe, JSSC Apr. 1992]

 Input currents are amplified and subtracted from each

other using current mirrors.
▪ Useful when series termination is used on the receiver.
▪ Gain is obtained from current mirror ratio.
▪ I–V conversion gain depends on rds of transistors.
 T-line sees R= 1/gm.
▪ PVT variations.
▪ 1/gm> 50 Ohms is likely
RX Circuitry 12
 Reducing Rin in Current Mode Pre-Amps

 Negative feedback can be used to reduce Rin.

 Maintaining loop gain at high frequencies would be

power hungry.

RX Circuitry 13
 Bandwidth Extension: Terminology
 BW extension ratio (BWER) = f3dB, ext / f3dB, ref
 Settling Time (1%) reduction ratio (STRR) = 𝝉s, ref / 𝝉 s, ext
 Rise Time (10-90%) reduction ratio (RTRR) = 𝝉 r, ref / 𝝉 r, ext
 BWER, STRR & RTRR hard to maximize simultaneously.
▪ Optimize for desired application.

RX Circuitry 14
 BW Extension: Shunt Peaking

R  sL m = 2 → 1.84X & 1.5dB Peaking

Z( s ) 
1  sRC  s 2 LC • Introduces a pole-zero pair.
R 2C 1
m 0  • L improves impedance with freq.
L RC
1  s / m 0
Z N ( s) 
1  s / 0  s 2 / m02
RX Circuitry 15
 BW Extension: Bridged Shunt Peaking

 1  s  kB  s
2
1    2
Z N ( s) 
m 
  0  m  0
s  kB  1  s 2  kB  s 3
1    
0  m  02  m  03
m = 2.4, kB = 0.3 → 1.83X flat
• CB is inductor parasitics.
R 2C 1 CB
m 0  kB 
L RC C

RX Circuitry 16
 Bridged-Shunt Peaking Advantages

 Incorporates inductor parasitics (Add more CB if

needed).
 Maximum BW possible with flat gain (No 1.5dB peaking)
 m ↑, L↓ → Smaller Area
 Area overhead for added CB minimal

RX Circuitry 17
BW Extension: Series Peaking
1 R 2C 1
Z N ( s)  m 0 
1  s / 0  s 2 / m02 L RC

• Lack of zero
• Inferior to shunt peaking
• m = 2 → 1.41x
Z N ( s) 
1 C1
s  1  kC  s 2  kC (1  kC )  s 3
kC 
1     3 C
0  m  02  m  0

• Extra Pole

RX Circuitry 18
Bridged-Shunt-Series Peaking

RX Circuitry 19
BW Extension: Symmetric T-Coil

• L1=L2
• Maximum flat BW
• m = 2, k=-1/2 → 2.83x

RX Circuitry 20
BW Extension: Asymmetric T-Coil
C1 km  M / L1 L2
kC 
C
R 2C R 2C
m1  m2 
L1 L2

kC km m1 m2 STRR RTRR BWER

0.7 4.0 1.6 1.90 4.20 4.63
0.6 3.5 1.6 1.32 4.50 4.92
0.1
0.6 3.5 1.2 1.57 4.43 5.59
0.7 4.1 1.6 2.91 4.19 4.66
0.6 5.5 2.4 1.94 3.39 4.14
0.6 3.0 2.0 1.23 3.91 4.51
0.2
0.5 4.0 2.4 1.42 3.80 4.86
0.7 4.6 2.2 4.11 3.35 3.34
0.5 4.0 2.8 1.54 3.40 3.93
0.4 3.5 2.0 1.09 3.45 3.98
0.3
0.4 4.0 2.8 1.10 3.52 4.54
0.6 5.0 2.6 3.70 3.06 3.07

RX Circuitry 21
 BW Extension: Negative capacitance

 Active reduction of capacitance

▪ Use positive feedback to obtain effective negative
capacitance.
 Have to sustain loop gain past the signal bandwidth.
▪ Difficult and/or power hungry

RX Circuitry 22
 Outline

 RX Overview
▪ Parameters
▪ Architecture choices
 RX Amplifiers
▪ Pre-amplifiers
▪ Bandwidth extension techniques
 Clocked Comparators
▪ Circuits
▪ Characterization techniques
 Demultiplexing
 RX Sensitivity
▪ Offset
▪ Noise

RX Circuitry 23
 RX Clocked Comparators
 Also called regenerative amplifier, sense-amplifier, flip-
flop, latch.
 Samples the continuous input at clock edges and resolves
the differential to a binary 0 or 1.
 Characteristics
▪ Offset and hysteresis (hysteresis is data dependent)
▪ Sampling aperture, timing resolution, uncertainty window
▪ Regeneration gain, voltage sensitivity, metastability
▪ Random decision errors, input-referred noise

RX Circuitry 24
 Regenerative Latch Basics

 Operation
▪ Track phase: Some amplification is achieved (normal
and regenerative)
▪ Hold/Reset phase: In some versions, more amplification
(+ve feedback) is achieved. In other versions, the held
value is reset.
 Requirements
▪ Low input capacitance
▪ Small setup-hold window, high sampling bandwidth
▪ Low power consumption
RX Circuitry 25
 Dynamic Comparator Circuits

Strong-Arm Latch CML Latch

 To form a flip-flop
▪ After strong-arm latch, cascade an R-S latch
▪ After CML latch, cascade another CML latch
 Strong-Arm flip-flop has the advantage of no static
power dissipation and full CMOS output levels.

RX Circuitry 26
 StrongARM Latch Operation

 4 operating phases: reset, sampling, regeneration, and

decision

RX Circuitry 27
 StrongARM Latch: Sampling Phase
 Sampling phase starts when
clk goes high, t0, and ends
when PMOS transistors turn
on, t1.
 M1 pair discharges X/X’.
 M2 pair discharges out+/-.

RX Circuitry 28
 StrongARM Latch: Regeneration
 Regeneration phase starts
when PMOS transistors turn
on, t1, until decision time, t2.
 Assume M1 is in linear region
and circuit no longer sensitive
to vin.
 Cross-coupled inverters
amplify signals via positive-
feedback:

RX Circuitry 29
 Conventional RS Latch

 RS latch holds output data

during latch pre-charge
phase.

-∆𝑽 +∆𝑽

 Conventional RS latch
rising output transitions 1 1 0
first, followed by falling
transition.
1 0 0 1

RX Circuitry 30
 Optimized RS Latch

 Optimizing RS latch for

symmetric pull-up and pull-
down paths allows for
considerable speed-up.
 During evaluation, large driver
transistors are activated to
change output data and the
keeper path is disabled.
 During pre-charge, large driver
transistors are tri-stated and
small keeper cross-coupled
inverter activated to hold data.
[Nikolic, JSSC Jun. 2000] Drivers Keepers
RX Circuitry 31
 CML Latch Operation

 At the beginning of regeneration phase

 Then

RX Circuitry 32
Comparison of SA and CML Comparator (1)

 CML latch has higher sampling gain with small input

pair.
 StrongARM latch has higher sampling bandwidth.
▪ For CML latch increasing input pair also directly
increases output capacitance.
▪ For SA latch increasing input pair results in
transconductance increasing faster than capacitance.
RX Circuitry 33
 Low-Voltage SA (1)

(𝑉𝑂𝑆 𝛼 𝑉𝑂𝑉 )
[Schinkel, ISSCC 2007]
▪ But requires Clk and Clk_b.
RX Circuitry 34
 Low-Voltage SA (2)

[Goll, TCAS-II Nov. 2009]

 Similar stacking to conventional SA latch

 However, now P0 and P1 are initially on during
evaluation which speeds up operation at lower voltages.
 Requires clk & clk_b.
RX Circuitry 35
 Charge-Steering Concept

Vout1, Vout2

VCT
[Razavi, CICC Sep 2013]

 Tail current sources converted into a charge source.

 Two phases: Reset Phase (CK Low) and Amplification Phase (CK
High)
 In Reset phase, CT is discharged and Vout Reset
 In amplification phase, charge redistribution occurs between CD
and CT. Vout difference exists based on Vin.

RX Circuitry 36
 Charge-Steering Comparator

[Jung, JSSC Feb 2015] [Ayesh, MWSCAS Aug 2015]

 Cross-coupled pairs added for regeneration.

 Two-phase design has contention between cross-coupled pair and
differential pair.
 Three-phase design resolves this issue and results in better
sensitivity.
 Overall, low power operation is achieved. (66 μW at 6 GHz with 1-
mV sensitivity)

RX Circuitry 37
 RX Demultiplexing

 Demultiplexing allows
for lower clock
frequency relative to
data rate.
 Gives extra
regeneration and pre-
charge time in
comparators.
 Need precise phase
spacing, but not as
sensitive to duty-cycle
as TX multiplexing.

RX Circuitry 38
 1:4 Demultiplexing

 Increased demultiplexing allows for higher data rate at

the cost of increased input or pre-amp load
capacitance.
 Higher multiplexing factor more sensitive to phase
offsets in degrees

RX Circuitry 39
 Outline

 RX Overview
▪ Parameters
▪ Architecture choices
 RX Amplifiers
▪ Pre-amplifiers
▪ Bandwidth extension techniques
 Clocked Comparators
▪ Circuits
▪ Characterization techniques
 Demultiplexing
 RX Sensitivity
▪ Offset
▪ Noise

RX Circuitry 40
 Receiver Sensitivity
 RX sensitivity is a function of the input referred noise,
offset, and minimum latch resolution voltage.

 Gaussian (unbounded) input referred noise comes

from input amplifiers, comparators, and termination.
▪ A minimum signal-to-noise ratio (SNR) is required for a
given bit-error-rate (BER).
 Minimum latch resolution voltage comes from
hysteresis, finite regeneration gain, and bounded noise
sources.

 Input offset is due to circuit mismatch (primarily Vth

mismatch) & is most significant component if
uncorrected.
RX Circuitry 41
 Latch Resolution
 Taking CML latch as an example

 Define the resolution as the input voltage that yields an

output equal to 80% of the final value.

 Including Hysteresis, worst case resolution becomes

Where
RX Circuitry 42
 RX Sensitivity & Offset Correction
 RX sensitivity is a function of the input referred noise,
offset, and min latch resolution voltage.

 Circuitry is required to reduce input offset from a

potentially large uncorrected value (>50mV) to near
1mV.

RX Circuitry 43
 Input Referred Offset
 The input referred offset is primarily a function of Vth
mismatch and a weaker function of β (mobility) mismatch.

 To reduce input offset 2x, we need to increase area 4x.

▪ Not practical due to excessive area and power consumption.
▪ Offset correction necessary to efficiently achieve good
sensitivity.
 Ideally the offset coefficients are given by the design kit
and Monte Carlo is performed to extract offset sigma.
 Here are some common values:
▪ 𝐴𝑉𝑡 = 1mVµm per nm of tox.
• For 90nm technology, tox=2.8nm → 𝐴𝑉𝑡 ~2.8 mVµm.
▪ Aβ is generally near 2%µm.

RX Circuitry 44
 Offset Correction Range & Resolution
 Generally circuits are designed to handle a minimum
variation range of ±3σ for 99.7% yield.
 Example: Input differential transistors W=4μm, L=150nm

 If we assume (optimistically) that the input offset is only

dominated by the input pair Vt mismatch, we would need
to design offset correction circuitry with a range of about
±11mV.
 If we want to cancel within 1mV, we would need an offset
cancellation resolution of 5bits, resulting in a worst-case
offset of

RX Circuitry 45
 Current-Mode Offset Correction Example
 Differential current injected into
input amplifier load to induce an
input-referred offset that can
cancel the inherent amplifier
offset.
 Can be made with extended
range to perform link margining*.
 Passing a constant amount of
total offset current for all the
offset settings allows for
constant output common-mode
level.
 Offset correction performed both
at input amplifier and in
individual receiver segments of
the 2-way interleaved
architecture. [Balamurugan, JSSC Apr. 2008]
* Introducing offset and get BER to establish an eye.
RX Circuitry 46
 Capacitive Offset Correction Example
 A capacitive imbalance in the
sense-amplifier internal nodes
induces an input-referred offset.
 Pre-charges internal nodes to
allow more integration time for
more increased offset range.
 Additional capacitance does
increase sense-amp aperture
time.
 Offset is trimmed by shorting
inputs to a common-mode
voltage and adjusting settings
until an even distribution of
“1”s and “0”s are observed.
 Offset correction settings can
be sensitive to input common-
mode. [Palermo, thesis 2008]
RX Circuitry 47