TRAINING REPORT

ON
VLSI SoC DESIGN USING VERILOG HDL

Submitted on the completion of summer training from Maven Silicon

(From 5 June, 2021 to 2 July, 2021)
Submitted By – Submitted To -

Anmol singh Dr. Ramnish Kumar

180151520007 Assistant Professor

B.Tech(ECE) 6thSem

Completed under the kind guidance of Dr. Ramnish Kumar ( Assistant Professor )

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGNEERING

GURU JAMBESHWAR UNIVERSITY OF SCIENCE AND TECHNOLOGY,

HISAR
 ABSTRACT
This report focuses on the VERY LARGE SCALE
INTEGRATION(VLSI) SoCDesign using verilog HDL.
Very-large- scale integration (VLSI) is the
process of creating an integrated circuit (IC) by
combining thousands of transistors into a single chip.
VLSI began in the 1970s when
complex semiconductor and communication
technologies were being developed. The
microprocessor is a VLSI device.
The current cutting-edge technologies such as high
resolution and low bit-rate video and cellular
communications provide the end-users a marvelous
amount of applications, processing power and portability.
This trend is expected to grow rapidly, with very
important implications on VLSI design and systems
design.
In this I have tried to explain briefly the basic VLSI
system on chip designing using verilog HDL. Starting
with the introduction to VLSI, we will see the overview of
semiconductor industry and trends in VLSI industry. Then
we will go through the one of the important part of this
training
i.e. SoC design. After that we will see the backbone of
VLSI which is MOORE’S LAW . After that we will go
through various topics such as ASIC vs FPGA, VLSI
Design flow, ASIC design flow, front and back end design
and then we will vonplete this report by verilog.
I also want to say thanks to my teacher and guide Dr.
Ramnish Kumar for his guidance and constant
support throughout my training.
CERTIFICATE
Mail of maven silicon for Training
 CONTENTS

1. Abstract
2. Certificate
3. Introduction to VLSI
4. Semiconductor industry
overview
5. VLSI industry trends
6. System on Chip(SoC)
Design
7. Moore’s Law
8. ASIC and FPGA
9. VLSI design flow
10. ASIC design flow
11. Front end and back end design
12. Verilog
 Introduction to VLSI

Very-large-scale integration (VLSI) is the process of

creating an integrated circuit (IC) by combining
thousands of transistors into a single chip. VLSI began in
the 1970s when
complex semiconductor and communication
technologies were being developed. The
microprocessor is a VLSI device.
Before the introduction of VLSI technology, most ICs had
a limited set of functions they could perform. An
electronic circuit might consist of a CPU, ROM, RAM and
other glue logic. VLSI lets IC designers add all of these
into one chip.
The electronics industry has achieved a phenomenal
growth over the last few decades, mainly due to the rapid
advances in large scale integration technologies and
system design applications. With the advent of very large
scale integration (VLSI) designs, the number of
applications of integrated circuits (ICs) in high-
performance computing, controls, telecommunications,
image and video processing, and consumer electronics
has been rising at a very fast pace.
The current cutting-edge technologies such as high
resolution and low bit-rate video and cellular
communications provide the end-users a marvelous
amount of applications, processing power and portability.
This trend is expected to grow rapidly, with very
important implications on VLSI design and systems
design.
 Why VLSI ?

VLSI affords IC designers the ability to

design utilizing less space.
Typically, electronic circuits incorporate a
CPU, RAM, ROM, and other peripherals on a
single PCBA. However, very large-scale
integration (VLSI) technology affords an IC
designer the ability to add all of these into one
chip. If we examine the electronics landscape
over the last few decades, we will see
evidence of its rapid growth. The benefits
include increased functionality, improved
miniaturization, and increased overall
performance. However, this demand to place
more components while increasingly utilizing
less space translates into a lower margin of
error.
Keeping that in mind, it is understandable why,
over the last few years, Silicon (CMOS)
technology is now the leading fabrication
process for cost- effective and relatively high-
performance VLSI circuits.
SEMICONDUCTOR INDUSTRY OVERVIEW

The semiconductor industry is the

aggregate of companies engaged in the
design and fabrication of
semiconductors
and semiconductor devices such as
integrated circuits. It formed around 1960,
once the fabrication of semiconductor
devices became a viable business. The
industry's annual semiconductor sales
revenue has since grown to over $481
billion, as of 2018.The semiconductor
industry is in turn the driving force behind
the wider electronics industry with
annual power electronics sales of £135
billion ($216 billion) as of 2011,
annual consumer electronics sales
expected to reach $2.9 trillion by 2020,
tech industry sales expected to reach $5
trillion in 2019, and e-commerce with
over $29 trillion in 2017.
 System on Chip(SoC) design

SoC acronym for system on chip is an IC which

integrates all the components into a single chip. It
may contain analog, digital, mixed signal and other
radio frequency functions all lying on a single chip
substrate. Today, SoCs are very common in
electronics industry due to its low power
consumption. Also, embedded system
applications make great use of SoCs.
SoCs consists of:
 Control Unit: In SoCs, the major control
units are microprocessors,
microcontrollers, digital signal processors
etc.
 Memory Blocks: ROM, RAM. Flash
memory and EEPROM are the basic
memory units inside a SoC chip.
 Timing Units: Oscillators and PLLs are
the timing units of the System on chip.
 Other peripherals of the SoCs are counter
timers, real-time timers and power on reset
generators.
 Analog interfaces, external interfaces,
voltage regulators and power
management units form the basic
interfaces of the SoCs.

 SOC Structure and design
flow

Design flow of SoC aims in the development of

hardware and software of SoC designs. In
general, the design flow of SoCs consists of:
 Hardware and Software Modules: Hardware
blocks of SoCs are developed from pre-
qualified hardware elements and software
modules integrated using software
development environment. The hardware
description languages like Verilog, VHDL
and SystemC are being used for the
development of the modules.
 Functional Verification: The SoCs are verified
for the logic correctness before it is being
given to the foundry.
 Verify hardware and software designs: For
the verification and debug of hardware and
software of SoC designs, engineers have
employed FPGA, simulation acceleration,
emulation and other technologies.
 Place and Route: After the debugging of the
SoC, the next step is to place and route the
entire design to the integrated circuit before it
is being given to the fabrication. In the
fabrication process, full custom, standard cell
and FPGA technologies are commonly used.
 Advantages and Disadvantages of SoC

 Advantages of SoC
1. Low power.
2. Low cost.
3. High reliability.
4. Small form factor.
5. High integration levels.
6. Fast operation.
7. Greater design.
8. Small size.
 Disadvantages of SoC
1. Fabrication cost.
2. Increased complexity.
3. Time to market demands.
4. More verification.
 SoCVarities

 NVIDIA Tegra 3
NVIDIA Tegra 3 is a SoC of the Tegra family
and this is used in various Android devices.
Some devices like Asus Eee Pad, HTC One X
and Google Nexus Tablet is using the Tegra 3
on the board. This comes with a CPU and five
cores. Each core is a Cortex A9 ARM chip,
while the fifth core is made of a low power
silicon process and has a speed of 500MHz.
 Qualcomm Snapdragon S4
Qualcomm is important when Android smart
phones and tablets are being used. It has a
processor which is similar to the ARM Cortex
A15 CPU.
 Samsung Exynos 4 Quad
This SoC is based on the ARM architecture. It
has a 1.4GHz ARM Mali-400 MP4 quad-core
GPU and Quad-core ARM Cortex – A9 CPU.
This processor
supports many applications like 3D gaming,
multi- tasking and video recording and
playback.
 Intel Medfield
Medfield SoCs are not based on ARM
architecture. It uses the x86 technologies to
make these SoCs. Medfield SoCs can offer
OEMs a 1.6- 2GHz single-core processor and
PowerVR’s SGX540 GPU.
 Texas Instruments OMAP 4
It is the fourth generation OMAPs where ARM
Cortex A9 45nm architecture is being used.
Some Android devices that use this SoC are
Motorola Atrix 2, Motorola Droid RAZR, LG
Optimus 3D and LG Optimus Max.
 SoC design Challenges

The different SoC design challenges are

given below:
1. Architecture Strategy
2. Design for Test Strategy
3. Validation Strategy
4. Synthesis Backend Strategy
5. Integration Strategy
6. On chip Isolation
 Architecture Strategy
The kind of processor that we use to
design the SoC is really an important
factor to be considered. Also, the kind of
bus that has to be implemented is another
matter of choice.
 Design for Test Strategy
Most of the common physical defects are
modeled as faults here. While the
necessary
circuits included in the SoC design help in
checking the faults.
 Validation Strategy
Validation Strategy of SoC designs
involves two major issues. First issue is
that we have to verify the IP cores. While
the second issue is that we need to verify
the integration of the system.
 Synthesis and Backend Strategy
There are many physical effects that have
to be considered while designing the SoC
synthesis and strategy. Effects like IR
drop, cross talk, 3D noise, antenna
effects and EMI effects. Inorder to tackle
these issues, chip planning, power
planning, DFT planning, clock planning,
timing and area budgeting is required in
the early stage of the design.
  Integration Strategy
In the integration strategy, all the above
listed facts have to be considered and
assembled to bring out a smooth strategy.
 On chip Isolation
In on chip isolation, many effects like
impact of process technology, grounding
effects, guard rings, shielding and on- chip
decoupling is to be considered.
 ARM Holdings and SoC

System on Chip devices became popular because

of some major breakthroughs provided by ARM
Holdings, a British company that has contributed
significantly to the field of embedded systems. ARM
developed and licensed processor designs that
could be used by other companies to develop
chips. This enabled greater flexibility in design and
manufacture of chips. Chip manufacturers could
build upon these CPU designs and add other
necessary components to come up with SoC.
IP Cores
IP Cores or Intellectual Property Cores are
fundamental building blocks of SoC. It is a reusable
layout of IC design that is provided by companies
like ARM to chip manufacturers subject to license
agreements. IP Cores can be Soft cores or Hard
cores. Soft cores are generally RTL schematics
written in some hardware description language.
They are called so because they can be subjected
to small changes suiting the design. Hard cores are
mostly analog components and certain digital cores
whose function cannot be changed by designers.
Open Cores
One of the advantage of having reusable IC design
layouts is that it facilitates a more open approach to
designing. Having philosophies similar to the Free
Software Movement an open source hardware
community exists that develops digital open source
hardware. This community called Open Cores
publish core designs under Lesser General Public
License (LGPL). Their aim is to develop tools and
standards for open source cores and platforms and
provide documentation for the same.
Software and Protocol Stacks
Hardware is not the only focus during SoC design.
The chips developed must be supported by
software drivers that control the operation of
hardware. Since an SoC has to manage
networking also the protocol stacks have to be
written along with drivers. These stacks are
software implementations of networking protocols.
Functional Verification
Functional verification is a very important task in
SoC manufacturing. It is the process of verifying
that the hardware developed follows the logic
intended by the designer. This involve testing the
performance of the hardware against the various
permutations and combinations of situations. The
very number of such possibilities make this process
extremely challenging. Experts use various
methods to reduce this number and take help of
software tools like Aldec at this stage.
On-chip debugging
On-chip debugging is emerging as a cheap
alternative to simulative and emulative verification
techniques. Simulations are not very close to
physical hardware and methods to improve
simiulation capabilities can be very costly. The cost
can be brought down and more effective debugging
can be ensured by the use of instrumentation
techniques for on-chip debugging. On- Chip
debugging for a component in an SoC is different
from others. We may look into on-chip debugging of
a processor as an example.
On-Chip Debugging of a Processor
This On-Chip Debugging System(OCDS) uses
JTAG interface. It consists of three blocks – the
OCDS module, core debug port and the JTAG
module. The debugging operation is controlled
using breakpoints. Breakpoints are triggers that
alter the sequential operation of a processor. The
processor is driven into required modes using
breakpoints for performing analysis.
Instruction Breakpoints
Instruction breakpoints are triggers set against
instruction value of the processor. This helps in
tracking the occurrence of instructions in the
processor. A processor OCDS monitor concurrent
instructions by having multiple instruction
breakpoints.
Instructions are evaluated by comparing the data or
register values set by instructions.

Fabrication of SoC
Most common methods for fabricating SoCs are as
a standard cell, full custom designing or using
FPGAs. Full custom designing involves specifying
the layout of every component of hardware design.
Due to the labor intensiveness of this method it is
preferred only when large number of repetition is
needed. A more common method is the use of
standard cells which are libraries already written by
full custom designing. FPGAs allow implementation
of complex combinational logical functions by a
user with the help of programmable logic blocks
and interconnects.

Applications of SoCs
Most common use of SoCs has been found in the
mobile devices industry. The use of SoCs have
enabled manufaturers of such devices to come up
with devices good of very small form factor that
offer ample performance. It also enables them to
focus on features they project to the target
customers than relying on capabilities of chips
provided by some other company. SoCs also
brought about a revolution in embedded systems
by paving way for very small and portable single-
board computers.
 Examples of SoCs
Most of the SoCs available in the market today are
ARM based. Some examples among SoCs in
smartphone industry are Qualcomm's Snapdragon
SoCs, Apple A4, and NvidiaTegra series.
Raspberry Pi 2 comes with Broadcom BCM2836
SoC. Several SoCs have been developed by the
Open Cores community.
 MOORE’S LAW

Moore's Law refers to Gordon Moore's

perception that the number of transistors on a
microchip doubles every two years, though the
cost of computers is halved. Moore's Law
states that we can expect the speed and
capability of our computers to increase every
couple of years, and we will pay less for them.
Another tenet of Moore's Law asserts that this
growth is exponential.
In 1965, Gordon E. Moore—co-founder of Intel
— postulated that the number of transistors
that can be packed into a given unit of space
will double about every two years.
Gordon Moore did not call his observation
"Moore's Law," nor did he set out to create a
"law." Moore made that statement based on
noticing emerging trends in chip
manufacturing at Intel. Eventually, Moore's
insight became a prediction, which in turn
became the golden rule known as Moore's
Law.
In the decades that followed Gordon Moore's
original observation, Moore's Law guided the
semiconductor industry in long-term planning
and setting targets for research and
development (R&D). Moore's Law has been a
driving force of technological and social
change, productivity, and economic growth
that are hallmarks of the late- twentieth and
early twenty-first centuries.
 ASIC & FPGA

What Is an ASIC?

ASIC in VLSI stands for application-specific

integrated circuit. This integrated circuit is aptly
named since an ASIC microchip is designed and
manufactured for one specific application and does
not allow you to reprogram or modify it after it is
produced. This means ASICs are not intended for
general use. You must have ASICs created to your
specifications for your product.

Types of ASICs

ASICs come in a few different types, including gate

array,
standard cell and custom designs. These types
are differentiated from each other by the level of
customization they offer during the design process.

What Are ASICs Used For?

ASIC chip technology has a wide array of

valuable
applications. Generally, engineers use ASICs in
products that are intended for permanent
applications since they aren’t designed to be
modified. This includes electronic devices like
smartphones, computers, voice recorders,
and TVs, for example. There is virtually no limit to the
types of applications for specific integrated circuits.

What Is an FPGA?

FPGA stands for field programmable gate array.

These chips are manufactured for general use with
configurable logic blocks (CLBs) and programmable
interconnects. This means you can program and
reprogram FPGAs to perform numerous functions
after they have left the manufacturer and are being
used in the field. You can program some FPGAs
one time, while others can be reprogrammed as
many times as needed.

What Is an FPGA Used For?

FPGAs are useful for a range of applications. Many

engineers use FPGAs in prototypes when designing
a product, but once the product design is complete
and ready for mass production, they switch to ASICs
designed for their application. FPGAs are also useful
for applications that require ongoing flexibility, such
as safety applications in vehicles or image
processing in security applications.
 VLSI Design flow
In order to fulfill futuristic demands of chip design,
changes are required in design tools,
methodologies, and software/hardware capabilities.
For those changes, ASIC design flow adopted by
engineers for efficient structured ASIC chip
architecture and focus on its design functionalities

ASIC design flow is a mature and silicon-proven IC

design process which includes various steps like
design conceptualization, chip optimization,
logical/physical implementation, and design
validation and verification. Let’s have an overview
of each of the steps involved in the process.

Step 1. Chip Specification

This is the stage at which the engineer defines
features, microarchitecture,
functionalities (hardware/software
interface), specifications (Time, Area, Power,
Speed) with design guidelines of ASIC. Two
different teams are involved at this juncture:

 Design team: Generates RTL code.

 Verification team: Generates test bench.
Step 2. Design Entry / Functional Verification
Functional verification confirms the functionality and
logical behavior of the circuit by simulation on a
design entry level. This is the stage where the
design team and verification team come into the
cycle where they generate RTL code using test-
benches. This is known as behavioral simulation.
In this simulation, once the RTL code (RTL code is
a set of code that checks whether the RTL
implementation meets the design verification) is
done in HDL, a lot of code coverage metrics
proposed for HDL. Engineers aim to verify
correctness of the code with the help of test
vectors and trying to achieve it by 95% coverage
test. This code coverage includes statement
coverage, expression coverage, branch coverage,
and toggle coverage.
There are two types of simulation tools:
 Functional simulation tools: After the testbench

and design code, functional simulation verifies

logical behavior and its implementation based
on design entry.
 Timing simulation tools: Verifies that circuit
design meets the timing requirements and
confirms the design is free of circuit signal
delays.
Step 3. RTL block synthesis / RTL Function
Once the RTL code and testbench are generated,
the RTL team works on RTL description – they
translate the
RTL code into a gate-level netlist using a logical
synthesis tool that meets required timing
constraints. Thereafter, a synthesized database of
the ASIC design is created in the system. When
timing constraints are met with the logic synthesis,
the design proceeds to the design for testability
(DFT) techniques.
Step 4. Chip Partitioning
This is the stage wherein the engineer follows the
ASIC design layout requirement and specification
to create its structure using EDA tools and proven
methodologies. This design structure is going to be
verified with the help of HLL programming
languages like C++ or System C.

After understanding the design specifications, the

engineers partition the entire ASIC into multiple
functional blocks (hierarchical modules), while
keeping in mind ASIC’s best performance, technical
feasibility, and resource allocation in terms of area,
power, cost and time. Once all the functional blocks
are implemented in the architectural document, the
engineers need to brainstorm ASIC design
partitioning by reusing IPs from previous projects
and procuring them from other parties.
Step 5. Design for Test (DFT) Insertion
With the ongoing trend of lower technology nodes,
there is an increase in system-on-chip variations
like size, threshold voltage and wire resistance.
Due to these factors, new models and techniques
are introduced to high-quality testing.

ASIC design is complex enough at different stages

of the design cycle. Telling the customers that the
chips have fault when you are already at the
production stage is embarrassing and disruptive.
It’s a situation that no engineering team wants to
be in. In order to overcome this situation, design for
test is introduced with a list of techniques:

 Scan path insertion: A methodology of linking

all registers elements into one long shift
register (scan path). This can help to check
small parts of design instead of the whole
design in one go.
 Memory BIST (built-in Self-Test): In the lower
technology node, chip memory requires lower
area and fast access time. MBIST is a device
which is used to check RAMs. It is a
comprehensive solution to memory testing
errors and self-repair proficiencies. 
 ATPG (automatic test pattern generation):
ATPG is a method of creating test vectors /
sequential
 input patterns to check the design for faults
generated within various elements of a circuit.
Step 6. Floor Planning (blueprint your chip)
After, DFT, the physical implementation process is
to be followed. In physical design, the first step in
RTL-to- GDSII design is floorplanning. It is the
process of placing blocks in the chip. It includes:
block placement, design portioning, pin placement,
and power optimization.

Floorplan determines the size of the chip, places

the gates and connects them with wires. While
connecting, engineers take care of wire length, and
functionality which will ensure signals will not
interfere with nearby elements. In the end, simulate
the final floor plan with post-layout verification
process.

A good floorplanning exercise should come across

and take care of the below points; otherwise, the
life of IC and its cost will blow out:

 Minimize the total chip area

 Make routing phase easy (routable) 

 Improve signal delays

Step 7. Placement
Placement is the process of placing standard cells
in row. A poor placement requires larger area and
also degrades performance. Various factors, like
the timing
requirement, the net lengths and hence the
connections of cells, power dissipation should be
taken care. It removes timing violation.

RELATED BLOG
Frequently Asked Questions – ASIC-FPGA-SoC
Design
and Solutions
Step 8. Clock tree synthesis
Clock tree synthesis is a process of building the
clock tree and meeting the defined timing, area and
power requirements. It helps in providing the clock
connection to the clock pin of a sequential element
in the required time and area, with low power
consumption.

In order to avoid high power consumption, increase

in delays and a huge number of transitions, certain
structures can be used for optimizing CTS structure
such as Mesh Structure, H-Tree Structure, X-Tree
Structure, Fishbone Structure and Hybrid structure.

With the help of these structures, each flop in the

clock tree gets the clock connection. During the
optimization, tools insert the buffer to build the CTS
structure. Different clock structures will build the
clock tree with a minimum buffer insertion and
lower power consumption of chips.
Step 9. Routing
1. Global Routing: Calculates estimated values for
each net by the delays of fan-out of wire.
Global routing is mainly divided into line
routingand maze
routing.
2. Detailed Routing: In detailed routing, the actual
delays of wire is calculated by various
optimization methods like timing optimization,
clock tree synthesis, etc.
As we are moving towards a lower technology
node, engineers face complex design challenges
with the need for implanting millions of gates in a
small area. In order to make this ASIC design
routable, placement density range needs to be
followed for better QoR. Placement density analysis
is an important parameter to get better outcomes
with less number of iterations.

Step 10. Final Verification (Physical Verification and

Timing)
After routing, ASIC design layout undergoes three
steps of physical verification, known as signoff
checks. This stage helps to check whether the
layout working the way it was designed to. The
following checks are followed to avoid any errors
just before the tapeout:

1. Layout versus schematic(LVS) is a process of

checking that the geometry/layout matches the
schematic/netlist.
 2. Design rule checks(DRC) is the process of
checking that the geometry in the GDS file
follows the rules given by the foundry.
3. Logical equivalence checks(LVC) is the
process of equivalence check between pre and
post design layout.
Step 11. GDS II – Graphical Data Stream
Information Interchange
In the last stage of the tapeout, the engineer
performs wafer processing, packaging, testing,
verification and delivery to the physical IC. GDSII is
the file produced and used by the semiconductor
foundries to fabricate the silicon and handled to
client.
 FRONT END & BACK END DESIGN
Front End Design:
Front end design process starts with the
specification received from the customer end. RTL
(Register Transfer Level) design engineer converts
the specification into an RTL code using the HDL
(Hardware Description Language) generally either
in Verilog or VHDL. Once the RTL code is written,
RTL designer simulates the code in RTL Simulator
and check the functionality of the design. Once
the functionality of code is correct and verified by
the verification engineers and if there is no bug
found, This RTL code is taking to the next stage
which is logic synthesis. This flow starts with RTL
coding and ends with GDS (Graphic Data Stream)
file which is the final output of back end design, so
this complete flow is also known as RTL to GDS
(RTL2GDS) flow. A Simple flow diagram has been
described here.
Back End Design:
RTL code received from the front end engineer is
technology independent, now the next step is Logic
synthesis.

Logic Synthesis: In logic synthesis, a high-level

description of the design (RTL Code) is
converted into
an optimized gate-level representation of a given
standard cell library and certain design constraints.
Now the code is in the form of a gate-level netlist of
a particular standard cell library. LEC (Logic
Equivalence Check is must in this stage to make
sure that there are not logical changes occurred
during the synthesis. During logical Synthesis, we
also get various reports on timing power and area
of design. We also get an SDC (Synopsys Design
Constraint) file in this stage which is used in the
next stage. DFT (Design For Testability) Insertion is
also done in this stage to verify the chip after
fabrication is done.

Place and Route (PnR): Gate level netlist after DFT

Insertion and SDC file is taken as input for the PnR
and based on standard cells library, PnR starts.
The goal of PnR stage is to place all the standard
cells, Macros and I/O pads with minimal area, with
minimal delay and Route them together in such a
way that there is no DRC (Design Rule Check)
error. The final output of this stage is the layout of
design in the form of GDSII file which is defacto
standard of layout file in the industry.
PnR stage is a very challenging stage with large
design cycle time depending on the complexity of a
chip. This stage is further divided into various sub-
stages. The
main stages are starting from Design Import,
followed by FloorPlan, Power Plan, Placement,
CTS (Clock Tree Synthesis), and Routing.
After routing we expect the design has met the
timing and all DRC, But in the modern chip, it's not
easy to close the design in this stage. So Further
we go to Signoff stage.

Signoff: If there are some timing violations in post

route design, we have a further stage called ECO
(Engineering Change Order) where we can fix the
timing violations. Apart from timing violation, there
may be issues like IR Drop, DRC Violations all
these are fixed in this stage and a final layout file
free from all the violation is streamed out in GDSII
format. This process is known as tapeout in ASIC
flow. This is the final design stage and gdsII file is
sent to fabrication lab for the fabrication of chip.
 VERILOG
Verilog is a HARDWARE DESCRIPTION
LANGUAGE
(HDL). It is a language used for describing a digital
system like a network switch or a microprocessor or
a memory or a flip−flop. It means, by using a HDL
we can describe any digital hardware at any level.
Designs, which are described in HDL are
independent of technology, very easy for designing
and debugging, and are normally more useful than
schematics, particularly for large circuits.
Verilog supports a design at many levels of
abstraction. The major three are −

Behavioral level

Register-transfer

level Gate level

Behavioral level
This level describes a system by concurrent
algorithms (Behavioural). Every algorithm is
sequential, which
means it consists of a set of instructions that are
executed one by one. Functions, tasks and blocks
are the main elements. There is no regard to the
structural realization of the design.
Register−Transfer Level
Designs using the Register−Transfer Level specify
the characteristics of a circuit using operations and
the transfer of data between the registers. Modern
definition of an RTL code is "Any code that is
synthesizable is called RTL code".
Gate Level
Within the logical level, the characteristics of a
system are described by logical links and their
timing properties. All signals are discrete signals.
They can only have definite logical values (`0', `1',
`X', `Z`). The usable operations are predefined
logic primitives (basic gates). Gate level modelling
may not be a right idea for logic design. Gate level
code is generated using tools like synthesis tools
and his netlist is used for gate level simulation and
for backend.
Lexical Tokens
Verilog language source text files are a stream of
lexical tokens. A token consists of one or more
characters, and each single character is in exactly
one token.
The basic lexical tokens used by the Verilog HDL
are similar to those in C Programming Language.
Verilog is case sensitive. All the key words are in
lower case.
White Space

White spaces can contain characters for spaces,

tabs, new-lines and form feeds. These characters
are ignored except when they serve to separate
tokens.
White space characters are Blank space, Tabs,
Carriage returns, New line, and Form feeds.

Comments

There are two forms to represent the comments

1) Single line comments begin with the token // and

end with carriage return.

Ex.: //this is single line syntax

2) Multiline comments begins with the token /* and

end with token */
Ex.: /* this is multiline Syntax*/

Numbers

You can specify a number in binary, octal, decimal

or hexadecimal format. Negative numbers are
represented in 2’s compliment numbers. Verilog
allows integers, real numbers and signed &
unsigned numbers.
The syntax is given by − <size><radix><value>
Size or unsized number can be defined in <Size>
and
<radix> defines whether it is binary, octal,
hexadecimal or decimal.

Identifiers

Identifier is the name used to define the object,

such as a function, module or register. Identifiers
should begin with an alphabetical characters or
underscore characters. Ex. A_Z, a_z,_
Identifiers are a combination of alphabetic, numeric,
underscore and $ characters. They can be up to
1024 characters long.

Operators

Operators are special characters used to put

conditions or to operate the variables. There are
one, two and sometimes three characters used to
perform operations on variables.
Ex. >, +, ~, &! =.

Verilog Keywords

Words that have special meaning in Verilog are

called the Verilog keywords. For example, assign,
case, while, wire, reg, and, or, nand, and module.
They should not be used as identifiers. Verilog
keywords also include compiler directives, and
system tasks and functions.

Gate Level Modelling

Verilog has built-in primitives like logic gates,
transmission gates and switches. These are rarely
used for design work but they are used in post
synthesis world for modelling of ASIC/FPGA cells.
Gate level modelling exhibits two properties −
Drive strength − The strength of the output gates is
defined by drive strength. The output is strongest if
there is a direct connection to the source. The
strength decreases if the connection is via a
conducting transistor and least when connected via
a pull- up/down resistive. The drive strength is
usually not specified, in which case the strengths
defaults to strong1 and strong0.
Delays − If delays are not specified, then the gates
do not have propagation delays; if two delays are
specified, then first one represents the rise delay
and the second one, fall delay; if only one delay is
specified, then both, rise and fall are equal. Delays
can be ignored in synthesis.

Gate Primitives

The basic logic gates using one output and many

inputs are used in Verilog. GATE uses one of the
keywords -
and, nand, or, nor, xor, xnor for use in Verilog for N
number of inputs and 1 output.
Operators

Arithmetic

Operators

These operators is perform arithmetic operations.

The
+ and −are used as either unary (x) or binary (z−y)
operators.
The Operators which are included in arithmetic
operation are −
+ (addition), −(subtraction), * (multiplication), /
(division), % (modulus)

Relational Operators

These operators compare two operands and return

the result in a single bit, 1 or 0.
Wire and reg variables are positive. Thus (−3’d001)
= = 3’d111 and (−3b001)>3b110.
The Operators which are included in
relational operation are −
== (equal to)

!= (not equal to)

> (greater than)

>= (greater than or equal to)

< (less than)

<= (less than or equal

to) Bit-wise Operators

Bit-wise operators which are doing a bit-by-bit

comparison between two operands.
The Operators which are included in Bit wise
operation are −

& (bitwise AND)

| (bitwiseOR)

~ (bitwise NOT)

^ (bitwise XOR)

~^ or ^~(bitwise XNOR)
Reduction Operators

Reduction operators are the unary form of the

bitwise operators and operate on all the bits of an
operand vector. These also return a single-bit
value.
The operators which are included in Reduction
operation are −

& (reduction AND)

| (reduction OR)

~& (reduction NAND)

~| (reduction NOR)

^ (reduction XOR)

~^ or ^~(reduction XNOR)