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    (BTL2 - Understanding) PO - (1, 2, 12), PSO - (1) (BTL2 - Understanding) PO - (1, 2, 12), PSO

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    Veera Swamy
    The document appears to be an exam for a Digital Electronics course assessing three course outcomes: classifying number systems and realizing Boolean functions, minimizing switching functions using Boolean theorems, and designing combinational logic circuits. The exam contains two sets of three questions each assessing students' understanding of number systems, codes, logic gates, K-maps, subtraction using 2's complement, error detection, Boolean function simplification using tabulation, and multiplexer design. Students are asked to translate numbers, realize logic gates, construct and minimize Boolean functions, perform arithmetic operations, decode error detection codes, simplify functions, and implement a multiplexer.

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    (BTL2 - Understanding) PO - (1, 2, 12), PSO - (1) (BTL2 - Understanding) PO - (1, 2, 12), PSO

    Uploaded by

    Veera Swamy
    23 views2 pages
    The document appears to be an exam for a Digital Electronics course assessing three course outcomes: classifying number systems and realizing Boolean functions, minimizing switching functions using Boolean theorems, and designing combinational logic circuits. The exam contains two sets of three questions each assessing students' understanding of number systems, codes, logic gates, K-maps, subtraction using 2's complement, error detection, Boolean function simplification using tabulation, and multiplexer design. Students are asked to translate numbers, realize logic gates, construct and minimize Boolean functions, perform arithmetic operations, decode error detection codes, simplify functions, and implement a multiplexer.

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    DE MID-I QP

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    The document appears to be an exam for a Digital Electronics course assessing three course outcomes: classifying number systems and realizing Boolean functions, minimizing switching functions using Boolean theorems, and designing combinational logic circuits. The exam contains two sets of three questions each assessing students' understanding of number systems, codes, logic gates, K-maps, subtraction using 2's complement, error detection, Boolean function simplification using tabulation, and multiplexer design. Students are asked to translate numbers, realize logic gates, construct and minimize Boolean functions, perform arithmetic operations, decode error detection codes, simplify functions, and implement a multiplexer.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    23 views2 pages

    (BTL2 - Understanding) PO - (1, 2, 12), PSO - (1) (BTL2 - Understanding) PO - (1, 2, 12), PSO

    Uploaded by

    Veera Swamy
    The document appears to be an exam for a Digital Electronics course assessing three course outcomes: classifying number systems and realizing Boolean functions, minimizing switching functions using Boolean theorems, and designing combinational logic circuits. The exam contains two sets of three questions each assessing students' understanding of number systems, codes, logic gates, K-maps, subtraction using 2's complement, error detection, Boolean function simplification using tabulation, and multiplexer design. Students are asked to translate numbers, realize logic gates, construct and minimize Boolean functions, perform arithmetic operations, decode error detection codes, simplify functions, and implement a multiplexer.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    of 2

    DHANEKULA INSTITUTE OF ENGINEERING & TECHNOLOGY

    GANGURU::VIJAYAWADA – 521 139


    Name of the program: B.Tech in EEE Academic year: 2020-2021 SET-I
    Name of the Course : Digital Electronics
    Year & Semester : II - CO No R19C212. 1 R19C212. 2 R19C212.3 Total
    II Marks 4 4 2 10
    Name of the Exam : MID-
    I
    H T No of Candidate:
    Max Marks : 10M Duration : 90Min Date :25.08.21
    -----------------------------------------------------------------------------------------------------------
    Description of Course outcomes being assessed:
    R19C212. 1- Classify different number systems, codes and realize Boolean functions
    using logic gates.
    R19C212. 2- Minimize switching functions using Boolean theorems and design
    arithmetic circuits using K-maps.
    R19C212. 3- Design combinational logic circuits using LSI, MSI.
    -------------------------------------------------------------------------------------------------------
    1(a) Translate the following numbers into decimal numbers
    i) 10110111011011102
    ii) A0CB.EE16 [BTL2 - Understanding] PO-(1, 2, 12), PSO-(1)
    (b) Realize a 2 input EX-OR gate using minimum number of 2 input
    NAND gates. [BTL2 - Understanding] PO-(1, 2, 12), PSO-(1)

    2(a) Construct the following Boolean function using K-Map in SOP Form
    F=∑m(4,5,7,8,10,11,13,14) +d(0,1,2)
    [BTL5- Evaluating] PO-(1, 2, 3, 12), PSO-(1)

    (b) Write De Morgan's theorem and solve


    [BTL5- Evaluating] PO-(1, 2, 3, 12), PSO-(1)

    3. Design full adder using two half adders and also explain operation.
    [BTL5- Evaluating] PO-(1, 2, 3, 12), PSO-(1)
    DHANEKULA INSTITUTE OF ENGINEERING & TECHNOLOGY
    GANGURU::VIJAYAWADA – 521 139
    Name of the program: B.Tech in EEE Academic year: 2020-2021 SET-II
    Name of the Course : Digital Electronics
    Year & Semester : II - CO No R19C212. 1 R19C212. 2 R19C212.3 Total
    II Marks 4 4 2 10
    Name of the Exam : MID-
    I
    H T No of Candidate:
    Max Marks : 10M Duration : 90Min Date :25.08.21
    -----------------------------------------------------------------------------------------------------------
    Description of Course outcomes being assessed:
    R19C212. 1- Classify different number systems, codes and realize Boolean functions
    using logic gates.
    R19C212. 2- Minimize switching functions using Boolean theorems and design
    arithmetic circuits using K-maps.
    R19C212. 3- Design combinational logic circuits using LSI, MSI.
    -------------------------------------------------------------------------------------------------------

    1 (a) Perform the subtraction using 2’s complement method. 2(M)


    (i) 11010 – 10011 (ii) 11000 – 1011
    [BTL2 - Understanding] PO-(1, 2, 12), PSO-(1)

    (b) The message below coded in the 7-bit Hamming code is transmitted through noisy channel.
    Decode the message assuming that at most a single error occurred in given code word 1001001. 2(M)
    [BTL2 - Understanding] PO-(1, 2, 12), PSO-(1)

    2. Simplify the following Boolean function using Tabulation method. 4(M)


    Y(A,B,C,D) = ∑m(1,3,5,8,9,11,15) [BTL5- Evaluating] PO-(1, 2, 3, 12), PSO-(1)

    3. Design a 8x1 multiplexer with suitable inputs. Implement the following Boolean function with an
    8X1 Multiplexer. choose B,C and D as select lines. 2(M)
    F(A,B,C,D)=∑m(0,3,4,7,8,9,12,14)
    [BTL5- Evaluating] PO-(1, 2, 3, 12), PSO-(1)

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