Chapter-2: Simple-As-Possible (SAP) Computer

1. Simple As Possible Introduction:

SAP-1 is the first stage in the evolution toward modern computers. It include its architecture, its
programming, and its circuits.

SAP-2 is the next step in the evolution towards modern computers because it includes jump instructions.
These new instruction force the computer to repeat or skip part of a program.

SAP-3 is the third stage in the evolution. It is a 8-bit microcomputer that is upward-compatible with 8085
microprocessor. In this chapter the emphasis is on the SAP-3 instruction set. It also include its programming
model which have a new register the stack pointer or SP, a 16-bit register. This new register controls a portion
of memory known as stack. SAP-3 also have additional CPU register the registers D, E, F, H (for more efficient
data processing) and L (which stores flag bits S, Z and others).

2. SAP-1 Architecture:
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by
Albert Paul Malvino. The SAP-1 design contains the basic necessities for a functional
Microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor
works, interacts with memory and other parts of the system like input and output. The instruction set
is very limited and is simple.

SAP (Simple-As-Possible)-1 is the first stage in the evolution toward modern computers.

SAP is Simple-As-Possible Computer. The type of computer is specially designed for the academic
purpose and nothing has to do with the commercial use. The architecture is 8 bits and comprises of
16 X 8 memory i.e. 16 memory location with 8 bits in each location, therefore, need 4 address lines
which either comes from the PC (Program Counter which may be called instruction pointer) during
computer run phase or may come from the 4 address switches during the program phase. All
instructions (5 only) get stored in this memory. It means SAP cannot store program having more than
16 instructions.
SAP can only perform addition and subtraction and no logical operation. These arithmetic operations
are performed by an adder/subtractor unit.

There is one general purpose register (B register) used to hold one operand of the arithmetic operation
while another is kept by the accumulator register of the SAP-1.

In addition, there are 8 LEDs which work as output unit and connected with the 8 bit output register.

All timely moment of data or activities are performed by the controller/sequencer part of the SAP-1.

Program Counter
 It counts from 0000 to 1111.
 It signals the memory address of next instruction to be fetched and executed.
Inputs and MAR (Memory Address Register)
 During a computer run, the address in PC is latched into Memory Address Register (MAR).
The RAM
 The program code to be executed and data for SAP-1 computer is stored here.
 During a computer run, the RAM receives 4-bit addresses from MAR and a read operation
is performed. Hence, the instruction or data word stored in RAM is placed on the W bus for
use by some other part of the computer.
 It is asynchronous RAM, which means that the output data is available as soon as valid
address and control signal are applied.
Instruction Register
 IR contains the instruction (composed of OPCODE+ADDRESS) to be executed by SAP1
computer.
Controller-Sequencer
 It generates the control signals for each block so that actions occur in desired sequence.
CLK signal is used to synchronize the overall operation of the SAP1 computer.
 A 12-bit word comes out of the Controller-Sequencer block. This control word determines
how the registers will react to the next positive CLK edge.
Accumulator
 It is a 8-bit buffer register that stores intermediate results during a computer run.
 It is always one of the operands of ADD, SUB and OUT instructions.
Adder/Subtractor
 It is a 2's complement adder-subtractor.
 This module is asynchronous (unclocked), which means that its contents can change as soon
as the input words change.
B-register
 It is 8-bit buffer register which is primarily used to hold the other operand (one operand is
always accumulator) of mathematical operations.
Output Register
 This registers hold the output of OUT instruction.
Binary Display
 It is a row of eight LEDs to show the contents of output register.
 Binary display unit is the output device for the SAP-1 microprocessor.
3. What is SAP-2 Computer?
SAP-1 is a computer because it stores a program and data before calculations begin; then it
automatically carries out the program instructions without human intervention. And yet, SAP-1 is a
primitive computing machine. It compares to a modern computer the way a Neanderthal human
would compare to a modern person. Something is missing, something found in every modern
computer.
SAP-2 is the next step in the evolution toward modern computers because it includes jump
instructions. These new instructions force the computer to repeat or skip part of a program. As you
will discover, jump instructions open up a whole new world of computing power.
4. Bidirectional Registers:
To reduce the wiring capacitance of SAP-2, we will run only one set of wires between each register
and the bus. Figure a shows the idea. The input and output pins are shorted; only one group of wires
is connected to the bus.
Does this shorting the input and output pins ever cause trouble? No during a computer run, either
LOAD or ENABLE may be active, but not both at the same time. An active LOAD means that a
binary word flows from the bus to the register input; during a load operation, the output lines are
floating. On the other hand, an active ENABLE means that a binary word flows from the register to
the bus; in this case, the input lines float.
The IC manufacturer can internally connect the input and output pins of a three –state register. This
not only reduces the wiring capacitance; it also reduces the number of I/O pins. For instance, fig. b
has four I/O pins instead of eight.
Figure c is the symbol for a three-state register with internally connected input and output pins. The
double headed arrow reminds us that the path is bidirectional; data can move either way.

Figure: Bidirectional Registers.

5. SAP-2 Architecture:
The following figure shows the architecture of SAP-2. All register outputs to the W bus are three-
state. As before, the controller-sequencer sends control signals (not shown) to each register. These
control signals load, enable, or otherwise prepare the register for the next positive clock edge. A brief
description of each box is given now:
 Figure: SAP-2 block architecture
SAP-2 Ports:
SAP-2 has two input ports, numbered 1 and 2. A hexadecimal keyboard encoder is connected to port
1. It allows us to enter hexadecimal instructions and data through port
1. Notice that the hexadecimal keyboard encoder sends a READY signal to bit 0 of port 2. This
signal indicates when the data in port 1 is valid. Also notice the SERIAL IN signal going to
pin 7 of port
2. A later example will show you how to convert serial input data to parallel data.
Program counter
This time, the program counter has 16 bits; therefore, it can count from
PC = 0000 0000 0000 0000
to
PC = 1111 1111 1111 1111
This is equivalent to 0000H to FFFFH, or decimal 0 to 65,535.
A low CLR(complement) signal resets the PC before each computer run, so the data processing starts
with the instruction stored in memory location 0000H.
MAR and Memory:
During the fetch cycle, the MAR receives 16-bit address from the program counter. The two-state
MAR output then address the desired memory location. The memory has a 2K ROM with addresses
of 0000H to 07FFH. This ROM contains a program called a monitor that initializes the computer on
power-up, interprets the keyboard inouts, and so forth. The rest of the memory is a 62K RAM with
address from 0800H to FFFFH.
Memory Data Register:
The memory data register (MDR) is an 8-bit buffer register. Its output sets up the RAM. The memory
data register receives data from the bus before a write operation, and it sends data to the bus after a
read operation.
Instruction Register:
Because SAP-2 has more instructions that SAP-1, we will use 8 bits for the op code rather than 4. An
8 bit op code can accommodate 256 instructions. SAP-2 has only 42 instructions, so there will be no
problem coding them with 8 bits. Using an 8-bit op code also upward compatibility with the
8080/8085 instruction set because it is based on an 8-bit op code. As mentioned earlier, all SAP
instructions are identical with 8080/8085 instructions.
Controller-Sequencer:
The controller-sequencer produces the control words or microinstructions that coordinate and direct
the rest of the computer. Because SAP-2 has a bigger instruction set, the controller-sequencer has
more hardware. Although the CON word is bigger, the idea is the same: the control word or
microinstruction determines how the registers react to the next positive clock edge.
Accumulator:
The two-state output of the accumulator goes to the ALU; the three-state output to the W bus.
Therefore, the 8-bit word in the accumulator continuously derives the ALY, but this same word
appears on the bus only when EA is active.
ALU and Flags:
Standard ALUs are commercially available as integrated circuits, These ALUs have 4 or more control
bits that determine the arithmetic or logic operations performed on words A and B. The ALU used
in SAP-2 includes arithmetic and logic operations.
In this topic a flag is a flip-flop that keeps track of a changing condition during a computer run. The
SAP-2 computer has two flags. The sign flag is set when the accumulator contents become negative
during the execution of some instructions. The zero flag is set when the accumulator contents become
zero.
TMP, B, and C Registers:
Instead of using the B register to hold the data being added or subtracted from the accumulator, a
temporary (TMP) register is used. This allows us more freedom in using the B register. Besides the
TMP and B registers, SAP-2 includes a C register. This gives us more flexibility in moving data
during a computer run.
Output Ports:
SAP-2 has two output ports, numbered 3 and 4. The contents of the accumulator can be loaded into
port 3, which derives a hexadecimal display. This allows us to see the processed data.
The contents of the accumulator can also be sent to port 4. Notice that pin 7 of port 4 sends an
ACKNOWLEDGE signal to the hexadecimal encoder. This ACKNOWLEDGE signal and the
READY signal are part of a concept called handshaking, to be discussed later.
Also notice the SERIAL OUT signal from pin 0 of port4;
6. JUMP and CALL Instructions:
SAP-2 has four jump instructions; these can change the program sequence. In other words, instead
of fetching the next instruction in the usual way, the computer may jump or branch to another part of
the program.
JMP:
To begin with, JMP is the mnemonic for jump, it tells the computer to get the next instruction includes
an address that is loaded into the program counter. For instance,
JMP 3000H
Tells the computer to get the next instruction form memory location 3000H.

Figure: (a) Unconditional jump, (b) conditional jump

Here is what happens. Suppose JMP 3000H is stored at 2005H, as shown in the figure (a). At the end
of the fetch cycle, the program counter contains,
PC = 2006H
During the execution cycle, the JMP 3000H loads the program counter with the designated address:
PC = 3000H
When the next fetch cycle begins, the next instruction comes from 3000H rather than 2006H. See
figure (a).
JM:
Sap-2 has two flags called the sign flag and the zero flag. During the execution of some instruction,
these flags will be set or reset, depending on what happens tp the accumulator contents. If the
accumulator contents become negatice, the sign flag will be set; otherwise, the sign flag is cleared.
Symbolically,
0 𝑖𝑓 𝐴 ≥ 0
𝑠={
1 𝑖𝑓 𝐴 < 0
Where S stands for sign flag. The sign flag will remain set or clear until another operation that affects
the flag.
JM is a mnemonic for jump if minus; the computer will jump to a designated address if and only if
the sign flag is set. As an example, suppose a JM 3000H is stored at 2005H. After this instruction has
been fetched,
PC = 2006H
If S = 1, the execution of JM 3000H loads the program counter with
PC = 3000H
Since the program counter now points to 3000H, the next instruction will come from 3000H.
If the jump condition is not met (S=0), the program counter is unchanged during the execution cycle.
Therefore, when the next fetch cycle begins, the instruction is fetched from 2006H.
Figure (b) symbolizes the two possibilities for a JM instruction. If the minus condition is satisfied,
the computer jumps to 3000H for the next instruction. If the minus condition is not satisfied, the
program falls through to the next instruction.
JZ:
The other flag affected by accumulator operations is the zero flag. During the execution of some
instructions, the accumulator will become zero to record this event, the zero flag is set; if the
accumulator contents do not go to zero, the zero flag is reset. Symbolically,
0 𝑤ℎ𝑒𝑛 𝐴 ≠ 0
𝑍={
1 𝑤ℎ𝑒𝑛 𝐴 = 0
JZ is the mnemonic for jump if zero; it tells the computer to jump to the designated address only if
the zero flag is set. Suppose a JZ 3000H is stored at 2005H. If Z=1 during the execution of JZ 3000H.
On the other hand, if Z=0, the next instruction will come from 2006H.
JNZ:
JNZ stands for jump if not zero. In this case, we get a jump when the zero flag is clear and no jump
when it is set. Suppose a JNZ 7800H is stored at 2100H, if Z=0, the next instruction will come from
7800H; however, if Z=1, the program falls through to the instruction at 2101H.
JM, JZ, and JNZ are called conditional jumps because the program jump occurs only if certain
conditions are satisfied. On the other hand, JMP is unconditional; once this instruction is fetched, the
execution cycle always jumps the program to the specified address.
7. CALL and RET Instructions
A subroutine is a program stored in the memory for possible use in another program. Many
microcomputers have subroutines for finding sines, cosines, tangent, logarithms, square roots, etc.
These subroutines are part of the software supplied with the computer.
CALL is the mnemonic for call the subroutine. Every CALL instruction musrt incude the starting
address of the desired subroutine. For instance, if a square-root subroutine starts at address 5000H
and a logarithm subroutine at 6000H, the execution of
CALL 500H
Will jump to the square-root subroutine. On the other hand, a
CALL 6000H
Produces a jump to the logarithmic subroutine.
RET stands for return. It is used at the end of every subroutine to tell the computer to go back to the
original program. A RET instruction is to a subroutine as a HLT is to a program. Both tell the
computer that something is finished. If you forget to use a RET at the end of a subroutine, the
computer cannot get back to the original program and you will get computer trash.
When a CALL is executed in the SAP-2 computer, the contents of the program counter are
automatically saved in memory locations FFFEH and FFFFH (the lst two memory locations). The
CALL address is the loaded into the program counter, so that execution begins with the first
instruction in the subroutine. After the subroutine is finished, the RET instruction causes the address
in memory locations FFFEH and FFFFH to be loaded back into the program counter. This returns
control to the original program.

Figure: CALL Instruction

The above figure shows the program flow during a subroutine. The CALL 500H sends the computer
to the subroutine located at 5000H. After this subroutine has been completed, the RET sends the
computer back to the instruction following the CALL. CALL is unconditional, like JMP. Once a
CALL has been fetched into the instruction register, the computer will jump to the starting address
of the subroutine.
8. What is SAP-3 Computer?
The SAP-3 computer is an 8-bit microcontroller that is upward-compatible with the 8085
microprocessor. In this topic, the emphasis is on the SAP-3 instruction set. This instruction set
includes all the SAP-2 instructions of the preceding chapter plus new instructions to be discussed. It
includes T-states, flags, and so forth, for the SAP-3 instructions.
9. SAP-3 Programming Model:
All you need to know about SAP-3 programming model of the following figure this is a diagram
showing the CPU registers needed by a programmer.
Some of the CPU registers are familiar from SAP-2. For instance, the program counter (PC) is a 16
bit register that can count form 0000H to FFFFH or decimal 0 to 65,535. As you know, the program
counter sends out the address of the next instruction to be fetched. This address is latched into the
MAR.
CPU registers A, B, and C are the same as in SAP-2. These 8-bit registers are used in arithmetic and
logic operations. Since the accumulator is only 8 bit wide, the range of unsigned numbers is 0 to 255;
the range of signed 2’s complement numbers is -128 to +127.
SAP-3 has additional CPU registers (D, E, H, and L) for more efficient data processing. The 8-bit
registers can be loaded with MOV and MVI instructions, the same as the A, B, and C registers. Also
notice the F register, which stores flag bits S, Z, and others.
Finally, there is the stack pointer (SP), a 16 bit register. This new register controls a protion of
memory known as the stack. The following figure shows all the CPU registers needed to understand
the SAP-3 instruction set. With the programing model we can discuss the SAP-3 instruction set,
which is upward-compatible with the 8080 and 8085.

Figure: SAP-3 Programming model

10. JUMP Instruction in SAP-3 Computer:

Here are the SAP-2 jump instructions that become part of the SAP-3 instruction set:
JMP address (Unconditional jump)
JM address (Jump of minus)
JZ address (Jump if zero)
JNZ address (Jump if not zero)
Here are some more SAP-3 jump instructions.
JP:
JM stands for jump if minus. When the program encounters a JM address, it will jump to the specified
address if the sign flag is set. The JP instruction has the opposite effect. JP stands for jump if positive
(including zero). This means that
JP address
Produces a jump to the specified address if the sign flag is reset.
JC and JNC:
The instruction
JC address
Means to jump to the specified address if the carry flag is set. In short, JC stands for jump if carry.
Similarly,
JNC address
Means to jump to the specified address if the carry flag is not set. That is, jump if no carry.
Here is a program segment to illustrate JC and JNC:
Label Instruction Comment
REPEAT: MVI A, FEH
ADI 01H
JNC REPEAT
MVI A, C4H
JC ESCAPE
.
.
.
MOV L,A
ESCAPE:
The MVI loads the accumulator with FEH. The ADI adds 1 to get FEH. Since no carry takes place,
the JNC takes the program back to the REPEAT point, where a second ADI is executed. This time
the accumulator overflows to get contents of 00H with a carry. Since the CY flag is set, the program
falls through the JNC. The accumulator is loaded with C4H. Then the JC produces a jump to the
ESCAPE point, where the C4H is loaded into the L register.
JPE and JPO:
Besides the sign, zero, and carry flag, SAP-3 has a parity flag designated P. During the execution of
certain instruction (like ADD, INR, etc), the ALU result is checked for parity. If the result has an
even number of 1s, the flag is reset.
The instruction
JPE address
Produces a jump to the specified address when the parity flag is set (even parity). On the other
hand,
JPO address
Results in a jump when the parity flag is reset (odd parity). For instance, given these flags,
S=1 Z=0 CY=0 P=1
The program would jump if it encountered a JPE instruction; but it would fall through a JPO
instruction.
11. The stack:

Figure: (a) SAP-2 Stack & (b) Example of stack

A stack is a portion of memory set aside primarily for saving return addresses. SAP-2 has a stack
because addresses FFFEH and FFFFH are used exclusively for saving the return address of a
subroutine call. Figure(a) shows how to visualize the SAP-2 stack.
SAP-3 is different. To begin with, the programmer decides where to locate the stack and how large
to make it. As an example, figure(b) shows a stack between addresses 20E0H and 20FFh. This stack
contains 32 memory locations for saving return addresses. Programmers can locate the stack
anywhere they want in memory, but once they have set up the stack, they no longer use that portion
of memory for program and data. Instead, the stack becomes a special space in memory, used for
storing the return addresses of subroutines calls.
12. Stack PUSH Instructions:
The contents of the accumulator and the flag register are known as the program status word (PSW).
The format for this word is
PSW = AF
Where,
A=contents of accumulator
F=contents of flag register
The accumulator contents are the high byte, and the flag contents the low byte. When calling
subroutines, we usually have to save the program status word, so that the main program can resume
after the subroutine is executed. We may also have to save the contents of the other registers.
PUSH instructions allow us to save data in the stack. Here are the four PUSH instructions:
PUSH B
PUSH D
PUSH H
PUSH PSW
Where,
B stands for BC
D stands for DE
H stands for HL
PSW stands for program status word
When a PUSH instruction is executed, the following things happen:
1. The stack pointer is decremented to get a new value of SP-1.
2. The high byte in the specified register pair is stored in 𝑀𝑠𝑝−1
3. The stack pointer is decremented again to get SP-2
4. The low byte in the specified register pair is stored in 𝑀𝑠𝑝−2

Figure: Stack PUSH Instructions

 Here is an example. Suppose:
BC = 5612H
SP=2100H

When a PUSH B is executed,

1. The stack pointer is decremented to get 20FFH
2. The high byte 56H is stored at 20FFH (fig. a)
3. The stack pointer is again decremented to get 20FEH
4. The low byte 12H is stored at 20FEH (fig. b).

13. Stack POP Instructions:

Here are four POP instructions:
POP B
POP D
POP H
POP PSW
Where, B stands for BC
D stands for DE
H stands for HL
PSW stands for program status word
When a POP is executed, the following happens:
1. The low byte is read from the memory location addressed by the stack pointer. This byte
is stored in the lower half of the specified register pair.
2. The stack pointer is incremented.
3. The high byte is read and stored in the upper half of the specified register pair.
4. The stack pointer is incremented.
Here’s an example. Suppose the stack is loaded as shown in the following figure. Then the
execution of POP B does the following:
1. Byte 25H is read from 20FAH () and stored in the C register.
2. The stack pointer is incremented to get 20FBH. Byte 9AH is read from 20FBH and stored
in the B register. The BC register pair now contains.
BC = 9A25H
3. The stack pointer is incremented to get 20FCH
Each time we execute a POP, 2 bytes come off the stack. If we were to execute a POP PSW and a
POP H in figure, the final register contents would be
AF = 5678H
HL = 1234H
And the stack pointer would contain
SP = 2100H
 Figure: Implementation of POP instruction

14. Differences between SAP-1 and SAP-2 Architecture

SAP-1 SAP-2
It has 8-bit bus. It has 16-bit bus.
PC is 4-bit. PC is 16-bit.
It does not have hexadecimal keyboard encoder. It has hexadecimal keyboard encoder.
It has single input. It has two input ports.
MAR receives 4-bit address from PC. MAR receives 16-bit address from PC.
It does not have ROM. It has 2 KB ROM.
It has 16 Byte memory. It has 62 KB memory.
It does not have MDR. It has MDR.
It has only adder/subtractor. It has ALU.
It does not have flag. It has 2 flags.
It does not have temporary register. It has temporary register.
It has single register (B). It has 2 registers (B and C).
It has single output port. It has 2 output ports.
It has 5 instruction sets. It has 42 instruction sets.