This document summarizes different types of memory used in microprocessor-based systems. It discusses read-only memory (ROM) and random access memory (RAM), describing their purposes and characteristics. It then covers various memory devices like SRAM and DRAM. The rest of the document details how memory devices interface with microprocessors, including address decoding, control signals, and designing the memory interface.
This document summarizes different types of memory used in microprocessor-based systems. It discusses read-only memory (ROM) and random access memory (RAM), describing their purposes and characteristics. It then covers various memory devices like SRAM and DRAM. The rest of the document details how memory devices interface with microprocessors, including address decoding, control signals, and designing the memory interface.
This document summarizes different types of memory used in microprocessor-based systems. It discusses read-only memory (ROM) and random access memory (RAM), describing their purposes and characteristics. It then covers various memory devices like SRAM and DRAM. The rest of the document details how memory devices interface with microprocessors, including address decoding, control signals, and designing the memory interface.
This document summarizes different types of memory used in microprocessor-based systems. It discusses read-only memory (ROM) and random access memory (RAM), describing their purposes and characteristics. It then covers various memory devices like SRAM and DRAM. The rest of the document details how memory devices interface with microprocessors, including address decoding, control signals, and designing the memory interface.
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Memory Interface
Every µP-based system has a memory system. All systems contain two types of memories. Read-Only Memory (Volatile Memory) Random Access Memory (Read/Write Memory or Non-volatile Memory) ROM contains system software and permanent system data. RAM contains system temporary data and system application software. Memory Devices: Read-Only Memory Static Random Access Memory (SRAM) Flash Memory (EEPROM) Dynamic Random Access Memory (DRAM) Memory Pin Connections: Pin connections common to all memory devices are: Address Inputs Data Outputs or Input(s)/Output(s) Selection Input Control input to selects READ or Write Address Connections: Address inputs selects a memory location within the memory device. Labeled from A0, least significant address input AN, ‘N’ labeled, ‘N-1’then the total number of address pins Address Pins Address Memory Memory (N) Connections Locations (2N) 1K 10 A0-A9 1024 2K 11 A0-A10 2048 4K 12 A0-A11 4096 8K 13 A0-A12 8192 1M 20 A0-A19 1,048,576 Memory Device Memory Sys. Section Decoded Starting Address Last Location Address 1K 400H (1024) 10000H 103FFH (10000H+400H-1H) 4K 1000H (4096) 14000H 14FFFH (14000H+1000H-1H) 64K 10,000H 30000H 3FFFFH 1M 100,000H - - Data Connections: All memory deices has a set of data outputs or input(s)/output(s). Today, many devices have bi-directional common IO pins. Data pins are labeled with D7-D0 for an 8-bit-wide memory (Means memory device stores 8-bit of data in each of its Memory locations). 8-bit-wide memory device is often called byte-wide memory Mostly devices are 8-bit-wide, some devices are 16-bits, 4-bits or just 1-bit-wide
Datasheet (Catalog Listing) of memory devices often
Represented by: Memory Locations x Bits per Location Ex: Memory Device with 1-K memory locations and 8-bits in each location is often listed as 1K x 8 by the manufacturer. (64K x 4 , 16K x 1) Sometime memory devices classified as Total bit Capacity. Ex: 8K, 256K Selection Connections: Memory devices has one or more selection or enable inputs Chip Select (CS) Chip Enable (CE) Select (S)
RAM has at least one CS or S.
ROM has at least one CE.
If CS, CE or S input is active (Logic 0), memory device performs a read or write operation If CS, CE or S input is inactive (Logic 1), memory device do not performs a read or write operation b/c it is turned OFF or Disabled. Control Connections: Memory devices have control input (s). ROM has only one control input RAM has one or two control inputs
Control input on a ROM is Output Enable (OE) or Gate (G).
If OE = 0 and CE = 0, output is enabled If OE = 1 and CE = 0, output is at high-impedance state (disabled) Control input on a RAM, if one R/W and CS = 0 Two inputs WE (or W) = 0, to perform memory write OE (or G) = 0, to perform memory read these two pins must not be activated (Logic 0) at the same time ROM Memory: ROM most commonly used type is EPROM (Erasable Programmable Read-Only Memory) EEPROM (Electrically Erasable Programmable Read-Only Memory) or Flash Memory
Types of EPROM with following part numbers:
2704 512 x 8 Each has 2708 1K x 8 Address inputs 2716 2K x 8 Eight data pins 2732 4K x 8 One or more Chip Selection inputs (CE), and output enable (OE) 2764 8K x 8 27128 16K x 8 27256 323K x 8 27512 64K x 8 271024 128K x 8 Commonly used EPROM is 2716 EPROM has 11 address inputs and 8 data outputs It is 2K x 8 memory device
OE
CE Static RAM (SRAM): TMS4016 is a 2K x 8 read/write memory 11 address inputs 8 data input/output Address Decoding: Its is necessary to decode the address sent from the µP Without address decoder only one memory can be connected
Why Decode Memory:
8088 is compared to the 2716 EPROM
20-bit 11-bit 1M x 8 2K x 8
The decoder corrects the mismatch by decoding the address pins that do not connect to the memory device. Steps to Memory Interface Design (Decode)
• Design Questions 1. How many memory chips required? 2. How many address lines are required? 3. Determine Address range of each memory device. 4. Complete interface design using decoder. If the 20-bit binary address is decoded by the NAND gate Leftmost 9 bits are 1’s Rightmost 11 bits are X’s By this actual address range of EPROM can be determined
• Design Questions 1. How many memory chips required? 2. How many address lines are required? 3. Determine Address range of each memory device. 4. Complete interface design using decoder. F F
F F F 1111 XXXX XXXX XXXX XXXX OR Starting Address 1111 0000 0000 0000 0000 = F0000H to Ending Address 1111 1111 1111 1111 1111 = FFFFFH (its 64K-byte span of memory)
Data bus is 16-bit wide M/IO BHE (Bus High Enable) A0 or BLE
8086 must be able to write data to any 16-bit location or any 8-bit location 16-bit bus must be divided into 2 separate sections (banks) Low Bank High Bank Bank Selection is accomplish in two ways: Separate Bank Decoders Separate Bank Write Strobes
