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Planar transformer winding technique for reduced capacitance in LLC power

converters

Conference Paper · September 2016

DOI: 10.1109/ECCE.2016.7855352

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 Planar Transformer Winding Technique for
Reduced Capacitance in LLC Power Converters
Mohammad Ali Saket, Navid Shafiei, and Martin Ordonez
Electrical and Computer Engineering, The University of British Columbia, Vancouver, BC V6T1Z4 Canada
Email: alisaket@ece.ubc.ca, navid@ece.ubc.ca, and mordonez@ieee.org

Abstract— Planar transformers (PTs) offer advantages over The large intra-winding capacitance gives rise to a high charging
traditional wire-wound transformers including low-height, low current at the transformer input, resulting in a loss of overall
leakage inductance, excellent thermal characteristics, Excep- efficiency [9]. In addition, this capacitor distorts the transformer
tional reproducibility and manufacturing simplicity. Despite
voltage of LLC resonant converters in light-loading condition.
these features, PTs have very high parasitic capacitance due
Fig. 2 (a) shows the typical transformer voltage waveform of
to the large overlapping area and the small distance between
consecutive layers. These parasitic capacitances can severely LLC resonant converters in light-load condition. This distorted
affect the performance of power converters and limit the voltage causes severe problems for light-load voltage regulation.
application of PTs in high frequencies. In this paper, a new PT The output voltage cannot be regulated by sweeping the frequency
with very low parasitic capacitance is introduced to mitigate at light loading, therefore this parasitic capacitance should be
the problems that arise from the parasitic capacitances. The
minimized in order to operate with a wide voltage range [4].
superiority of the proposed PT is confirmed through finite
On the other hand, the large inter-winding capacitance produces a
element analysis (FEA) and the experimental measurements
and it is shown that the proposed transformer has 21.2 times significant displacement currents that contribute to EMI problems
less intra and 16.6 times less inter-winding capacitance than [10–12]. The distorted primary current due to these high frequency
traditional spiral PT. This significant capacitance reduction displacement currents have been shown in Fig. 2 (b). The total
has a tangible effect on the performance of power converter size and cost of the filter depends on the noise amplitudes in the
and the experimental results of employing the proposed trans- circuit and large common mode chokes or shielded EMI filters
former in 1.2 kW LLC resonant converter shows considerable
are required if the noise levels are significant. Reducing the inter-
performance improvement of the converter in terms of common
winding capacitance significantly attenuates the common mode
mode (CM) noise and light-loading voltage regulation.
(CM) noise which simplifies the filter design and shrink the total
I. I NTRODUCTION filter size.

Planar transformers (PTs) have several advantages over the In this paper a novel planar transformer with extremely low
traditional wire-wound transformers that makes them very desirable parasitic capacitances is introduced to mitigate the aforementioned
for the high power density applications. These advantages include problems. In order to reduce the intra-winding capacitance, a
lower leakage inductance, excellent thermal behaviour, low-height, novel winding layout is proposed that minimizes the voltage
increased reproducibility, significant manufacturing simplicity and gradient between overlapping traces. On the other hand, the inter-
higher reliability [1–4]. In spite of these features, the proximity winding capacitance reduction is achieved through optimizing the
of layers causes planar transformers to have much higher parasitic
C13
capacitance. While many publications have been dedicated to the
C14
reduction of leakage inductance and AC resistance [5–7], not much
publications are dedicated to the parasitic capacitance [8]. Indeed, ip Rac1 Llk1 Rac2 Llk2 is
the parasitic capacitances have severe effects on the performance +
vp + C12 RC Lm C34 vs
of power converters, especially in high frequency applications. - -
The parasitic capacitances in the transformer can be classified C24
into two groups of intra- and inter-winding capacitances. Fig. 1
shows the equivalent circuit of the transformer considering the C23
parasitic capacitances. In this figure, the intra- and inter-winding Fig. 1. The equivalent circuit of the transformer including parasitic
capacitances are shown with purple and red colors, respectively. capacitors
 Light-Load Full-Load
iLS
1
VTrans

t t

(c) (d)
Fig. 2. (a) Effect of the parasitic capacitance on the transformer voltage of LLC converter under no-load condition and (b) the effect of inter-winding
capacitance on the CM noise.

transformer structure and using low permittivity materials in the in- 4. This figure clearly shows that the proposed winding layout
tersections of primary and secondary. The validity of the hypothesis considerably mitigates the intra-winding energy and so minimizes
and superiority of the proposed transformer are confirmed by FEA the intra-winding parasitic capacitance.
and experimental results. In comparison to the traditional spiral
While the new winding layout significantly reduces the value of
PT, experimental measurements using high accuracy frequency
intra-winding capacitance, it has a negligible effect on the value of
response analyzer shows that combining the proposed winding
inter-winding capacitance. The value of inter-winding capacitance
layout and structure, the proposed PT has 21.2 times less intra
is proportional to the number of intersections between primary and
and 16.6 less inter-winding capacitance, respectively. Finally, the
secondary, the overlapping area, the distance between layers and
proposed transformer is employed in a 1.2kW LLC resonant con-
the permeability of the material between primary and secondary
verter. Given much lower parasitic capacitance, the experimental
layers. Minimizing the overlapping area of primary and secondary
measurements of the converter show a significant improvement in
windings is mentioned in [2]. However, no investigation of the DC
the performance of the converter in terms of voltage regulation and
and AC resistance are provided. In fact, the 50% utilization of PCB
CM noise.
leads to roughly double DC resistance. More importantly, in the
II. T HE PROPOSED LOW PARASITIC PLANAR minimized overlapping strategy, the interleaving does not improve
TRANSFORMER the AC resistance of windings as different windings do not meet
each other. The results of FEA shows that due to the high proximity
There are different ways to reduce the value of parasitic capac-
effect, the ratio of AC to DC resistance is around 5-7 times, even
itance between overlapping traces of a PCB. The first approach is
in the fully interleaved structures. Increasing the distance between
based on minimizing the overlapping between traces of top and
primary and secondary windings also is not a wise way of reducing
bottom side. Although this method can significantly reduce the
the inter-winding capacitance as larger separation means less space
value of parasitic capacitance, avoiding overlapping requires only
for copper and consequently, higher DC resistance. The number of
50% utilization of PCB and therefore, the DC resistance roughly
intersections depends on the structure of the transformer. Therefore,
increases two times. The other method in minimizing the value of
among all influential factors, only the number of intersections and
intra-winding capacitance is through reducing the voltage gradient
the permeability of the material in the intersections of primary and
between overlapping turns. On this basis, Fig. 3 shows a new
secondary can be manipulated to reduce the value of inter-winding
winding layout with zero voltage gradient between overlapping
capacitance, without compromising the resistance.
layers of the same PCB.
Instead of having top and bottom turns in series like traditional To find an optimized structure, different structures are simulated
spiral winding layout, the top and bottom traces are connected using FEA and the value of parasitic elements are calculated.
in parallel. The rest of the turns are duplicated on both sides FEA results clearly show that interleaved structures provide lower
of another PCB and are connected to the first PCB through a AC resistance and leakage inductance while at the same time
middle connection. In other word, each two PCBs make a complete have larger inter-winding capacitance. In this paper, an optimized
winding and the top and bottom traces of each PCB are connected structure is selected considering both AC resistance and inter-
in parallel, making the voltage gradient between overlapping traces winding capacitance. The comparison of different structures shows
zero. The comparison of intra-winding energy of the proposed that the P SSP P SSP can offer almost the same AC resistance of
winding layout and traditional spiral winding is shown in the Fig. fully interleaved structure P SP SP SP S with three intersections
 Primary 1 Secondary 2 Primary 2 Secondary 1 Secondary 1 Primary 1
Connection between
Primary 1 and 2.

S2-P2

Connection between
Secondary 1 and 2.
AIR & AIR & Kapton AIR &
Kapton Kapton Kapton

(a)

Secondary Primary Secondary Primary Secondary Primary

S-P

PCB PCB PCB PCB

(b)
Fig. 3. The comparison of the proposed transformer and traditional transformer. (a) The proposed transformer with the P 1−S1S1−P 2P 2−S2S2−P 1
structure. The top and bottom turns of each PCB are connected in parallel, providing zero voltage gradient between overlapping layers. F R4 is replaced
by air in the intersections of PCBs. (b) The traditional planar transformer. Top and bottom turns of each PCB are connected in series, resulting large
voltage gradients between top and bottom side.

3
Energy (J/m ) V V/2 3
Energy (J/m ) V V/2
7.1e-005 7.1e-005

4.2e-005 4.2e-005

4.6e-006 4.6e-006
0 V/2 V V/2
(a) 33 pJ (b) 1.1 pJ
Fig. 4. Intra-winding energy of one single PCB for (a) traditional spiral winding layout (b) the proposed winding layout
3 3
Energy (J/m ) Energy (J/m )
5.9e-004 5.9e-004

2.8e-004 2.8e-004

4.6e-006 4.6e-006
(b) (a)
Fig. 5. Inter-winding energy of one intersection between primary and secondary with different materials (a) air and (b) F R4

less. It means that by going from fully interleaved structure to the at the operating frequency. Otherwise the current is not evenly
P SSP P SSP , the value of the static inter-winding capacitance shared between top and bottom layers of PCBs and AC resistance
reduces by 43%. It should be mention that P SSP P SSP struc- increases. In that condition, FI structure gives better AC resistance.
ture for the proposed winding layout gives good results for AC However, it also increases the inter-winding capacitance as the
resistance only if the thickness of the traces is less than skin depth number of intersections increases.
 Connection of two
parts of primary

Trad-FR4
PSPSPSPS Zero Gradient
PSSPPSSP

Fig. 6. Example of the frame that is used for providing air separation
method.

The value of the inter-winding capacitance can further reduced

by employing low permittivity materials in the intersections of the Connection of two
parts of primary
windings. This option is only available in the PTs constructed by
modularly stacked double layers PCBs. For these type of PTs,
instead of using F R4 as insulation between layers, air can be used
(a)
to effectively reduce the value of inter-winding capacitance. Fig.
5 (a) and (b) show the inter-winding energy of one intersection
of primary and secondary with different insulation materials. This
figure confirms that employing the air can considerably reduce the
inter-winding capacitance. In comparison to F R4 with permittivity
equal to 4.7, the permittivity of air is around 1 and it means
(b)
employing air can reduce the value of inter-winding capacitance
4.7 times. FEA shows that replacing F R4 with air also has no
impact on the value of leakage inductance and AC resistance.
The required insulation can be provided by Kapton tape. The air
separation method can be implemented by the frames. Frames can
be realized either using hollow PCBs or plastic frames. Fig. 6
shows an example of frame that can be used to realize air separation (c)
method and maintain the physical integrity of the transformer.
Fig. 7. Experimental prototype of traditional spiral PT and the proposed
Since the frames only are required in the soldering process (the transformer (a) top view, (b) and (c) side views. In the new design, F R4
is replaced by air in the intersections.
transformer will maintain its physical structure after soldering),
they may be designed in a way that allows them to be removed the impedance of the prototypes with open secondary side. It is
after the soldering. evident that reducing the value of parasitic capacitance has pushed
the self-resonant frequency from 370 kHz to 1.7 M Hz. Finally,
III. E XPERIMENTAL R ESULTS
in order to show the effect of parasitic capacitance reduction on the
In order to confirm the validity of the hypothesis and show
performance of the power converter, the prototypes are employed
the superiority of the proposed PT, prototypes of the new and
in a 1.2kW LLC resonant converter. Fig. 9 (a) and (b) show
traditional spiral PTs are manufactured and compared in terms of
full load waveforms of the converter. It is clear that reducing the
parasitic capacitance. Fig. 7 (a), (b), and (c) show the top and side
inter-winding capacitance greatly mitigates the CM noise problem
views of the traditional PT and the proposed transformer. Table.
and makes the current waveform sinusoidal. Fig. 9 (c) shows
I shows the specifications and parasitic of the prototypes. The
the no-load waveforms of the converter with the traditional spiral
structure of PT with traditional winding layout is P SP SP SP S
transformer. This distorted voltage makes the FHA approximation
and PCB is used as insulation between separate PCBs. On the
invalid and consequently, predicting the output voltage behaviour is
other hand, the structure of the proposed PT is P SSP P SSP
not possible. Under this condition, the relationship between output
and air is used between PCBs of different windings. The required
voltage and frequency is not monolithic and the output voltage
insulation clearance is provided using Kapton tape. Fig. 8 shows
 Traditional
356 kHz New
1.787 MHz
TABLE I
P ROTOTYPE CHARACTERISTICS

Converter Parameters Parasitic capacitances (pF)

Parameters Value Type Cp−intra Cinter
Np /Ns 8/4
Core ELP 58/11/38 New 32 85
PCB Thickness 0.6 mm
Copper Thickness 4 Oz
Primary Layers 4 Trad 680 1414
Secondary Layers 4

Fig. 8. Frequency response of prototypes with open secondary side.

Reducing the parasitic capacitance has pushed the self-resonant frequency
considerably.

High frequency CM noise on primary Noise-free primary current due to

current due to high inter-winding Cap very low value of inter-winding Cap

CM current at the secondary side No CM current at the secondary side

(a) (b)

High frequency ocilation on transformer Small voltage ocilations damp very soon.
voltage due to the high value of stray Cap

(c) (d)
Fig. 9. Experimental results of prototypes employed in a LLC resonant converter. Channel 1, 2, 3, and 4 are associated with inverter voltage, primary
current, secondary voltage, and secondary current, respectively. (a) Full-Load waveforms of the traditional transformer, (b) Full-Load waveforms of the
proposed transformer,(c) No-Load waveforms of the traditional transformer,(d) No-Load waveforms of the proposed transformer

of converter cannot be regulated. Fig. 9 (d) shows the no-load and verified by the FEA and experimental measurements. In order
voltage of the converter with the proposed transformer. The impact to reduce the intra-winding capacitance, a novel winding layout
of reducing the parasitic capacitance is evident. The transformer with zero voltage gradient between overlapping traces is proposed
voltage is very similar to a square waveform and therefore, the that strongly mitigates the intra-winding capacitance between top
output voltage varies monolithically with the frequency and can and bottom traces of the PCB. The inter-winding capacitance is
be regulated. addressed through optimizing the transformer structure and using
IV. C ONCLUSION the low permeability materials in the intersections. FEA is used
In this paper, a novel planar transformer with very low parasitic for finding an optimized structure with minimum AC resistance
capacitance for high frequency switch-mode converters is proposed and inter-winding capacitance. Combining the proposed parasitic
 capacitance reduction methods, the value of intra and inter-winding
capacitances are reduced 21.2 and 16.6 times, respectively. Finally,
the proposed transformer is employed in a 1.2kW LLC resonant
converter and the converter’s performance improvement in terms of
CM noise and voltage regulation is showed through experimental
measurements.
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