Tda 6110 XJ

ORDER NO.
KMS0510141CE
Bus Master Card
KX-TDA6110XJ
KX-TDA6110X
(for Europe, Asia Oceania, Middle Near East, Latin
America, Russia and Africa)
IMPORTANT INFORMATION ABOUT LEAD FREE, (PbF), SOLDERING

If lead free solder was used in the manufacture of this product the printed circuit boards will be marked PbF.
Standard leaded, (Pb), solder can be used as usual on boards without the PbF mark.
When this mark does appear please read and follow the special instructions described in this manual on the use of PbF and how
it might be permissible to use Pb solder during service and repair work.
© 2005 Panasonic Communications Co., Ltd. All

rights reserved. Unauthorized copying and
distribution is a violation of law.
KX-TDA6110XJ / KX-TDA6110X
CONTENTS
Page Page
1 ABOUT LEAD FREE SOLDER (PbF: Pb free) 3 9.1. PREPARATION 37
1.1. SUGGESTED PbF SOLDER 3 9.2. REMOVAL PROCEDURE 37
1.2. HOW TO RECOGNIZE THAT Pb FREE SOLDER IS 9.3. INSTALLATION PROCEDURE 37
USED 4 9.4. REMOVING SOLDER FROM BETWEEN PINS 37
2 FOR SERVICE TECHNICIANS 4 10 TERMINAL GUIDE OF ICS, TRANSISTORS AND DIODES 38
3 GENERAL DESCRIPTION 4 11 CABINET AND ELECTRICAL PARTS LOCATION 39
4 BUS-M CARD HARDWARE FUNCTION SPECIFICATION 5 12 ACCESSORIES AND PACKING MATERIALS 40
5 SYSTEM CONSTRUCTION 6 13 REPLACEMENT PARTS LIST 41
5.1. INSTALLING/REMOVING THE OPTIONAL SERVICE 13.1. CABINET AND ELECTRICAL PARTS LOCATION 41
CARDS 7 13.2. ACCESSORIES AND PACKING MATERIALS 41
6 BLOCK DIAGRAM 13 13.3. MAIN BOARD PARTS 41
6.1. BLOCK DISCRIPTION 14 14 FOR SCHEMATIC DIAGRAM 45
6.2. DESCRIPTION OF THE SIGNAL OF BUS-M 15 14.1. WAVEFORM 46
7 TROUBLESHOOTING GUIDE 17 14.2. BUS-M BLOCK DIAGRAM 47
7.1. START UP 17 15 SCHEMATIC DIAGRAM 48
7.2. CONNECTION BETWEEN SHELVES 20 15.1. No.1 48
8 IC DATA 25 15.2. No.2 50
8.1. FPGA (IC614) 25 15.3. No.3 54
8.2. PROM (IC210) 28 15.4. No.4 56
8.3. CTSW (IC101) 29 15.5. No.5 58
8.4. CIRCLINK (IC301) 34 16 PRINTED CIRCUIT BOARD 60
9 HOW TO REPLACE A FLAT PACKAGE IC 37 16.1. Component View 60
2
1 ABOUT LEAD FREE SOLDER (PbF: Pb free)

Note:
In the information below, Pb, the symbol for lead in the periodic table of elements, will refer to standard solder or solder that
contains lead.
We will use PbF when discussing the lead free solder used in our manufacturing process which is made from Tin, (Sn), Silver,
(Ag), and Copper, (Cu).
This model, and others like it, manufactured using lead free solder will have PbF stamped on the PCB. For service and repair
work we suggest using the same type of solder although, with some precautions, standard Pb solder can also be used.
Caution
• PbF solder has a melting point that is 50° ~ 70° F, (30° ~ 40°C) higher than Pb solder. Please use a soldering iron with
temperature control and adjust it to 700° ± 20° F, (370° ± 10°C). In case of using high temperature soldering iron, please
be careful not to heat too long.
• PbF solder will tend to splash if it is heated much higher than its melting point, approximately 1100°F, (600°C).
• If you must use Pb solder on a PCB manufactured using PbF solder, remove as much of the original PbF solder as possible
and be sure that any remaining is melted prior to applying the Pb solder.
• When applying PbF solder to double layered boards, please check the component side for excess which may flow onto the
opposite side (See figure, below).
1.1. SUGGESTED PbF SOLDER

There are several types of PbF solder available commercially. While this product is manufactured using Tin, Silver, and Copper,
(Sn+Ag+Cu), you can also use Tin and Copper, (Sn+Cu), or Tin, Zinc, and Bismuth, (Sn+Zn+Bi). Please check the manufac
turer’s specific instructions for the melting points of their products and any precautions for using their product with other
materials.
The following lead free (PbF) solder wire sizes are recommended for service of this product: 0.3mm, 0.6mm and 1.0mm.
3
1.2. HOW TO RECOGNIZE THAT Pb FREE SOLDER IS USED
2 FOR SERVICE TECHNICIANS

ICs and LSIs are vulnerable to static electricity.
When repairing, the following precautions will help prevent recurring malfunctions.
1. Cover the plastic parts boxes with aluminum foil.
2. Ground the soldering irons.
3. Use a conductive mat on the worktable.
4. Do not touch IC or LSI pins with bare fingers.
3 GENERAL DESCRIPTION
This card (BUS-M card) is mounted in the BUS-M slot of TDA600´s basic shelf.
It has a function to operate TDA620 expansion shelves as one PBX by connecting them with a inter-shelf connecting cable. One
BUS-M card can be connected with one expansion shelf and the number of connected shelves can be increased up to 3 by
mounting an interface expansion card (BUS-ME card).
4
4 BUS-M CARD HARDWARE FUNCTION SPECIFICATION

The outline specification of the BUS-M card is described below.
Functional Name Functional contents
Local TSW (TSW for CT-BUS) The PCM data on the CT-BUS at the back board of each shelf is routed to a local highway for inter-shelf
connections.
Upstream CT-BUS(Backplane)→Direction of local highway
A feature to Drop arbitrary 384ch on local highway from the CT-BUS of 1024ch(128ch x 8)
Downstream Local highway→Direction of CT-BUS(Backplane)
A feature to ADD arbitrary 384ch from the CT-BUS to arbitrary 16 slots on 1024ch (128ch x 8)
CT-BUS switch composition
Backboard (CT-BUS) side is 8MHz X 8stream.
Communication highway between It connects PCM highways among the basic shelf, expansion shelf 1, expansion shelf 2 and expansion
shelves shelf 3.
It wires them in a star shape configuration centering the CTSW on the BUS-M mounted on the basic shelf.
It uses switching function between local highways of the CT-SW in the basic shelf to connect expansion
shelves.
Allocation between TSW shelves of 2048ch X 1024ch in capacity (physical channel number) is as follows:
Basic shelf 384ch
Expansion shelf 1 384ch
Expansion shelf 2 384ch (when equipped with the first interface extension card)
Expansion shelf 3 384ch (when equipped with the second interface extension card)
Highway 8MHz X 9stream, 3stream for each expansion shelf
It sets a loop path for delay adjustment as one highway at the local stream side of CT-SW.
It operates in a fixed delay mode which ensures isochronous frames.
It generates a inter-shelf highway clock (SHW_CLK) and frame header (SHW_FH) which are synchronized
with the basic shelf´s CT-BUS using the BUS-M/CTSW.
It delivers SHW_CLK and SHW_FH generated by the BUS-M/CTSW to the BUS-S card in the expansion
shelf.
Clock distribution and selection based Distribution of clock based on the network
on the network It drives the NETREF on the basic shelf by selecting line synchronization signal (one input for each shelf)
from the expansion shelf on the M-BUS card.
Interface Option Board It has the differential interfaces of expansion connector #2 and #3 and communication controller (CircLink-
chip) on an option board.
Control System Function
CPU Interface It extends the local bus of an SH4/CPU of an MPR into the BUS-M card.
Address 26bit
Data 16bit
Intersystem Communication Controller It has a CircLink (TMC20073) chip as a inter-shelf communication controller.
It connects shelves on a one-on-one basis and mounts 3 CircLink on the BUS-M card chips for the
expansion shelf #1, #2 and #3.
CPU-Internal Device Interface Interface to bus card internal device
Protocol conversion of a SH4-local bus and an interface to local control bus to which the following are
connected; 1) BMCTL, 2) CT-SW and 3) 3 CircLink
Interruption It relays the BUS-M interruptions, which are triggered by a CircLink #1, #2 or #3, nLOS signal or detection
of connect (or disconnect) of the expansion shelf #1, #2 and #3, to the MPR.
Equipped with interruption factor registers and enable registers.
Operation and MaintenanceFault Connect and disconnect detection of expansion shelf # 1
Detection Function Connect and disconnect detection of expansion shelf # 2
Connect and disconnect detection of expansion shelf # 3
Notification of line board clock disconnect of expansion shelf # 1(nLOS1)
It delivers RING_SYNC of a basic shelf to expansion shelf # 1, # 2, and # 3.
Display function of status notification port of expansion shelf # 1, # 2, and # 3 within 2bits.
It delivers connect signal of each shelf and shelf number to expansion shelf # 1, # 2, and # 3.
Reset Control It relays basic shelf system reset signal
Reset signal generation according to cabinet
Other Specifications
Other Specifications It sets 4 LEDs (three kinds) in the front pane: "CARD_STATUS" red/green 2 color LED ,"EXPANSION
SHELF 1 STATUS", "EXPANSION SHELF 2 STATUS", and "EXPANSION SHELF 3 STATUS".
Backboard Connector System bus extension connector (80 pins)
SH4 bus signal, CKIO, BM_nIRQ
PCM highway extension connector (90 pins)
CT_D[0:7],CT_NETREF,CT_nFRAME,CT_C8
Other signals EC_nRST, RING_SYNC
Inter-shelf connection connector Mount a connector (40 pin) for a connecting cable between the basic shelf and expansion shelves on the
front panel of the BUS card
Power Circuit Input: +15V
Output: +3.3V(DC-DC converter), For FPGA:+2.5V,+1.2V(Series Reg.)
Attention During Installation The BUS-M card does not support hot-plug.
It is assumed that the power supply is turned off when inserting or removing the BUS-M card.
5
5 SYSTEM CONSTRUCTION
6
5.1. INSTALLING/REMOVING THE OPTIONAL SERVICE CARDS

Slot Condition
Card Type Slot Type
Free 1-10 EMPR BUS-S
EMPR Card No Yes No
BUS-M Card No No Yes
Trunk Cards Yes No No
Extension Cards Yes No No
OPB3 Card Yes No No
CTI-LINK Card Yes No No
EECHO Card Yes No No
Caution:
To protect the back board from static electricity, do not touch parts on the back board in the main unit and on the optional
service cards.To discharge static, touch ground or wear an earthing strap.
BUS-M connector between shelves
Mount 3 same connectors for the connection to expansion shelves on the basic shelf.
The connector map for inter-shelf connections is described in the table below.
A 20Pair twisted pair cable with 20 pin connectors is assumed as a cable for connection.
Table 0-1 Connector map for connections between shelf #1
A/B Pin No Signal Name Pin No Signal Name I/O Note
A 1 S1_CCLINK_P 2 S1_CCLINK_N I/O CircLink Bus
3 S1HWU0_N 4 S1HWU0_P I Inter-shelf Hiway(up)#0
5 S1HWU1_P 6 S1HWU1_N I Inter-shelf Hiway(up)#1
9 S1_NETREF_P 10 S1_NETREF_N I Network Reference Signal
11 S1_SHW_nFH_N 12 S1_SHW_nFH_P O Inter-shelf Frame header Signal
13 S1_SHW_CLK_P 14 S1_SHW_CLK_N O Inter-shelf Hiway Clock(8.192MHz)
15 S1_nRESET_N 16 S1_nRESET_P O Expansion shelf Reset Signal
17 S1_RINGSYNC_P 18 S1_RINGSYNC_N O Ringer Sync Signal
19 S1HWD0_N 20 S1HWD0_P O Inter-shelf Hiway(down)#0
B 1 GND 2 GND - Digital Ground
3 S1_CPU_STATUS1_N 4 S1_CPU_STATUS1_P I BUS-S Status #1
5 S1_CPU_STATUS0_P 6 S1_CPU_STATUS0_N I BUS-S Status #0
7 S1_nLOS0_P 8 S1_nLOS0_N I Loss of Sync Signal
9 NSLF_PRS0/(Pull-up) 10 NSLF_PRS0/(GND) I Expansion shelf connect Status
11 ESLFID0[0]/GND 12 ESLFID0[1]/GND O Extension Shelf ID
13 NC 14 NC Reserved pin
15 S1_HWD2_P 16 S1_HWD2_N O Inter-shelf Hiway(down)#2
17 S1_HWD1_N 18 S1_HWD1_P O Inter-shelf Hiway(down)#1
19 GND 20 GND Digital Ground

A 1 S2_CCLNK_P 2 S2_CCLNK_N I/O Circ-Link Bus
B 1 GND 2 GND Digital Ground
11 ESLFID0[0]/(Pull-up) 12 ESLFID0[1]/GND O Extension Shelf ID
13 NC 14 NC
7

A 1 S3_CCLNK_P 2 S3_CCLNK_N I/O Circ-Link Bus
B 1 GND 2 GND Digital Ground
11 ESLFID0[0]/GND 12 ESLFID0[1]/(Pull-up) O Extension Shelf ID
13 NC 14 NC
Connector 1(for expansion shelf #1)15pair

Signal name I/O type Description
S1_CCLINK_P, I/O CircLink signal conductor
S1_CCLINK_N
S1_nRESET_P, O Reset signal drive to expansion shelf # 1
S1_nRESET_N
ESLFID1[1:0] O Driven by connection from a basic shelf, shelf number notification signal(not differential signal),
"00".
nSLF_PRSA,nSLF_PRSB I/O Connect detection signal to a basic shelf(not differential signal)
S1_nLOS_P,S1_nLOS_N I Expansion shelf # 1Loss of Sync detection
S1_CPU_STATUS[1:0]_P, I Status notification port of expansion shelf #1[1:0]
S1_CPU_STATUS[1:0]_N
S1_RINGSYNC_P, O Driven by expansion shelf # 1RINGER synchronizing signal
S1_RINGSYNC_N
S1HWD0-2_P,S1HWD0-2_N O Downstream highway (BUS-M→BUS-S#1 8M:128ch X 3)
S1HWU0-2_P,S1HWU0-2_N I Upstream highway (BUS-S#1→BUS-M 8M:128ch X 3)
S1_SHW_nFH1_P, O Highway frame signal (width of 8.192MHz) output between shelves(basic shelf→expansion shelf)
S1_SHW_nFH1_N It outputs SHW_FH of Tacker.
S1_SHW_CLK_P, O Highway clock (8.192MHz) output between shelves(basic shelf→expansion shelf)It inputs the
S1_SHW_CLK_N clock for speech communication delivered from a basic shelf.
S1_NETREF_P, I Line synchronizing signal between shelves(expansion shelf→basic shelf)Line synchronizing
S1_NETREF_N signal output from a expansion shelfIt outputs synchronizing signal extracted from the line card
mounted on the expansion shelf
Connector 2(for connecting expansion shelf #2)

S2_CCLINK_P,S2_CCLINK_N I/O CircLink signal conductor
S2_nRESET_P, O Reset signal for expansio shelf #2
S2_nRESET_N
ESLFID2[1:0] O Driven by connection from a basic shelf,shelf number notification signal(not differential signal),
"01"
nSLF_PRSA,nSLF_PRSB I/O Connect detection signal to a basic shelf(not differential signal)
S2_nLOS_P,S2_nLOS_N I Expansion shelf # 2Loss of Sync detection
S2_CPU_STATUS[1:0]_P, I Status notification port of expansion shelf #2[1:0] (not differential signal)
S2_RINGSYNC_P, O Driven by expansion shelf # 2RINGER synchronizing signal
S2_RINGSYNC_N
S2HWD0-2_P,S2HWD0-2_N O Downstream highway(BUS-M→BUS-S#2 8M:128ch X 3)
S2HWU0-2_P, S2HWU0-2_N I Upstream highway (BUS-S#2→BUS-M 8M:128ch X 3)
S2_SHW_nFH_P, O Highway frame signal (width of 8.192MHz) output between shelves(Basic shelf → expansion
S2_SHW_nFH_N shelf) It outputs SHW_FH of Tacker.
S2_SHW_CLK_P, O Highway clock (8.192MHz) output between shelves(basic shelf → expansion shelf)It inputs the
S2_NETREF_P, I Line synchronizing signal between shelves(expansion shelf → basic shelf)Line synchronizing
S2_NETREF_N signal between shelves(expansion shelf → basic shelf)Line synchronizing signal output from a
expansion shelfInput synchronizing signal extracted from the line card mounted on the
expansion shelf
8
Connector 3(for connecting expansion shelf #3)

S3_CCLINK_P, I/O CircLink signal conductor
S3_CCLINK_N
S3_nRESET_P, O Reset signal for expansio shelf #3
S3_nRESET_N
ESLFID3[1:0] O Driven by connection from a basic shelf, shelf number notification signal(not differential signal),
"10".
nSLF_PRSA,nSLF_PRSB I/O Connect detection signal to basic shelf(not differential signal)
S3_nLOS_P,S3_nLOS_N I Expansion shelf #3 Loss of Sync detection
S3_CPU_STATUS[1:0]_P, 1 Status notification port of expansion shelf #3 [1:0]
S3_RINGSYNC_P, O Driven by expansion shelf #3 RINGER synchronizing signal
S3_RINGSYNC_N
S3HWD0-2_P,S3HWD0-2_N O Downstream highway (BUS-M→BUS-S#3 8M:128ch X 3)
S3HWU0-2_P,S3HWU0-2_N I Upstream highway (BUS-S#3→BUS-M 8M:128ch X 3)
S3_SHW_nFH_P, O Highway frame signal (width of 8.192MHz) output between shelves(Basic shelf→expansion
S3_SHW_nFH_N shelf) It outputs SHW_FH of Tacker.
S3_SHW_CLK_P, O Highway clock (8.192MHz) output between shelves(basic shelf→expansion shelf)It inputs the
S3_NETREF_P, I Line synchronizing signal between shelves(expansion shelf→basic shelf)Line synchronizing
S3_NETREF_N signal output from a expansion shelfIt inputs synchronizing signal extracted from the line card
mounted on the expansion shelf
9
BUS-M Card
Function
Optional shelf expansion card required when mounting Expansion Shelves. To be installed in the Basic Shelf only.
Accessories and User-supplied Items

Accessories (included): Bus Cable X 1
User-supplied (not included): none
LED Indications
Indication Color Description
CARD STATUS Green Card status indication
OFF: Starting up
Green ON: Normal
Red Card status indication
Red ON: Fault (Includes reset)
Red Flash: Out of Service
LINK3 Green Link status indication for Expansion Shelf 3
OFF: Connection error or it is not used or the bus cable is not connected.
ON: Normal connection
Note:
A postscript for LEDs of LINK 1 to LINK 3.
The conditions to light up the green LINK LED are as follows.
• Detection of the bus cable connection.
• Power on of the expansion shelf.
Lighting of the green LINK LED doesn´t necessarily mean that the communication between the base shelf and the extended
shelf has established.
10
Connecting Shelves
For a 3- or 4-shelf system, you need to install BUS-ME card(s) into the BUS-M card in the Basic Shelf. To connect the shelves,
plug the Bus Cables (supplied with the BUS-M card or BUS-ME card) into the BUS-M card. Then, plug the other end of each
Bus Cable into the BUS-S card built in to each Expansion Shelf.
Note
When installing or removing the BUS-M card, make sure that the DC power supply is turned off.
1. Mount 1 BUS-ME card (for a 3-shelf system), or 2 BUS-ME cards (for a 4-shelf system) on the BUS-M card as shown below.
11
Installing Optional Service Cards

1. Insert the card along the guide rails.
2. Holding the card as follows, push the release lever in the direction of the arrow so that the card is made to engage with the
connector on the back board securely.
3. Turn the 2 screws clockwise to fix the card.
12
6 BLOCK DIAGRAM
BSOP1[1:0] +1.2V
+2.5V
BSOP2[1:0]
+3.3V
LED/Green
BSOP3[1:0] Serial
+2.5V
LED control +3.3V
PROM
LED/Red nDIAG1,nCMIBYP1
nDIAG2,nCMIBYP2
ES1Status/Green IC614 BM_nPRS
nDIAG3,nCMIBYP3
* Dashed functions are mounted
ES2Status/Green on BUS-ME (KX-TDA6111) S1_NETREF
ES2Status/Green S2_NETREF CT_NETREF
40MHz S3_NETREF [FPGA] nEC_RST
X'tal
Expansion Backboard connect or

BMCTL BM_nRST
nINTR3 BM_nIRQ
BUS-S#3
LVDS nDIAG1,nCMIBYP1 nINTR2
Transceiver
[Circlink chip]
TMC20073 nINTR1
nEC_RST
EMPR Control Signal
Inter shelf connector #3
nMRESET1
LSTo[9:11] nMRESET2 BUS
SHW_CLK nMRESET3 EMPR
LVDS nLOS1 data bus
SHW_FH nLOS2 address bus
Driver
RINGERSYNC nLOS3
nMRESET3 nSLF1_PRS
LSTi[9:11] nSLF2_PRS
nSLF3_PRS
LVDS
S3_NETREF
nLOS3 BUS-M internal bus
Receiver
BSOP3[1:0]
16MHz
X'tal
nSLF3_PRS
ESLID3[1:0] " 10"
BUS-S#2 nEC_RST
SHW_CLK
LVDS [Circlink chip] nINTR2
Transceiver
TMC20073 nDIAG2,nCMIBYP2 SHW_FH
LSTo[6:8] LSTo[9:11]
SHW_CLK
40MHz LSTi[9:11] IC101
LVDS SHW_FH
Driver X'tal LSTo[6:8]
RINGERSYNC
nMRESET2 LSTi[6:8] CT- BUS
Switch
S2_NETREF ZL50031
LSTi[6:8] LSTo[3:5]
LVDS
nLOS2 LSTi[3:5]
Receiver
BSOP2[1:0] nEC_RST
nSLF2_PRS LSTo[0:2] CT_D[7:0]

ESLID2[1:0] " 01"
LSTi[0:2]
nEC_RST CT_C8,
IC301 CT_FRAME
IC311 BUS-S#1 nINTR3
Back Board Connector
LVDS
Transceiver [Circlink chip] nDIAG3,nCMIBYP3
TMC20073
System Clock (20MHz) RINGERSYNC
LSTo[3:5] DIV(1/ 2)
IC312 SHW_CLK 40MHz
CT_NETREF
IC313 SHW_FH X'tal IC612
+1.2V 1.2V
LVDS RINGERSYNC Regulator
Driver nMRESET1
S3_NETREF +2.5V 2.5V

IC314 LSTi[3:5] Regulator
IC604
IC315 nLOS1 IC605
LVDS
DC/ DC +15V
Receiver
BSOP1[1:0] +3.3V Conv.
ESLID1[1:0] " 00"

nSLF1_PRS
KX-TDA6110XJ/KX-TDA6110X BUS-M BLOCK DIAGRAM
13
6.1. BLOCK DISCRIPTION

The BUS-M card consists of the interface with the EMPR, the BMCTL (FPGA) comprising a control circuit within the card, the
CTSW (system TSW) exchanging the PCM highway interface of the basic shelf backboard and the PCM highways of the expansion
shelves, the CircLink (communication controller) realizing the control message communication between the basic shelf and expsion
shelves, the connectors connecting the shelf-to-shelf communication cables, and the differential receiver (LVDS standard)
comprising the differential communication channels.
BMCTL Block
The BMCTL has a glue logic function to connect the expansion bus of the EMPR card and the internal control bus of the BUS-
M card and a function to terminate and relay the control signals connected to the control register in the BUS-M card and the
expansion shelves.
The main functions of the BMCTL are as follows.

1. Termination of the triggers such as CircLink interruption (nINTRRCL1, nINTRCL2, nINTRCL3), cable insert detection
interruption (SSSTAT1, SSSTAT2, SSSTAT3) and line out of sync detection interruption (nLOS1, nLOS2, nLOS3) within the
BUS-M card, and generation of the BUS-M interruption signal (BM_nIRQ) for the EMPR card.
2. Generation of reset signal (nMRESET1, nMRESET2,nMRESET3) according to each expansion shelf.
3. Selection of line synchronizing signal (S1_NETREF,S2_NETREF, S3_NETREF) input from expansion shelf and drive of line
synchronizing signal line (CT_NETTREF) on basic shelf backboard.
4. Control of maintenance function signal (nCMIBYP3, nDIAG1, nCMIBYP1, nDIAG2, nCMIBYP2, and nDIAG3) control to
CircLink # 1(IC301), # 2, and # 3.
5. Control of output pin enable signal (ODEZL) of CT-BUS switch (IC101).
6. Control of status LED control signal (LED_RED,LED_GR) and link LED control signal (ES1S_LED, ES2S_LED, and
ES3S_LED).
7. Register display of extended shelf status display signal (BSOP1,BSOP2,BSOP3).
8. Generation of address decode to CircLink # 1 (IC301), #2, and #3 and chipselect (nCSCL1, nCSCL2, nCSCL3).
9. Generation of address decode to CT-BUS switch (IC101) and chipselect (nCSZL).
CT-BUS switch
The CTSW has the following functions; 1) to exchange 1536ch of PCM highways in total which consists of 384ch of the
PCM highways on the basic shelf backboard and 1152ch to be connected to three expansion shelves (384ch for each shelf),
2) to generate the PCM highway clock and frame synchronization signal which are distributed among the expansion shelves.
Communication Controller block
The CircLink is a communication controller to realize control message communication between the basic shelf and
expansion shelves. The CircLink chips on expansion shelves and the CircLink chips on the BUS-M card are connected one-
on-one basis. But the CircLink chip initially mounted on the BUS-M card only corresponds to the extended port #1, so the
CircLink chips corresponding to the extended ports #2 and #3 should be added by mounting BUS-ME cards (KX-TDA6111).
Shelf Interface block
The shelves are connected with 20 pairs of twisted pair cables. Three ports of 40 pin half pitch connectors for cable
connections and an LVDS interface ship as a driver receiver of board-to-board signal are mounted on the board.
But the LVDS device initially mounted on the BUS-M card only corresponds to the extended port #1, so the LVDS devices
corresponding to the extended ports #2 and #3 should be added by mounting BUS-ME cards (KX-TDA6111).
Power block
The BUS-M card uses three types of power supplies; +3.3 V, +2.5 V and +1.2 V. Since a power supply of +15 V is supplied
from the backboard, the power block consists of three types of devices; a DC/DC converter converting +15 V into +3.3 V and
series regulators converting +3.3 V into +2.5 V and +3.3 V into +1.2 V.
Others
- Mount two 120 pin board-to-board connectors on the board for mounting 2 ports of the BUS-ME cards.
- Since the BMCTL is implemented by SRAM-type FPGA (IG614), it is necessary to read the configuration data during start-
up. The configuration data is stored in a serial PROM (IC210). The reading of the configuration data occurs when power is
on and the EC_nRST signal is asserted. Since the status of the internal register is random just after the completion of
configuration, it requires logical reset by the EC_nRST.
14
6.2. DESCRIPTION OF THE SIGNAL OF BUS-M

Signal Name Function
BM_nPRS Signal informing the EMPR card that the BUS-M card is inserted
BM_DATA[15:0] Data path extended from EMPR card
BM_AD[25:0] Address bus extended from EMPR card
BM_nRST BUS-M card logic reset signal controlled by EMPR card
BM_nIRQ BUS-M card interrupt signal to be notified to EMPR card
BM_nCS Chip select signal to BUS-M card extended from EMPR card
BM_nRDY Ready signal extended from EMPR card
BM_WE[1:0] Write signal extended from EMPR card
BM_RDnWR Bus direction control signal extended from the EMPR card
MnWRD NWrite/Read signal from EMPR Card (Local control signal in BUS-M card)
MnWE0 Write enable low byte signal from EMPR Card (Local control signal in BUS-M card)
MnWE1 Write enable low byte signal from EMPR Card (Local control signal in BUS-M card)
MnRD Read signal from EMPR Card (Local control signal in BUS-M card)
MnRDY Ready signal to EMPR Card (Local control signal in BUS-M card)
MnCS Chip select signal from EMPR Card (Local control signal in BUS-M card)
MnIRQ Interrupt signal to EMPR Card (Local control signal in BUS-M card)
LD[15:0] Local data bus in BUS-M card
LA[25:22] LA[14:0] Local address bus in BUS-M card
nDETCL3 BUS-ME Card #3 detection
nCMI3B CircLink #3 CMI Modem control signal
nMRESET3 Expansion shelf #3 Reset signal
SSTAT3 Expansion shelf #3 BUS cable presence detection bit
nCSCL3 Chip select signal for CircLink #3 on BUS-ME card
S3_NETREF Network reference clock from Exoansion shelf #3
nDIAG3 Diagnosis function contorl signal for CircLink #3
nINTRCL3 Interrupt signal from CircLink #3 on BUS-ME card
BS32, BS31 Expansion shelf #3 BUS-S card Status signal 2
nLOS3 Loss of sync signal from Expnsion shelf #3
nDETCL2 BUS-ME Card #2 detection
nCMI2B CircLink #2 CMI Modem control signal
SSSTAT2 Expansion shelf #2 BUS cable detection port
S2_NETREF Network reference clock from Exoansion shelf #2
nDIAG2 Diagnosis function contorl signal for CircLink #2 on BUS-ME Card
nINTRCL2 Interupt singnal from CircLink #2
nLOS2 Loss of sync signal from Expnsion shelf #2
nCMI1B CircLinkk #1 CMI Modem control signal
SSSTAT1 Expansion shelf #1 BUS cable detection port
S1_NETREF Network reference clock from Expansion shelf #1
nDIAG1 Diagnosis function contorl signal for CircLink #1
nINTRCL1 Interupt singnal from CircLink #1
nLOS1 Loss of sync signal from Expansion shelf #1
nWRZL nWrite/Read signal for CTSW
nDTAZL Data acknowledge signal for CTSW
nDSZL Data strobe signal for CTSW
nCSZL Chip strobe signal for CTSW
ODEZL Output port enable signal for CTSW
C16M Global Clock Buffer Input (16MHz)
nRDCL Read signal for CircLink #1 #2 #3
nWECL Write signal for CircLink #1 #2 #3
CRDID0-7 Card ID port [0-7]
LED_RED Status LED control port (RED)
LED_GR Status LED control port (GREEN)
ES1S_LED LINK LED #1 control port
NRST System reset input port from EMPR Card
DONE Configuration Done Delay Start-up Sequence
COLK Configuration Clock
TDO JTAG Test Data output
15
Signal Name Function

TCK JTAG Test Clock
TMS JTAG Test Mode Select
TDI JTAG Test Data input
HSWAP_EN Disable Weak Pull-up Resistors During Configuration
PROG_B Program/Configure Device
EC_nRST EC bus reset signal
CT_D[0-7] Voice bus on backboard
CT_NETREF Network reference timing signal on the backboard
16
7 TROUBLESHOOTING GUIDE
7.1. START UP
17
18
19
7.2. CONNECTION BETWEEN SHELVES

7.2.1. Expansion shelf No.1
20
21
22
7.2.4. Check of call path
23
24
8 IC DATA
8.1. FPGA (IC614)
Pin No. Pin Name I/O DiscriptionPin Usage

1 nCSCL3 O chip select signal for CircLink#3 on BUS-ME card
2 S3_NETREF I Network reference clock from Expansion shelf #3
3 +3.3V(I/OVoltage) Power Supply for Output Buffer Drivers(per bank)
4 nDIAG3 O Diagnosis function contorl signal for CircLink#3
5 nINTRCL3 I Interupt singnal from CircLink#3 on BUS-ME card
6 BS32 I Expansion shelf #3 BUS-S card Status signal2
8 nLOS3 I Loss of sync signal from Expansion shelf #3
9 Groud Ground
10 nDETCL2 I BUS-ME Card #2 detection
11 nCMI2B O Circlnk#2 CMI Modem control signal
12 nSRST2 O Expansion shelf #2 Reset signal
13 SSSTAT2 I Expansion shelf #2 BUS cable detection port
14 nCSCL2 O chip select signal for CircLink #2 on BUS-ME card
25

16 Groud Ground
17 nDIAG2 O Diagnosis function contorl signal for CircLink #2 on BUS-ME Card
18 nINTRCL2 I Interupt singnal from CircLink #2
22 Groud Ground
26 SSSTAT1 I Expansion shelf #1 BUS cable detection port
27 nCSCL1 O chip select signal for CircLink #1 on BUS-ME card
29 Groud Ground
30 nDIAG1 O Diagnosis function contorl signal for CircLink #1
31 nINTRCL1 I Interupt singnal from CircLink #1
36 nWRZL O nWrite/Read signal for CTSW
37 M1 Configuration Mode Selection
40 (NC) UNUSED
41 (NC) UNUSED
42 Groud Ground
44 nDTAZL I Data acknowledge signal for CTSW
45 Groud Ground
46 nDSZL O Data strobe signal for CTSW
47 nCSZL O Chip select signal for CTSW
48 +2.5V(AUX Voltage) Power Supply for Auxiliary Circuits
49 +1.2V(CoreVoltage) Power Supply for Internal Core Logic
50 (NC) UNUSED
51 (NC) UNUSED
52 (NC) UNUSED
53 C16M I Global Clock Buffer Input(16MHz)
55 (NC) UNUSED
56 (NC) UNUSED
57 (NC) UNUSED
58 (NC) UNUSED
59 (NC) UNUSED
60 nCSTK O not use this signal
63 (NC) UNUSED
64 Groud Ground
65 (NC) UNUSED
67 Groud Ground
68 (NC) UNUSED
69 ODEZL O Output port enable signal for CTSW
70 MnWRD I nWrite/Read signal from EMPR Card
71 DONE "Configuration Done
72 CCLK Configuration Clock
73 MnWE0 I Write enable low byte signal from EMPR Card
74 MnWE1 I Write enable low byte signal from EMPR Card
76 MnRD I Read signal from EMPR Card
77 (NC) UNUSED
78 MnRDY O Ready signal to EMPR Card
79 MnCS I Chip select signal from EMPR Card
80 MnIRQ O Interupt signal to EMPR Card
81 Groud Ground
26

82 LA[0] UNUSED (Rserved)
83 LA[1] I Address bus(EMPR local bus)[1]
88 Groud Ground
89 CT_NETREF 3sO
90 nRDCL O Read signal for CircLink #1
92 nWECL O Write signal for CircLink #1
93 nRST I Syetem reset input port from EMPR Card
94 Groud Ground
95 LA[22] UNUSED (Rserved)
99 LD[0] I/O Data bus(EMPR local data bus)[0]LSB
100 LD[1] I/O Data bus(EMPR local data bus)[1]
101 Groud Ground
108 LD[7] 3s.O Data bus(EMPR local data bus)[7]MSB
109 TDO JTAG Test Data output
110 TCK JTAG Test Clock
111 TMS JTAG Test Mode Select
112 CRDID0 I Card ID port[0]
114 Groud Ground
117 Groud Ground
125 (NC) UNUSED
127 LED_RED O Status LED control port(RED)
128 LED_GREEN O Status LED control port(GREEN)
129 ES1S_LED O LINK LED #1 control port
132 LOCAL_nRST UNUSED (Rserved)
135 nDETCL3 I BUS-ME Card #3 detection
136 Groud Ground
139 Groud Ground
141 SSTAT3 I Expansion shelf #3 BUS cable detect port
142 HSWAP_EN Disable Weak Pull-up Resistors During Configuration
143 PROG_B Program/Configure Device
144 TDI I JTAG Test Data Input
Note
3s.O: 3State Output
27
8.2. PROM (IC210)
Pin No. Pinl Name I/O DiscriptionPin Usage

1 D0 O D0 is the DATA output pin to provide data for configuring an FPGA in serial mode.
2 DNC Do not connect.
3 CLK I Configuration Clock Input.
4 TDI I JTAG Serial Data Input.
5 TMS I JTAG Mode Select Input.
6 TCK I JTAG Clock Input.
7 nCF O Configuration Pulse(Open-Drain Output).
8 OE/nRESET O Output Enable/Reset(Open-Drain I/O).
10 nCE I Chip Enable Input.
11 GND Ground
13 nCEO O (not use port) Chip Enable Output.
17 TDO O JTAG Serial Data Output.
18 VCCINT +3.3V Supply.
19 VCCO +2.5V I/O Supply.
20 VCCJ +2.5V JTAG I/O Supply.
28
8.3. CTSW (IC101)

1 A13 I Address 13
2 A12 I Address 12
3 A11 I Address 11
4 A10 I Address 10
5 A9 I Address 9
6 A8 I Address 8
7 Vss Ground
8 VDD +3.3 Volt Power Supply.
9 A7 I Address 7
10 A6 I Address 6
11 A5 I Address 5
12 A4 I Address 4
13 A3 I Address 3
14 A2 I Address 2
15 A1 I Address 1
16 A0 I Address 0
17 Vss Ground
19 nRESET I Device Reset
20 TDo 3s.O Test Serial Data Out (Unused ) *not use this device JTAG function
21 TMS I Test Mode Select (Unused )
22 TCK I Test Clock (Unused )
23 nTRST I Test Reset (Unused )
24 TDi I Test Serial Data In (Unused )
25 IC_GND This pin must be connected to ground for normal operation.
29

26 IC_OPEN This pin must be left open for normal operation.
30 nST_FPo1 O ST-BUS Frame Pulse Output (Unused )
31 nST_CKo1 O ST-BUS Clock Output (Unused )
36 Vss Ground
43 VSS Ground
44 APLLVDD +3.3 Volt Analog PLL Power Supply.
45 APLLVSS Analog PLL Ground.
46 C20i I Master Clock
48 VSS Ground
54 LREF3 I Local Reference (Unused )
58 C1M5o O C1.5o Clock (Unused )
59 VSS Ground
60 nST_FPo0 O Inter shelves data transmission Frame Pulse Output
61 nST_CKo0 O Inter shelves data transmission Clock Output
63 C32/64o O C32/64o Clock (Unused )
64 SEC_LOS I Secondary Reference Lost (Unused )
65 PRI_LOS I Primary Reference Lost (Unused )
66 NREFo O Network Reference Output (Unused )
67 CTREF2 I CT-Bus Reference 2 (Unused )
68 CTREF1 I CT-Bus Reference 1 (Unused )
69 VSS Ground
71 FAIL_B O B Failure (Unused )
72 FRAME_B_io I/O Frame Reference B (Unused )
73 C8_B_io I/O Clock B (Unused )
74 FAIL_A O A Failure (Unused )
75 FRAME_A_io I/O CT_Frame input port
76 C8_A_io I/O CT_C8 input port
77 VSS Ground
79 ODE I Output Drive Enable
80 NC This pin must be left unconnected for normal operation.
88 VSS Ground
30

94 VSS Ground
96 LSTo15 3s.O Local Serial Output Streams 15
100 VSS Ground
106 VSS Ground
112 VSS Ground
119 VSS Ground
125 VSS Ground
134 VSS Ground
136 LSTi15 I Local Serial Input Streams 15
144 VSS Ground
154 nPCI_OE I PCI Output Enable
155 VDD5V +5.0 V/+3.3 V Power Supply.
159 BSTio31 I/O Backplane Serial Input/Output Streams 31(Unused )
31

163 VSS Ground
171 VSS Ground
179 VSS Ground
188 VSS Ground
203 VSS Ground
211 VSS Ground
215 BSTio7 I/O Backplane CT_D[7] Input/Output Streams 7
219 VSS Ground
32

230 VSS Ground
233 nDTA O Data Transfer Acknowledge
234 D15 I/O Data Bus 15
242 VSS Ground
252 VSS Ground
254 nCS I Chip Select
255 nDS I Data Strobe
256 R/nW I Read/Write
Note
3s.O: 3State Output
33
8.4. CIRCLINK (IC301)

2 A3/ALEPOL I Address (bit3)
3 A4 I Address (bit4)
4 A5 I Address (bit5)
5 NC (Open) No Connection.
7 nDSINV I nDS Polarity Specification/CMI Reception Error Mode
8 nRD/nDS I Read Signal Input/Data Strobe/Standalone Output Port (bit6)
9 nTMODE I Test Mode
10 nWR/DIR I Write Signal Input/Access Direction Specification/Standalone Output Port (bit7)
11 nSMODE I Scanning Mode
12 VSS Ground
13 D0/AD0 I/O Data Bus (bit0)
34

20 VSS Ground
21 D6 I/O Data Bus (bit6)
22 D7 I/O Data Bus Åibit17)
28 VSS Ground
32 VSS Ground
38 nRESET I Reset Input (low active)
39 VSS Ground
40 nINTR O Interrupt Output
41 TXEN O Port1 Transmission Enable Output
42 TXD O Transmission Data Output (Port 1 2 common)
43 TXEN2 O Port2 Transmission Enable Output
44 VSS Ground
45 TXENPOL I TXEN TXEN2 Polarity Specification
46 RXIN I Port1 Reception Data Input
47 ET1 I ARCNET Enhancing Timer Setting 1
48 RXIN2 I Port2 Reception Data Input
50 nDIAG Diagnostic Mode Selection
51 nSTALONE =H I Standalone Mode Selection
52 NSTPRE0 I NST Resolution Setting
56 PS0 I Page Size Specification (0 fixed)
57 PS1 I Page Size Specification (0 fixed)
59 NID0 I Local Node Number Setting (1 fixed)
64 VSS Ground
67 MAXID0 I MAX Identification Number Setting (0 fixed)
73 CKP0 I Transmission Rate Setting (0 fixed)
76 VSS Ground
80 MCKIN I External Master Clock Input
82 X1 I Crystal Oscillator
83 X2 O Crystal Oscillator
84 VSS Ground
85 nNSTCOUT O NST Carry Output
86 FLASHO 3s.O External Output for FLASH
35

87 NC (Open) Hi.Z This pin must be left unconnected for normal operation.
90 VSS Ground
96 VSS Ground
98 WPRE0 I Warning Timer Resolution Setting
102 nTEST0 I Test Terminal
106 NC (High) I This pin must be connected to VDD
107 nEHRD I Enhanced Read Setting
108 VSS Ground
109 nEHWR I Enhanced Write Setting
110 NC (High) I This pin must be connected to VDD
111 nCMIBYP I Bypass Setting of CMI Encoding/Decoding Circuit
112 NOPMD I Optical Transceiver Mode Selection
114 nHUBON I ON/OFF Setting of Built-in HUB Function
116 nMUX I Address Multiple Mode Selection
117 nRWM I R/W Mode Selection
118 W16 I Data Bus Width Selection
119 nSWAP I Swap Mode Selection
120 nCS I Chip Selection Input
121 VSS Ground
124 A0 I Address Input (bit0)
126 A1 I Address Input (bit1)
127 A2/ALE I Address Input (bit2)/ALE
128 VSS Ground
Note
3s.O: 3State Output
Hi.Z: High Impedance
36
9 HOW TO REPLACE A FLAT PACKAGE IC

Even if you do not have the special tools (for example, a spot heater) to remove the Flat IC, with some solder (large amount),
a soldering iron and a cutter knife, you can easily remove the ICs that have more than 100 pins.
9.1. PREPARATION solder is left at the joint on the board, the new IC will not be
attached properly.
• PbF (: Pb free) Solder
• Soldering Iron 9.3. INSTALLATION PROCEDURE
Tip Temperature of 700°F ± 20°F (370°C ± 10°C) 1. Tack the flat pack IC to the PCB by temporarily soldering
Note: We recommend a 30 to 40 Watt soldering iron. An two diagonally opposite pins in the correct positions on the
expert may be able to use a 60 to 80 Watt iron where PCB.
someone with less experience could overheat and damage
the PCB foil.
• Flux
Recommended Flux: Specific Gravity → 0.82.
Type → RMA (lower residue, non-cleaning type)
Note: See ABOUT LEAD FREE SOLDER (PbF: Pb free)
(P.3).
9.2. REMOVAL PROCEDURE Be certain each pin is located over the

correct pad on the PCB.
1. Put plenty of solder on the IC pins so that the pins can be
completely covered. 2. Apply flux to all of the pins on the IC.
Note:
If the IC pins are not soldered enough, you may give
pressure to the P.C. board when cutting the pins with a
cutter.
3. Being careful to not unsolder the tack points, slide the

soldering iron along the tips of the pins while feeding
enough solder to the tip so that it flows under the pins as
2. Make a few cuts into the joint (between the IC and its pins) they are heated.
first and then cut off the pins thoroughly.
9.4. REMOVING SOLDER FROM

3. While the solder melts, remove it together with the IC pins.
BETWEEN PINS
1. Add a small amount of solder to the bridged pins.
2. With a hot iron, use a sweeping motion along the flat part of
the pin to draw the solder from between the adjacent pads.
When you attach a new IC to the board, remove all solder

left on the land with some tools like a soldering wire. If some
37
10 TERMINAL GUIDE OF ICS, TRANSISTORS AND DIODES
38
11 CABINET AND ELECTRICAL PARTS LOCATION
39
12 ACCESSORIES AND PACKING MATERIALS
40
13 REPLACEMENT PARTS LIST

1. RTL (Retention Time Limited) Ref. Part No. Part Name & Description Remarks
No.
Note: The marking (RTL) indicates that the Retention Time 10 XUC25VW RETAINING RING
is limited for this item.
After the discontinuation of this assembly in production, the 13.2. ACCESSORIES AND PACKING
item will continue to be available for a specific period of
time. The retention period of availability is depends on the
MATERIALS
type of assembly, and in accordance with the laws Ref. Part No. Part Name & Description Remarks
governing parts and product retention. No.
A1 J0KG00000019 FILTER, CORE
After end of this period, the assembly will no longer be A2 PSJS40P34Z CORD
available. P1 PSPD1344Z CUSHION
P2 PSPP1069Z PROTECTION COVER
2. Important safety notice
P3 PSZKDA6110XJ GIFT BOX (KX-TDA6110XJ)
Components identified by mark have special P3 PSZKDA6110XU GIFT BOX (KX-TDA6110X)
characteristics important for safety. When replacing any of
these components, use only manufacture´s specified parts. 13.3. MAIN BOARD PARTS
3. The S mark means the part is one of some identical parts.
Ref. Part No. Part Name & Description Remarks
For that reason, it may be different from the installed part. No.
4. ISO code (Example: ABS-94HB) of the remarks column (ICS)
IC101 C1CB00001993 IC
shows quality of the material and a flame resisting grade
IC113 C0JBAA000319 IC
about plastics. IC114 C0JBAB000551 IC
5. RESISTORS & CAPACITORS IC200 C0JBAZ001765 IC
IC202 C0JBAZ001765 IC
Unless otherwise specified; IC203 C0JBAZ001466 IC
All resistors are in ohms (Ω) K=1000Ω, M=1000kΩ IC204 C0JBAZ001466 IC
IC205 C0JBAZ001466 IC
All capacitors are in MICRO FARADS (µF) P=µµF IC206 C0JBAZ001466 IC
*Type & Wattage of Resistor IC210 C3ZBH0000017 IC
IC211 C0JBAA000174 IC
IC301 C1DB00001428 IC
IC302 C0JBAB000535 IC
IC303 C0JBAF000484 IC
IC311 C0ZBZ0001155 IC
IC312 C0ZBZ0001153 IC
IC313 C0ZBZ0001153 IC
IC314 C0ZBZ0001154 IC
IC315 C0ZBZ0001154 IC
IC604 C0DBAGZ00029 IC
IC605 C0CBAAE00016 IC
IC607 C0EBE0000176 IC
IC612 C0CBCAD00078 IC
IC614 C1ZBZ0002890 IC
(TRANSISTORS)
Q201 B1GHCFJJ0007 TRANSISTOR(SI) S
Q202 PQVTDTA114EU TRANSISTOR(SI) S
Q601 B1DFDC000002 TRANSISTOR(SI)
Q602 B1DHCD000018 TRANSISTOR(SI)
(DIODES)
13.1. CABINET AND ELECTRICAL D600

D601
B0JCND000009
MA8051
DIODE(SI)
DIODE(SI) S
PARTS LOCATION D602 MA110 DIODE(SI) S
LED201 PSVD1VGCT LED S
Ref. Part No. Part Name & Description Remarks LED202 PSVD1VGCT LED S
No. LED203 PSVD1VGCT LED S
1 PQDF996Z SHAFT LED204 PQVDBRPY1204 LED S
2 PQHR10005Z SPACER (COILS)
3 PQUB14Z2 LEVER, EJECTOR FIL302 G1BYYYBA0002 COIL
4 PSHD1088Z SCREW FIL303 G1BYYYBA0002 COIL
5 PSHE1122Z SPACER FIL304 G1BYYYBA0002 COIL
6 PSHR1238Z SPACER, PANEL LIGHT FIL305 G1BYYYBA0002 COIL
7 PSMH1305Z PANEL, FRONT FIL306 G1BYYYBA0002 COIL
8 PSUS1020Z TORSION SPRING FIL307 G1BYYYBA0002 COIL
9 PSUS1021Y TORSION SPRING FIL308 G1BYYYBA0002 COIL
41
Ref. Part No. Part Name & Description Remarks Ref. Part No. Part Name & Description Remarks
No. No.
FIL309 G1BYYYBA0002 COIL C105 F1G1C1030008 0.01
L634 G1A330G00008 COIL C106 F1G1C1030008 0.01
(CONNECTORS) C107 F1G1C1030008 0.01
CN101 K1KA90B00009 CONNECTOR, 90P C108 F1G1C1030008 0.01
CN201 K1KB80B00027 CONNECTOR, 80P C109 F1G1C1030008 0.01
CN401 K1KAC0A00052 CONNECTOR C113 F1G1C1030008 0.01
CN402 K1KAC0A00052 CONNECTOR C114 F1G1C1030008 0.01
(COMPONENTS PARTS) C115 F1G1C1030008 0.01
RA105 D1H84704A024 RESISTOR ARRAY, 47 C116 F1G1C1030008 0.01
RA112 D1H81034A024 RESISTOR ARRAY, 10K C122 F1G1C1030008 0.01
RA302 D1H8R0040009 RESISTOR ARRAY, 10K C229 F1G1C1030008 0.01
RA306 D1H8R0040009 RESISTOR ARRAY, 0 C234 F1G1C1030008 0.01
(CRYSTAL OSCILLATOR) C240 F1G1C1030008 0.01
X301 H0J400500013 CRYSTAL OSCILLATOR C241 F1G1C1030008 0.01
X602 PSVCC0025GT CRYSTAL OSCILLATOR S C242 F1G1C1030008 0.01
(FILTERS) C243 F1K1A4750003 4.7
FIL301 J0HAAH000003 IC FILTER C244 F1K1A4750003 4.7
FIL310 J0HAAH000003 IC FILTER C245 F1K1A4750003 4.7
FIL601 J0HAAH000003 IC FILTER C246 F1G1C1030008 0.01
FIL602 J0HAAB000020 IC FILTER C247 F1G1C1030008 0.01
L101 PFVF1B221SB CERAMIC FILTER S C248 ECUV1H332KBV 0.0033
L633 PFVF2P600SG CERAMIC FILTER S C249 ECUV1H332KBV 0.0033
LA101 J0JAD0000036 IC FILTER C250 ECUV1H332KBV 0.0033
LA102 J0JAD0000036 IC FILTER C301 F1G1C1030008 0.01
(FUSES C305 F1G1C1030008 0.01
IP600 K5H502Z00003 FUSE C306 F1G1C1030008 0.01
IP601 K5H122Z00003 FUSE C307 F1G1C1030008 0.01
(CAPACITORS) C308 F1G1C1030008 0.01
C104 F1G1C1030008 0.01 C309 F1G1C1030008 0.01
42
No. No.
C311 F1G1C1030008 0.01 C1013 F1G1C1030008 0.01
C312 ECUV1H220JCV 22P C1014 F1G1C1030008 0.01
C313 ECUV1H220JCV 22P C1025 F1G1C1030008 0.01
C314 ECUV1C104ZFV 0.1 C1026 F1G1C1030008 0.01
C315 F1G1C1030008 0.01 C1027 F1G1C1030008 0.01
C316 F1G1C1030008 0.01 C1028 F1G1C1030008 0.01
C317 F1G1C1030008 0.01 C1029 F1G1C1030008 0.01
C318 F1G1C1030008 0.01 C1030 F1G1C1030008 0.01
C319 F1G1C1030008 0.01 C1031 F1G1C1030008 0.01
C320 ECUV1C104ZFV 0.1 C1032 F1G1C1030008 0.01
C610 F2G1E3310005 330 C1033 F1G1C1030008 0.01
C636 ECUV1E104ZFV 0.1 C1034 F1G1C1030008 0.01
C652 ECUV1C104ZFV 0.1 C1035 F1G1C1030008 0.01
C654 F2G1A4710013 470 C1036 F1G1C1030008 0.01
C656 ECUV1A105KBV 1 C1037 F1G1C1030008 0.01
C657 ECUV1A105KBV 1 C1038 F1G1C1030008 0.01
C658 ECUV1A106ZF 10 S C1039 F1G1C1030008 0.01
C659 ECUV1A106ZF 10 S C1040 F1G1C1030008 0.01
C660 F1G1C104A083 0.1 C1203 ECJ0EC1H221J 220P
C661 F1G1C104A083 0.1 C1205 ECJ0EC1H221J 220P
C662 ECUV1H120JCV 12P C1206 ECJ0EC1H221J 220P
C663 ECUV1H180JCV 18P C1210 ECJ0EC1H221J 220P
C664 F1G1C104A083 0.1 C1211 ECJ0EC1H221J 220P
C665 F1G1C104A083 0.1 C1215 ECJ0EC1H221J 220P
C666 F1G1C104A083 0.1 C1217 ECJ0EC1H221J 220P
C667 F1G1C104A083 0.1 C1218 ECJ0EC1H221J 220P
C668 F1G1C104A083 0.1 C1221 ECJ0EC1H221J 220P
C669 F1G1C104A083 0.1 C1224 ECJ0EC1H221J 220P
C670 ECUV1A105KBV 1 C1225 ECJ0EC1H221J 220P
C671 F1G1C104A083 0.1 C1227 ECJ0EC1H221J 220P
C672 F1G1C104A083 0.1 C1228 ECJ0EC1H221J 220P
C673 F1G1C104A083 0.1 C1229 ECJ0EC1H221J 220P
C674 F1G1C104A083 0.1 C1230 ECJ0EC1H221J 220P
C675 F1G1C104A083 0.1 (RESISTORS)
C676 ECUV1H103KBV 0.01 J101 ERJ3GEY0R00 0
C677 F1G1C104A083 0.1 J209 ERJ3GEY0R00 0
C678 F1G1C104A083 0.1 J601 ERJ3GEY0R00 0
C679 F1G1C104A083 0.1 J617 ERJ2GEYJR00 0
C681 F1G1C104A083 0.1 J630 PQ4R18XJ000 0 S
C682 F1G1C104A083 0.1 J632 PQ4R18XJ000 0 S
C683 F1G1C104A083 0.1 J636 ERJ3GEY0R00 0
C684 F1J1A2250008 2.2 J642 ERJ3GEY0R00 0
C685 ECUV1A105KBV 1 J643 ERJ3GEY0R00 0
C686 ECUV1H332KBV 0.0033 J646 ERJ3GEY0R00 0
C688 F1G1C104A083 0.1 L636 ERJ3GEY0R00 0
C689 F1G1C104A083 0.1 R109 ERJ3GEYJ103 10K
C951 ECJ0EC1H221J 220P R111 ERJ3GEYJ103 10K
C959 ECJ0EC1H221J 220P R116 ERJ3GEYJ470 47
C969 ECJ0EC1H221J 220P R122 ERJ2GEJ221 220 S
C1001 F1G1C1030008 0.01 R206 ERJ3GEYJ470 47
C1002 F1G1C1030008 0.01 R211 ERJ3GEYJ470 47
C1003 F1G1C1030008 0.01 R213 ERJ3GEYJ472 4.7K
C1004 F1G1C1030008 0.01 R215 ERJ3GEYJ331 330
C1005 F1G1C1030008 0.01 R217 ERJ3GEYJ151 150
C1006 F1G1C1030008 0.01 R218 ERJ3GEYJ151 150
C1007 F1G1C1030008 0.01 R219 ERJ3GEYJ151 150
C1008 F1G1C1030008 0.01 R220 ERJ3GEYJ472 4.7K
C1009 F1G1C1030008 0.01 R221 ERJ3GEYJ330 33
C1010 F1G1C1030008 0.01 R222 ERJ3GEYJ330 33
C1011 F1G1C1030008 0.01 R223 ERJ3GEYJ330 33
C1012 F1G1C1030008 0.01 R230 ERJ3GEYJ103 10K
43
No. No.
R231 ERJ3GEYJ103 10K R674 ERJ3GEYJ103 10K
R232 ERJ3GEYJ103 10K R675 ERJ3GEYJ103 10K
R233 ERJ3GEYJ103 10K
R242 ERJ3GEYJ221 220
R302 ERJ2GEJ101 100 S
R303 ERJ2GEJ101 100 S
R304 ERJ2GEJ101 100 S
R309 ERJ3GEYJ680 68
R310 ERJ3GEYJ680 68
R311 ERJ3GEYJ680 68
R312 ERJ2GEJ101 100 S
R313 ERJ2GEJ101 100 S
R314 ERJ2GEJ101 100 S
R315 ERJ2GEJ101 100 S
R327 ERJ3GEYJ680 68
R328 ERJ3GEYJ680 68
R329 ERJ3GEYJ680 68
R330 ERJ3GEYJ680 68
R333 ERJ3GEYJ680 68
R334 ERJ3GEYJ680 68
R335 ERJ3GEYJ680 68
R339 ERJ3GEYJ680 68
R340 ERJ3GEYJ680 68
R341 ERJ3GEYJ105 1M
R342 ERJ3GEYJ470 47
R364 ERJ2GEJ560X 56
R417 ERJ3GEYJ330 33
R601 ERJ3GEYJ560 56
R603 ERJ3GEY0R00 0
R607 ERJ3GEYJ1R0 1
R608 ERJ3GEYJ1R0 1
R621 ERJ3GEYJ105 1M
R622 ERJ3GEYJ332 3.3K
R623 ERJ3GEYJ680 68
R636 ERJ2GEYJ103 10K S
R637 ERJ2GEYJ103 10K S
44
14 FOR SCHEMATIC DIAGRAM

Note:
1. DC voltage measurements are taken with voltmeter from the negative voltage line.
2. This schematic diagram may be modified at any time with the development of new technology.
45
14.1. WAVEFORM
46
14.2. BUS-M BLOCK DIAGRAM
47
15 SCHEMATIC DIAGRAM
15.1. No.1
1 2 3 4 5 6
2:6B;3:7C;4:2G;5:4C
LD[0-15]
(1)
LD[0]
LD[1]
LD[2]
LD[3]
LD[4]
LD[5]
LD[6]
LD[7]
A
LD[8]
LD[9]
LD[10]
LD[11]
LD[12]
LD[13]
LD[14]
LD[15]
CT_D[0]
8 CT_D[1]
7 CT_D[2]
6 CT_D[3]
CT_D[4]
CT_D[5]
CT_D[6]
CT_D[7]
5
8
7
6
5
RA105 RA106
47 47
3
1
2
3
1
2
4
+3.3V +3.3V
TP1767
8 TP1766
7 TP1765
6 TP1764
TP1771
8 TP1770
7 TP1769
6 TP1768
R230
10k
R123
5
5
10k
LA102 LA101
+3.3V
3
1
2
4
3
1
2
4
nDTAZL
2:3F
TP158
TP162
TP165
TP167
+3.3V +3.3V
nCSZL +3.3V +3.3V
TP143
TP146
TP149
TP151
2:3F DG DG DG
TP1773
TP1772
TP1728
DG
nDSZL
TP1727
TP1726
0.01u 0.01u 0.01u 0.01u
2:3F
B nWRZL C120 C118 C114 C124
2:2E
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
#R/W
#DS
#CS
VDD253
VSS252
D0
D1
D2
D3
D4
D5
D6
D7
VDD243
VSS242
D8
D9
D10
D11
D12
D13
D14
D15
#DTA
NC232
VDD231
VSS230
VDD5V229
NC228
NC227
BSTio0
BSTio1
BSTio2
BSTio3
NC222
NC221
VDD220
VSS219
BSTio4
BSTio5
BSTio6
BSTio7
LA[1-14] 2:7D;3:7B;4:2G;5:4C
LA[14] 1 A13
LA[13] 2 A12
LA[12] 3 A11
LA[11] 4 A10
LA[10] 5 A9
LA[9] 6 A8
DG
7 VSS7
C105
0.01u
8 VDD8
+3.3V
C LA[8] 9 A7
LA[7] 10 A6
LA[6] 11 A5
LA[5] 12 A4
LA[4] 13 A3
LA[3] 14 A2
LA[2] 15 A1
LA[1] 16 A0
DG
VSS17
C127
17
0.01u
18 VDD18
+3.3V
9B;2:1B;2:2A;3:9F;4:10D;4:5D 19 #RESET
LOCAL_nRST
TP1729 20 TDo
D TP1730 21 TMS
TP1755 22 TCK
R115
10K
TP1731 23 #TRST
R118
10K
TP1732 24 TDi
DG 25 IC_GND25
DG DG
TP1733 26 IC_OPEN26
TP1734 27 IC_OPEN27
TP1735 28 IC_OPEN28
TP1736 29 IC_OPEN29
TP1737 30 ST_FPo1
IC101
TP1738 31 ST_CKo1
TP1739 32 IC_OPEN32 [CTSW]
TP1740 33 IC_OPEN33
E TP1741 34 IC_OPEN34
TP1742 35 IC_OPEN35
0.01u
C129
DG
36 VSS36
37 VDD37
38 IC_GND38
+3.3V
39 IC_GND39
DG 40 IC_GND40
TP1743
41 IC_OPEN41
TP1744
42 IC_OPEN42
VSS43
DG
+3.3V 43
44 APLLVDD
C123
0.01u
45 APLLVSS
F DG 46 C20i
47 IC_GND47
DG
48 VSS48
C128
0.01u
DG 49 VDD49
+3.3V
50 IC_GND50
ZL_C20M
51 IC_GND51
+3.3V
3:12F 52 IC_GND52
R114
10K
+3.3V
53 IC_GND53
54 LREF3
IC114
5
C135 55 LREF2
3 0.01u 56 LREF1
TP1754
DG
57 LREF0
TP1753 58 C1M5o
G
VSS59
DG
59
TP106 R116 TP1747 L101 TP1745 60 ST_FPo0
SHW_FH TP1746
3:6C;4:10E;4:5E;5:9B 47 61 ST_CKo0
TP105 R117 RE1
4 2 62 VDD62
+3.3V
SHW_CLK
FRAME_B_io
FRAME_A_io
1
3:6C;4:10E;4:5E;5:9B 100 TP2006 IC114 63 C32o
0.01u
C126
64 SEC_LOS
CTREF2
CTREF1
TP1932
C8_B_io
C8_A_io
VDD101
VSS100
LSTo15
LSTo14
LSTo13
LSTo12
LSTo11
LSTo10
FAIL_B
FAIL_A
NREFo
VDD70
VDD78
VDD89
VDD95
PRI_LOS
VSS69
VSS77
VSS88
VSS94
LSTo9
LSTo8
NC80
NC81
NC82
NC83
NC84
NC85
NC86
NC87
NC90
NC91
NC92
NC93
79 ODE
NC 47 NC
100
101
102
103
104
105
2:4F
65
66
67
68
69
70
71
TP1604 72
73
74
75
76
77
78
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
TP107 TP1749 TP1748

TP1720
TP1719
TP1718
TP1717
TP1716
TP1715
TP1714
TP1713
TP1712
TP1711
TP1710
TP1709
C32_ZL
TP1721
TP1603
TP1752
R119 L102
TP159
TP163
C125
R112
TP156
TP147
TP150
TP152
TP154
10K
0.01u C121 0.01u C117 C115

TP166
H C119
0.01u DG
0.01u 0.01u
DG DG
DG
8
7
6
5
+3.3V +3.3V DG
5
8
7
6
+3.3V
DG +3.3V RA107 +3.3V

LA103
+3.3V
68
10K TP1750
3
1
2
+3.3V
6 3
8 1
7 2
5 4
TP1600
R109 10K TP1751 TP1602
R113 TP1599 RA109
TP1601
68
CT_FRAME 11E;5:12E
4:10D3
4:10E1
4:10D2
4:5E 4
9G
9G
9G
9G
CT_C8 11E;5:12E
R111
10K
2:2G
SHW_LP[6]
SHW_LP[5]
SHW_LP[4]
SHW_LP[3]
SHWD3[2]
SHWD3[1]
SHWD3[0]
SHWD2[2]
ODEZL
DG
KX-TDA6110XJ/KX-TDA6110X BUS-M CARD SCHEMATIC DIAGRAM No.1 (1/2)
48
7 8 9 10 11
CN101
TP1607 A1 +15VPTA1
A (1) TP1608 B1 +15VPTB1
TP1609 A2 +40V
+3.3V
+15VIN B2 +15V
+15VIN
5:1G A3 POWER_GNDA3
IC113
5 +3.3V
C130 B3 POWER_GNDB3
R124
+3.3V P.G
10k
3 0.01u TP256 J646 TP2143
A4 EC_CLK
100k
R120
TP2107 J101 nPOW_RST EC_CLK
+3.3V
DG
5:12C 0 TP1610 B4
EC_nSTOP
IC113 2:1B;5:4A;5:4E A5 GNDA5
TP1959 1
4
LOCAL_nRST 2 DG B5 GNDB5
8
7
6
5
5
8
7
6
+3.3V TP1611
RA116 RA117 2D;2:1B;2:2A;3:9F;4:10D;4:5D A6 EC_nTRDY
TP1612
3
1
2
4
+3.3V +3.3V
3
1
2
4
B6 EC_nPERR
TP1680
0.01u
TP1677
TP1678
TP1679
TP1763
TP1762
TP1761
TP1760
DG DG TP1613
TP1759
TP1758
TP1757
TP1756
TP1723
C132
TP1722
A7 EC_nFRAM
TP1725
TP1724
0.01u 0.01u
TP1614
B7 EC_PAR
B C116 C122
DG TP1615
A8 EC_nCBE[0]
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
TP1616
B8 EC_nCBE[1]
TP1617
NC214
NC213
VDD212
VSS211
BSTio8
BSTio9
BSTio10
BSTio11
NC206
NC205
VDD204
VSS203
BSTio12
BSTio13
BSTio14
BSTio15
VDD198
VDD5V197
NC196
NC195
NC194
NC193
5:12D TP1676 R122 A9 EC_IDSEL
EC_nRST TP257
B9 EC_nRST
220
3300p
C686
NC192 192 TP1681 A10 GNDA10
NC191 191 TP1682 DG
B10 GNDB10
TP1618
NC190 190 TP1683 A11 EC_AD[0]
DG TP1619
NC189 189 TP1684 B11 EC_AD[1]
0.01u DG
TP1620
VSS188 188 A12 EC_AD[2]
5:12D
C107
TP1621
VDD5V187 187 +3.3V
B12 EC_AD[3]
+3.3V
TP1622
BSTio16 186 CT_D[0-7] A13 EC_AD[4]
TP1685 1 8 TP1623
BSTio17 185 TP1686 2 7
B13 EC_AD[5]
C BSTio18 184 TP1687
TP1688
3 6 A14 GNDA14
4 5
BSTio19 183 B14 GNDB14
RA115
DG
NC182 182 TP1701
10k
TP1624 A15 EC_AD[6]
NC181 181 TP1702 TP1625 B15 EC_AD[7]
+3.3V
VDD180 180 TP1626 A16 EC_AD[8]
C112
0.01u
VSS179 179 TP1627 B16 EC_AD[9]
DG
BSTio20 178 TP1628 A17 EC_AD[10]
TP1689 1 8
BSTio21 177 TP1690 2 7
TP1629 B17 EC_AD[11]
TP1691 3 6
BSTio22 176 TP1692 4 5
A18 GNDA18
TP1630
BSTio23 175 B18 ReservedB18
RA112
DG
TP1703 TP1631
10k
NC174 174 A19 EC_AD[12]
TP1704 TP1632
NC173 173 B19 EC_AD[13]
+3.3V
TP1633
D VDD172 172 A20 EC_AD[14]
C110
0.01u
TP1634
VSS171 171 DG B20 EC_AD[15]
TP1635
BSTio24 170 A21 EC_nINT
TP1693 1 8 TP1636
BSTio25 169 TP1694 2 7
B21 EC_nCDET
TP1695 3 6 TP1637
BSTio26 168 TP1696 4 5
A22 GNDA22
TP1638
BSTio27 167 B22 ReservedB22
RA113
NC166 166 TP1705

10k
CT_D[0] TP1668 A23 CT_D[0]

TP1706
NC165 165 CT_D[1] TP1669 B23 CT_D[1]
+3.3V
VDD164 164 CT_D[2] TP1670 A24 CT_D[2]

0.01u
C106
VSS163 163 CT_D[3] TP1671 B24 CT_D[3]

DG
BSTio28 162 CT_D[4] TP1672 A25 CT_D[4]

TP1697
BSTio29 161 TP1698
1
2
8
7
CT_D[5] TP1673 B25 CT_D[5]
TP1699
BSTio30 160 TP1700
3
4
6
5
CT_D[6] TP1674 A26 CT_D[6]
E BSTio31 159 CT_D[7] TP1675 B26 CT_D[7]
RA114
10k
NC158 158 TP1707 A27 GNDA27

TP1708 TP1639 B27
NC157 157 DG ReservedB27
+3.3V
VDD156 156 CT_NETREF A28 CT_NETRE

0.01u
CT_NETREF
C131
VDD5V155 155 10k 2:6D CT_C8 B28 CT_C8

CT_C8
PCI_OEB 154 DG
TP2142
R121 2H;5:12E CT_FRAME A29 CT_FRAME
DG
CT_FRAME
LSTi0 153 TP2003 2H;5:12E B29 nLOS
SHW_LP[0] TP1640
LSTi1 152 TP2004 8H A30 GNDA30
SHW_LP[1]
LSTi2 151 TP2005 8H B30 GNDB30
SHW_LP[2] DG
LSTi3 150 7H A31 ReservedA31

SHWU1[0] TP1641
LSTi4 149 3:7D B31 ReservedB31
SHWU1[1] TP1642
LSTi5 148 3:7D A32 ReservedA32
SHWU1[2] TP1643
F LSTi6 147 3:7D B32 ReservedB32
SHWU2[0] TP1644
SHWU2[1] TP1645
+3.3V 4:4D
VDD145 145 B33 ReservedB33
0.01u
TP1646
C108
VSS144 144 TP1647 A34 TXD2

DG
LSTi8 143
SHWU2[2] TP1648 B34 RXD2
LSTi9 142 4:4E A35 ReservedA35
SHWU3[0] TP1649
LSTi10 141 4:10D B35 ReservedB35
SHWU3[1] TP1650
SHWU3[2] TP1651
LSTi12 139 4:10E B36 ReservedB36
SHW_LP[3] TP1652
LSTi13 138 6H A37 ReservedA37
SHW_LP[4] TP1653
LSTi14 137 6H B37 ReservedB37
SHW_LP[5] TP1654
LSTi15 136 6H A38 +30VA38
SHW_LP[6] TP1655
VDD135 135 +3.3V 6H B38 +30VB38
0.01u
C104
TP1656
G
VSS134 134 TP1657 A39 RINGER
TP206
IC_GND133 133 RINGERSYNC
B39 RING_SYNC
IC_GND132 132 DG TP1658 A40 nHALT
3:6C;4:10E;4:5E
IC_GND131 131 TP1659 B40 RING_SIN
IC_GND121
IC_GND122
IC_GND123
IC_GND124
IC_GND126
IC_GND130 130 A41 GNDA41

IC_GND127
IC_GND129 129 DG TP1660

IC_GND128
B41 (+3.3V)
VDD107
VDD113
VDD120
VSS106
VSS112
VSS119
VSS125
NC118
LSTo7
LSTo6
LSTo5
LSTo4
LSTo3
LSTo2
LSTo1
LSTo0
TP1661 A42 (DC_ALM)

TP1662 B42 (AC_ALM)
TP1663 A43 (nEXTPOW[0])
106
107
TP170 108
TP171 109
TP172 110
TP173 111
112
113
TP174114
TP176115
TP178116
117
118
119
120
121
122
123
124
125
126
127
128
TP1664 B43 (nEXTPOW[1])

TP1463
TP1665 A44 DIAG_R

C113 C111 C109 DG TP1666 B44 DIAG_T
H
0.01u 0.01u 0.01u A45 GNDA45
5
8
7
6
5
8
7
6
TP179
DG TP1667
DG +3.3V LA104 +3.3V LA105 DG +3.3V DG DG B45 RINGER_AC
3
1
2
3
1
2
DG
8
7
6
5
5
6
7
8
RA108 RA110
68 68
3:5B 3
9F 2
4:5D 1
4:5D 2
3:5B 4
3:5B
4
9F 3
9F 1
SHWD2[1]
SHWD2[0]
SHWD1[2]
SHWD1[1]
SHWD1[0]
SHW_LP[2]
SHW_LP[1]
SHW_LP[0]
49
1/4
1 2 3 4 5 6
+2.5V 1:2D;1:9B;1B;3:9F;4:10D;4:5D +3.3V
LOCAL_nRST
Q205
+3.3V E
14 Q203
15.2. No.2
B
IC211 GREEN
C230
0.01u
7 ES1S_LED LED204 C Q201
LED203 R218 R201 TP524
0
RED 5
A 1
DG TP2110 150 TP330 +3.3V 120
2 1 TP526 2
DG
9
IC211 TP1782 Q202
8 +3.3V +3.3V
10 GREEN
NC
NC
NC
NC
NC
NC
NC
NC
43
TP527 R202 TP525 3
ES2S_LED 4 3 4
12
IC211 TP1783
LED202 R217 (a)
11 120
5
6
7
8
5
6
7
8
5
6
7
8
13 TP2111 TP331 +3.3V

150 DG GREEN RA223
RA221 RA222
J200
J201
J202
J203
J204
J205
J206
J207
Q204 +3.3V 10k
+3.3V 10k 10k
2
4
3
1
2
2
4
3
1
4
3
1
GREEN TP364
DG +2.5V 5 4
LED201 R219 ES3S_LED LED_GREEN TP366
TP367 6 3
10K
TP369 7 2
IC211 150 TP332
1 TP1929 TP2112 TP371 8 1
DG
10k
TP1930 3
R241
LD[15
LD[14]
LD[13]
LD[12]
LD[11]
LD[10]
LD[9]
LD[8]
LD[7]
LD[6]
LD[5]
LD[4]
nPOW_RST 2 IC211 LED_RED TP373 5 4 LD[0-15]

4 TP1781 PROG_B C250 6 3
(b)
TP1931 6 1:2A;3:7C;4:2G;5:4C
K10
1:10B;5:4A;5:4E
RA202 RA203
7 2
DG
5 LOCAL_nRST TP375
LOCAL_nRST 3300p 8 1
1:2D;1:9B;2A;3:9F;4:10D;4:5D TP346
nDETCL3 4:9D +1.2V
+2.5V TP343 +1.2V
DG
DG +3.3V
TP379
nCMI3B
4:10E +2.5V
DG
NC
nSRST3
J208
4:11E TP341 TP380
C228
TP2113 TP351
C227
+3.3V
0.01u
B TP339
DG DG TP383
0.01u TP354 TP359 +3.3V DG
+2.5V TP357 0.01u
SSSTAT3 DG TP356 TP384
4:6C
C226
0.01u
TP335 C242 TP362
DG
C225
C224
0.01u
HsWAP_EN Junmper TP334 DG
J209
0.01u 0.01u C229134
DG
144 TDI
110 TCK
111 TMS
109 TDO
116 IO116
139 GND139
136 GND136
117 GND117
114 GND114
143 PROG_B
4:11E 1
TP308 IO_L01P_7/VRN_7 IO_L01P_2/VRP_2 108
135 IO_L27P_0
131 IO_L30P_0
122 IO_L31P_1
118 IO_L28P_1
137 IO_L27N_0
132 IO_L30N_0
130 IO_L31N_0
119 IO_L28N_1
nCSCL3 (c)
133 VCCINT133
121 VCCINT121
142 HSWAP_EN
VCCAUX134
120 VCCAUX120
4:10E TP313
2 IO_L01N_7/VRP_7 IO_L01P_2/VRN_2 107
50
(d)
138 VCCO_TOP138
126 VCCO_TOP126
S3_NETREF 115 VCCO_TOP115
3 C223
VCCO_LEFT3 VCCO_RIGHT106 106
140 IO_L01P_0/VRN_0
113 IO_L01N_1/VRP_1
112 IO_L01P_1/VRN_1
127 IO_L32P_0/GCLK6
124 IO_L32P_1/GCLK4
+3.3V
128 IO_L32N_0/GCLK7
125 IO_L32N_1/GCLK5
DG
129 IO_L31P_0/VREF_0
+3.3V
123 IO_L31N_1/VREF_1
141 IO_L01N_0/VRNP_0
0.01u
DG
0.01u C232 4
TP322 IO/VREF_7 IO_L20N_2 105
nDIAG3 (e)
4:10D 5
TP317 IO_L20P_7 IO_L20P_2 104 LD[4]
nINTRCL3 (f)
4:11E 6 103
TP316 IO_L20N_7 IO_L21N_2 LD[3]
BS32 4:10E (g)
C TP320
7 IO_L21P_7 IO_L21P_2 102 LD[2]
BS31 4:10E (h)
TP300
8 IO_L21N_7 GND101 101
nLOS3
DG
4:10E 9 100
GND9 IO_L22N_2 LD[1]
DG
(i)
TP307 10 IO_L22P_7 IO_L22P_2 99 LD[0]
nDETCL2 (j)
4:3D 11 98
nCMI2B TP306 IO_L22N_7 IO_L23N_2 LA[25]
4:4E (k)
TP301
12 IO_L23P_7 IO_L23P_2 97 LA[24]
nSRST2 (m)
4:5E 13 96
TP304 IO_L23N_7 IO_L24N_2 LA[23]
SSSTAT2 4:1C (n)
TP312
14 95 LA[22]
nCSCL2 IO_L24P_7 IO_L24P_2 (p)
4:6E 15 94
TP303 IO_L24N_7 GND94
DG
S2_NETREF
4:4E 16 93 TP393
GND16 IO_L40N_2
DG
(q)
TP302 17 92 TP397 3:7C;4:10E;4:5E
nDIAG2 IO_L40P_7 IO_L40P_2/VREF_2 nWECL
4:5D TP311 18 91 +3.3V
nINTRCL2 IO_L40N_7/VREF_7 VCCO_RIGHT91 C241
DG
4:6E +3.3V 19 [FPGA] 90

0.01u VCCO_LEFT19 IO_L40N_3/VREF_3
D C233 0.01u TP396 nRDCL
DG
TP305
20 89
BS22 IO_L40P_6/VREF_6 IC614 IO_L40P_3 3:7C;4:10E;4:5E
4:4E 21 88
TP309 IO_L40P_6 GND88 TP398 1:11E
DG
BS21
4:4E 22 87 CT_NETREF
GND22 IO_L24N_3 (r)
DG
TP310 23 86
nLOS2 IO_L24P_6 IO_L24P_3 (s)
4:4E
(1) (2) (3) (4)

2/4
1 2 3 4 5 6
(1) (2) (3) (4)
TP315
24 IO_L24N_6/VREF_6 IO_L23N_3 85
nCMI1B (t)
3:7A 25 84
nSRST1 TP314 IO_L23P_6 IO_L23P_3/VREF_3
3:6C (u)
TP323
26 IO_L23N_6 IO_L22N_3 83
SSSTAT1 (v)
3:4A TP319 27 82
nCSCL1 3:7A IO_L22P_6 IO_L22P_3 (w)
TP321
28 81
IO_L22N_6 GND81
DG
S1_NETREF
3:7D 29 80
GND29 IO_L21N_3 TP401
DG
(x)
3:9G TP318
30 79 TP404
nDIAG1 IO_L21P_6 IO_L21P_3 (y)
3:9F TP326
31 78 TP405
nINTRCL1 IO_L21N_6 IO_L20N_3 (z)
E 3:6G TP324
32 IO_L20P_6 IO_L20P_3 77 TP402
BS12 (A)
3:6G TP325
33 IO_L20N_6 IO76 76 TP403
BS11 (B)
+3.3V 34 75
4.7u 0.01u C234 VCCO_LEFT34 VCCO_RIGHT75
+3.3V
C243
DG
TP327
35 74
nLOS1 IO_L01P_6/VRN_6 IO_L01N_3/VRP_3
3:6G
C240
0.01u
TP328
36 73 TP399
C244 DG IO_L01N_6/VRP_6 IO_L01P_3/VRN_3
DG
nWRZL 1:2B
4.7u
DG
TP400
+3.3V +1.2V +2.5V

IO_L01N_5/RDWR_B
M1
M0
M2
IO_L01P_5/CS_B
GND42
VCCO_BOTTOM43
IO/VREF_5
GND45
IO_L28P_5/D7
IO_L28P_5/D6
VCCAUX48
VCCINT49
IO_L28P_5/D5
IO_L28N_5/D4
IO_L32P_5/GCLK2
IO_L32N_5/GCLK3
VCCO_BOTTOM54
IO_L32P_4/GCLK0
IO_L32N_4/GCLK1
IO_L31P_4/DOUT/BUS
IO_L31N_4/INIT_B
IO_L30P_4/D3
IO_L3ON_4/D2
VCCINT61
VCCAUX62
IO_L27P_4/D1
GND64
IO_L27N_4/DIN/D0
VCCO_BOTTOM66
GND67
IO_L01P_4/VRN_4
IO_L01N_4/VRP_4
IO/VREF_4
DONE
CCLK
4.7u
C245 DG
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Bypass Capacita for mid-frequency

TP394
DG DG
0.01u TP347 TP358
TP337
+2.5V TP361 TP370 TP385
TP368
TP340
+1.2V
TP1605
TP353
TP1606
TP372 (C)
C239
C235 DG TP345 +3.3V

DG TP381
TP350
0.01u
TP344 DG
DG +3.3V
0.01u
C238
TP365 +1.2V
C236
0.01u
F TP342 TP363 +3.3V
nDTAZL DG
M0-M2:Master-Serial MODE DG
0.01u
C237
C221
1:2B
0.01u
Setting nDSZL
1:2B DG DG
0.01u
C222
51
1:2B TP382
nCSZL DG
5:4B +2.5V
nWETK
5:4B
nRDTK
TP360
C32_ZL 1:1H +2.5V
5:4B
nWAITTK (D)
330
R215
(E)
C16M C16M
5:8G TP386 R223
nCSTK 33
TP387
R222
5:4B
33
ODEZL +2.5V
G 1:2I
IC210 C247
1 20
DG
D0 VCCJ
+2.5V
TP377 2 19
0.01u +3.3V
NC2 VCCO
3 18 0.01u
4.7K
+2.5V
DG
CLK VCCINT
R220
C246
CN405 +3.3V 4 17TP388
TDI TDO
5 16 TP389
R221
1 TMS NC16 33
4.7K
R213
6 15 TP395
2 TCK NC15
TP2115 7 14 TP392
3 #CF NC14
DG
8 13 TP391
4 OE/#RESET #CEO
NC TP378 9 12 TP390
5 NC9 NC12
10 11
6 %CE GND
TP2114 DG
7
H 8
[ISP Connector for Debug]

(F)

3/4
7 8 9 10 11
A CN201
A1 GND
(a)
5
6
7
8
B1 GND
RA224
10k TP519 A2 NC
2
4
3
1
+3.3V TP523 B2 NC
A3 BM_nPRS
LD[3]
LD[2]
LD[1]
LD[0]
TP520 B3 NC
(b) C201
1 DIR VCC 20
0.01u TP521 A4 nSLFAN_ALM
DG B4
19 /2G B1 18 TP427 TP522 NC
LD[15] TP1960 2 A1 B2 17 TP428 A5 GND
LD[14] TP1961 TP429 B5
3 A2 B3 16 GND
LD[13] TP1962 4 A3 B4 15 TP430 5 4 BM_DATA[15] TP467
B A6 BM_DATA[15]
6 3
LD[12] B6
47
TP1963 5 A4 B5 14 TP431 7 2 BM_DATA[14] TP466 BM_DATA[14]
RA204
8 1
LD[11] TP1964 6 A5 B6 13 TP432 BM_DATA[13] TP468 A7 BM_DATA[13]
LD[10] TP1965 7 A6 B7 12 TP433 BM_DATA[12] TP461 B7 BM_DATA[12]
LD[9] TP1966 TP434 5 4 BM_DATA[11] TP462 A8
8 A7 B8 11 BM_DATA[11]
6 3
LD[8] BM_DATA[10]
TP1967 9 A81 GND 0 7 47 2 TP463 B8 BM_DATA[10]
8 RA205 1
BM_DATA[9]
DG TP464 A9 BM_DATA[9]
IC200 +3.3V BM_DATA[8] B9
LD[7] TP465 BM_DATA[8]
(c)
C202 A10
LD[6] GND
52
(d) 0.01u
1 DIR VCC 20
DG
B10 GND
19 /2G B1 18 TP435
LD[5] 5 4 BM_DATA[7] TP483 A11 BM_DATA[7]
(e) LD[7] TP1968 2 A1 B2 17 TP436 6 3 BM_DATA[6] TP474
7 2 BM_DATA[5] B11
47
(f) BM_DATA[6]
RA206

A12 BM_DATA[5]
(g) LD[5] 4 A3 B4 15 TP438
C TP1970 TP476
B12 BM_DATA[4]
(h) LD[4] TP1971 5 A4 B5 14 TP439
TP485
5 4 BM_DATA[3] A13 BM_DATA[3]
7 2 BM_DATA[1] B13
47
BM_DATA[2]
RA207
(i) LD[2] TP1973 7 A6 B7 12 TP441 8 1 BM_DATA[0]

TP487 A14
(j) BM_DATA[1]
LD[1] TP1974 8 A7 B8 11 TP442
TP488
B14
(k) +3.3V BM_DATA[0]
LD[0] TP1975 9 A81 GND 0
A15 GND
(m)
5
6
7
8
5
6
7
8
+3.3V IC202 B15 GND

(n) RA216 RA213 BM_AD[25]
C203 10k 10k A16 BM_AD[25]
2
2
4
3
1
4
3
1
(p) BM_AD[24]
0.01u B16
1 BM_AD[24]
DG
20 VCC #1G
C248 BM_AD[23]
TP1976 18 1Y1 1A1 2 TP443 A17 BM_AD[23]
DG
(q)
3300p TP1977 4 TP444 BM_AD[22] B17
16 1Y2 1A2 BM_AD[22]
TP1978 14 1Y3 1A3 6 TP445 BM_AD[21] A18 BM_AD[21]
TP1979 12 1Y4 1A4 8 TP446 BB_AD[20] B18 BM_AD[20]
D
TP1776 9 11 TP447 BM_AD[19] A19
LA[0-14] LA[0-14] 2Y1 2A1 BM_AD[19]
TP1777 7 13 TP448 BM_AD[18
] B19
5:4C;1:2B;3:7B;4:2G 2Y2 2A2 BM_AD[18]
LA[5] TP1778 TP449
BM_AD[17] A20
(r) 5 2Y3 2A3 15 BM_AD[17]
LA[4] TP1779 3 17 TP450 BM_AD[16] B20
(s) 2Y4 2A4 BM_AD[16]
(5) (6) (7) (8) (9) (10)(11) (12)

4/4
7 8 9 10 11
(5) (6) (7) (8) (9) +3.3V
(10)(11) (12)
8
7
6
5
LA[3] 10 GND #2G 19 A21 GND
(t) RA211
DG IC209 NC +3.3V B21
LA[2] GND
3
1
2
4
(u) TP1775 6 2
LA[1] IC203 NC TP2108 BM_AD[15] A22
(v) +3.3V DG 1
IC209 BM_AD[15]
TP1774 3 5
5
6
7
8
5
6
7
8
LA[0] NC TP2109 BM_AD[14] B22
(w) 0.01u 7 RA210 RA212 BM_AD[14]
C204 DG 10k 10k BM_AD[13]
20 1 A23
2
2
4
3
1
4
3
1
VCC #1G DG BM_AD[13]
DG
TP1780 18 2 TP413
BM_AD[12] B23
(x) 1Y1 1A1 BM_AD[12]
LA[14] TP1980 16 1Y2 1A2 4 TP414 BM_AD[11] A24 BM_AD[11]
(y)
LA[13] TP1981 14 1Y3 1A3 6 TP415 BM_AD[10] B24 BM_AD[10]
(z)
E LA[12] TP1982 12 8 TP416 BM_AD[9] A25
(A) 1Y4 1A4 BM_AD[9]
+3.3V
DG
LA[11] TP1983 9 2Y1 2A1 11 TP417 BM_AD[8] B25 BM_AD[8]
(B)
5
6
7
8
5
6
7
8
LA[10] TP1984 7 2Y2 2A2 13 TP418 A26 GND
RA215 RA217
LA[9] TP1985 5 2Y3 2A3 15 TP419 10k 10k B26 GND
2
2
4
3
1
4
3
1
LA[8] TP1986 3 2Y4 2A4 17 TP412 BM_AD[7] A27 BM_AD[7]
10 GND #2G 19 BM_AD[6] B27 BM_AD[6]
DG
+3.3V DG BM_AD[5] A28 BM_AD[5]
IC204 BM_AD[4
] B28 BM_AD[4]
C205 BM_AD[3] A29
0.01u BM_AD[3]
20 VCC #1G 1
DG
BM_AD[2] B29 BM_AD[2]
LA[7] TP1987 18 2 TP420
1Y1 1A1 BM_AD[1] A30
(C) BM_AD[1]
LA[6] TP1988 16 1Y2 1A2 4 TP421
BM_AD[0] B30 BM_AD[0]
LA[5] TP1989 14 6 TP422
F 1Y3 1A3 A31
LA[4] GND
TP1990 12 1Y4 1A4 8 TP423
B31 GND
LA[3] TP1991 9 TP424
2Y1 2A1 11 A32
TP469 NC
53
LA[2] TP1992 7 2Y2 2A2 13 TP425
TP515 B32 NC
LA[1] TP1993 5 2Y3 2A3 15 TP426
TP516 A33 NC
LA[0] TP1994 3 TP1924
2Y4 2A4 17 B33
TP517 BM_nRST
10 GND #2G 19
nIRQ_c TP477 A34 BM_nIRQ
DG DG
(D) B34 GND
IC205 +3.3V
(E) TP470 A35 BM_nCS
TP484 B35 NC
10k
R235
10k
R211 TP471 A36
R234
BM_nRDY
47
TP472 B36 BM_nWE[1]
TP478 A37 BM_RDnwR
G B37
R206 TP479 BM_nRD
+3.3V 47
TP480 A38 BM_nBS
IC209 8 TP481 B38 BM_nWE[0]
+3.3V NC
TP482 A39 NC
NC
C207
4
B39 GND
DG
DG
0.01u TP473 A40 BM_CLKIO
DG
20 VCC #1G 1 TP518 B40 NC
C206
18 1Y1 1A1 2 R242
TP451
TP407 BM_nRST
16 1Y2 1A2 4 220
R225 TP1995 TP2153 8 1 TP2152
14 1Y3 1A3 6 TP459 7 2 BM_nBS
6 3 BM_nCS
47
NC 12 1Y4 1A4 8 TP455 5 4 BM_nRD

TP456 8 1 BM_nWE[1]
8 1 TP408 9 2Y1 2A1 11 TP457 7 2 BM_nWE[0]
H 5 4 TP409
6 3
TP458 BM_RDnWR
47
6 3 TP410 7 13
RA209 RA208
47
2Y2 2A2 TP454 5 4 BM_CLKIO
RA201
7 2 TP411
5 2Y3 2A3 15
R228 TP1996
M_CLKIO 3 2Y4 2A4 17
(F)
NC 10 GND #2G 19
C249
DG
3300p
DG IC206
DG
15.3. No.3
1 2 3 4 5 6
A R365
SSTAT1 SSSTAT1
560 2:2E
J313 NC
TP2135 TP610 DG
TP1957
0
RA631
3 4 1 8
TP1958
TP2136 FIL309 TP611
2 7
3 6
2 1
4 5 DG C317 +3.3V
J318 NC TP1833 0.01u

DOUT4- EN*
TP1834 9 8
DOUT4+ DIN4 TP1997
TP1835 10 7
J315 NC TP1836 11
DOUT3+ DIN3
6
SHWD1[2]
TP2137 TP612 DOUT3- GND 1:7H
TP1837 12 5
3 4 TP1838 13
DOUT2- VCC
4 TP1998 1:7H
1 8 14
DOUT2+ DIN2
3 TP1999
SHWD1[1]
TP1839 SHWD1[0]
0
TP2138 FIL307 TP613 DOUT1+ DIN1
2 7 15 2
TP1840 1:7H
RA302
2 1 DOUT1- EN
3 6 16 1
4 5
J317 NC IC313 +3.3V
B J316 NC
TP2139 TP614
3 4
TP2140 FIL308 TP615
2 1
J314
NC
J312
TP2134
NC
3 4 TP632
TP2133 FIL306
2 1 DG
TP633
CN301 J311 NC DG
0.01u
S1HWD0_P J309 NC C316
B20 A20 +3.3V
TP2132
TP634
DG
B19 A19 S1HWD0_N 3 4 1 8 TP1841
0
S1HWD1_P FIL305 DOUT4- EN* 1:11G;4:10E;4:5E RINGERSYNC
RA307 RA306
2 7 TP1842 9 8
C B18 A18 S1_RINGSYNC_N TP2131
2 1 TP635 3 6 TP1843 10
DOUT4+
DOUT3+
DIN4
DIN3
7
nSRST1
S1HWD1_N 4 5 TP1844 11 6 2:2E
B17 A17 S1_RINGSYNC_P 1 8 TP1845 12
DOUT3- GND
5
0
J310 NC 2 7 DOUT2- VCC 1:1G;4:10E;4:5E;5:9B
S1HWD2_N B16 S1_nRESET_P TP1846 13
DOUT2+ DIN2
4
SHW_CLK
A16 J308 NC 3 6 TP1847 14
DOUT1+ DIN1
3
SHW_FH
S1HWD2_P S1_nRESET_N 4 5 TP1848 15 2 1:1G;4:10E;4:5E;5:9B
B15 A15
TP2130
16
DOUT1- EN
1
R238
TP636
3 4 IC312
10k
TP600 B14 A14 S1_SHW_CLK_N FIL304
TP2129
TP601 B13 A13 S1_SHW_CLK_P 2 1
TP637 +3.3V
DG
B12 A12 S1_SHW_nFH_P J307 NC
DG S1_SHW_nFH_N J306 NC
B11 A11 TP2128
+3.3V
DG S1_NETREF_N
R301
10k
B10 A10 3 4 TP638

DG S1_NETREF_P TP2127 FIL303
TP2141 B9 A9 2 1
S1_nLOS_P S1HWU2_P TP639
B8 A8
S1_nLOS_N S1HWU2_N J305 NC
B7 A7 +3.3V
S1_CPU_STATUS0_N S1HWU1_N
B6 A6
D IC315
R327
B5 A5 S1HWU1_P 1 8 TP1849 1 16 S1_NETREF
2 7 TP1850 RIN1- EN 68 2:2E
S1HWU0_P
RA303
2 15 TP672
100
TP616 R312 RIN1+ ROUT1
22
B4 A4 3 6 TP1851 3
RIN2+ ROUT2
14 TP673 TP2000
SHWU1[2]
S1HWU0_N 4 5 TP1852 4 13 R328
B3 A3 5
RIN2- VCC
12
68 1:9F
RIN3- GND 68 TP2001 1:9F
6 11 TP674 R329 SHWU1[1]
B2 A2 S1_CCLINK_N TP617
7
RIN3+ ROUT3
10 TP675 TP2002 SHWU1[0]
R313
100
RIN4+ ROUT4
8 9 1:9F
B1 A1 S1_CCLINK_P RIN4- EN* R330
TP618 C319 68
0.01u +3.3V
DG DG
TP619
R314
100
1 8 TP1853
R315
100
DG
RA304
2 7 TP1854
TP620
22
3 6 TP1855
4 5 TP1856
TP621
TP622
E
TP623
S1_CCLINK_N +3.3V +3.3V
R331
R332
10k
10k
J303 +3.3V
NC C315
TP1951 TP1857
S1_CPU_STATUS1_N TP608 TP1870
TP1859 0.01u
R333
(1)
TP1954 DG
F 3 4
0
68
R364
#RE GND TP666 TP1808

FIL302 1 8 5 4 (2)
56
RA630
TP1860 DO-/RI- ROUT

TP1871 2 1 2 7 6 3 TP668
DO+/RI+ DIN
S1_CPU_STATUS1_P TP609 3 6 7
VCC DE
2 TP667 (3)
S1_CCLINK_P TP1953
4 5 TP1858 8 1
J304 NC IC311 NC
TP604 1 8 TP1952
S1_CPU_STATUS0_P TP1864 TP1861 R318 4
22
RA301
2 7
3 6
TP1865
TP1866 3
R326
0
10k
4 5 TP1867
S1_CPU_STATUS0_N TP605
R302
R304
+3.3V
IC314
100
100
DG R309
S1_nLOS_N TP606
1
RIN1- EN
16 68 2:2E
2 15 TP669 BS12
RIN1+ ROUT1
3 14 TP670 BS11
RIN2+ ROUT2
R303
4 13 R310 68 2:2E
100
1 8 RIN2- VCC
TP1868 5 12
22
TP607 RIN3- GND TP671

RA305
S1_nLOS_P 2 7 TP1869 6
RIN3+ ROUT3
11 R311 68 nLOS1
TP1955 3 6 TP1862 7 10
TP1956 4 5 TP1863 8
RIN4+ ROUT4
9
2:2E
RIN4- EN* C318 TP1872
0.01u
DG +3.3V
54
7 8 9 10 11
+3.3V
A
R236
10k
nCMI1B
2:2D
nCSCL1
2:2E
+3.3V
+3.3V +3.3V
2
1
3
RA633
10K +3.3V
+3.3V
5
6
7
8
+3.3V +3.3V
R351
4
2
1
3
10k
10k
RA632
J302 NC
R350 10k
R352
10K
LA[5]
C305
J301
0.01u
C307
NC
5
6
7
8
+3.3V +3.3V
DG +3.3V
DG 0.01u
R343
TP1820
10k
TP1831
B LA[1-5]
TP1822
TP1826
TP1827
TP1830
TP1823
TP1829
TP1821
TP1824
TP1828
DG
TP1784
LA[2]
LA[1]
1:2B;2:7D;4:2G;5:4C
TP1825
TP1832
TP1805
LA[4]
LA[3]
TP1807
NC122 122 TP1806

C311
DG
DG DG DG
DG 0.01u
VSS128 128
A2(ALE)/PO2 127
A1/PO1 126
VDD125 125
A0/PO0(nPOSTR) 124
NC123 123
VSS121 121
nCS/SCM4 120
nSWAP/SCM3 119
W16/SCM2 118
nRWM/SCM1 117
nMUX/SCM0 116
NC115 115
nHUBON 114
VDD113 113
nOPMD 112
nCMIBYP 111
(High)/NSTC3 110
nEHWR/NSTC2 109
VSS108 108
nEHRD/NSTC1 107
(High)/NSTC0 106
nTEST3 105
nTEST2 104
nTEST1 103
nTEST0 102
NC101 101
WPRE2/SPRE2 100
WPRE1/SPRE1 99
WPRE0/SPRE0 98
VDD97 97
DG
0.01u
DG
C304
+3.3V
1 VDD1 VSS96 96
DG
2 A3/PO3 (Open)/PO15 95 TP1785
3 A4/PO4 (Open)/PO14 94 TP1786
4 A5/PO5 (Open)/PO13 93 TP1787
TP1801 5 NC5 (Open)/PO12 92 TP1788

+3.3V
TP1800 6 NC6 (Open)/PO11 91 TP1789
R353 TP1802 7 nDSINV/CMIERRM
D VSS90 90
C DG
2:6D;4:10E;4:5E 10K 8 89 TP1790
TP1819
nRDCL nRD(nDS)/PO6 (Open)/PO10
9 88 TP1791 +3.3V
nTMODE (Open)/PO9 FIL301
IC302 1 3
nWECL 2:6D;4:10E;4:5E 10 nWR(DIR)/PO7 (Open)/PO8 87 TP1792
8
0.01u
2
C314
11 nSMODE FLASHO 86 TP1793
IC302 4
1:2A;2:6B;4:2G;5:4C 5 3
12 VSS12 nNSTCOUT 85 TP1794
LD[0-15] TP730
DG
LD[0] DG 13 D0(AD0)/PI0(nPISTR) VSS84 84
DG
LD[1] 14 D1(AD1)/PI1 X2 83 TP710 6
LD[2] 15 82 C309
D2(AD2)/PI2 X1
DG
+3.3V
+3.3V DG 0.01u
LD[3] 16 D3(AD3)/PI3 VDD81 81
TP726 R340 IC302 IC302
17 VDD17 [Circlink] MCKIN 80 2 6 7 1
TP1817
LD[4] 18 D4(AD4)/PI4 IC301 NC79 79 68 C40M
0.01u
C301
19 78 TP711 R341
LD[5] D5(AD5)/PI5 NC78
R335
D
68
20 VSS20 NC77 77 TP712 R342 1M
DG
DG TP713
47 40.00MHz
LD[6] 21 D6/PI6 VSS76 76
TP733 3 TP734
LD[7] 22 D7/PI7 CKP2 75 4
DG
C313 X301
LD[8] 23 D8/PI8 CKP1 74 22p 22p
+3.3V
C312
LD[9] 24 D9/PI9 CKP0 73
25 72 40MHz DG
VDD25 NC72
LD[10] 26 D10/PI10 MAXID4 71 TP714
X302 NC
0.01u
C302
LD[11] 27 D11/PI11 MAXID3 70

28 VSS28 MAXID2 69 +3.3V
LD[12] DG 29 D12/PI12 MAXID1 68 R362
DG
30 67 TP71510K
LD[13] D13/PI13 MAXID0
40 nINTR/NSTUNLOC
TP681
31 NC31 NC66 66
+3.3V
TP709
32 VSS32 VDD65 65
TP727
E
51 nSTALONE
45 TXENPOL
52 NSTPRE0
53 NSTPRE1
54 NSTPRE2
TP1818
34 D14/PI14
35 D15/PI15
+3.3V
38 nRESET
IC303
0.01u
C308
33 VDD33
43 TXEN2
49 VDD49
FIL310
39 VSS39
44 VSS44
64 VSS64
50 nDIAG
48 RXIN2
41 TXEN
36 NC36
37 NC37
NC55
58 NC58
46 RXIN
59 NID0
60 NID1
61 NID2
62 NID3
63 NID4
3 1
42 TXD
8
CLK 1
56 PS0
57 PS1
ET1
DG VCC
0.01u
2
C303
0.01u
C320
7
DG PRE D 2
TP1796 47
R361 TP1795 55
TP728
TP1812
+3.3V
6
Q 3
TP1816
CLR
TP705
TP1814
TP1811
TP1797
TP1799
TP1798
TP703
TP1809
TP1810
TP1813
5
GND 4
DG
TP1815
DG Q
DG
R357
10K
R363
10K R359
10K
+3.3V
R360 10K
10K
R356
10K
LD[14]
R334 68
R339 68
10K
R358
DG
LD[15]
+3.3V +3.3V
0.01u
C306
TP729 R417 C20M

+3.3V ZL_C20M
+3.3V 1:1F
CCLINK_TXEN DG 33
R338
(1)
10k
DG
DG
F (2)
(3) CCLINK_TXD 5
LOCAL_nRST
1:2D;1:9B;2:1B;2:2A;4:10D;4:5D
nINTRCL1
2:2E
nDIAG1
2:2E
55
15.4. No.4
1 2 3 4 5
[BUS-ME#1 connector]
S2HWD2_P TP920 1 2
S2HWD2_N TP958 3 4
TP1896
S2HWD1_N TP922 5 6 DG
B +3.3V
S2HWD1_P TP923 7 8
CN302
A20 S2HWD0_P TP924 9 10
B20
DG S2HWD0_N
B19 A19
TP925 11 12 TP1897
B18 S2_RINGSYNC_N TP926 13 14 TP1898

A18
B17 S2_RINGSYNC_P TP927 15 16 TP1899
A17
B16 S2_nRESET_P TP928 17 18 TP1900
A16
B15 S2_nRESET_N TP929 19 20 TP1901
A15
TP1920 S2_SHW_CLK_N
+3.3V B14 A14
TP930 21 22 TP1902
TP1921 S2_SHW_CLK_P
B13 A13
TP931 23 24 TP1903
R404
10k
DG S2_SHW_nFH_P
B12 A12
TP932 25 26
DG S2_ESLFID0 S2_SHW_nFH_N
TP2144 B11 A11
TP933 27 28
+3.3V
S2_NETREF_N DG
TP1904
29 30
R401
TP934
10k
B10 A10 +3.3V

R405 SSTAT2 TP2151 DG S2_NETREF_P
C B9 A9
TP935 31 32
SSSTAT2 2:2D
560 S2HWU2_P
TP904
B8 A8
TP936 33 34
TP905
B7 A7 S2HWU2_N TP937 35 36 TP1905
S2HWU1_N
TP906
B6 A6
TP938 37 38 TP1906
TP907 S2HWU1_P TP939 39 40 TP1907

B5 A5
TP908
B4 A4 S2HWU0_P TP940 41 42 TP1908
S2HWU0_N
TP909
B3 A3
TP941 43 44 TP1909
S2_CCLINK_N TP942 45 46 TP1910

B2 A2
S2_CCLINK_P
B1 A1
TP943 47 48 TP1911
S2_CPU_STATUS1_N 49 50 TP1912
DG S2_CPU_STATUS1_P 51 52
S2_CPU_STATUS0_P 53 54 DG
S2_CPU_STATUS0_N 55 56 TP1913 +3.3V

D S2_nLOS_N 57 58
S2_nLOS_P +3.3V 59 60
61 62 2:2D nDIAG2
R672
TP944 TP985
10k
1:2D;1:9B;2:1B;2:2A;3:9F;10D
nDETCL2 TP945 63 64
2:2C LOCAL_nRST
TP946 65 66 TP986 1:7H
SHWU2[0] 1:9F SHWD2[0]
TP947 67 68 TP987 1:7H
TP948 69 70 TP988 1:7H
TP949 71 72 TP989 1:11G;3:6C;10E
S2_NETREF 2:2D RINGERSYNC
TP921 73 74 TP990 2:2C
nLOS2 2:2D nSRST2
1:1G;3:6C;10E;5:9B
R232
TP950 75 76 TP991
10k
BS21 2:2D SHW_CLK
+3.3V
TP951 77 78 TP992 SHW_FH
BS22 2:2D
R675
1:1G;3:6C;10E;5:9B
10k
DG
79 80
DG DG
TP952 81 82 TP978 2:2D
E nCMI2B 2:2C +3.3V
nINTRCL2
+3.3V
83 84
TP1916 2:6D;3:7C;10E
85 86 TP979
+3.3V
nRDCL
TP1917 2:6D;3:7C;10E
R239
10k
87 88 TP980
nWECL
TP1918
89 90 TP981 2:2D
nCSCL2
TP1919
91 92 TP982 LA[5]
LA[4] TP910 93 94 TP983 LA[3]
LA[2] TP911 95 96 TP984 LA[1]
97 98
TP919
LD[15] DG 99 100 DG
TP995 LD[14]
LD[13] TP912 101 102 TP996 LD[12]

LD[11] TP913 103 104 TP997 LD[10]
LD[9] TP914 105 106 TP1000 LD[8]

F
LD[7] TP915 107 108 TP998 LD[6]
LD[5] TP916 109 110 TP999 LD[4]
LD[3] TP917 111 112 TP993 LD[2]

LD[1] TP918 113 114 TP994 LD[0]
+3.3V +3.3V
115 116
TP1915 117 118 TP1914
119 120
DG CN401 DG
1:2A;2:6B;3:7C;5:4C
G LD[0-15] (1)
1:2B;2:7D;3:7B;5:4C
LA[1-5] (2)
56
6 7 8 9 10 11
[BUS-ME#2 connector]
1 2
3 4
TP1050DG
5 6 +3.3V
B 7 8
CN303 TP1017
B20 A20 S3HWD0_P 9 10
DG S3HWD0_N TP1018 TP1873
B19 A19 11 12
S3HWD1_P TP1005
B18 TP1019 TP1874
S3_RINGSYNC_N 13 14
TP1006
A18
S3HWD1_N B17 TP1020 TP1875
S3_RINGSYNC_P 15 16
TP1007
A17
S3HWD2_N B16 TP1021 TP1876
S3_nRESET_P 17 18
TP1008
A16
S3HWD2_P B15 TP1022 TP1877
+3.3V S3_nRESET_N 19 20
A15
TP1922 TP1023 TP1878
B14 S3_SHW_CLK_N 21 22
R403
A14
10k
TP1923 TP1024 TP1879

B13 S3_SHW_CLK_P 23 24
A13
S3_ESLFID1 S3_SHW_nFH_P TP1025
TP2145 25 26
B12 A12
S3_SHW_nFH_N TP1026
B11 A11 27 28 DG
+3.3V
R402 S3_NETREF_N TP1027 TP1880
29 30
10k
DG B10 A10 +3.3V
SSSTAT3 R406 DG S3_NETREF_P TP1028
C TP2150
B9 A9 31 32
2:2B SSTAT3 TP1009
560 S3HWU2_P TP1029
B8 A8 33 34
TP1010 TP1030 TP1881
B7 A7 S3HWU2_N 35 36
TP1011 TP1031 TP1882
S3HWU1_N
B6 A6 37 38
TP1012 TP1032 TP1883
B5 S3HWU1_P 39 40
A5
TP1013 TP1033 TP1884
B4 A4 S3HWU0_P 41 42
TP1014 TP1034 TP1885
S3HWU0_N
B3 A3 43 44
TP1035 TP1886
B2 S3_CCLINK_N 45 46
A2
S3_CCLINK_P TP1036 TP1887
B1 A1 47 48
TP1888
S3_CPU_STATUS1_N 49 50
DG
S3_CPU_STATUS1_P 51 52
S3_CPU_STATUS0_P 53 54 DG
TP1889
S3_CPU_STATUS0_N 55 56 +3.3V
D S3_nLOS_N 57 58
+3.3V
S3_nLOS_P 59 60
R673
TP1037 2:2C
10k
61 62 nDIAG3
2:2B 1:2D;1:9B;2:1B;2:2A;3:9F;5D
TP1016 63 64
nDETCL3
LOCAL_nRST
1:9F TP1038 65 66
TP1070 1:7H
SHWU3[0] SHWD3[0]
TP1074 1:7H
SHWU3[1] 1:9G TP1039 67 68 SHWD3[1]
1:9G TP1049 TP1068 1:6H
SHWU3[2] 69 70 SHWD3[2]
2:2C TP1040 71 72 1:11G;3:6C;5E
S3_NETREF RINGERSYNC
2:2C TP1041 TP1071 2:2B
nLOS3 73 74
nSRST3
R233
10k
2:2C TP1042 75 76 1:1G;3:6C;5E;5:9B
BS31 SHW_CLK
1:1G;3:6C;5E;5:9B +3.3V
BS32 2:2C TP1043
77 78
SHW_FH DG
R674
10k
79 80
2:2B DG TP1072 DG nINTRCL3
TP1015 81 82
E nCMI3B
+3.3V 2:2C
+3.3V
83 84
85 86 2:6D;3:7C;5E
TP1890
nRDCL +3.3V
R237
2:6D;3:7C;5E
10k
TP1891 87 88
nWECL
TP1073 2:2C
TP1892 89 90
nCSCL3
TP1893 91 92 LA[5]
LA[4] 93 94 LA[3]
LA[2] 95 96 LA[1]
97 98
LD[15] DG 99 100 DG LD[14]
LD[13] 101 102 LD[12]

LD[11] 103 104 LD[10]
LD[9] 105 106 LD[8]

F
LD[7] 107 108 LD[6]
LD[5] 109 110 LD[4]
LD[3] 111 112 LD[2]

LD[1] 113 114 +3.3V LD[0]
+3.3V
115 116
TP1894 TP1895
117 118
119 120
DG CN402 DG
G (1)
(2)
57
15.5. No.5
1 2 3 4 5 6
nPOW_RST
A 1:10B;2:1B;4E
2:4G
nWAITTK (1)
nRDTK 2:3F
2:3F
nRDTK
nWETK
(2)
nWETK
(3)
B
2:2G
nCSTK (4)
1:2A;2:6B;3:7C;4:2G LD[0-7]
LD[0-7] (5)
2:7D;1:2B;3:7B;4:2G LA[0-12]
LA[0-12] (6)
+3.3V
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
C1025
C1001
C1002
C1003
C1004
C1005
C1006
C1007
C1008
C1009
C1010
C1011
C1012
C1013
C1014
C1026
C1027
C1028
C1029
C1030
C1031
C1032
C1033
C1034
C1035
C1036
C1037
C1038
C1039
C1040
+3.3V
DG
220P
220P
C1203 220P
220P
C1205 220P
C1206 220P
220P
220P
220P
C1210 220P
C1211 220P
220P
220P
220P
C1215 220P
220P
C1217 220P
C1218 220P
220P
220P
C1221 220P
220P
220P
C1224 220P
C1225 220P
220P
C1227 220P
C1228 220P
C1229 220P
C1230 220P
D
C951
C952
C954
C957
C958
C959
C962
C963
C964
C966
C969
C970
C972
C973
C976
DG
+3.3V
5 4 (6)
RA602
+3.3V NC NC 6 3 (7)
NC
RESET IC
0 0 7 2 (8)
J644 J645 8
5
1
4
(9)
(11) (10)
TP1202
NC
RA603
1 5 6 3
M/R Vcc
7 2
R602
(13) (12)
470
D602
2 8 1 TP2054
SUB IC613 IC613 J602
1:10B;2:1B;4A
E 3
GND Vout
4
TP1936
1 2 3 4 nPOW_RST NC
TP1935 +3.3V
DG
IC607 J603 NC
5 4 TP2055 (6)
RA605 RA604
6 3 TP2056 (7)
NC
7 2 NC
8 1 J604
(9) (8)
5
6
4
(10)
7
NC 3
2 (11) (12)
8 1
IC613 (13)
5 6 TP1937
C660
0.1
IC613
9 8 TP1938
+3.3V
IC613
11 10 TP1939
0.01u
C689
J605
J606
J607
14
NC
NC
IC613
NC
13 12 TP1940
7
IC613 +3.3V
F DG
C661
0.1
+15VIN
+15V +3.3V
+15VIN IP600 TP1205 L634 TP1206

D
Q602 S
J601 TP2116 IP601 +3.3V

1:11A 5A 1.9A/33u
R604
680
0
330u/25V
C652
1.25A
L633
Q601
470u/6.3V
G
C610
D
TP1208
TP1203 TP2117
D601
G
5.1V
D600
R603
0.1u
C654
+1.2V
G S
0
L636
R601
56
P.G P.G
+1.2V
P.G P.G P.G
J600
R605
P.G TP1207
680
0 IC612
4.7u
+3.3V +3.3V
C658
TP1204 IC604 1
VDD VOUT
5
J642
R608
P.G
J640 J643
P.G P.G 2
1
0
0
5 Vin ON/OFF 1 GND

DG P.G TP1209 TP1933 TP1934
3 4
Vss 2 #CE ECO
TP2126
J641
NC
C659
NC
0
4.7u
4 EXT Vout 3
0
PG
DG DG DG
C636
P.G DG
0.1uF/25V P.G
(13)
H (14)
IC605 +2.5V
(15)
3 VIN VOUT 2
TP1211 J636
+2.5V
(16)
(17)
R607
VSS
1
C656
1
1u
TP1210
C657
1u
DG
DG
DG
58
7 8 9 10 11
+3.3V +3.3V +3.3V +3.3V

A
NC R643
NC R640
NC R638
R646
NC
TP2057
+3.3V +3.3V
+3.3V +3.3V +3.3V +3.3V +3.3V
R629
R635 NC
R231
NC R631
SHW_CLK
R624
R625
NC R632
10K
NC
TP2059 1:1G;3:6C;4:10E;4:5E
NC
1:1G;3:6C;4:10E;4:5E
SHW_FH
NC
(1)
(2)
(3)
B
TP2060
(4)
TP2058
TP2061
J619 NC
TP1328
+3.3V
J620 NC
R627 NC
0.01
C676
NC R626
R628 NC
(5) +3.3V
TP1331
TP1333
DG +3.3V
+3.3V
(6)
R634
R639
NC
R630
NC
R633
NC R641
LA[10]
LA[11]
LA[12]
LD[0]
LD[1]
LD[2]
LD[3]
LD[4]
LD[5]
LD[6]
LD[7]
LA[0]
LA[1]
LA[2]
LA[3]
LA[4]
LA[5]
LA[6]
LA[7]
LA[8]
LA[9]
J614 NC
R636
R637
NC
NC
NC
NC
+3.3V
+3.3V
TP1271
TP1272
TP1273
TP1275
TP1277
TP1279
TP1281
TP1284
TP1287
TP1289
TP1290
TP1291
TP1293
TP1295
TP1296
TP1298
TP1299
TP1300
TP1301
TP1302
TP1304
TP1305
TP1306
TP1307
TP1308
TP1309
TP1310
TP1311
TP1312
TP1313
TP1314
TP1315
TP1317
TP1318
TP1319
TP1320
TP1321
TP1322
TP1323
TP1324
128 TP2124
127 TP1941
124 TP1942
126 TP2125
8
7
6
5
8
7
6
5
C RA608 RA610
NC NC
SHW_FH 130
SHW_CLK 129
125
123
LDHW[0] 122
LUHW[0] 121
3
3
1
2
4
1
2
34
33
32
31
30
28
27
25
24
23
22
CS[0] 10
19
18
17
16
15
14
13
12
52
51
50
49
48
47
46
45
43
42
41
40
39
26
38
37
CS[1] 9
IRQ[0] 8
IRQ[1] 7
LD[0]
LD[1]
LD[2]
LD[3]
LD[4]
LD[5]
LD[6]
LD[7]
LA[0]
LA[1]
LA[2]
LA[3]
LA[4]
LA[5]
LA[6]
LA[7]
LA[8]
LA[9]
LA[10]
LA[11]
LA[12]
SBACK
SBREQ
BGAK
BACK
BREQ
RESET
WAIT
L_NRST
WR
RD
CSI
CS_SAM
CS_DMA
ALE
LUHW[1]
LDHW[1]
L_NETREF
HW_FH
HW_CLK[1]
HW_CLK[0]
TP2007 142 P0[0]
TP2008 143 P0[1]
TP2009 144 P0[2]
TP2010 145 P0[3] EC_CLK 1:11A
TP2011 146 P0[4] EC_CLK
TP2012 147 P0[5] EC_CLK 105 +3.3V
TP2013 148 P0[6] EC_STOP 103 TP2062 5 4
P0[7]
RA623 RA618
TP2014 149
EC_TRDY 102 TP2063 6 3
NC
+3.3V EC_PERR 101 TP2064 7 2
EC_FRAME 100 TP2065 8 1
EC_PAR 99 TP2066 5 4
EC_BE[0] 97 TP2067 6 3 EC_nRS
T 1:10B EC_nRST
NC
1 8 TP2015 151 P1[0] EC_BE[1] 96
RA609 RA629
152 P1[1] TP2068 7 2

NC
2 7 TP2016
3 6 TP2017 153 P1[2] EC_IDSEL 95 TP2069 8 1
4 5 TP2018 154 P1[3] EC_NRST 94
1 8 TP2019 155 P1[4] 1:10C CT_D[0-7]
+3.3V
NC
2 7 TP2020 156 P1[5]

157 P1[6] EC_AD[0] 92 TP2071 5 4 +3.3V
RA617 RA615 RA616 RA614

3 6 TP2021
EC_AD[1] 91 TP2072 6 3
NC
4 5 TP2022 158 P1[7] EC_AD[2] 90 TP2073 7 2
D EC_AD[3] 89 TP2074 8 1 CT_D[7] 8 1
RA628 RA627
NC
EC_AD[4] 86 TP2075 5 4 CT_D[6] 7 2
+3.3V EC_AD[5] 85 TP2076 6 3 CT_D[5] 6 3
NC
5 4 TP2023 161 P2[0] EC_AD[6] 84 TP2077 7 2 CT_D[4] 5 4
EC_AD[7] 83 CT_D[3]
RA607 RA606
TP2024 162 P2[1] TP2078 8 1 8 1

6 3
NC
EC_AD[8] 81 TP2079 5 4 CT_D[2] 7 2
NC
7 2 TP2025 163 P2[2] EC_AD[9] 80 TP2080 6 CT_D[1]
NC
TP2026 164 P2[3] 3 6 3
8 1 EC_AD[10] 79
5 4 TP2027 165 P2[4]
TP2081 7 2 CT_D[0] 5 4
6 3 TP2028 166 P2[5] NC EC_AD[11] 78 TP2082 8 1
NC
7 2 TP2029 167 P2[6] EC_AD[12] 75 TP2083 5 4 DEBUG ONLY

EC_AD[13] 74 TP2084 6 3
NC
168 P2[7]
8 1 TP2030
IC603 EC_AD[14]
EC_AD[15]
73
72
TP2085
TP2086
7
8
2
1
CT_D[0] 68 TP2087 5 4 TP2095 5 4 CT_D[0]
LA601
RA621 RA620
CT_D[1]
NC
CT_D[1] 67 TP2088 TP2096 6 3
(6) 6 3
NC
TP2031 170 P3[0] DEBUG ONLY
171 P3[1] CT_D[2] 66 TP2089 7 2 TP2097 7 2 CT_D[2]
(7) TP2032
TP2033 172 P3[2] CT_D[3] 65 TP2090 8 1 TP2098 8 1 CT_D[3] +3.3V
(8) CT_D[4] 62 TP2091 5 4 TP2099 5 4 CT_D[4]
NC R668
NC R669
173 P3[3]
(9) TP2034
CT_D[5] 61 CT_D[5]
LA602
6 3
NC
174 TP2092 6 3 TP2100
TP2035 P3[4]
NC
(10) (11) TP2036 175 P3[5] CT_D[6]
CT_D[7]
60
59
TP2093 7 2 TP2101 7
8
2
1
CT_D[6]
CT_D[7]
(12) (13)
TP2037
TP2038
176
177
P3[6]
P3[7]
[TACKER] TP2094
+3.3V
8 1 TP2102
EC_INT 71 TP1360
E EC_DET 70 TP1361
CT_NETREF 57 TP1362 1:11E;1:2H
CT_C8_A 56 TP1363 CT_C8
(6) TP2039
TP2040
192
193
P4[0]
P4[1] CT_FRAME_A 55 TP1364
CT_FRAME
(7) TP2041 194 P4[2] RINGER 54
+3.3V 1:11E;1:2H
(8) (9) TP2042 195 P4[3]
TP2043 196 P4[4]
(10) 197 P4[5]
MODE[0] 118 TP2118 5 4 +3.3V
RA613
TP2044
(12) (11)
MODE[1] 117
NC
TP2045 198 P4[6] TP2119 6 3
MODE[2] 116 TP2120 7 2 5 4
199 P4[7]
RA622
TP2046
(13) MODE[3] 115 TP2121
NC
8 1 6 3
MODE[4] 114 TP2122 7 2
MODE[5] 113 TP2123 8 1
J622
J623
J625
J626
J628
J629
+3.3V
5 4 TP2047 201 P5[0]
RA612 RA611
6 3 TP2048 202 P5[1]

NC
NC
NC
NC
NC
7 2 TP2049 203 P5[2]

NC
NC
8 1 TP2050 204 P5[3]

5 4 TP2051 205 P5[4]
6 3 TP2052 206 P5[5] VREFMINUS 182 DG
NC
7 2 TP2053 207 P5[6] VREFPLUS 181

8 1 TP1943 208 P5[7] +3.3V +3.3V
TP1219 DG
F TDO 109
TP2103
TMS 111 TP2104 5 4
RA624
183 RX[0] TRST 110 TP2105 6 3

NC
184 RX[1] TDI 108 7 2

185 RX[2] TCK 107 TP2106 8 1
AVDD180
AVDD191
186 RX[3]
J33 NC
3 PLLGND
5 PLLVDD
GND104
GND112
GND119
GND131
GND141
GND150
GND160
GND179
C_CS[0]
C_CS[1]
C_CS[2]
C_CS[3]
VDD106
VDD120
VDD132
VDD159
VDD178
4 PLLCLK
6 PLLAT1
J30 NC
J32 NC
187 RX[4] TEST1 200

GND11
GND21
GND29
GND35
GND44
GND58
GND64
GND69
GND76
GND82
GND88
GND93
GND98
VDD20
VDD36
VDD53
VDD63
VDD77
VDD87
DG
DOUT
GND1
DCLK
VDD2
188 RX[5] TEST0 169

CP[0]
189 RX[6]
DIN
190 RX[7]
140
139
138
137
136
135
134
133
C675 106
C677 120
C678 132
C679 159
C681 178
C682 180
C683 191
104
112
119
131
141
150
160
179
20
36
53
63
77
87
11
21
29
35
44
58
64
69
76
82
88
93
98
2
1
J617 TP1316
+3.3V
TP1294
DG
TP1297
TP1945
TP1946
TP1947
TP1948
TP1949
TP1950
TP1944
C667
C668
C669
C671
C672
C673
C674
+3.3V
TP1303
C665 J609
FIL601
NC
TP2146
3 1 DG
J618 NC
C685
C684
NC
2.2
2
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
DG J611
0.1
8
C688
IC610
0
J613
4 IC610 NC
NC
DG
1 7 TP1462 DG
FIL603
C664
0.1
DG DG 1 3 DG
G
7 2
J612
+3.3V
J608
J610
NC
NC NC
IC610 IC610
C670
C666
0.1
6
TP1220
2 3 5
TP1270
1 3
R623
1
2 TP1283 68 C16M
R621 FIL602
DG DG DG DG DG DG DG DG DG DG DG
DG
1M R622 DG
TP1217 2:2G
3.3k C16M
X602
16.384MHz
TP1221
C663
12p
C662
18p
DG J630 0
3216
DG
(13) FG
H (14) J632 0
3216
(15)
(16) FG DG
(17)
59
KXTDA6110XUK
KXTDA6110XJ
H
KX-TDA6110XJ/KX-TDA6110X BUS-M BOARD COMPONENT VIEW
A
L633 D600
CN201
R601
B2 B40 Q602 CN101 C976

B1 B39
A2 A40 L634 C1036
4
A1 A39 A1
R636
IC604 A45
B1
5
A10
1
R206 C1001
C951
B10 A20 A30 A40 B45

R120
C1002
R122
C1013
C969 B20 B30 B40

C963
IP600 C970
C666
J646
C1225
C952
R603 C1035
J101
C1029 C1030
R211
C601 3 1
R124
C654 Q601 IC113 RA105 RA106
R604 D601
C130
RA204 RA205 RA206 RA207 RA213 RA211
C202
RA212 RA217 RA208 4

C201
R605 5
C203 C204 C205 C206 RA628 LA101
RA627 LA102 RA116
20 11 11 11 C207 11 11 11
R225
RA117
20 20 8 20 20 20
IC204
IC205
IC206
C652
IC200
IC202
IC203
5 RA623 RA616 RA617 RA621 C118 C122

1 4 RA620 C120 C114 C124 C116 C132
R668
R669
RA624
1 1
IC209 1 1 1 1 RA618 RA614 RA615 LA602 R123 256 193
10 10 10 10 10 10 J32 LA601 192
RA221
1
C672 C671
RA222
KX-TDA6110
C674 C673
C107
C127 C105
RA115
C1205 J33 104
RA223
RA224
RA216 C675
R242
R228
C249
RA210 RA215 J30 53

RA613 RA622
RA209
RA201
J622
C112
C954 52
RA114 RA112
C1004 C1005 J623
C235
C246
J625 105
C110
C247
RA113
C234 J626 R115 C1230
C677
11 J628
J614
R626 R118
C669
C106
20
C129
C248 C964 J629 C1040
C1007
C223
C241
C240
R627 C1039
R221
C1014 R643 IC101
C104 C108 C131

IC210 R646 C676 C1229
J200 C957 R640
R638 R641 R629
C126 R114 C123

1 10 J620 R637 R639 R628 R121
RA203
C242
IC603 R625
C128
J201
C668
C239
J600
J619
R215
RA110
IP601 R624
RA610
J202 J601 R636
C678
R213
L102 L101 R116

J203 R630
C689
C656 R602
R222
R223
R220
J204 C229 R231

RA202
C658 14 8 R633 R632

J642 J641
J205 5
C238
C222 3 1 4 R634
RA609 RA608
IC613
J206 C228
IC605
IC607
IC612
C659 R635 R631

J207 64 129
9
C667
IC614 C237 J609 C665
R112
C227
R230
RA629
4 5 J613 65 C125
R113
C244 C236 1 3 C115 C111 128
J643 R608
R111
C226 C221 1 7 J611
RA633 LA107
RA109 LA103
RA108 LA104
R109 C117 C113 C109
J636 J644
C664
FIL603
156
J618
J612
J610
C225
J617
C235
C245 J640 1
60
R119
C657
J645 IC114
R607
L636
157 C119
D602
R117
LA105
C679 C682 C683 C121
R406 R233C250 J209 C224
C681 208
CN405
C685
RA632
J301 C1038
J602
C135
C1228
R623
C962 C684 C660 C666
16 PRINTED CIRCUIT BOARD
R343
FIL602
C670
C1012
J607
RA606 RA602
RA605
RA612
RA611
C232
C233
R236 C234
J208
J608
C243 C1227
R351
R352
J302
PSUP1512Z*
RA607
R350
1
8
IC610
J606
RA604 C305 C1037
RA603 FIL601 C307 C311 97
R238
R237
R232
R239
128
5
96
C303 C302 C301 C304

C663 R622 R621 C662 C688 1
1
R342 R341 C312

R675
R672
R674
R673
C309
J603
J604
J605
J661
X602 R340
R353
R405
R365
C1206 C1210 C1215 4 1 C1224
R335
PbF
IC301
X302
X301
C1006 C1010 5 8
C308
C1025 R362 C1034
FIL301
C1217
C313
32
C1027 33 64 65 C314
R339
C306 R417 5
IC303 4
R334
R357
R359
R360
R361
R363
8 1
R329 C320
C1211
C1221
C1031
FIL310
R358
R356
R309
R310
R311
R338
R333
R332
R331
C1203 C1011
R327
R328
R330
C317 C316
C1003 8 1 8 1
9 4 1 16
C315
R301
16
IC313
IC312
9
R326
R318
C319
16.1. Component View
IC314
2 12 20 30 40 50 60 70 80 90 100 110 120 2 12 20 30 40 50 60 70 80 90 100 110 120 IC315 IC311
9 9
BUS-M
16 16
14
C318
8 1 1 8
IC2111 RA306 RA307 8 5
11 CN402 CN401 R312
R241 R315 R364 8R304 R303
C230
RA631 RA302 R313 R302
J304 RA630
FIL307
FIL306
FIL305
FIL304
FIL303
R314
RA303
1 7 21 31 41 51 61 71 81 91 101 111 119 1 11 21 31 41 51 61 71 81 91101 111 119
J306
J305
Q201 1 FIL308
Q205
J310
J317
J316
J313
J308
C972
RA301
RA305
RA304
Q203 Q202
J303
J307
J318
J314
J312
J309
R401
R404
J311
Q204
FIL309
C1032
FIL302
C958 R402 C973
CN303 CN302 J315 CN301
R202
C966 C1228
J630
C1008 R403
R218
R217
R219
R201 C1009 A20 A2 A20 A2 A20 A2 C1033
LED204
C959 A19 A1 C1026 A19 A1 C1028 A19 A1
LED201
B20 B2 B20 B2 B20 B2 J632
LED202
LED203
B19 B1 B19 B1 B19 B1

Tda 6110 XJ

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ORDER NO.

Bus Master Card

IMPORTANT INFORMATION ABOUT LEAD FREE, (PbF), SOLDERING

© 2005 Panasonic Communications Co., Ltd. All

1 ABOUT LEAD FREE SOLDER (PbF: Pb free)

1.1. SUGGESTED PbF SOLDER

1.2. HOW TO RECOGNIZE THAT Pb FREE SOLDER IS USED

2 FOR SERVICE TECHNICIANS

4 BUS-M CARD HARDWARE FUNCTION SPECIFICATION

5.1. INSTALLING/REMOVING THE OPTIONAL SERVICE CARDS

Table 0-2 Connector map for connections between shelf #2

Table 0-3 Connector map for connections between shelf #3

Connector 1(for expansion shelf #1)15pair

Connector 2(for connecting expansion shelf #2)

Connector 3(for connecting expansion shelf #3)

Accessories and User-supplied Items

Installing Optional Service Cards

3. Turn the 2 screws clockwise to fix the card.

Expansion Backboard connect or

nSLF2_PRS LSTo[0:2] CT_D[7:0]

S3_NETREF +2.5V 2.5V

ESLID1[1:0] " 00"

KX-TDA6110XJ/KX-TDA6110X BUS-M BLOCK DIAGRAM

6.1. BLOCK DISCRIPTION

The main functions of the BMCTL are as follows.

6.2. DESCRIPTION OF THE SIGNAL OF BUS-M

Signal Name Function

7.2. CONNECTION BETWEEN SHELVES

7.2.2. Expansion shelf No.2

7.2.3. Expansion shelf No.3

7.2.4. Check of call path

Pin No. Pin Name I/O DiscriptionPin Usage

Pin No. Pin Name I/O DiscriptionPin Usage

Pin No. Pin Name I/O DiscriptionPin Usage

8.2. PROM (IC210)

Pin No. Pinl Name I/O DiscriptionPin Usage

8.3. CTSW (IC101)

Pin No. Pin Name I/O DiscriptionPin Usage

Pin No. Pin Name I/O DiscriptionPin Usage

Pin No. Pin Name I/O DiscriptionPin Usage

Pin No. Pin Name I/O DiscriptionPin Usage

Pin No. Pin Name I/O DiscriptionPin Usage

8.4. CIRCLINK (IC301)

Pin No. Pin Name I/O DiscriptionPin Usage

Pin No. Pin Name I/O DiscriptionPin Usage

Pin No. Pin Name I/O DiscriptionPin Usage

9 HOW TO REPLACE A FLAT PACKAGE IC

9.2. REMOVAL PROCEDURE Be certain each pin is located over the

3. Being careful to not unsolder the tack points, slide the

9.4. REMOVING SOLDER FROM

When you attach a new IC to the board, remove all solder

10 TERMINAL GUIDE OF ICS, TRANSISTORS AND DIODES

11 CABINET AND ELECTRICAL PARTS LOCATION

12 ACCESSORIES AND PACKING MATERIALS

13 REPLACEMENT PARTS LIST

13.1. CABINET AND ELECTRICAL D600

14 FOR SCHEMATIC DIAGRAM

14.2. BUS-M BLOCK DIAGRAM

TP107 TP1749 TP1748